TFT substrate and manufacturing method thereof, liquid crystal display panel and OLED display panel

Abstract

The embodiment of the present application provides a TFT substrate and a manufacturing method thereof, a liquid crystal display panel and an OLED display panel. The TFT substrate provided in the embodiment of the present application is obtained by etching a source electrode and a drain electrode through a conductive layer, wherein the conductive layer includes a first metal layer and a second metal layer stacked in layers, and the standard electrode potential of the first metal layer is set to be lower than the standard electrode potential of the second metal layer, and the thickness of the first metal layer is set to be greatly reduced compared with the prior art, which is conducive to making the etched source electrode and drain electrode have a smaller Taper angle.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a TFT substrate and a manufacturing method thereof, a liquid crystal display panel and an OLED display panel. Background Art

[0002] Thin film transistors (TFTs) are an important component of display devices. TFTs can be formed on glass substrates or plastic substrates and are usually used as switching components and driving components in display devices such as liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs).

[0003] Compared with a-si (amorphous silicon), oxide semiconductor TFT has unique advantages: the sub-bandgap state density of oxide semiconductor is much smaller than that of amorphous silicon, which makes the subthreshold swing of oxide semiconductor TFT very small; metal oxide semiconductors are easier to produce band conduction than amorphous silicon and have higher mobility; compared with low-temperature polycrystalline silicon thin-film transistors, oxide semiconductor TFT exhibits better uniformity; oxide semiconductor TFT exhibits extremely low leakage current because the generation and transmission of holes are more difficult, and the lower leakage current can achieve the low refresh drive requirements of TFT.

[0004] However, the source and drain of the oxide semiconductor TFT usually need to be etched to form a preset pattern. After etching, the sides of the obtained source and drain are usually perpendicular to the substrate, that is, the Taper angle is about 90 degrees. However, when the Taper angle is around 90 degrees, the passivation layer deposited above the source and drain is difficult to adhere to the surface of the side edges of the source and drain, which causes the passivation layer to easily fall off the source and drain, and the source and drain cannot be effectively protected. Summary of the invention

[0005] The embodiments of the present application provide a TFT substrate and a manufacturing method thereof, a liquid crystal display panel and an OLED display panel. In the TFT substrate, the Taper angles of the source and the drain are small, the passivation layer can be well adhered to the source and the drain, and is not easy to fall off from the source and the drain, so the source and the drain can be effectively protected.

[0006] In a first aspect, an embodiment of the present application provides a TFT substrate, comprising a substrate, a gate, an active layer, a source-drain electrode layer, and a passivation layer, wherein the gate and the active layer are both arranged between the substrate and the source-drain electrode layer, the passivation layer covers a side of the source-drain electrode layer away from the substrate, and the source-drain electrode layer comprises a source electrode and a drain electrode arranged at intervals;

[0007] The source electrode and the drain electrode are both obtained by etching a conductive layer, wherein the conductive layer includes a first metal layer and a second metal layer stacked in layers, wherein the first metal layer is disposed on a side of the second metal layer away from the substrate; the standard electrode potential of the first metal layer is lower than the standard electrode potential of the second metal layer, and the thickness of the first metal layer is

[0008] In some embodiments, the material of the first metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, the material of the second metal layer is copper, and the thickness of the second metal layer is

[0009] In some embodiments, the conductive layer further includes a third metal layer, and the third metal layer is disposed on a side of the second metal layer away from the first metal layer;

[0010] The material of the third metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, and the thickness of the third metal layer is

[0011] In some embodiments, the angle between the side of the source and the plane where the substrate is located is 50° to 70°, and the angle between the side of the drain and the plane where the substrate is located is 50° to 70°.

[0012] In some embodiments, the conductive layer further includes a third metal layer, and the third metal layer is disposed on a side of the second metal layer away from the first metal layer;

[0013] The material of the third metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, and the thickness of the third metal layer is

[0014] In some embodiments, the angle between the side of the source and the plane where the substrate is located is 50° to 70°, and the angle between the side of the drain and the plane where the substrate is located is 50° to 70°.

[0015] In some embodiments, the TFT substrate further includes a gate insulating layer, and the substrate, the gate, the gate insulating layer, the active layer, the source-drain electrode layer, and the passivation layer are sequentially stacked; wherein the gate insulating layer covers the gate, the active layer and the gate are correspondingly arranged, the source and the drain are both in contact with the active layer, and the passivation layer covers the source-drain electrode layer and the active layer; or

[0016] The TFT substrate also includes a gate insulating layer and an interlayer insulating layer, and the substrate, the active layer, the gate insulating layer, the gate, the interlayer insulating layer, the source-drain electrode layer and the passivation layer are stacked in sequence; wherein the gate insulating layer covers the active layer, the interlayer insulating layer covers the gate, the active layer and the gate are arranged correspondingly, the gate insulating layer and the interlayer insulating layer are provided with a source contact hole and a drain contact hole, the source electrode contacts the active layer via the source contact hole, the drain electrode contacts the active layer via the drain contact hole, and the passivation layer covers the source-drain electrode layer.

[0017] In a second aspect, the present application also provides a method for manufacturing a TFT substrate, comprising:

[0018] A substrate is provided, and a gate, an active layer and a conductive layer are arranged on the substrate, wherein the gate and the active layer are arranged between the substrate and the conductive layer, and the conductive layer includes a source electrode and a drain electrode arranged at intervals; the conductive layer includes a first metal layer and a second metal layer arranged in a stacked manner, and the first metal layer is arranged on a side of the second metal layer away from the substrate; the standard electrode potential of the first metal layer is lower than the standard electrode potential of the second metal layer, and the thickness of the first metal layer is

[0019] Etching the conductive layer to obtain a source-drain electrode layer, wherein the source-drain electrode layer includes a source electrode and a drain electrode that are spaced apart;

[0020] A passivation layer is disposed on a side of the source and drain electrode layer away from the substrate.

[0021] In some embodiments, the material of the first metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, the material of the second metal layer is copper, and the thickness of the second metal layer is

[0022] In some embodiments, the conductive layer further includes a third metal layer, and the third metal layer is disposed on a side of the second metal layer away from the first metal layer;

[0023] The material of the third metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, and the thickness of the third metal layer is

[0024] In some embodiments, the angle between the side of the source and the plane where the substrate is located is 50° to 70°, and the angle between the side of the drain and the plane where the substrate is located is 50° to 70°.

[0025] In a third aspect, an embodiment of the present application provides a liquid crystal display panel, comprising:

[0026] a first substrate;

[0027] a second substrate, disposed opposite to the first substrate, wherein the second substrate is the TFT substrate as described above or a TFT substrate manufactured by the manufacturing method of the TFT substrate as described above;

[0028] The liquid crystal layer is sandwiched between the first substrate and the second substrate.

[0029] In a fourth aspect, an embodiment of the present application provides an OLED display panel, including:

[0030] A driving substrate, wherein the driving substrate is the TFT substrate as described above or a TFT substrate manufactured by the manufacturing method of the TFT substrate as described above;

[0031] The OLED device is disposed on the driving substrate, and the OLED device is electrically connected to the driving substrate.

[0032] The TFT substrate provided in the embodiment of the present application is obtained by etching the source electrode and the drain electrode through a conductive layer, wherein the conductive layer includes a first metal layer and a second metal layer stacked in layers, and the standard electrode potential of the first metal layer is set lower than the standard electrode potential of the second metal layer. Therefore, during the etching process of the conductive layer, a galvanic corrosion effect can be formed between the first metal layer and the second metal layer, and the first metal layer acts as an anode and the second metal layer acts as a cathode. Since the thickness of the first metal layer in the embodiment of the present application is In the related art, the thickness of the first metal layer is set to Compared with the technical solution of the present invention, the thickness of the first metal layer is greatly reduced, thereby reducing the contact area between the first metal layer and the etching solution, and further increasing the ratio b / a between the contact area b between the cathode and the etching solution and the contact area a between the anode and the etching solution. It is known that when b / a increases, the corrosion rate of the anode, i.e., the first metal layer, is accelerated, so a gap is formed between the first metal layer and the second metal layer. Since the amount of etching solution filled in the gap is small and the etching ability is weak, the longitudinal etching rate of the portion corresponding to the gap on the second metal layer is small; and since the amount of etching solution above the portion corresponding to the periphery of the gap on the second metal layer is large, the longitudinal etching rate of the portion corresponding to the periphery of the gap on the second metal layer is large, and finally the edge area of ​​the second metal layer shows a trend of gradually decreasing thickness, and finally the etched source and drain have a smaller Taper angle. When the Taper angle of the source and drain is small, the passivation layer can be better attached to the source and drain, and is not easy to fall off from the source and drain, so the source and drain can be effectively protected. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0034] Figure 1 A flow chart of a method for manufacturing a TFT substrate provided in an embodiment of the present application.

[0035] Figure 2 A schematic diagram of forming a gate, a gate insulating layer and an active layer on a substrate provided in an embodiment of the present application.

[0036] Figure 3 A schematic diagram of forming a conductive layer on an active layer and a gate insulating layer provided in an embodiment of the present application.

[0037] Figure 4 A schematic diagram of the cross-sectional structure of the conductive layer provided in an embodiment of the present application.

[0038] Figure 5 A schematic diagram of etching a conductive layer to obtain a source and a drain provided in an embodiment of the present application.

[0039] Figure 6 FIG. 1 is a schematic diagram of a process of etching a conductive layer in a method for manufacturing a TFT substrate according to an embodiment of the present application.

[0040] Figure 7 for Figure 6 Schematic diagram of the effect after the conductive layer is etched in the method for manufacturing a TFT substrate.

[0041] Figure 8 FIG. 1 is a schematic diagram of a process of etching a conductive layer in a method for manufacturing a TFT substrate according to another embodiment of the present application.

[0042] Fig. 9 for Figure 8 Schematic diagram of the effect after the conductive layer is etched in the method for manufacturing a TFT substrate.

[0043] Fig.10 This is a schematic diagram of the first structure of the TFT substrate provided in an embodiment of the present application.

[0044] Fig.11 A second structural schematic diagram of the TFT substrate provided in an embodiment of the present application.

[0045] Fig.12 A schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of the present application.

[0046] Fig.13This is a schematic diagram of the structure of the OLED display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] See also Figure 1 , Figure 1 Flow chart of a method for manufacturing a TFT substrate provided in an embodiment of the present application. An embodiment of the present application provides a method for manufacturing a TFT substrate, comprising:

[0049] S100, see Figures 2 to 4 , a substrate 10 is provided, a gate 20, an active layer 40 and a conductive layer 50 are arranged on the substrate 10, wherein the gate 20 and the active layer 40 are arranged between the substrate 10 and the conductive layer 50, and the conductive layer 50 includes a source electrode 61 and a drain electrode 62 arranged at intervals; the conductive layer 50 includes a first metal layer 51 and a second metal layer 52 arranged in a stacked manner, and the first metal layer 51 is arranged on a side of the second metal layer 52 away from the substrate 10; the standard electrode potential of the first metal layer 51 is lower than the standard electrode potential of the second metal layer 52, and the thickness of the first metal layer 51 is

[0050] It can be understood that the first metal layer 51 is the topmost metal layer in the conductive layer 50 .

[0051] Exemplarily, the thickness h of the first metal layer 51 may be wait.

[0052] For example, the material of the first metal layer 51 may be molybdenum-titanium alloy (MoTi), molybdenum (Mo) or molybdenum-niobium alloy (MoNb). The standard electrode potential of molybdenum-titanium alloy (the molar ratio of Mo to Ti is 1:1) is 0.29V, the standard electrode potential of molybdenum is -0.2V, and the standard electrode potential of molybdenum-niobium alloy (the molar ratio of Mo to Nb is 9:1) is -0.1V.

[0053] For example, the material of the second metal layer 52 may be copper (Cu), and the thickness of the second metal layer 52 may be For example It is known that the standard electrode potential of copper (Cu) is 0.34 V, that is, the standard electrode potential of molybdenum-titanium alloy (MoTi), molybdenum (Mo) or molybdenum-niobium alloy (MoNb) is lower than that of copper (Cu).

[0054] It can be understood that the second metal layer 52 is the metal layer with the largest thickness in the conductive layer 50 . By setting the material of the second metal layer 52 to copper (Cu), the conductive performance of the conductive layer 50 can be improved.

[0055] It should be noted that, by providing the first metal layer 51 on the upper surface of the second metal layer 52 , the second metal layer 52 can be protected and the copper in the second metal layer 52 can be prevented from being oxidized.

[0056] Please combine Figure 4 , Figure 4 Schematic diagram of the cross-sectional structure of the conductive layer provided in the embodiment of the present application. The conductive layer 50 may further include a third metal layer 53, which is disposed on a side of the second metal layer 52 away from the first metal layer 51. It should be noted that by disposing the third metal layer 53 on the lower surface of the second metal layer 52, it is possible to block the diffusion of copper elements in the second metal layer 52, thereby preventing the copper elements from diffusing into the active layer 40 and affecting the performance of the semiconductor material in the active layer 40.

[0057] For example, the material of the third metal layer 53 may be a molybdenum-titanium alloy, molybdenum or a molybdenum-niobium alloy, and the thickness of the third metal layer 53 is For example wait.

[0058] Exemplarily, the first metal layer 51 , the second metal layer 52 and the third metal layer 53 are all prepared by physical vapor deposition (PVD).

[0059] Exemplarily, “arranging the gate 20, the active layer 40 and the conductive layer 50 on the substrate 10” may specifically include:

[0060] S110, please combine Figure 2 , forming a gate 20, a gate insulating layer 30 and an active layer 40 stacked in sequence on a substrate 10;

[0061] S120, please combine Figure 3 and Figure 4 , a conductive layer 50 is formed on the active layer 40 and the gate insulating layer 30 .

[0062] By way of example, the substrate 10 may be a rigid substrate or a flexible substrate. The material of the rigid substrate may be glass, and the material of the flexible substrate may be a polymer, such as polyimide.

[0063] Exemplarily, the material of the gate 20 may be metal. In some embodiments, the material of the gate 20 may include one or more of aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) and neodymium (Nd). In the embodiments of the present application, multiple may refer to two or more, such as three, four, five, six, seven, eight, nine, ten, eleven, etc.

[0064] Exemplarily, the preparation method of the gate 20 may include: depositing a metal layer, and patterning the metal layer to obtain the gate 20. In some embodiments, the metal layer may be deposited by physical vapor deposition (PVD) such as sputtering, and the metal layer may be patterned by dry etching or wet etching.

[0065] For example, the material of the gate insulating layer 30 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) or more thereof. Exemplarily, the gate insulating layer 30 may be prepared by a chemical vapor deposition (CVD) method.

[0066] Exemplarily, the material of the active layer 40 may include an oxide semiconductor, such as indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. In some other embodiments, the material of the active layer 40 may also be amorphous silicon, single crystal silicon, low temperature polysilicon, etc.

[0067] Exemplarily, the preparation method of the active layer 40 may include: depositing an oxide semiconductor layer, and patterning the oxide semiconductor layer to obtain the active layer 40. In some embodiments, the oxide semiconductor layer may be deposited by chemical vapor deposition (CVD), and the oxide semiconductor layer may be patterned by dry etching or wet etching.

[0068] After step S100, the method for manufacturing the TFT substrate of the embodiment of the present application may further include:

[0069] S200, see Figure 5 , the conductive layer 50 is etched to obtain a source-drain electrode layer, wherein the source-drain electrode layer includes a source electrode 61 and a drain electrode 62 that are spaced apart.

[0070] For example, the conductive layer 50 may be etched by wet etching. Compared with dry etching, wet etching has a higher etching rate, thereby improving the production efficiency of the TFT substrate.

[0071] For example, when the conductive layer 50 is etched by wet etching, the etching solution may include hydrogen peroxide. It is understood that the etching solution of the hydrogen peroxide system has the advantages of constant and easy-to-control etching rate and simple post-processing; preferably, the etching solution does not contain fluorine element, has little environmental pollution, and will not damage the glass substrate during the etching process.

[0072] See also Figure 6 and Figure 7 , Figure 6 FIG. 1 is a schematic diagram of a process of etching a conductive layer in a method for manufacturing a TFT substrate according to an embodiment of the present application. Figure 7 for Figure 6 Schematic diagram of the effect after the conductive layer is etched in the manufacturing method of the TFT substrate. It should be noted that, since the standard electrode potential of the first metal layer 51 is lower than the standard electrode potential of the second metal layer 52, during the etching process of the conductive layer 50, a galvanic corrosion effect can be formed between the first metal layer 51 and the second metal layer 52, and the first metal layer 51 acts as an anode and the second metal layer 52 acts as a cathode; the contact area between the anode (first metal layer 51) and the etching solution is defined as a, and it can be understood that a is the total area of ​​the side 515 of the first metal layer 51, and the greater the thickness of the first metal layer 51, the greater a; the contact area between the cathode (second metal layer 52) and the etching solution is defined as b, and it can be understood that b is the total area of ​​the side 525 of the second metal layer 52.

[0073] like Figure 6 As shown, when the thickness of the first metal layer 51 is When the thickness of the first metal layer 51 is small, the contact area a between the anode (first metal layer 51) and the etching solution is small, so that the ratio b / a between the contact area b between the cathode (second metal layer 52) and the etching solution and the contact area a between the anode (first metal layer 51) and the etching solution is large. When b / a is larger, the corrosion rate of the anode (first metal layer 51) is faster, so a gap 80 is formed between the first metal layer 51 and the second metal layer 52.

[0074] from Figure 6 It can be seen from the figure that, since the amount of etching liquid filled in the gap 80 is small and the etching ability is weak, the longitudinal etching rate of the portion of the second metal layer 52 corresponding to the gap 80 is small; since the amount of etching liquid above the portion 520 of the second metal layer 52 corresponding to the periphery of the gap 80 is large, the longitudinal etching rate of the portion 520 of the second metal layer 52 corresponding to the periphery of the gap 80 is large, and finally the edge area of ​​the second metal layer 52 shows a trend of gradually decreasing thickness, thereby forming a smaller Taper angle α1 (such as Figure 7 shown).

[0075] See also Figure 8 and Fig. 9 , Figure 8 FIG. 1 is a schematic diagram of a process of etching a conductive layer in a method for manufacturing a TFT substrate according to another embodiment of the present application. Fig. 9 for Figure 8 Schematic diagram of the effect after the conductive layer is etched in the method for manufacturing a TFT substrate. Figure 8 As shown, when the thickness of the first metal layer 51 is When the thickness of the first metal layer 51 is large, that is, the contact area a between the anode (first metal layer 51) and the etching solution is large, the ratio b / a between the contact area b between the cathode (second metal layer 52) and the etching solution and the contact area a between the anode (first metal layer 51) and the etching solution is small. When b / a is smaller, the corrosion rate of the anode (first metal layer 51) is slower, so it is difficult to form a gap between the first metal layer 51 and the second metal layer 52. The etching solution mainly corrodes the side surface 525 of the second metal layer 52 from the lateral direction. Since the lateral etching rates of the second metal layer 52 at different positions in the vertical direction (from the first metal layer 51 to the third metal layer 53) are relatively close, a larger Taper angle α2 is finally formed (such as Fig. 9 shown).

[0076] After step S200, the method for manufacturing the TFT substrate of the embodiment of the present application may further include:

[0077] S300, see Figure 5 A passivation layer 70 is disposed on a side of the source and drain layer away from the substrate 10 .

[0078] For example, the material of the passivation layer 70 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y )

[0079] Please combine Figure 5The angle α3 (i.e., the Taper angle) between the side of the source electrode 61 and the plane where the substrate 10 is located is 50° to 70°, for example, 50°, 51°, 52°, 53°, 54°, 55°, 56°, 57°, 58°, 59°, 60°, 61°, 62°, 63°, 64°, 65°, 66°, 67°, 68° The angle α4 (i.e., Taper angle) between the side of the drain 62 and the plane where the substrate 10 is located is 50° to 70°, such as 50°, 51°, 52°, 53°, 54°, 55°, 56°, 57°, 58°, 59°, 60°, 61°, 62°, 63°, 64°, 65°, 66°, 67°, 68°, 69°, 70°, etc. Exemplarily, α3 is equal to α4. It can be seen that, compared with the source and drain electrodes with a Taper angle of 90° obtained by the existing TFT substrate manufacturing method, the embodiment of the present application significantly reduces the Taper angle of the source 61 and the drain 62, that is, a certain slope is generated on the sides of the source 61 and the drain 62, so that the passivation layer 70 can be better attached to the source 61 and the drain 62 and is not easy to fall off from the source 61 and the drain 62, thereby effectively protecting the source 61 and the drain 62.

[0080] In summary, the manufacturing method of the TFT substrate provided in the embodiment of the present application sets the standard electrode potential of the first metal layer 51 to be lower than the standard electrode potential of the second metal layer 52. Therefore, during the etching process of the conductive layer 50, a galvanic corrosion effect can be formed between the first metal layer 51 and the second metal layer 52. In addition, the first metal layer 51 acts as an anode and the second metal layer 52 acts as a cathode. Since the thickness of the first metal layer 51 in the embodiment of the present application is In the related art, the thickness of the first metal layer 51 is set to Compared with the technical solution of , the thickness of the first metal layer 51 is greatly reduced, thereby reducing the contact area between the first metal layer 51 and the etching solution, and further increasing the ratio b / a between the contact area b between the cathode and the etching solution and the contact area a between the anode and the etching solution. It is known that when b / a increases, the corrosion rate of the anode, i.e., the first metal layer 51, is accelerated, so a larger gap is formed between the first metal layer 51 and the second metal layer 52, which is beneficial to increase the corroded area of ​​the second metal layer 52 on the edge of the side facing the first metal layer 51, thereby helping to reduce the Taper angle of the source and the drain. When the Taper angle of the etched source 61 and the drain 62 is small, the passivation layer 70 can be better attached to the source 61 and the drain 62, and is not easy to fall off from the source 61 and the drain 62, so the source 61 and the drain 62 can be effectively protected.

[0081] See also Fig.10 and Fig.11 , Fig.10 This is a schematic diagram of the first structure of the TFT substrate provided in the embodiment of the present application. Fig.11 A second structural schematic diagram of a TFT substrate provided in an embodiment of the present application. The embodiment of the present application also provides a TFT substrate 100, which can be manufactured using the above-mentioned method for manufacturing a TFT substrate. The TFT substrate 100 may include a substrate 10, a gate 20, an active layer 40, a source-drain electrode layer, and a passivation layer 70, wherein the gate 20 and the active layer 40 are both arranged between the substrate 10 and the source-drain electrode layer, the passivation layer 70 covers the side of the source-drain electrode layer away from the substrate 10, and the source-drain electrode layer includes a source electrode 61 and a drain electrode 62 arranged at intervals.

[0082] Please combine Figure 4 The source electrode 61 and the drain electrode 62 are both obtained by etching the conductive layer 50. The conductive layer 50 includes a first metal layer 51 and a second metal layer 52 which are stacked. The first metal layer 51 is arranged on a side of the second metal layer 52 away from the substrate 10. The standard electrode potential of the first metal layer 51 is lower than the standard electrode potential of the second metal layer 52, and the thickness of the first metal layer 51 is

[0083] Please combine Fig.10 , the TFT in the TFT substrate 100 may be a bottom-gate TFT, in which case the TFT substrate 100 may further include a gate insulating layer 30, a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a source-drain electrode layer and a passivation layer 70 are sequentially stacked;

[0084] The gate insulating layer 30 covers the gate 20 , the active layer 40 and the gate 20 are arranged correspondingly, the source 61 and the drain 62 are both in contact with the active layer 40 , and the passivation layer 70 covers the source and drain layer and the active layer 40 .

[0085] Please combine Fig.11 , the TFT in the TFT substrate 100 may also be a top-gate TFT. In this case, the TFT substrate 100 may further include a buffer layer 91, a gate insulating layer 92 and an interlayer insulating layer 30. The substrate 10, the buffer layer 91, the active layer 40, the gate insulating layer 92, the gate 20, the interlayer insulating layer 30, the source-drain electrode layer and the passivation layer 70 are sequentially stacked.

[0086] Among them, the gate insulating layer 92 covers the active layer 40, the interlayer insulating layer 30 covers the gate 20, the active layer 40 and the gate 20 are arranged correspondingly, and the gate insulating layer 92 and the interlayer insulating layer 30 are provided with a source 61 contact hole and a drain 62 contact hole. The source 61 contacts the active layer 40 via the source 61 contact hole, and the drain 62 contacts the active layer 40 via the drain 62 contact hole. The passivation layer 70 covers the source and drain layers.

[0087] For example, the material of the first metal layer 51 may be a molybdenum-titanium alloy, molybdenum or a molybdenum-niobium alloy, the material of the second metal layer 52 may be copper, and the thickness of the second metal layer 52 may be

[0088] Please combine Figure 4 The conductive layer 50 may further include a third metal layer 53 , and the third metal layer 53 is disposed on a side of the second metal layer 52 away from the first metal layer 51 .

[0089] For example, the material of the third metal layer 53 may be a molybdenum-titanium alloy, molybdenum or a molybdenum-niobium alloy, and the thickness of the third metal layer 53 may be

[0090] Exemplarily, the angle α3 (ie, Taper angle) between the side of the source 61 and the plane of the substrate 10 is 50° to 70°, and the angle α4 (ie, Taper angle) between the side of the drain 62 and the plane of the substrate 10 is 50° to 70°.

[0091] See also Fig.12 , Fig.12 The present invention also provides a liquid crystal display panel 200, comprising a first substrate 210 and a second substrate 220 arranged opposite to each other, and a liquid crystal layer 230 sandwiched between the first substrate 210 and the second substrate 220, wherein the second substrate 220 may be the TFT substrate 100 in any of the above embodiments or a TFT substrate 100 manufactured by the manufacturing method of the TFT substrate in any of the above embodiments.

[0092] By way of example, the first substrate 210 may be a color filter (CF) substrate.

[0093] See also Fig.13 , Fig.13 The present invention also provides an OLED display panel 300, including a driving substrate 310 and an OLED device 320, wherein the OLED device 320 is disposed on the driving substrate 310, and the OLED device 320 is electrically connected to the driving substrate 310. The driving substrate 310 may be the TFT substrate 100 in any of the above embodiments or a TFT substrate 100 manufactured by the manufacturing method of the TFT substrate in any of the above embodiments.

[0094] For example, the OLED device 320 may include an anode (Anode), a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Tranport Layer), an emission layer (EML, Emissionlayer), an electron transport layer (ETL, Electron Transport Layer) and a cathode (Cathode) which are stacked in sequence.

[0095] The TFT substrate and its manufacturing method, liquid crystal display panel and OLED display panel provided in the embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A TFT substrate, characterized in that: The invention comprises a substrate, a gate, an active layer, a source-drain electrode layer and a passivation layer, wherein the gate and the active layer are both arranged between the substrate and the source-drain electrode layer, the passivation layer covers a side of the source-drain electrode layer away from the substrate, and the source-drain electrode layer comprises a source electrode and a drain electrode arranged at intervals; The source electrode and the drain electrode are both obtained by etching a conductive layer, wherein the conductive layer includes a first metal layer and a second metal layer stacked in layers, wherein the first metal layer is arranged on a side of the second metal layer away from the substrate; the standard electrode potential of the first metal layer is lower than the standard electrode potential of the second metal layer, and the thickness of the first metal layer is The material of the first metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, the material of the second metal layer is copper, and the thickness of the second metal layer is The conductive layer further comprises a third metal layer, and the third metal layer is arranged on a side of the second metal layer away from the first metal layer; The material of the third metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, and the thickness of the third metal layer is A gap is formed between the first metal layer and the second metal layer; The longitudinal etching amount of the portion of the second metal layer corresponding to the gap is smaller than the longitudinal etching amount of the portion of the second metal layer corresponding to the periphery of the gap; The thickness of the edge region of the second metal layer gradually decreases.

2. The TFT substrate according to claim 1, characterized in that: The angle between the side of the source and the plane where the substrate is located is 50° to 70°, and the angle between the side of the drain and the plane where the substrate is located is 50° to 70°.

3. The TFT substrate according to any one of claims 1 to 2, characterized in that: The TFT substrate further includes a gate insulating layer, and the substrate, the gate, the gate insulating layer, the active layer, the source-drain electrode layer and the passivation layer are stacked in sequence; wherein the gate insulating layer covers the gate, the active layer and the gate are arranged correspondingly, the source electrode and the drain electrode are both in contact with the active layer, and the passivation layer covers the source-drain electrode layer and the active layer; or The TFT substrate also includes a gate insulating layer and an interlayer insulating layer, and the substrate, the active layer, the gate insulating layer, the gate, the interlayer insulating layer, the source-drain electrode layer and the passivation layer are stacked in sequence; wherein the gate insulating layer covers the active layer, the interlayer insulating layer covers the gate, the active layer and the gate are arranged correspondingly, the gate insulating layer and the interlayer insulating layer are provided with a source contact hole and a drain contact hole, the source electrode contacts the active layer via the source contact hole, the drain electrode contacts the active layer via the drain contact hole, and the passivation layer covers the source-drain electrode layer.

4. A method for manufacturing a TFT substrate, characterized in that: include: A substrate is provided, and a gate, an active layer and a conductive layer are arranged on the substrate, wherein the gate and the active layer are arranged between the substrate and the conductive layer, and the conductive layer includes a source electrode and a drain electrode arranged at intervals; the conductive layer includes a first metal layer and a second metal layer arranged in a stacked manner, and the first metal layer is arranged on a side of the second metal layer away from the substrate; the standard electrode potential of the first metal layer is lower than the standard electrode potential of the second metal layer, and the thickness of the first metal layer is The material of the first metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy, the material of the second metal layer is copper, and the thickness of the second metal layer is The conductive layer further includes a third metal layer, which is disposed on a side of the second metal layer away from the first metal layer. The material of the third metal layer is molybdenum-titanium alloy, molybdenum or molybdenum-niobium alloy. The thickness of the third metal layer is A gap is formed between the first metal layer and the second metal layer, a longitudinal etching amount of a portion of the second metal layer corresponding to the gap is smaller than a longitudinal etching amount of a portion of the second metal layer corresponding to the periphery of the gap, and a thickness of an edge region of the second metal layer gradually decreases; Etching the conductive layer to obtain a source-drain electrode layer, wherein the source-drain electrode layer includes a source electrode and a drain electrode that are spaced apart; A passivation layer is disposed on a side of the source and drain electrode layer away from the substrate.

5. The method for manufacturing a TFT substrate according to claim 4, characterized in that: The angle between the side of the source and the plane where the substrate is located is 50° to 70°, and the angle between the side of the drain and the plane where the substrate is located is 50° to 70°.

6. A liquid crystal display panel, characterized in that: include: a first substrate; a second substrate, arranged opposite to the first substrate, wherein the second substrate is a TFT substrate according to any one of claims 1 to 3 or a TFT substrate manufactured by the method for manufacturing a TFT substrate according to any one of claims 4 to 5; The liquid crystal layer is sandwiched between the first substrate and the second substrate.

7. An OLED display panel, characterized in that: include: A driving substrate, wherein the driving substrate is a TFT substrate according to any one of claims 1 to 3 or a TFT substrate manufactured by the manufacturing method of a TFT substrate according to any one of claims 4 to 5; The OLED device is disposed on the driving substrate, and the OLED device is electrically connected to the driving substrate.

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