Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the structure comprising: a substrate; a gate structure on the substrate; a source-drain doped layer in the substrate on both sides of the gate structure; an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer; a first dielectric layer on the gate structure and the interlayer dielectric layer; a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; an etching-resistant layer on the first dielectric layer and the source-drain contact plug; a second dielectric layer on the etching-resistant layer; and a forming step of a source-drain cap layer, comprising: etching the second dielectric layer to form a groove exposing the etching-resistant layer, and forming the source-drain cap layer in the groove. Because the etching difficulty of the second dielectric layer is less than that of the etching-resistant layer, the source-drain contact plug at the bottom of the etching-resistant layer is not easy to be mis-etched, the conduction resistance of the source-drain contact plug is not easy to be too large, and the circuit is not easy to be broken, so that the electrical performance and the uniformity of the electrical performance of the semiconductor structure can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened accordingly.

[0003] In order to better adapt to the decrease of feature size, semiconductor processes gradually begin to transition from planar MOSFET to three-dimensional transistors with higher efficiency, such as FinFET. In the FinFET, the gate structure can control the ultra-thin body (fin) from at least two sides, and compared with the planar MOSFET, the gate structure has stronger control ability on the channel, which can well suppress the short channel effect; the gate structure also changes from the original polysilicon gate structure to the metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.

[0004] The semiconductor structure includes a substrate, a gate structure located on the substrate, and source-drain doped layers located in the substrate on both sides of the gate structure, and the semiconductor structure further includes source-drain contact plugs located on the source-drain doped layers, for realizing the connection of the source-drain doped layers with external circuits, and the formation quality of the source-drain contact plugs plays a crucial role in the electrical performance of the semiconductor structure.

[0005] In addition, in order to further improve the integration of the semiconductor structure, the Contact Over Active Gate (COAG) process is introduced. Compared with the traditional gate contact hole plug located above the gate structure in the isolation region, the COAG process can make the gate contact hole plug above the gate structure in the active area (AA), so that the integration of the semiconductor structure is higher. SUMMARY

[0006] The problem solved by the embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the formation quality of the source-drain contact plug and optimize the electrical performance of the semiconductor structure.

[0007] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate; a source-drain doped layer in the substrate on both sides of the gate structure; an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer; a first dielectric layer on the gate structure and the interlayer dielectric layer; a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; an etch-resistant layer on the first dielectric layer and the source-drain contact plug; a second dielectric layer on the etch-resistant layer, the etching difficulty of the second dielectric layer is less than that of the etch-resistant layer; and a source-drain cap layer penetrating the second dielectric layer and contacting the etch-resistant layer.

[0008] The embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate is provided with a gate structure, a source-drain doped layer in the substrate on both sides of the gate structure, an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer, and a first dielectric layer on the gate structure and the interlayer dielectric layer; forming a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; forming an etch-resistant layer on the first dielectric layer and the source-drain contact plug; forming a second dielectric layer on the etch-resistant layer, the etching difficulty of the second dielectric layer is less than that of the etch-resistant layer; etching the second dielectric layer to form a groove exposing the etch-resistant layer; and forming a source-drain cap layer in the groove.

[0009] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0010] In the semiconductor structure provided by the embodiment of the present application, the forming step of the source-drain cap layer comprises: etching the second dielectric layer to form a groove exposing the etch-resistant layer, and forming a source-drain cap layer in the groove. Because the etching difficulty of the second dielectric layer is less than that of the etch-resistant layer, the top of the etch-resistant layer can be used as the etching stop position, and accordingly, the source-drain contact plug at the bottom of the etch-resistant layer is not easy to be etched by mistake, and the thickness of the source-drain contact plug meets the process requirement, so that the conduction resistance of the source-drain contact plug is not easy to be too large, and the source-drain contact plug is less likely to be disconnected, which is beneficial to improve the electrical performance and the uniformity of the electrical performance of the semiconductor structure, and improve the yield of the semiconductor structure meeting the electrical performance. In addition, in the step of etching the second dielectric layer to form a groove exposing the etch-resistant layer, the top of the etch-resistant layer can be used as the etching stop position, so that the topography quality of the groove is high in uniformity, and accordingly, the source-drain cap layer formed in the groove is high in uniformity, which is beneficial to improve the uniformity of the electrical performance of the semiconductor structure.

[0011] The method for forming a semiconductor structure provided by the embodiment of the present application comprises the following steps: providing a substrate, wherein a gate structure, a source-drain doped layer in the substrate on both sides of the gate structure, an interlayer dielectric layer covering the sidewall of the gate structure, and a first dielectric layer on the gate structure and the interlayer dielectric layer are formed on the substrate; forming a source-drain contact plug penetrating through the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; forming an etching-resistant layer on the first dielectric layer and the source-drain contact plug, and forming a second dielectric layer on the etching-resistant layer, wherein the etching difficulty of the second dielectric layer is lower than that of the etching-resistant layer; thus, in the step of etching the second dielectric layer to form a groove exposing the etching-resistant layer, the top of the etching-resistant layer can be used as the etching stop position, and the source-drain contact plug at the bottom of the etching-resistant layer is not easily etched by mistake, and the thickness of the source-drain contact plug meets the process requirement, so that the on-resistance of the source-drain contact plug is not easily too large, and the circuit is not easily broken, which is beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structure and improving the yield of the semiconductor structure meeting the electrical performance of the semiconductor structure. In addition, in the step of etching the second dielectric layer to form a groove exposing the etching-resistant layer, the top of the etching-resistant layer can be used as the etching stop position, so that the topography quality of the groove is high in uniformity, and the source-drain cap layer formed in the groove is high in uniformity, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1 to 8 FIG. 1 is a structure schematic diagram of a semiconductor structure corresponding to each step in a method for forming a semiconductor structure;

[0013] Figure 9 FIG. 2 is a structure schematic diagram of an embodiment of the semiconductor structure of the present application;

[0014] Figures 10 to 21 FIG. 3 is a structure schematic diagram of each step in an embodiment of the method for forming a semiconductor structure of the present application. DETAILED DESCRIPTION

[0015] As known from the background, the currently formed semiconductor structure still has the problem of poor performance. Now, the reasons for the poor performance of the semiconductor structure are analyzed in combination with a method for forming a semiconductor structure.

[0016] REFERENCE Figures 1 to 8 FIG. 1 shows a structure schematic diagram of a semiconductor structure corresponding to each step in a method for forming a semiconductor structure.

[0017] As Figure 1As shown, a substrate is provided, the substrate including a substrate 1, a fin 2 located on the substrate 1, a gate structure 3 spanning the fin 2, a gate capping layer 4 located on top of the gate structure 3, and source / drain doped layers 5 located in the fins 2 on both sides of the gate structure 3; an interlayer dielectric layer 6 is formed covering the sidewalls of the gate structure 3 and the source / drain doped layers 5, and exposing the top of the gate capping layer 4; a first dielectric layer 8 is formed on the interlayer dielectric layer 6; the first dielectric layer 8 and the interlayer dielectric layer 6 are etched to form a first opening (not shown in the figure); after forming the first opening, a portion of the thickness of the first dielectric layer 8 on the side of the first opening is etched to form a groove (not shown in the figure) exposing the first opening; a contact metal material layer 7 is formed in the groove and the first opening.

[0018] like Figure 2 As shown, a wet etching process is used to remove the contact metal material layer 7 in the groove 10 to form the source / drain contact plug 9 and the groove 10 located on the source / drain contact plug 9.

[0019] like Figure 3 As shown, a source / drain cap layer 11 is formed in the groove 10.

[0020] like Figure 4 As shown, a second dielectric layer 12 is formed covering the source / drain cap layer 11 and the first dielectric layer 8.

[0021] like Figure 5 As shown, the second dielectric layer 12, the first dielectric layer 8, and the gate cap layer 4 are etched to form a second opening 13 that exposes the gate structure 3.

[0022] like Figure 6 As shown, a gate plug 14 is formed in the second opening 13.

[0023] like Figure 7 As shown, the second dielectric layer 12 and the source / drain cap layer 11 are etched to form a third opening 15 that exposes the source / drain contact plug 9.

[0024] like Figure 8 As shown, a source-drain interconnect structure 16 is formed in the third opening 15.

[0025] During the wet etching process to etch the contact metal material layer 7 to form the source / drain contact plugs 9 and the groove 10, it is difficult to maintain a consistent etching rate in different areas. This can easily lead to the contact metal material layer 7 in the first opening also being partially etched, resulting in hole defects (such as...). Figure 2As shown in FIG. 1C, the thickness of the source-drain contact plug 9 in some areas does not reach the preset thickness, and accordingly, the on-resistance of the source-drain contact plug 9 is too large when the semiconductor structure is in operation, and in the extreme case, the contact metal material layer 7 in some areas of the first opening is even removed (as shown in FIG. 1D), which causes the semiconductor structure to have poor electrical performance. Figure 2 As shown in FIG. 1E, the thickness of the source-drain contact plug 9 in some areas does not reach the preset thickness, and accordingly, the on-resistance of the source-drain contact plug 9 is too large when the semiconductor structure is in operation, and in the extreme case, the contact metal material layer 7 in some areas of the first opening is even removed (as shown in FIG. 1F), which causes the semiconductor structure to have poor electrical performance.

[0026] To solve the technical problem, the semiconductor structure comprises: a substrate; a gate structure located on the substrate; a source-drain doped layer located in the substrate on both sides of the gate structure; an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer; a first dielectric layer located on the gate structure and the interlayer dielectric layer; a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; an etching-resistant layer located on the first dielectric layer and the source-drain contact plug; a second dielectric layer located on the etching-resistant layer, the etching difficulty of the second dielectric layer being smaller than that of the etching-resistant layer; and a source-drain cap layer penetrating the second dielectric layer and in contact with the etching-resistant layer.

[0027] In the semiconductor structure provided by the embodiment of the present application, the forming step of the source-drain cap layer comprises: etching the second dielectric layer to form a groove exposing the etching-resistant layer, and forming the source-drain cap layer in the groove. Because the etching difficulty of the second dielectric layer is smaller than that of the etching-resistant layer, the top of the etching-resistant layer can be used as the etching stop position, and accordingly, the source-drain contact plug at the bottom of the etching-resistant layer is not easy to be etched by mistake, and the thickness of the source-drain contact plug meets the process requirement, so that the on-resistance of the source-drain contact plug is not easy to be too large when the semiconductor structure is in operation, and a short circuit is not easy to occur, which is beneficial to improve the electrical performance and the uniformity of the electrical performance of the semiconductor structure, and improve the yield of the semiconductor structure meeting the electrical performance. In addition, in the step of etching the second dielectric layer to form the groove exposing the etching-resistant layer, the top of the etching-resistant layer can be used as the etching stop position, so that the topography quality of the groove is high in uniformity, and accordingly, the source-drain cap layer formed in the groove is high in uniformity, which is beneficial to improve the uniformity of the electrical performance of the semiconductor structure.

[0028] Figure 9 FIG. 1 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application.

[0029] The semiconductor structure comprises: a substrate 100; a gate structure 101 located on the substrate 100; a source-drain doped layer 102 located in the substrate 100 on both sides of the gate structure 101; an interlayer dielectric layer 105 covering the sidewall of the gate structure 101 and the source-drain doped layer 102; a first dielectric layer 106 located on the gate structure 101 and the interlayer dielectric layer 105; a source-drain contact plug 107 penetrating the first dielectric layer 106 and the interlayer dielectric layer 105 and connected with the source-drain doped layer 102; an etch-resistant layer 110 located on the first dielectric layer 106 and the source-drain contact plug 107; a second dielectric layer 111 located on the etch-resistant layer 110, the etch-resistant layer 110 has a greater etching difficulty than the second dielectric layer 111; and a source-drain cap layer 117 penetrating the second dielectric layer 111 and in contact with the etch-resistant layer 110.

[0030] In the semiconductor structure provided by the embodiment of the present application, the forming step of the source-drain cap layer 117 comprises: etching the second dielectric layer 111 to form a groove exposing the etch-resistant layer 110, and forming the source-drain cap layer 117 in the groove. Because the etching difficulty of the etch-resistant layer 110 is greater than that of the second dielectric layer 111, the top of the etch-resistant layer 110 can be used as the etching stop position, and accordingly, the source-drain contact plug 107 at the bottom of the etch-resistant layer 110 is not easily etched by mistake, and the thickness of the source-drain contact plug 107 meets the process requirement, so that the on-resistance of the source-drain contact plug 107 is not easily too large, and the open circuit is less likely to occur when the semiconductor structure works, which is beneficial to improve the electrical performance and the uniformity of the electrical performance of the semiconductor structure, and improve the yield of the semiconductor structure meeting the electrical performance.

[0031] In the embodiment, the semiconductor structure is taken as an example of a fin field effect transistor (FinFET), and the substrate 100 comprises: a substrate 103 and a fin 104 located on the substrate 103. In other embodiments, the substrate can also be a planar substrate, and accordingly, the semiconductor structure can also be a planar transistor (MOSFET). In some other embodiments, the substrate further comprises a plurality of suspended channel layers located on the fin, and the channel layers are arranged in the normal direction of the substrate surface, and accordingly, the semiconductor structure is a gate-all-around transistor (GAA).

[0032] In this embodiment, the substrate 103 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0033] In this embodiment, the material of the fin 104 is the same as the material of the substrate 103, and the material of the fin 104 accordingly includes silicon.

[0034] The substrate further includes an isolation layer (not shown in the figure) on the substrate 103 on the side of the fin 104, and the isolation layer covers part of the sidewall of the fin 104. The isolation layer is a shallow trench isolation (STI) structure.

[0035] The isolation layer is used to electrically isolate the substrate 103 and the gate structure 101.

[0036] In this embodiment, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used dielectric material in the process, has a relatively low cost, and has a high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the isolation layer. In addition, the dielectric constant of silicon oxide is relatively small, which is also conducive to improving the role of the subsequent isolation layer in isolating adjacent devices.

[0037] The gate structure 101 is located on the isolation layer, straddles the fin 104, and covers part of the top wall and part of the sidewall of the fin 104.

[0038] The gate structure 101 is used to turn on or off the channel when the semiconductor structure is working.

[0039] It should be noted that the lateral direction is perpendicular to the extension direction of the gate structure 101.

[0040] The semiconductor structure further includes a gate cap layer 201 located on the top of the gate structure 101.

[0041] The gate cap layer 201 is used to protect the top of the gate structure 101 from being etched by mistake.

[0042] In this embodiment, the material of the gate cap layer 201 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron carbon silicon nitride. In this embodiment, the material of the gate cap layer 201 includes silicon nitride.

[0043] The interlayer dielectric layer 105 is used to electrically isolate the source-drain contact plug 107.

[0044] In this embodiment, the material of the ILD layer 105 is insulating material. Specifically, the material of the ILD layer 105 includes silicon oxide.

[0045] When the semiconductor structure is in operation, the S / D doping layer 102 is used to provide stress for the channel, and to increase the migration rate of the carriers in the channel.

[0046] When the semiconductor structure is used to form a PMOS, the material of the S / D doping layer 102 is P-type ion doped silicon germanium. Specifically, the P-type ion includes boron, gallium or indium. When the semiconductor structure is used to form an NMOS, the material of the S / D doping layer 102 is N-type ion doped silicon carbide or silicon phosphide. Specifically, the N-type ion includes phosphorus, arsenic or antimony.

[0047] The semiconductor structure further includes a sidewall layer 202 located on the sidewall of the gate structure 101. The sidewall layer 202 is used to electrically isolate the S / D doping layer 102 and the gate structure 101, and to reduce the parasitic capacitance between the S / D doping layer 102 and the gate structure 101.

[0048] In this embodiment, the sidewall layer 202 is a stacked structure. Specifically, the sidewall layer 202 includes a first sidewall 2021 and a second sidewall 2022 located farther away from the gate structure 101 than the first sidewall 2021. The material of the first sidewall 2021 includes silicon oxide, and the material of the second sidewall 2022 includes silicon nitride. In other embodiments, the sidewall layer can also be a single-layer structure.

[0049] The first dielectric layer 106 is used to prepare for the formation of the S / D contact plug 107.

[0050] In this embodiment, the material of the first dielectric layer 106 includes silicon oxide.

[0051] The S / D contact plug 107 is used to connect the S / D doping layer 102 and the S / D interconnect structure 122.

[0052] Specifically, the material of the S / D contact plug 107 includes one or more of Co, W and Ru. In this embodiment, the material of the S / D contact plug 107 includes Co. Co has a low resistivity, which is beneficial to improve the signal delay of the back-end RC, to increase the processing speed of the semiconductor structure, and to reduce the resistance of the S / D contact plug 107, and accordingly to reduce the power consumption.

[0053] It should be noted that, since the etching-resistant layer 110 can protect the source-drain contact plug 107 from being etched by mistake, the uniformity of the source-drain contact plug 107 is higher, and accordingly, the uniformity of the resistance (Rs) of the source-drain contact plug 107 is higher when the semiconductor structure is working, which is beneficial to improve the uniformity of the electrical performance of the semiconductor structure.

[0054] The semiconductor structure further comprises a metal silicide layer 109 between the source-drain doped layer 102 and the source-drain contact plug 107, for reducing the contact resistance between the source-drain doped layer 102 and the source-drain contact plug 107.

[0055] In this embodiment, the material of the metal silicide layer 109 comprises one or more of cobalt silicide, nickel silicide and titanium silicide.

[0056] It should be noted that the semiconductor structure further comprises a barrier layer 204 between the source-drain contact plug 107 and the sidewall layer 202, and between the source-drain doped layer 102 and the source-drain contact plug 107. The barrier layer 204 is used to reduce the probability of ion diffusion in the source-drain contact plug 107 to the source-drain doped layer 102 and the gate structure 101. The material of the barrier layer 204 comprises TaN.

[0057] In this embodiment, the etching difficulty of the etching-resistant layer 110 is greater than the etching difficulty of the second dielectric layer 111.

[0058] In this embodiment, the material of the etching-resistant layer 110 comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride. In this embodiment, the material of the etching-resistant layer 110 comprises silicon nitride.

[0059] It should be noted that the etching resistant layer 110 is not too thick or too thin. If the etching resistant layer 110 is too thick, it needs to spend too much process time to form the etching resistant layer 110, which leads to low efficiency of forming the etching resistant layer 110, and also leads to the thickness of the whole semiconductor structure being too large, and the thickness of the gate plug 119 connected with the gate structure 101 and the source / drain interconnection structure 122 connected with the source / drain contact plug 107 being too large. The gate plug 119 and the source / drain interconnection structure 122 are prone to have void defects and seam defects, which leads to large on-resistance of the gate plug 119 and the source / drain interconnection structure 122. If the etching resistant layer 110 is too thin, in the step of etching the second dielectric layer 111 to form a groove exposing the etching resistant layer 110, the etching resistant layer 110 cannot well play the role of etching stop, and the etching resistant layer 110 is prone to be etched through, so that the source / drain contact plug 107 below the etching resistant layer 110 is prone to be etched partially in thickness. In the extreme case, even part of the area of the source / drain contact plug 107 is removed. Correspondingly, in the working of the semiconductor structure, a short circuit occurs, which leads to poor electrical performance of the semiconductor structure. In the embodiment, the thickness of the etching resistant layer 110 is 50-500 nm.

[0060] In the embodiment, the second dielectric layer 111 is used for electrically isolating adjacent devices. The material of the second dielectric layer 111 is an insulating material.

[0061] Specifically, the material of the second dielectric layer 111 includes silicon oxide. Silicon oxide is a commonly used dielectric material in the process, and has low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the second dielectric layer 111.

[0062] In the forming process of the semiconductor structure, the source / drain cap layer 117 is used for protecting the top of the source / drain contact plug 107 from being etched by mistake.

[0063] Specifically, the material of the source / drain cap layer 117 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride. In the embodiment, the material of the source / drain cap layer 117 includes silicon nitride.

[0064] The semiconductor structure further includes a third dielectric layer 118 located on the source / drain cap layer 117 and the second dielectric layer 111.

[0065] The third dielectric layer 118 is used for electrically isolating adjacent devices. The material of the third dielectric layer 118 is an insulating material.

[0066] Specifically, the material of the third dielectric layer 118 includes silicon oxide.

[0067] The gate plug 119 penetrates the third dielectric layer 118, the second dielectric layer 111, the etching-resistant layer 110, and the first dielectric layer 106, and is connected with the gate structure 101.

[0068] The gate plug 119 is used to connect the gate structure 101 with the metal in the back-end.

[0069] The gate plug 119 is used to connect the gate structure 101 with the metal in the back-end. The gate plug 119 is located in the active area (AA), and accordingly, the gate plug 119 is a contact over active gate (COAG) plug, which can improve the integration of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0070] In the embodiment, the material of the gate plug 119 includes one or more of Co, Ru, and W. In the embodiment, the material of the gate plug 119 includes W. The resistivity of W is relatively low, which is conducive to improving the signal delay of the back-end RC, improving the processing speed of the semiconductor structure, and accordingly reducing the power consumption.

[0071] It should be noted that in the embodiment, the gate plug 119 also penetrates the gate cap layer 201.

[0072] It should be noted that in other embodiments, the semiconductor structure further includes a first linear oxide layer (not shown in the figure) located on the sidewall of the gate plug.

[0073] The first linear oxide layer is used to electrically isolate the gate plug from the remaining film layers, and also makes the metal ions in the gate plug less likely to diffuse, reducing the impact on the performance of the back-end circuit. The material of the first linear oxide layer includes silicon oxide.

[0074] The semiconductor structure further includes a source-drain interconnection structure 122 penetrating the third dielectric layer 118, the source-drain cap layer 117, and the etching-resistant layer 110, and connected with the source-drain contact plug 107.

[0075] The source-drain interconnection structure 122 is used to connect the source-drain contact plug 107 with the metal in the back-end.

[0076] Specifically, the material of the source-drain interconnection structure 122 includes one or more of Cu, Co, W, and Ru. In other embodiments, the material of the source-drain interconnection structure 122 includes W. The resistivity of W is relatively low, which is conducive to improving the signal delay of the back-end RC, improving the processing speed of the chip, and accordingly reducing the power consumption.

[0077] In addition, the etching-resistant layer 110 is located on top of the source-drain contact plug 107, and the etching-resistant layer 110 protects the top of the source-drain contact plug 107 from being etched by mistake, so that the source-drain contact plug 107 has higher uniformity, and the contact resistance (Rc) between the source-drain interconnection structure 122 and the source-drain contact plug 107 has higher uniformity, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure.

[0078] In other embodiments, the semiconductor structure further includes a second linear oxide layer located on the sidewall of the source-drain interconnection structure. The second linear oxide layer is used to prevent metal ions in the source-drain interconnection structure from diffusing, thereby reducing the impact on the performance of the back-end circuit. The material of the second linear oxide layer includes silicon oxide.

[0079] Figures 10 to 21 is a structure diagram corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present application.

[0080] Reference Figure 10 A substrate 100 is provided, and the substrate 100 is formed with a gate structure 101, source-drain doped layers 102 in the substrate 100 on both sides of the gate structure 101, an interlayer dielectric layer 105 covering the sidewall of the gate structure 101 and the source-drain doped layers 102, and a first dielectric layer 106 located on the gate structure 101 and the interlayer dielectric layer 105.

[0081] The substrate 100 provides a process basis for subsequent formation of a semiconductor structure.

[0082] In this embodiment, the semiconductor structure to be formed subsequently is taken as an example of a fin field effect transistor (FinFET), and in the step of providing the substrate 100, the substrate 100 includes a substrate 103 and a fin portion 104 located on the substrate 103. In other embodiments, the substrate can also be a planar substrate, and accordingly, the semiconductor structure can also be a planar transistor (MOSFET). In still other embodiments, the substrate further includes a plurality of suspended channel layers located on the fin portion, and the channel layers are arranged at intervals in the normal direction of the surface of the substrate. Accordingly, the semiconductor structure is a gate-all-around transistor (GAA).

[0083] In this embodiment, the substrate 103 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0084] In this embodiment, the material of the fin portion 104 is the same as that of the substrate 103, and accordingly, the material of the fin portion 104 includes silicon.

[0085] The substrate further includes an isolation layer (not shown in the figure) on the substrate 103 at the sides of the fin 104, and the isolation layer covers part of the sidewall of the fin 104. The isolation layer is a shallow trench isolation (STI) structure.

[0086] The isolation layer is used to electrically isolate the substrate 103 and the gate structure 101. In this embodiment, the material of the isolation layer includes silicon oxide.

[0087] The gate structure 101 is located on the isolation layer, across the fin 104 and covers part of the top wall and part of the sidewall of the fin 104.

[0088] The gate structure 101 is used to turn on or off the channel when the semiconductor structure is working.

[0089] It should be noted that the lateral direction is perpendicular to the extension direction of the gate structure 101.

[0090] In the step of providing the substrate 100, a gate cap layer 201 is further formed on the top of the gate structure 101.

[0091] In the subsequent formation process of the semiconductor structure, the gate cap layer 201 is used to protect the top of the gate structure 101 from being etched by mistake.

[0092] In this embodiment, the material of the gate cap layer 201 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride. In this embodiment, the material of the gate cap layer 201 includes silicon nitride.

[0093] The interlayer dielectric layer 105 is used to electrically isolate the source-drain contact plug formed subsequently.

[0094] In this embodiment, the material of the interlayer dielectric layer 105 is an insulating material. Specifically, the material of the interlayer dielectric layer 105 includes silicon oxide.

[0095] In the working of the semiconductor structure, the source-drain doped layer 102 is used to provide stress for the channel to improve the migration rate of the carriers in the channel.

[0096] When the semiconductor structure is used to form a PMOS, the material of the source-drain doped layer 102 is silicon germanium doped with P-type ions. Specifically, the P-type ions include boron, gallium or indium. When the semiconductor structure is used to form an NMOS, the material of the source-drain doped layer 102 is silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include phosphorus, arsenic or antimony.

[0097] In this embodiment, the sidewall of the gate structure 101 is further formed with a sidewall spacer 202. The sidewall spacer 202 is used to electrically isolate the source-drain doped layer 102 and the gate structure 101, and to reduce the parasitic capacitance between the source-drain doped layer 102 and the gate structure 101.

[0098] In this embodiment, the sidewall spacer 202 is a stacked structure. Specifically, the sidewall spacer 202 includes a first sidewall 2021 and a second sidewall 2022 which is farther away from the gate structure 101 than the first sidewall 2021. The material of the first sidewall 2021 includes silicon oxide, and the material of the second sidewall 2022 includes silicon nitride. In other embodiments, the sidewall spacer can also be a single-layer structure.

[0099] The first dielectric layer 106 is prepared for the subsequent formation of a source-drain contact plug. In this embodiment, the material of the first dielectric layer 106 includes silicon oxide.

[0100] Specifically, the first dielectric layer 106 is formed on the gate cap layer 201 and the interlayer dielectric layer 105.

[0101] It should be noted that the thickness of the first dielectric layer 106 and the interlayer dielectric layer 105 determines the thickness of the source-drain contact plug which is formed later to connect the source-drain doped layer 102.

[0102] Compared with the case of etching the first dielectric layer and the interlayer dielectric layer to form a first opening, etching the first dielectric layer on the side of the first opening by a partial thickness to form a groove exposing the first opening, forming a contact metal material layer in the groove and the first opening, and removing the metal material layer in the groove, leaving the metal material layer as a source-drain contact plug, the thickness of the first dielectric layer 106 in this embodiment is relatively thin, and the formation efficiency of the first dielectric layer 106 is relatively high.

[0103] Reference Figure 11 The source-drain contact plug 107 is formed through the first dielectric layer 106 and the interlayer dielectric layer 105 and connected to the source-drain doped layer 102.

[0104] The source-drain contact plug 107 is used to connect the source-drain doped layer 102 to the subsequently formed source-drain interconnection structure. In addition, the source-drain contact plug 107 and the first dielectric layer 106 provide a process platform for the subsequent formation of an etching-resistant layer.

[0105] In this embodiment, the top surface of the source-drain contact plug 107 is flush with the top surface of the first dielectric layer 106.

[0106] Specifically, the material of the source-drain contact plug 107 includes one or more of Co, W and Ru. In this embodiment, the material of the source-drain contact plug 107 includes Co. Co has a low resistivity, which is beneficial to improve the signal delay of the back-end RC, improve the processing speed of the semiconductor structure, and also beneficial to reduce the resistance of the source-drain contact plug 107, and accordingly reduce the power consumption.

[0107] The step of forming the source-drain contact plug 107 penetrating through the first dielectric layer 106 and the interlayer dielectric layer 105 and connected with the source-drain doped layer 102 includes: forming a source-drain plug mask material layer (not shown in the figure) on the first dielectric layer 106, the source-drain plug mask material layer including an organic material layer, an anti-reflective coating layer on the organic material layer, and a first photoresist material layer on the anti-reflective coating layer; providing a mask (Mask); exposing the first photoresist material layer using the mask to form a first photoresist layer with a first photoresist groove; etching the anti-reflective coating layer and the organic material layer exposed by the first photoresist groove, with the top of the first dielectric layer 106 as the etching stop position, and the remaining first photoresist layer, anti-reflective coating layer and organic material layer as the source-drain plug mask layer; etching the first dielectric layer 106 and the interlayer dielectric layer with the source-drain plug mask layer as a mask to form a source-drain opening (not shown in the figure) penetrating through the first dielectric layer 106 and the interlayer dielectric layer and exposing the top of the source-drain doped layer 102; and forming the source-drain contact plug 107 in the source-drain opening.

[0108] Specifically, the step of forming the source-drain contact plug 107 in the source-drain opening includes: forming a metal material layer (not shown in the figure) in the source-drain opening and on the first dielectric layer 106; removing the metal material layer above the first dielectric layer 106, and the remaining metal material layer in the source-drain opening as the source-drain contact plug 107.

[0109] In this embodiment, the chemical mechanical polishing process (CMP) is used to remove the metal material layer above the first dielectric layer 106.

[0110] In this embodiment, the first dielectric layer 106 and the interlayer dielectric layer 105 are etched using a dry etching process with the source-drain plug mask layer as a mask to form the source-drain opening. The dry etching process has anisotropic etching characteristics and good etching profile control, which is beneficial to make the morphology of the source-drain opening meet the process requirements, and in the step of forming the source-drain opening using the dry etching process, the top of the source-drain doped layer 102 can be used as the etching stop position, so that the process control is stronger.

[0111] In the embodiment, the metal material layer is formed by an electrical chemical plating (ECP) process. The ECP process has the advantages of simple operation, fast deposition speed, and low cost.

[0112] It should be noted that, compared with the case of etching the first dielectric layer and the interlayer dielectric layer to form a first opening, etching a partial thickness of the first dielectric layer on a side of the first opening to form a groove exposing the first opening, forming a contact metal material layer in the groove and the first opening, and removing the metal material layer in the groove, leaving the metal material layer as a source-drain contact plug, in the embodiment, the step of forming the source-drain contact plug 107 includes: forming a source-drain opening (not shown in the figure) penetrating through the first dielectric layer 106 and the interlayer dielectric layer 105 and exposing a top of the source-drain doped layer 102; and forming the source-drain contact plug 107 in the source-drain opening, so that the source-drain contact plug has high uniformity, which is conducive to simplifying the forming step of the source-drain contact plug.

[0113] It should be noted that, after forming the source-drain opening, before forming the source-drain contact plug 107 in the source-drain opening, the method further includes: forming a metal silicide layer 109 on the top of the source-drain doped layer 102.

[0114] The metal silicide layer 109 is located between the source-drain doped layer 102 and the source-drain contact plug 107, and is used to reduce the contact resistance between the source-drain doped layer 102 and the source-drain contact plug 107.

[0115] In the embodiment, the material of the metal silicide layer 109 includes one or more of a cobalt-silicon compound, a nickel-silicon compound, and a titanium-silicon compound.

[0116] In the embodiment, the metal silicide layer 109 is formed by a self-aligned silicide (salicide) process.

[0117] The method further includes: after forming the metal silicide layer 109, forming a barrier layer 204 on a bottom surface and a sidewall of the source-drain opening. The barrier layer 204 is used to reduce the probability of ion diffusion in the subsequently formed source-drain contact plug to the source-drain doped layer 102 and the gate structure 101. The material of the barrier layer 204 includes TaN.

[0118] Reference Figure 12 An etching-resistant layer 110 is formed on the first dielectric layer 106 and the source-drain contact plug 107.

[0119] In the embodiment of the present application, the etch-resistant layer 110 is formed on the first dielectric layer 106 and the source-drain contact plug 107, and then the second dielectric layer is formed on the etch-resistant layer 110, the etching difficulty of the second dielectric layer is less than that of the etch-resistant layer 110, so that in the step of etching the second dielectric layer to form a groove exposing the etch-resistant layer 110, the top of the etch-resistant layer 110 can be used as the etching stop position, and correspondingly, the source-drain contact plug 107 at the bottom of the etch-resistant layer 110 is not easy to be etched by mistake, and the thickness of the source-drain contact plug 107 meets the process requirement, so that when the semiconductor structure works, the on-resistance of the source-drain contact plug 107 is not easy to be too large, and the open circuit is less likely to occur, which is beneficial to improve the electrical performance and uniformity of the electrical performance of the semiconductor structure, and improve the yield of the semiconductor structure meeting the electrical performance of the semiconductor.

[0120] Specifically, the material of the etch-resistant layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron silicon carbon nitride. In the embodiment, the material of the etch-resistant layer 110 includes silicon nitride.

[0121] In the embodiment, the etch-resistant layer 110 is formed by an atomic layer deposition (ALD) process. By the atomic layer deposition process, the etch-resistant layer 110 is formed on the surface of the first dielectric layer 106 and the source-drain contact plug 107 in the form of an atomic layer, so as to improve the uniformity of the deposition rate, the thickness uniformity of the etch-resistant layer 110, and the structure uniformity in the etch-resistant layer 110. In addition, the process temperature of the atomic layer deposition process is generally low, so as to reduce the thermal budget and reduce the probability of electrical performance deviation of the semiconductor structure. In other embodiments, the etch-resistant layer can also be formed by a chemical vapor deposition process.

[0122] In the step of forming the etching-resistive layer 110 on the first dielectric layer 106 and the source-drain contact plug 107, the etching-resistive layer 110 should not be too thick or too thin. If the etching-resistive layer 110 is too thick, it will take too much process time to form the etching-resistive layer 110, resulting in low efficiency of forming the etching-resistive layer 110, and also resulting in too large thickness of the whole semiconductor structure, and accordingly, too large thickness of the gate plug connected with the gate structure 101 and the source-drain interconnection structure connected with the source-drain contact plug 107, and the gate plug and the source-drain interconnection structure are prone to have void defects and seam defects, resulting in large on-resistance of the gate plug and the source-drain interconnection structure. If the etching-resistive layer 110 is too thin, in the step of forming the second dielectric layer on the etching-resistive layer 110, etching the second dielectric layer to form a groove exposing the etching-resistive layer 110, the etching-resistive layer 110 cannot well play the role of etching stop, and the etching-resistive layer 110 is prone to be etched through, so that the source-drain contact plug 107 below the etching-resistive layer 110 is prone to be etched partially, and in the extreme case, even some regions of the source-drain contact plug 107 are removed, and accordingly, in the working of the semiconductor structure, the source-drain contact plug 107 appears open circuit, resulting in poor electrical performance of the semiconductor structure. In the embodiment, the thickness of the etching-resistive layer 110 is 50 nm to 500 nm.

[0123] With reference to the foregoing Figure 12 The second dielectric layer 111 is formed on the etching-resistive layer 110, and the etching-resistive layer 110 is more difficult to be etched than the second dielectric layer 111.

[0124] The second dielectric layer 111 is prepared for subsequent formation of a groove exposing the etching-resistive layer 110. The etching-resistive layer 110 is more difficult to be etched than the second dielectric layer 111, so that in the process of forming the groove, the top of the etching-resistive layer 110 can be taken as the etching stop position, and the source-drain contact plug 107 at the bottom of the etching-resistive layer 110 is not prone to be damaged.

[0125] In the embodiment, the material of the second dielectric layer 111 is insulating material. Specifically, the material of the second dielectric layer 111 includes silicon oxide. Silicon oxide is a commonly used dielectric material in the process, and has low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the second dielectric layer 111.

[0126] In the embodiment, the second dielectric layer 111 is formed by a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capacity, which is beneficial to reduce the probability of forming defects such as holes in the second dielectric layer 111, and correspondingly beneficial to improve the film forming quality of the second dielectric layer 111.

[0127] Referring to Figures 13 to 15 , the second dielectric layer 111 is etched to form a groove 112 exposing the etch-resistant layer 110 (as shown in Figure 15 ).

[0128] Because the etching difficulty of the second dielectric layer 111 is less than that of the etch-resistant layer 110, the top of the etch-resistant layer 110 can be used as the etching stop position, and correspondingly, the source-drain contact plug 107 at the bottom of the etch-resistant layer 110 is not easy to be mis-etched. The thickness of the source-drain contact plug 107 meets the process requirements, so that the conduction resistance of the source-drain contact plug 107 is not easy to be too large, and the open circuit is not easy to occur when the semiconductor structure is working. This is beneficial to improve the electrical performance and uniformity of the electrical performance of the semiconductor structure, and to improve the yield of the semiconductor structure meeting the electrical performance of the semiconductor. In addition, in the step of etching the second dielectric layer 111 to form the groove 112 exposing the etch-resistant layer 110, the top of the etch-resistant layer 110 can be used as the etching stop position, so that the topography quality of the groove 112 is high in uniformity, and correspondingly, the source-drain cap layer formed in the groove 112 subsequently has high uniformity, which is beneficial to improve the uniformity of the electrical performance of the semiconductor structure.

[0129] The groove 112 provides process space for the subsequent formation of the source-drain cap layer.

[0130] Specifically, the step of etching the second dielectric layer 111 to form the groove 112 exposing the etch-resistant layer 110 includes:

[0131] As shown in Figure 13 and Figure 14 , a cap mask layer 203 is formed on the second dielectric layer 111.

[0132] The step of forming the cap mask layer 203 includes: forming a second mask material layer (not shown in the figure) on the second dielectric layer 111, the second mask material layer including an organic material layer 115, an anti-reflective coating 114 on the organic material layer 115, and a second photoresist material layer (not shown in the figure) on the anti-reflective coating 114; exposing the second photoresist material layer using the mask, to form a second photoresist layer 113 having a second photoresist groove 116. The top of the etch-stop layer 110 is taken as the etching stop position, and the anti-reflective coating 114 and the organic material layer 115 exposed by the second photoresist groove 116 are etched, and the remaining second photoresist layer 113, anti-reflective coating 114, and organic material layer 115 are taken as the cap mask layer 203.

[0133] In the embodiment, the material of the organic material layer 115 includes an organic material, for example, one or more of an ODL (organic dielectric layer) material, a DUO (Deep UV Light Absorbing Oxide) material, and an APF (Advanced Patterning Film) material.

[0134] The material of the anti-reflective coating 114 includes a DARC (dielectric anti-reflective coating) material or a BARC (bottom anti-reflective coating) material.

[0135] In the embodiment, the first photoresist material layer is exposed using the mask to form the first photoresist layer, and the second photoresist material layer is exposed using the mask to form the second photoresist layer 113. In the step of forming the source-drain contact plug 107 and in the step of forming the groove 112 exposing the etch-stop layer 110, the same mask is used, and the same mask is used, which is beneficial to reduce the process cost of forming the semiconductor structure.

[0136] It should be noted that in the process of exposing the second photoresist material layer using the mask, the exposure parameters are adjusted so that the lateral size of the second photoresist groove 116 is greater than the lateral size of the first photoresist groove.

[0137] The lateral dimension of the second photoresist groove 116 is larger than that of the first photoresist groove. Correspondingly, during the etching of the anti-reflective coating 114 and organic material layer 115 exposed by the second photoresist groove 116 to form the cap mask layer 203, the lateral dimension of the second dielectric layer 111 exposed by the cap mask layer 203 is larger than that of the source / drain contact plug 107. Therefore, during the subsequent etching of the second dielectric layer 111 using the cap mask layer 203 as a mask, the lateral dimension of the groove 112 formed is larger than that of the source / drain contact plug 107. In other words, the groove 112 can completely expose the source / drain contact plug 107.

[0138] In this embodiment, the antireflective coating 114 and the organic material layer 115 are etched using a dry etching process with the second photoresist layer 113 as a mask. The remaining second photoresist layer 113, antireflective coating 114, and organic material layer 115 serve as a capping mask layer 203 (e.g., ...). Figure 14 (As shown). Dry etching technology has anisotropic etching characteristics, good control over the etching profile, and can obtain fairly accurate pattern transformation. This is beneficial for transferring the second photoresist groove 116 in the second photoresist layer 113 to the cap mask layer 203, so that the morphology of the cap mask layer 203 meets the process requirements. Moreover, by using dry etching technology and changing the etching gas, the anti-reflective coating 114 and the organic material layer 115 can be etched in the same etching equipment, simplifying the process steps.

[0139] It should be noted that in this embodiment, during the step of forming the cap mask layer 203, the second photoresist layer 113 still has a partial thickness. In other embodiments, during the step of forming the cap mask layer, the second photoresist layer can also be completely removed.

[0140] like Figure 15 As shown, the second dielectric layer 111 is etched using the cap mask layer 203 as a mask to form a groove 112 that exposes the anti-etching layer 110.

[0141] In this embodiment, the second dielectric layer 111 is etched using a dry etching process with the cap mask layer 203 as a mask to form a groove 112 exposing the etch-resistant layer 110. The dry etching process has anisotropic etching characteristics and good control over the etching profile, ensuring that the morphology of the groove 112 meets the process requirements. Furthermore, in the step of etching the second dielectric layer 111 using the dry etching process, the top of the etch-resistant layer 110 can be used as the etching stop position, reducing damage to the source / drain contact plug 107 at the bottom of the etch-resistant layer 110.

[0142] It should be noted that, because the etching-resistant layer 110 can protect the source-drain contact plug 107 from being etched by mistake, the source-drain contact plug 107 has high uniformity, and accordingly, the resistance (Rs) of the source-drain contact plug 107 has high uniformity when the semiconductor structure is working, which is beneficial to improving the uniformity of the electrical performance of the semiconductor structure.

[0143] The method for forming the semiconductor structure further includes: removing the cap mask layer 203 after forming the recess 112.

[0144] The material of the cap mask layer 203 includes an organic material layer, and the cap mask layer 203 is removed in such a way that the organic material layer does not easily contaminate the machine.

[0145] In this embodiment, the ashing process is used to remove the cap mask layer 203.

[0146] Reference Figure 16 The source-drain cap layer 117 is formed in the recess 112.

[0147] In the process of forming the semiconductor structure, the source-drain cap layer 117 is used to protect the top of the source-drain contact plug 107 from being etched by mistake. In addition, because the bottom of the recess 112 is the etching-resistant layer 110, the recess 112 has high uniformity, and accordingly, the source-drain cap layer 117 formed in the recess 112 has high uniformity, which is beneficial to improving the uniformity of the semiconductor structure.

[0148] Specifically, the material of the source-drain cap layer 117 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron silicon carbon nitride. In this embodiment, the material of the source-drain cap layer 117 includes silicon nitride.

[0149] The step of forming the source-drain cap layer 117 in the recess 112 includes: forming a source-drain cap material layer (not shown in the figure) on the recess 112 and the second dielectric layer 111; removing the source-drain cap material layer higher than the second dielectric layer 111, and the remaining source-drain cap material layer in the recess 112 serves as the source-drain cap layer 117.

[0150] In this embodiment, the chemical vapor deposition process is used to form the source-drain cap material layer. The chemical vapor deposition process has the advantages of low cost and high process compatibility.

[0151] In this embodiment, the dry etching process is used to remove the source-drain cap material layer higher than the second dielectric layer 111, and the remaining source-drain cap material layer in the groove 112 serves as the source-drain cap layer 117. In the process of removing the source-drain cap material layer higher than the second dielectric layer 111 by the dry etching process, the top of the second dielectric layer 111 is used as the etching stop position. In other embodiments, the chemical mechanical polishing process can also be used to remove the source-drain cap material layer higher than the second dielectric layer.

[0152] The method for forming the semiconductor structure further includes: after forming the source-drain cap layer 117, performing a planarization process on the source-drain cap layer 117 and the second dielectric layer 111.

[0153] The planarization process on the source-drain cap layer 117 and the second dielectric layer 111 can improve the surface flatness of the source-drain cap layer 117 and the second dielectric layer 111, and can also thin the source-drain cap layer 117, so that the overall thickness of the source-drain cap layer 117 and the etching-resistant layer 110 is not too high, thereby reducing the thickness of the gate plug connected with the gate structure 101 and the source-drain interconnection structure connected with the source-drain contact plug 107, and reducing the probability of void defects and seam defects in the gate plug and the source-drain interconnection structure.

[0154] In this embodiment, the chemical mechanical polishing (CMP) process is used to planarize the source-drain cap layer 117 and the second dielectric layer 111.

[0155] Reference Figure 17 , the method for forming the semiconductor structure further includes: after forming the source-drain cap layer 117, forming a third dielectric layer 118 covering the source-drain cap layer 117 and the second dielectric layer 111.

[0156] The third dielectric layer 118 is used to prepare for the subsequent formation of the gate plug connected with the gate structure 101.

[0157] In this embodiment, the material of the third dielectric layer 118 is an insulating material. Specifically, the material of the third dielectric layer 118 includes silicon oxide. Silicon oxide is a commonly used dielectric material in the process, which has a low cost and high process compatibility, and is conducive to reducing the process difficulty and process cost of forming the third dielectric layer 118.

[0158] In this embodiment, the flowable chemical vapor deposition process is used to form the third dielectric layer 118.

[0159] ReferenceFigure 18 and Figure 19 forming a gate plug 119 (as shown in Figure 19 ) penetrating through the third dielectric layer 118, the second dielectric layer 111, the etching-resist layer 110 and the first dielectric layer 106, and connecting with the gate structure 101.

[0160] The gate plug 119 is used to connect the gate structure 101 with the metal in the back-end-of-line.

[0161] The gate plug 119 is used to connect the gate structure 101 with the metal in the back-end-of-line. The gate plug 119 is located in the active area (AA), and accordingly, the gate plug 119 is a contact over active gate (COAG) plug, which can improve the integration of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0162] In the embodiment, the material of the gate plug 119 includes one or more of Co, Ru and W. In the embodiment, the material of the gate plug 119 includes W. The resistivity of W is low, which is conducive to improving the signal delay of the back-end-of-line RC and improving the processing speed of the semiconductor structure, and at the same time, is conducive to reducing the resistance of the gate plug 119 and accordingly reducing the power consumption.

[0163] In the embodiment, the gate plug 119 is formed by using a self-alignment process.

[0164] Specifically, the step of forming the gate plug 119 penetrating through the third dielectric layer 118, the second dielectric layer 111, the etching-resist layer 110 and the first dielectric layer 106, and connecting with the gate structure 101 includes:

[0165] As shown in Figure 18 , the third dielectric layer 118, the second dielectric layer 111, the etching-resist layer 110 and the first dielectric layer 106 are etched to form a first opening 120 exposing the top of the gate structure 101.

[0166] In the embodiment, the third dielectric layer 118, the second dielectric layer 111, the etching-resist layer 110 and the first dielectric layer 106 are etched by using a dry etching process to form the first opening 120 exposing the gate structure 101. The dry etching process has anisotropic etching characteristics and has good etching profile control, which is conducive to making the morphology of the first opening 120 meet the process requirements. Moreover, by changing the etching gas, the third dielectric layer 118, the second dielectric layer 111, the etching-resist layer 110 and the first dielectric layer 106 can be etched in the same etching equipment by using the dry etching process, which simplifies the process steps.

[0167] Because the etching difficulty of the silicon oxide is less than that of the silicon nitride, in the step of forming the first opening 120, the etching difficulty of the second dielectric layer 111 is less than that of the source-drain cap layer 117, so that the first opening 120 formed can be self-aligned to expose the top of the gate structure 101.

[0168] It should be noted that in the step of forming the first opening 120 exposing the gate structure 101 by using the dry etching process, the first opening 120 also penetrates the gate cap layer 201.

[0169] As shown in FIG. 1C, a first metal layer (not shown in the figure) is formed in the first opening 120 and on the third dielectric layer 118; the first metal layer higher than the third dielectric layer 118 is removed, and the remaining first metal layer in the first opening 120 serves as a gate plug 119. Figure 19

[0170] In this embodiment, the electrochemical plating process is used to form the first metal layer, which has the advantages of simple operation, fast deposition speed, and low price.

[0171] In this embodiment, the chemical mechanical polishing process is used to remove the first metal layer higher than the third dielectric layer 118. In other embodiments, the dry etching process can also be used to remove the first metal layer higher than the third dielectric layer 118, with the top of the third dielectric layer as the etching stop position.

[0172] In other embodiments, the method for forming the semiconductor structure further comprises: after forming the first opening, before forming the first metal layer, forming a first linear oxide layer on the sidewall of the first opening.

[0173] The first linear oxide layer is used to electrically isolate the gate plug from the remaining film layers, and also to prevent metal ions in the gate plug from diffusing, thereby reducing the impact on the performance of the back-end circuit. The material of the first linear oxide layer includes silicon oxide.

[0174] Specifically, the step of forming the first linear oxide layer comprises: forming a first oxide material layer on the bottom and sidewall of the first opening and the surface of the third dielectric layer 118; removing the first oxide material layer on the top of the third dielectric layer 118 and the bottom of the first opening, and the remaining first oxide material layer on the sidewall of the first opening serves as the first linear oxide layer.

[0175] In this embodiment, the chemical vapor deposition process or the atomic layer deposition process is used to form the first oxide material layer. ​

[0176] refer to Figure 20 and Figure 21 A source-drain interconnect structure 122 is formed, penetrating the third dielectric layer 118, the source-drain cap layer 117, and the etch-resistant layer 110, and connected to the source-drain contact plug 107 (e.g., ...). Figure 21 (As shown).

[0177] The source-drain interconnect structure 122 is used to connect the source-drain contact plug 107 to the subsequent metal. Furthermore, during the formation of the source-drain cap layer 117, the anti-etching layer 110 protects the source-drain contact plug 107 from accidental etching, resulting in higher uniformity of the source-drain contact plug 107. Consequently, the contact resistance (Rc) between the source-drain interconnect structure 122 and the source-drain contact plug 107 is also highly uniform, which is beneficial for improving the uniformity of the electrical performance of the semiconductor structure.

[0178] Specifically, the material of the source-drain interconnect structure 122 includes one or more of Cu, Co, W, and Ru. In other embodiments, the material of the source-drain interconnect structure 122 includes W. W has low resistivity, which is beneficial for improving the signal delay of the subsequent RC circuit, increasing the processing speed of the chip, and correspondingly reducing power consumption.

[0179] Specifically, the step of forming a source-drain interconnect structure 122 that penetrates the third dielectric layer 118, the source-drain cap layer 117, and the etch-resistant layer 110 and is connected to the source-drain contact plug 107 includes:

[0180] like Figure 20 As shown, the third dielectric layer 118, the source / drain cap layer 117, and the anti-etching layer 110 are etched to form a second opening 123 that exposes the source / drain contact plug 107.

[0181] In this embodiment, a dry etching process is used to etch the third dielectric layer 118, the source / drain cap layer 117, and the etching resist layer 110, forming a second opening 123 exposing the source / drain contact plug 107. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the second opening 123 meets process requirements. Furthermore, by changing the etching gas, the third dielectric layer 118, the source / drain cap layer 117, and the etching resist layer 110 can be etched in the same etching equipment using the dry etching process, simplifying the process steps.

[0182] like Figure 21 As shown, a second metal layer (not shown) is formed on the second opening 123 and the third dielectric layer 118; the second metal layer above the third dielectric layer 118 is removed, and the remaining second metal layer in the second opening 123 serves as the source-drain interconnect structure 122.

[0183] In the embodiment, the second metal layer is formed by electrochemical plating process, which has the advantages of simple operation, fast deposition speed and low price.

[0184] In the embodiment, the second metal layer higher than the third dielectric layer 118 is removed by chemical mechanical polishing process. In other embodiments, the second metal layer higher than the third dielectric layer 118 can also be removed by dry etching process with the top of the third dielectric layer as the etching stop position.

[0185] In other embodiments, the method for forming the semiconductor structure further comprises: after forming the second opening 123 and before forming the second metal layer, forming a second linear oxide layer on the sidewall of the second opening 123.

[0186] The second linear oxide layer is used to prevent the diffusion of metal ions in the source-drain interconnection structure, thereby reducing the impact on the performance of the back-end circuit. The material of the second linear oxide layer comprises silicon oxide.

[0187] Specifically, the forming step of the second linear oxide layer comprises: forming a second oxide material layer on the bottom and sidewall of the second opening and the surface of the third dielectric layer 118; removing the second oxide material layer on the top of the third dielectric layer 118 and the bottom of the second opening, and the remaining second oxide material layer on the sidewall of the second opening serves as the second linear oxide layer.

[0188] In the embodiment, the second oxide material layer is formed by chemical vapor deposition process or atomic layer deposition process.

[0189] Although the embodiments of the present application have been disclosed as above, they are not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the embodiments of the present application, can make various modifications and changes, and therefore the protection scope of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a gate structure on the substrate; a source-drain doped layer in the substrate on both sides of the gate structure; an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer; a first dielectric layer on the gate structure and the interlayer dielectric layer; a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer; an etch-resistant layer on the first dielectric layer and the source-drain contact plug; a second dielectric layer on the etch-resistant layer, the etch-resistant layer having a greater etching difficulty than the second dielectric layer; a source-drain cap layer penetrating the second dielectric layer and contacting the etch-resistant layer.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a third dielectric layer on the source-drain cap layer and the second dielectric layer; a gate plug penetrating the third dielectric layer, the second dielectric layer, the etch-resistant layer and the first dielectric layer and connected with the gate structure; a source-drain interconnection structure penetrating the third dielectric layer, the source-drain cap layer and the etch-resistant layer and connected with the source-drain contact plug.

3. The semiconductor structure of claim 1 or 2, wherein, The material of the etch-resistant layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride.

4. The semiconductor structure of claim 1 or 2, wherein, The thickness of the etch-resistant layer is 50-500 nm.

5. A method of forming a semiconductor structure, characterized by, The semiconductor structure comprises: a substrate on which a gate structure, a source-drain doped layer in the substrate on both sides of the gate structure, an interlayer dielectric layer covering the sidewall of the gate structure and the source-drain doped layer and a first dielectric layer on the gate structure and the interlayer dielectric layer are formed; a source-drain contact plug penetrating the first dielectric layer and the interlayer dielectric layer and connected with the source-drain doped layer is formed; an etch-resistant layer on the first dielectric layer and the source-drain contact plug is formed; a second dielectric layer on the etch-resistant layer is formed, the etch-resistant layer having a greater etching difficulty than the second dielectric layer; the second dielectric layer is etched to form a groove exposing the etch-resistant layer; a source-drain cap layer in the groove and on the etch-resistant layer is formed.

6. The method of forming a semiconductor structure of claim 5, wherein, The method for forming the semiconductor structure further comprises: after the source-drain cap layer is formed, a third dielectric layer covering the source-drain cap layer and the second dielectric layer is formed; a gate plug penetrating the third dielectric layer, the second dielectric layer, the etch-resistant layer and the first dielectric layer and connected with the gate structure is formed; 7. The method of forming a semiconductor structure according to claim 5 or 6, wherein a source-drain interconnection structure penetrating the third dielectric layer, the source-drain cap layer and the etch-resistant layer and connected with the source-drain contact plug is formed.

8. The method of forming a semiconductor structure according to claim 5 or 6, wherein The material of the etch-resistant layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride and boron silicon carbon nitride.

9. The method of forming a semiconductor structure according to claim 5 or 6, wherein In the step of forming the etch-resistant layer on the first dielectric layer and the source-drain contact plug, the thickness of the etch-resistant layer is 50-500 nm. The etch-resistant layer is formed by a chemical vapor deposition process or an atomic layer deposition process.

10. The method of forming a semiconductor structure of claim 5 or 6, wherein, The material of the source-drain cap layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron silicon nitride, and boron carbon silicon nitride.

11. The method of forming a semiconductor structure of claim 5 or 6, wherein, The step of forming the source-drain cap layer in the recess comprises: forming a source-drain cap material layer on the recess and the second dielectric layer; removing the source-drain cap material layer above the second dielectric layer, and the remaining source-drain cap material layer in the recess as the source-drain cap layer.

12. The method of forming a semiconductor structure of claim 11, wherein, The source-drain cap material layer is formed by a chemical vapor deposition process.

13. The method of forming a semiconductor structure of claim 6, wherein, The method further comprises, after forming the source-drain cap layer and before forming the third dielectric layer, planarizing the source-drain cap layer and the second dielectric layer.

14. The method of forming a semiconductor structure of claim 5 or 6, wherein, The step of etching the second dielectric layer to form the recess exposing the etch-resistant layer comprises: forming a cap mask layer on the second dielectric layer; etching the second dielectric layer with the cap mask layer as a mask to form the recess exposing the etch-resistant layer.

15. The method of forming a semiconductor structure of claim 5 or 6, wherein, The same mask is used in the step of forming the source-drain contact plug and in the step of forming the recess exposing the etch-resistant layer.

16. The method of forming a semiconductor structure of claim 5 or 6, wherein, The second dielectric layer is etched by a dry etching process to form the recess exposing the etch-resistant layer.

17. The method of forming a semiconductor structure of claim 6, wherein, The step of forming the gate plug penetrating through the third dielectric layer, the second dielectric layer, the etch-resistant layer, and the first dielectric layer, and connecting with the gate structure comprises: etching the third dielectric layer, the second dielectric layer, the etch-resistant layer, and the first dielectric layer to form a first opening exposing the top of the gate structure; forming a first metal layer on the first opening and the third dielectric layer; removing the first metal layer above the third dielectric layer, and the remaining first metal layer in the first opening as the gate plug.

18. The method of forming a semiconductor structure of claim 6, wherein, The step of forming the source-drain interconnect structure penetrating through the third dielectric layer, the source-drain cap layer, and the etch-resistant layer, and connecting with the source-drain contact plug comprises: etching the third dielectric layer, the source-drain cap layer, and the etch-resistant layer to form a second opening exposing the source-drain contact plug; forming a second metal layer on the second opening and the third dielectric layer; removing the second metal layer above the third dielectric layer, and the remaining second metal layer in the second opening as the source-drain interconnect structure.

19. The method of forming a semiconductor structure of claim 5, wherein, The substrate comprises a substrate, a fin on the substrate, and an isolation layer covering part of the sidewall of the fin; The gate structure is formed on the isolation layer, across the fin, and covering part of the top wall and part of the sidewall of the fin.

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