Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a substrate and a fin protruding from the substrate, an interlayer dielectric layer is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, the gate opening crosses the fin and exposes part of the top and part of the sidewall of the fin; forming a filling layer on the sidewall of the gate opening and the sidewall of the fin, the filling layer is used to fill the corner of the sidewall of the gate opening and the sidewall of the fin; removing the filling layer on the sidewall of the gate opening and the sidewall of the fin; after removing the filling layer on the sidewall of the gate opening and the sidewall of the fin, forming a gate structure in the gate opening. By forming the filling layer to fill the corner of the sidewall of the gate opening and the sidewall of the fin, the line width dimension of the part of the gate opening close to the sidewall of the fin is similar to the line width dimension of the part far from the sidewall of the fin, so that the line width dimension uniformity of the formed gate structure is higher.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] MOS transistor is one of the most important elements in modern integrated circuits. The basic structure of MOS transistor includes: a semiconductor substrate; a gate structure on the surface of the semiconductor substrate, a source region in the semiconductor substrate on one side of the gate structure and a drain region in the semiconductor substrate on the other side of the gate structure. In the manufacturing process of the above MOS transistor, since the gate structure will directly affect the main electrical properties of the MOS transistor, therefore, in the process, special attention should be paid to the indicators of the gate structure.

[0003] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits become higher and higher. In order to improve the integration and reduce the cost, the key size of components is becoming smaller and smaller, and the influence of line width roughness (LWR) on integrated circuit processing technology cannot be ignored, which has become one of the bottleneck factors seriously restricting the sustainable development of integrated circuits and related industries. Especially, the line width roughness of the gate structure can cause the problems of threshold voltage (Vt) mismatch and high channel off-state leakage current (Loff), so it is very important to make the line width size of the gate structure reach the uniformity of process requirements. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which improves the morphology and line width size uniformity of the gate structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, which includes: a substrate including a substrate and a fin portion protruding from the substrate; an interlayer dielectric layer on the substrate; a gate opening in the interlayer dielectric layer, the gate opening crossing the fin portion and exposing part of the top and part of the sidewall of the fin portion; a filling layer filled at the corner of the sidewall of the gate opening and the sidewall of the fin portion; and a gate structure in the remaining gate opening exposed by the filling layer.

[0006] Optionally, the material of the filling layer includes one or more of silicon nitride, carbon-containing silicon nitride and oxygen-containing silicon nitride.

[0007] Optionally, the gate structure includes a metal gate structure.

[0008] Correspondingly, the application also provides a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a fin protruding from the substrate, an interlayer dielectric layer is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, the gate opening crosses the fin and exposes part of the top and part of the sidewall of the fin; forming a filling layer on the sidewall of the gate opening and the sidewall of the fin, the filling layer is used to fill the corner of the sidewall of the gate opening and the sidewall of the fin; removing the filling layer on the sidewall of the gate opening and the sidewall of the fin; after removing the filling layer on the sidewall of the gate opening and the sidewall of the fin, forming a gate structure in the gate opening.

[0009] Optionally, the method for removing the filling layer on the sidewall of the gate opening and the sidewall of the fin comprises: performing at least one thinning treatment on the filling layer; wherein the thinning treatment comprises: converting part of the thickness of the filling layer into a sacrificial layer, the etch resistance of the sacrificial layer is less than the etch resistance of the filling layer; removing the sacrificial layer.

[0010] Optionally, the sacrificial layer is formed by performing a plasma treatment on part of the thickness of the filling layer.

[0011] Optionally, the reaction gas used in the plasma treatment comprises a mixed gas of ammonia and hydrogen, a mixed gas of ammonia and nitrogen, or a mixed gas of bis(diethylamino)silane and oxygen.

[0012] Optionally, the parameters of the plasma treatment comprise: the processing time is 5 minutes to 10 minutes.

[0013] Optionally, in the step of removing the sacrificial layer, the etching selectivity ratio of the sacrificial layer and the filling layer is greater than 20:1.

[0014] Optionally, the sacrificial layer is removed by using a dry etching process.

[0015] Optionally, the dry etching process comprises: a SiCoNi etching process or a Certas etching process.

[0016] Optionally, the number of thinning treatments is 1 to 4.

[0017] Optionally, the filling layer is formed by using an atomic layer deposition process.

[0018] Optionally, the material of the filling layer comprises one or more of silicon nitride, carbon-containing silicon nitride and oxygen-containing silicon nitride.

[0019] Optionally, in the step of forming the filling layer on the sidewall of the gate opening and the sidewall of the fin, the thickness of the filling layer on the sidewall of the gate opening and the sidewall of the fin is to

[0020] Optionally, in each of the thinning processes, the thickness of the sacrificial layer on the gate opening sidewall and the fin sidewall is to

[0021] Optionally, before forming the interlayer dielectric layer, further comprising: forming a dummy gate layer on the substrate, the dummy gate layer crossing the fin and covering part of the top and part of the sidewall of the fin; forming the interlayer dielectric layer on the substrate at the side of the dummy gate layer, the interlayer dielectric layer exposing the top of the dummy gate layer; the step of forming the opening comprises: removing the dummy gate layer.

[0022] Optionally, the gate structure comprises a metal gate structure.

[0023] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0024] The semiconductor structure provided by the embodiment of the present application has a filling layer at the corner of the gate opening sidewall and the fin sidewall, wherein, in the forming process of the semiconductor structure, the gate structure is formed in the gate opening, when the line width dimension of the part of the gate opening close to the fin sidewall is larger and the line width dimension of the part of the gate opening far from the fin sidewall is smaller, the filling layer provided by the embodiment of the present application at the corner of the gate opening sidewall and the fin sidewall fills the divot at the corner, because the morphology of the gate structure is determined by the remaining space of the gate opening, so that the line width dimension of the part of the gate opening close to the fin sidewall is similar to the line width dimension of the part of the gate opening far from the fin sidewall, thereby making the sidewall perpendicularity of the gate structure formed in the gate opening higher, and the morphology of the gate structure is improved accordingly, and at the same time, the line width dimension of the part of the gate structure close to the fin sidewall is similar to the line width dimension of the part of the gate structure far from the fin sidewall, and the uniformity of the line width dimension of the gate structure is higher.

[0025] The forming method provided by the embodiment of the present application forms a filling layer on the side wall of the gate opening and the side wall of the fin, the filling layer is used to fill the corner of the side wall of the gate opening and the side wall of the fin; the filling layer on the side wall of the gate opening and the side wall of the fin is removed; after the filling layer on the side wall of the gate opening and the side wall of the fin is removed, a gate structure is formed in the gate opening. When the line width dimension of the part of the gate opening close to the side wall of the fin is larger and the line width dimension of the part of the gate opening far from the side wall of the fin is smaller, the embodiment of the present application fills the corner of the side wall of the gate opening and the side wall of the fin by forming the filling layer, that is, fills the recess at the corner, because the morphology of the gate structure is determined by the remaining space of the gate opening, so that the line width dimension of the part of the gate opening close to the side wall of the fin is similar to the line width dimension of the part of the gate opening far from the side wall of the fin, thereby making the side wall perpendicularity of the gate structure formed in the gate opening higher, and the morphology of the gate structure is improved, and the line width dimension of the part of the gate structure close to the side wall of the fin is similar to the line width dimension of the part of the gate structure far from the side wall of the fin, and the line width dimension uniformity of the gate structure is higher. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1 to 4 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0027] Figure 5 is a perspective view of an embodiment of the semiconductor structure of the present application;

[0028] Figure 6 is a top view of Figure 5 ;

[0029] Figures 7 to 14 is a top view structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0030] At present, the morphology quality and line width dimension uniformity of the gate structure still need to be improved. The reasons why the morphology quality and line width dimension uniformity of the gate structure still need to be improved are analyzed in combination with a forming method of a semiconductor structure.

[0031] Figures 1 to 4 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0032] Reference Figure 1 , Figure 1is a perspective view at a top position of the fin portion, providing a substrate (not shown) including a substrate 10 and a fin portion 12 protruding from the substrate 10, the fin portion 12 having an isolation structure 11 formed on the substrate 10 exposed by the fin portion 12, the isolation structure 11 covering part of the sidewall of the fin portion 12, the isolation structure 11 having a dummy gate layer 16 formed thereon across the fin portion 12, the dummy gate layer 16 covering part of the top and part of the sidewall of the fin portion 12, the isolation structure 11 at the side of the dummy gate layer 16 having an interlayer dielectric layer 13 formed thereon, the interlayer dielectric layer 13 exposing the top of the dummy gate layer 16.

[0033] It is to be noted that, Figure 1 is a perspective view at a top position of the fin portion, thus, Figure 1 the top of the dummy gate layer 16 and the top of the fin portion 12 are flush in Figure 1 is not shown in

[0034] It is to be further noted that a dummy gate oxide layer 15 is also formed between the dummy gate layer 16 and the fin portion 12.

[0035] With reference to Figure 2 and Figure 3 , Figure 2 is a perspective view based on Figure 1 , Figure 3 is a top view of Figure 2 , with the dummy gate layer 16 (as shown in Figure 1 ) removed, a gate opening 20 is formed in the interlayer dielectric layer 13, the gate opening 20 across the fin portion 12 and exposing part of the top and part of the sidewall of the fin portion 12.

[0036] With the dummy gate layer 16 removed, it further includes removing the dummy gate oxide layer 15 exposed by the gate opening 20.

[0037] With reference to Figure 4 , Figure 4 is a top view based on Figure 3 , a gate structure 21 is formed in the gate opening 20 (as shown in Figure 3 ).

[0038] In forming the dummy gate layer 16, the dummy gate layer 16 is formed by etching a dummy gate material layer, at the position close to the sidewall of the fin portion 12, the dummy gate layer 16 is prone to footing defects, thus, the line width dimension of the part of the dummy gate layer 16 close to the sidewall of the fin portion 12 is larger, while the line width dimension of the part of the dummy gate layer 16 away from the sidewall of the fin portion 12 is smaller.

[0039] The gate opening 20 is formed by removing the dummy gate layer 16, thus, the line width dimension of the part of the gate opening 20 close to the fin 12 sidewall is larger, the line width dimension of the part far from the fin 12 sidewall is smaller, and there is a divot at the corner of the gate opening 20 sidewall and the fin 12 sidewall, thus, the profile quality and line width dimension uniformity of the gate opening 20 is poor.

[0040] The gate structure 21 is formed in the gate opening 20, thus, the profile of the gate structure 21 is determined by the space of the gate opening 20, thus, the line width dimension of the part of the gate structure 21 close to the fin 12 sidewall is larger, the line width dimension of the part far from the fin 12 sidewall is smaller, the line width dimension of the part close to the fin 12 sidewall and the line width dimension of the part far from the fin 12 sidewall of the gate structure 21 differ greatly, the gate structure 21 has a footing defect at the position of the fin 12 sidewall, the sidewall verticality of the gate structure 21 is lower, thus, the profile quality and line width dimension uniformity of the gate structure 21 is also poor.

[0041] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, comprising a substrate and a fin protruding from the substrate, an interlayer dielectric layer is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, the gate opening crosses the fin and exposes part of the top and sidewall of the fin; forming a filling layer on the sidewall of the gate opening and the sidewall of the fin, the filling layer is used to fill the corner of the sidewall of the gate opening and the sidewall of the fin; removing the filling layer on the sidewall of the gate opening and the sidewall of the fin; after removing the filling layer on the sidewall of the gate opening and the sidewall of the fin, forming a gate structure in the gate opening.

[0042] The forming method provided by the embodiment of the present application forms a filling layer on the side wall of the gate opening and the side wall of the fin, the filling layer is used to fill the corner of the side wall of the gate opening and the side wall of the fin; the filling layer on the side wall of the gate opening and the side wall of the fin is removed; after the filling layer on the side wall of the gate opening and the side wall of the fin is removed, a gate structure is formed in the gate opening. When the line width dimension of the part of the gate opening close to the side wall of the fin is larger and the line width dimension of the part of the gate opening far from the side wall of the fin is smaller, the embodiment of the present application fills the corner of the side wall of the gate opening and the side wall of the fin by forming the filling layer, that is, fills the recess at the corner, because the morphology of the gate structure is determined by the remaining space of the gate opening, so that the line width dimension of the part of the gate opening close to the side wall of the fin is similar to the line width dimension of the part of the gate opening far from the side wall of the fin, thereby making the side wall perpendicularity of the gate structure formed in the gate opening higher, and correspondingly improving the morphology of the gate structure, and making the line width dimension of the part of the gate structure close to the side wall of the fin similar to the line width dimension of the part of the gate structure far from the side wall of the fin, thereby making the line width dimension uniformity of the gate structure higher.

[0043] In order to make the above-mentioned purpose, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0044] Reference is made to Figure 5 and Figure 6 , Figure 5 a perspective view of an embodiment of the semiconductor structure of the present application is shown, Figure 6 is Figure 5 a top view.

[0045] It should be noted that, Figure 5 is a perspective view at the position of the top of the fin, therefore, Figure 5 the top of the gate structure and the interlayer dielectric layer are flush with the top of the fin in Figure 5 the gate structure and the interlayer dielectric layer higher than the top of the fin are not shown in Figure 6 is a top view at the position of the top of the fin.

[0046] The semiconductor structure comprises: a substrate comprising a substrate 101 and a fin 121 protruding from the substrate 101; an interlayer dielectric layer 131 located on the substrate; a gate opening (not labeled) located in the interlayer dielectric layer 131, the gate opening crossing the fin 121 and exposing part of the top and part of the side wall of the fin 121; a filling layer 221 filled in the corner of the side wall 241 of the gate opening and the side wall 141 of the fin 121; and a gate structure 211 located in the remaining gate opening exposed by the filling layer 221.

[0047] The semiconductor structure provided by the embodiment of the present application has a filling layer 221 at the corner of the sidewall 241 of the gate opening and the sidewall 141 of the fin 121. During the forming process of the semiconductor structure, the gate structure 211 is formed in the gate opening. When the line width dimension of the part of the gate opening close to the sidewall 141 of the fin 121 is larger and the line width dimension of the part of the gate opening far from the sidewall 141 of the fin 121 is smaller, that is, when the corner of the sidewall 241 of the gate opening and the sidewall 141 of the fin 121 has a recess, the filling layer 221 at the corner of the sidewall 241 of the gate opening and the sidewall 141 of the fin 121 fills the recess at the corner. Since the morphology of the gate structure 211 is determined by the remaining space of the gate opening, the line width dimension of the part of the gate opening close to the sidewall 141 of the fin 121 is similar to the line width dimension of the part of the gate opening far from the sidewall 141 of the fin 121, so that the sidewall of the gate structure 211 formed in the gate opening has high verticality, the morphology of the gate structure 211 is improved, and the line width dimension of the gate structure 211 close to the sidewall 141 of the fin 121 is similar to the line width dimension of the gate structure 211 far from the sidewall 141 of the fin 121, so that the line width dimension of the gate structure 211 is uniform.

[0048] In the embodiment, the semiconductor structure is a fin field effect transistor (FinFET). The substrate includes a substrate 101 and a fin 121 protruding from the substrate 101.

[0049] The substrate 101 provides a process operation basis for the forming process of the semiconductor structure.

[0050] In the embodiment, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate 101 can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate 101 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate 101 can be a material suitable for process needs or easy to integrate.

[0051] In the embodiment, the material of the fin 121 is the same as the material of the substrate 101, both of which are silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0052] In this embodiment, the substrate further includes an isolation structure 111 on the substrate 101 exposed by the fin 121, the isolation structure 111 covering part of the sidewall of the fin 121. The isolation structure 111 is a shallow trench isolation structure, and the isolation structure 111 is used to achieve isolation between different device regions. The material of the isolation structure 111 includes silicon oxide.

[0053] The interlayer dielectric layer 131 is used to achieve electrical isolation between adjacent transistors.

[0054] In this embodiment, the interlayer dielectric layer 131 is also used to provide a process platform for forming the gate opening.

[0055] The material of the interlayer dielectric layer 131 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 131 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride or silicon oxynitride.

[0056] In this embodiment, the gate opening is used to provide a spatial position for forming the gate structure 211.

[0057] In this embodiment, the filling layer 221 is used to fill the corner between the sidewall 241 of the gate opening and the sidewall 141 of the fin 121. Specifically, the filling layer 221 is used to fill the recess at the corner.

[0058] In this embodiment, the material of the filling layer 221 includes one or more of silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon nitride.

[0059] The material properties of the silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon nitride are stable, and the etch resistance is high. After being filled in the corner, it is relatively stable and not easy to fall off or be consumed.

[0060] The gate structure 211 is a device gate structure, which is used to control the opening or closing of the channel of the transistor.

[0061] In this embodiment, the gate structure 211 corresponds to the fin 121 and covers part of the top and part of the sidewall of the fin 121.

[0062] In this embodiment, the gate structure 211 is a metal gate structure.

[0063] In this embodiment, the gate structure 211 includes a high-k gate dielectric layer (not labeled), a work function layer (not labeled) on the high-k gate dielectric layer, and a gate electrode layer (not labeled) on the work function layer.

[0064] The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0065] The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0066] The gate electrode layer is used to lead out the electrical property of the gate structure 211. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0067] In this embodiment, the semiconductor structure further includes a dummy gate oxide layer 151 located between the interlayer dielectric layer 131 and the fin 121. The material of the dummy gate oxide layer 151 can be silicon oxide.

[0068] It should be noted that during the formation of the semiconductor structure, a dummy gate layer is formed at the position of the gate structure 211, and the gate opening is formed by removing the dummy gate layer, and then the gate structure 211 is formed in the gate opening. A dummy gate oxide layer 151 is also formed between the dummy gate layer and the fin 121, and after removing the dummy gate layer, the dummy gate oxide layer 151 exposed by the gate opening is also removed. During the removal of the dummy gate oxide layer 151 exposed by the gate opening, the recess problem at the corner of the gate opening sidewall 241 and the fin 121 sidewall 141 is easily worsened.

[0069] It should also be noted that according to process requirements, a gate oxide layer (not labeled) can also be formed between the gate structure 211 and the fin 121. The material of the gate oxide layer can be silicon oxide.

[0070] Figures 7 to 14 is a structure diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present application.

[0071] In combination with reference Figures 7 to 9 , Figure 7 and Figure 8 is a perspective view, Figure 9 isFigure 8 FIG. 1 is a top view of a semiconductor structure, providing a substrate (not labeled) including a substrate 100 and a fin 120 protruding from the substrate 100, the substrate having an interlayer dielectric layer 130 formed thereon, the interlayer dielectric layer 130 having a gate opening 200 formed therein, the gate opening 200 spanning the fin 120 and exposing a portion of a top and a portion of a sidewall of the fin 120.

[0072] It is noted that, Figure 7 FIG. 2 is a perspective view at a location of a top of the fin, thus, Figure 8 FIG. 3 is a top view of the interlayer dielectric layer and the gate structure at the top of the fin, Figure 7 FIG. 4 is a perspective view of the interlayer dielectric layer and the gate structure at the top of the fin, Figure 8 FIG. 5 is a top view of the interlayer dielectric layer and the gate structure at the top of the fin, Figure 7 FIG. 6 is a perspective view of the interlayer dielectric layer and the gate structure at the top of the fin, Figure 8 FIG. 7 is a top view of the interlayer dielectric layer and the gate structure at the top of the fin. Figure 9

[0073] In this embodiment, the semiconductor structure formed is a fin field effect transistor (FinFET). The substrate includes a substrate 100 and a fin 120 protruding from the substrate 100.

[0074] The substrate 100 provides a process operation base for subsequent processes.

[0075] In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the substrate 100 can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other type of substrate. The material of the substrate 100 can be a material suitable for process needs or easy for integration.

[0076] In this embodiment, the material of the fin 120 is the same as the material of the substrate 100, both being silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0077] In this embodiment, the substrate further includes an isolation structure 110 located on the substrate 100 exposed by the fin 120, the isolation structure 110 covering a portion of the sidewall of the fin 120. The isolation structure 110 is a shallow trench isolation structure, and the isolation structure 110 is used to achieve isolation between different device regions. The material of the isolation structure 110 includes silicon oxide.

[0078] The interlayer dielectric layer 130 is used to achieve electrical isolation between adjacent transistors, and in this embodiment, the interlayer dielectric layer 130 is also used to provide a process platform for forming the gate opening 200.​

[0079] The interlayer dielectric layer 130 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 130 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride or silicon oxynitride.

[0080] In this embodiment, the gate opening 200 is used to provide a spatial position for the subsequent formation of the gate structure.

[0081] In this embodiment, the gate structure is formed by using a high-k last metal gate (high k last metal gate last) process, and therefore, the gate opening 200 is formed by removing the dummy gate layer.

[0082] Therefore, as shown in Figure 7 In this embodiment, before the interlayer dielectric layer 130 is formed, the method further includes: forming a dummy gate layer 160 on the substrate, the dummy gate layer 160 spans the fin 120 and covers part of the top and part of the sidewall of the fin 120.

[0083] The dummy gate layer 160 is used to occupy a spatial position for the subsequent formation of the gate structure.

[0084] In this embodiment, the material of the dummy gate layer 160 is polysilicon or amorphous silicon.

[0085] Specifically, the step of forming the dummy gate layer 160 includes: forming a dummy gate material layer covering the substrate; etching the dummy gate material layer to form the dummy gate layer 160 spanning the fin 120.

[0086] It should be noted that when the dummy gate layer 160 is formed, the dummy gate layer 160 is obtained by etching the dummy gate material layer, and at the part close to the sidewall of the fin 120, the dummy gate layer 160 is prone to have a footing defect, and therefore, the line width dimension of the part close to the sidewall of the fin 120 is larger, and the line width dimension of the part away from the sidewall of the fin 120 is smaller.

[0087] It should also be noted that before the dummy gate layer 160 is formed, the forming method further includes: forming a dummy gate oxide layer 150 on the surface of the fin 120.

[0088] In this embodiment, the material of the dummy gate oxide layer 150 is silicon oxide.

[0089] As shown in Figure 7 The interlayer dielectric layer 130 is formed on the substrate 100 at the side of the dummy gate layer 160, and the interlayer dielectric layer 130 exposes the top of the dummy gate layer 160.

[0090] As Figure 8 and Figure 9 shown, the step of forming the gate opening 200 includes removing the dummy gate layer 160.

[0091] Since the dummy gate layer 160 has a footing defect at the portion close to the fin 120 sidewall 240, after removing the dummy gate layer 160, a recess is easily formed at the corner of the gate opening 200 sidewall 240 and the fin 120 sidewall 140.

[0092] In this embodiment, after removing the dummy gate layer 160, it further includes removing the dummy gate oxide layer 150 exposed by the gate opening 200.

[0093] The line width dimension of the dummy gate oxide layer 150 exposed by the gate opening 200 is larger, so after removing the dummy gate oxide layer 150 exposed by the gate opening 200, the line width dimension of the portion of the gate opening 200 close to the fin 120 sidewall 140 is also increased, making the line width dimension non-uniformity of the portion of the gate opening 200 close to the fin 120 sidewall 140 and the portion far away from the fin 120 sidewall 140 more serious.

[0094] Referring to Figure 10 , Figure 10 is a top view, a filling layer 220 is formed at the corner of the gate opening 200 sidewall 240 and the fin 120 sidewall 140, and the filling layer 220 is used to fill the corner of the gate opening 200 sidewall 240 and the fin 120 sidewall 140.

[0095] When the gate opening 200 is formed, the part of the gate opening 200 close to the fin 120 sidewall 140 has a larger line width dimension, and the part of the gate opening 200 far from the fin 120 sidewall 140 has a smaller line width dimension. In this embodiment, a filling layer 220 is formed to fill the corner between the gate opening 200 sidewall 240 and the fin 120 sidewall 140, i.e. to fill the recess at the corner. After the filling layer 220 at the gate opening 200 sidewall 240 and the fin 120 sidewall 140 is removed, the filling layer 220 at the corner is left to fill the recess at the corner. Since the profile of the gate structure is determined by the remaining space of the gate opening 200, the line width dimension of the part of the gate opening 200 close to the fin 120 sidewall 140 is similar to the line width dimension of the part of the gate opening 200 far from the fin 120 sidewall 140, so that the sidewall of the gate structure formed in the gate opening 200 has a higher verticality, and the profile of the gate structure is improved. In addition, the line width dimension of the part of the gate structure close to the fin 120 sidewall 140 is similar to the line width dimension of the part of the gate structure far from the fin 120 sidewall 140, so that the line width dimension uniformity of the gate structure is higher.

[0096] In this embodiment, the filling layer 220 is formed by an atomic layer deposition process.

[0097] The atomic layer deposition process has good gap filling capability, so that the filling layer 220 can be filled in the corner between the gate opening 200 sidewall 240 and the fin 120 sidewall 140. The low-temperature atomic layer deposition process has a good filling effect on the corner, and the low-temperature atomic layer deposition process can accurately control the film thickness to meet the process requirements.

[0098] Correspondingly, in the step of forming the filling layer 220 on the gate opening 200 sidewall 240 and the fin 120 sidewall 140 in this embodiment, the filling layer 220 conformally covers the bottom and sidewall of the gate opening 200.

[0099] When the corner between the gate opening 200 sidewall 240 and the fin 120 sidewall 140 has a divot, as the material corresponding to the filling layer 220 is deposited, the filling layer 220 on the gate opening 200 sidewall 240 and the filling layer 220 on the fin 120 sidewall 140 are in contact at the corner, so that the recess at the corner is filled.

[0100] In this embodiment, the material of the filling layer 220 includes one or more of silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon nitride.

[0101] The material properties of the silicon nitride, carbon-containing silicon nitride and oxygen-containing silicon nitride are stable, the filling in the corner is stable and not easy to fall off or be lost.

[0102] In the embodiment, in the step of forming the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120, the thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is to

[0103] The thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 cannot be too large or too small. If the thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is too large, it is not conducive to remove the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 in the subsequent process. If the thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is too small, the filling effect of the filling layer 200 on the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is not ideal when the filling layer 200 is formed, so that the process requirement of filling the corner is not met. In the embodiment, the thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is to For example, the thickness of the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is

[0104] In combination with reference to Figures 11 to 13 , the filling layer 220 on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is removed.

[0105] In order not to affect the connection of the subsequently formed gate structure and the fin 120, the filling layer 220 on the sidewall 140 of the fin 120 needs to be removed, and the filling layer formed on the sidewall 240 of the gate opening 200 and the filling layer 220 on the sidewall 140 of the fin 120 have the same thickness, so they can be removed together.

[0106] Moreover, the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 has a recess, the boundary of the recess is recessed relative to the sidewall 240 of the gate opening 200, and the filling layer 220 is filled in the recess, so the filling layer 220 in the recess can be retained.

[0107] Specifically, with reference to Figure 11 and Figure 12 , the method for removing the filling layer 220 located at the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 comprises: performing at least one thinning treatment on the filling layer 220.

[0108] The at least one thinning treatment on the filling layer 220 is to remove the filling layer 220 located at the sidewall 140 of the fin 120, so as to expose the sidewall 140 of the fin 120, and further to prepare for the subsequent formation of a gate structure.

[0109] The number of thinning treatments is 1 to 4. If the number of thinning treatments is too large, the process will be complicated, and the fin 120 may be damaged.

[0110] In the embodiment, the number of thinning treatments is 2. By adopting 2 thinning treatments, each thinning treatment is used to remove a part of the thickness of the filling layer 220, so as to more accurately control the process of thinning treatment, and not to cause the process to be complicated due to too many treatments.

[0111] Specifically, with reference to Figure 11 , the thinning treatment comprises: converting a part of the thickness of the filling layer 220 into a sacrificial layer 230, and the etch resistance of the sacrificial layer 230 is less than that of the filling layer 220.

[0112] Converting a part of the thickness of the filling layer 220 into a sacrificial layer 230, and the etch resistance of the sacrificial layer 230 is less than that of the filling layer 220, which is beneficial to etching and removing the sacrificial layer 230 in the subsequent process, so that the sacrificial layer 230 is easily removed.

[0113] In the embodiment, in the step of each thinning treatment, the thickness of the sacrificial layer 230 located at the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is to

[0114] The thickness of the sacrificial layer 230 cannot be too small or too large. If the thickness of the sacrificial layer 230 is too small, the number of thinning treatments will be increased, resulting in a complicated process. If the thickness of the sacrificial layer 230 is too large, the filling layer 220 located at the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 will be converted into the sacrificial layer 230 too much, so that the filling layer 220 at the corner is removed too much in the subsequent process, and thus cannot fill the corner.

[0115] In this embodiment, the partial-thickness filling layer 220 is subjected to plasma treatment, thereby converting the partial-thickness filling layer 220 into the sacrificial layer 230.

[0116] The plasma treatment has the characteristic of forming the sacrificial layer 230 at a faster rate in a large space and at a slower rate in a small space, so that, in the same time, when the sacrificial layer 230 is formed, the space on the filling layer 220 located on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is larger, so the formed sacrificial layer 230 is thicker, and the space on the filling layer 220 located at the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is smaller, so the formed sacrificial layer 230 is thinner, then when the sacrificial layer 230 is removed by subsequent multiple thinning processes, the filling layer 220 located on the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is completely removed, while the filling layer 220 located at the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 is retained.

[0117] The reaction gas used in the plasma treatment includes a mixed gas of ammonia and hydrogen, a mixed gas of ammonia and nitrogen, or a mixed gas of bis(diethylamino)silane and oxygen. In this embodiment, the reaction gas used in the plasma treatment is a mixed gas of bis(diethylamino)silane and oxygen. The reaction gas used in the plasma treatment is a mixed gas of bis(diethylamino)silane and oxygen, bis(diethylamino)silane is used as plasma bombardment to treat the surface, and oxygen is used as oxidation, so that the growth rate of the sacrificial layer is easy to control, and the thickness of the sacrificial layer is easy to control.

[0118] The parameters of the plasma treatment include a processing time of 5 to 10 minutes.

[0119] The processing time of the plasma treatment cannot be too long or too short. If the processing time of the plasma treatment is too long, the formed sacrificial layer 230 will be too thick, which may cause the filling layer 220 located at the corner of the sidewall 240 of the gate opening 200 and the sidewall 140 of the fin 120 to be converted into the sacrificial layer 230 too much, thereby causing the filling layer 220 at the corner to be removed too much in the subsequent process and failing to fill the corner; if the processing time of the plasma treatment is too short, the formed sacrificial layer 230 will be too thin, which will excessively increase the number of thinning processes when the filling layer 220 is subjected to the thinning process, resulting in a complicated process.

[0120] In combination with reference to Figure 12 and Figure 13 , the thinning process further comprises: removing the sacrificial layer 230 (as shown in Figure 11 ).

[0121] By removing the sacrificial layer 230, the remaining filling layer 220 is exposed, thereby preparing for the next thinning process; or, the fin 120 sidewall 140 is exposed, thereby preparing for forming a gate structure.

[0122] In this embodiment, the etching selectivity ratio of the sacrificial layer 230 and the filling layer 220 is greater than 20:1 in the step of removing the sacrificial layer 230.

[0123] The etching selectivity ratio of the sacrificial layer 230 and the filling layer 220 is greater, which is conducive to etching to remove the sacrificial layer 230 and reduce damage to the filling layer 220, thereby protecting the filling layer 220 at the corner of the gate opening 200 sidewall 240 and the fin 120 sidewall 140 to better fill the corner.

[0124] In this embodiment, the sacrificial layer 230 is removed by a dry etching process.

[0125] The dry etching process is conducive to improving the etching selectivity ratio of the sacrificial layer 230 and the filling layer 220.

[0126] In this embodiment, the dry etching process includes a SiCoNi etching process or a Certas etching process.

[0127] The SiCoNi etching process or the Certas etching process has a high etching selectivity ratio for the sacrificial layer 230 and the filling layer 220, which is conducive to etching to remove the sacrificial layer 230 and reduce damage to the filling layer 220. Moreover, the etching rate uniformity of the SiCoNi etching process or the Certas etching process is high.

[0128] In combination with reference to Figure 13 , after removing the filling layer 220 located at the gate opening 200 sidewall 240 and at the fin 120 sidewall 140 (as shown in Figure 12 ), the filling layer 220 located at the corner of the gate opening 200 sidewall 240 and the fin 120 sidewall 140 is retained.

[0129] After removing the fill layer 220 located at the sidewall of the gate opening and at the sidewall 140 of the fin 120, the fill layer 220 filling the recess at the corner is left, so that the line width dimension of the portion of the gate opening 200 close to the sidewall 140 of the fin 120 is similar to the line width dimension of the portion of the gate opening 200 far from the sidewall 140 of the fin 120, thereby making the sidewall verticality of the gate structure formed in the gate opening 200 higher, and accordingly improving the profile of the gate structure, while making the line width dimension of the portion of the gate structure close to the sidewall 140 of the fin 120 similar to the line width dimension of the portion of the gate structure far from the sidewall 140 of the fin 120, and the line width dimension uniformity of the gate structure is higher.

[0130] It should be noted that in other embodiments, when the verticality of the sidewall of the gate opening is higher, that is, when the corner of the sidewall of the gate opening and the sidewall of the fin is not recessed, the gate opening can also not contain the fill layer after removing the fill layer located at the sidewall of the gate opening and at the sidewall of the fin.

[0131] Reference is made to Figure 14 , after removing the fill layer 220 located at the sidewall 240 of the gate opening 200 and at the sidewall 140 of the fin 120, a gate structure 210 is formed in the gate opening 200 (as shown in FIG. 2D). Figure 13

[0132] In this embodiment, the gate structure 210 includes a metal gate structure.

[0133] In this embodiment, the gate structure 210 includes a high-k gate dielectric layer (not labeled), a work function layer (not labeled) located on the high-k gate dielectric layer, and a gate electrode layer (not labeled) located on the work function layer.

[0134] The material of the high-k gate dielectric layer is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0135] ​The work function layer is used for adjusting the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0136] The gate electrode layer is used for leading out the electrical property of the gate structure 210. In the embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0137] It should be noted that according to the process requirement, a gate oxide layer (not labeled) can also be formed between the gate structure 210 and the fin 120. The material of the gate oxide layer can be silicon oxide.

[0138] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The method comprises the following steps: a substrate comprising a substrate and a fin protruding from the substrate; an interlayer dielectric layer on the substrate; a gate opening in the interlayer dielectric layer, the gate opening crossing the fin and exposing part of the top and part of the sidewall of the fin; a filling layer filling the recess at the corner of the sidewall of the gate opening and the sidewall of the fin; a gate structure in the remaining gate opening exposed by the filling layer.

2. The semiconductor structure of claim 1, wherein, The material of the filling layer comprises one or more of silicon nitride, carbon-containing silicon nitride and oxygen-containing silicon nitride.

3. The semiconductor structure of claim 1, wherein, The gate structure comprises a metal gate structure.

4. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate comprising a substrate and a fin protruding from the substrate, an interlayer dielectric layer formed on the substrate, and a gate opening formed in the interlayer dielectric layer, the gate opening crossing the fin and exposing part of the top and part of the sidewall of the fin; forming a filling layer on the sidewall of the gate opening and the sidewall of the fin, the filling layer being used to fill the recess at the corner of the sidewall of the gate opening and the sidewall of the fin; removing the filling layer on the sidewall of the gate opening and the sidewall of the fin; after removing the filling layer on the sidewall of the gate opening and the sidewall of the fin, forming a gate structure in the gate opening.

5. The method of forming a semiconductor structure of claim 4, wherein, The method for removing the filling layer on the sidewall of the gate opening and the sidewall of the fin comprises at least one thinning treatment on the filling layer; wherein the thinning treatment comprises converting part of the thickness of the filling layer into a sacrificial layer, the etch resistance of the sacrificial layer being less than that of the filling layer; removing the sacrificial layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The plasma treatment on part of the thickness of the filling layer forms the sacrificial layer.

7. The method of forming a semiconductor structure of claim 6, wherein, The reaction gas used in the plasma treatment comprises a mixture of ammonia and hydrogen, a mixture of ammonia and nitrogen, or a mixture of bis(diethylamino)silane and oxygen.

8. The method of forming a semiconductor structure of claim 6, wherein, The parameters of the plasma treatment include a treatment time of 5-10 minutes.

9. The method of forming a semiconductor structure of claim 5, wherein, In the step of removing the sacrificial layer, the etch selectivity ratio of the sacrificial layer and the filling layer is greater than 20:

1.

10. The method of forming a semiconductor structure of claim 5, wherein, The sacrificial layer is removed by a dry etching process.

11. The method of forming a semiconductor structure of claim 10, wherein, The dry etching process comprises a SiCoNi etching process or a Certas etching process.

12. The method of forming a semiconductor structure of claim 5, wherein, The number of thinning treatments is 1-4.

13. The method of forming a semiconductor structure of claim 4, wherein, The filling layer is formed by an atomic layer deposition process.

14. The method of forming a semiconductor structure of claim 4, wherein, The material of the filling layer comprises one or more of silicon nitride, carbon-containing silicon nitride and oxygen-containing silicon nitride.

15. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the filling layer on the sidewall of the gate opening and the sidewall of the fin, the thickness of the filling layer on the sidewall of the gate opening and the sidewall of the fin is 15-30 Å.

16. The method of forming a semiconductor structure of claim 5, wherein, In the step of each thinning treatment, the thickness of the sacrificial layer on the sidewall of the gate opening and the sidewall of the fin is 10-20 Å.

17. The method of forming a semiconductor structure of claim 4, wherein, Before forming the interlayer dielectric layer, the method further comprises forming a dummy gate layer on the substrate, the dummy gate layer crossing the fin and covering part of the top and part of the sidewall of the fin; the interlayer dielectric layer is formed on the substrate at the side of the dummy gate layer, and the interlayer dielectric layer exposes the top of the dummy gate layer; The step of forming the opening includes removing the dummy gate layer.

18. The method of forming a semiconductor structure of claim 4, wherein, The gate structure includes a metal gate structure.

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