Highly reliable siC trench power semiconductor device and method of fabrication

Abstract

The application relates to a high-reliability SiC trench power semiconductor device and a preparation method thereof. The device comprises an SiC semiconductor substrate and a cell region, wherein a plurality of second-conductivity-type doped buried layers traversing the cell region are arranged in the cell region; the cell trenches in the cell region are in a strip shape and are parallel to each other, and the length direction of the cell trenches is perpendicular to the length direction of the second-conductivity-type doped buried layers; on the cross section of the power semiconductor device, the second-conductivity-type doped buried layers comprise a buried layer first main surface and a buried layer second main surface opposite to the buried layer first main surface, wherein the buried layer second main surface is opposite to the back surface of the SiC semiconductor substrate, and the depth of the buried layer second main surface of the second-conductivity-type doped buried layers is not less than the bottom depth of the cell trenches. The application can effectively reduce the electric field at the bottom of the cell trenches, ensure the reliability of the gate oxide layer at the bottom of the cell trenches, reduce the channel conduction resistance, is compatible with the existing process, and is safe and reliable.

Description

TECHNICAL FIELD

[0001] The present application relates to a power semiconductor device and a preparation method, in particular to a high-reliability SiC trench power semiconductor device and a preparation method. BACKGROUND

[0002] Silicon carbide material is one of the most optimal substrate materials for power semiconductor devices due to its high breakdown field, wide bandgap, high thermal conductivity and other excellent characteristics. At present, the most popular silicon carbide power semiconductor device in the market is undoubtedly the silicon carbide trench field effect transistor (SiC Trench MOSFET). However, one of the key points in the design of the silicon carbide trench MOSFET device is to avoid the occurrence of local high electric field at the bottom of the trench in the cell area, so as to ensure the reliability of the gate oxide layer at the bottom of the trench.

[0003] Since the SiC trench MOSFET device will generate an excessively high electric field at the bottom of the trench in the blocking state, thereby causing a reliability problem of the bottom gate oxide layer in the trench, therefore, the current mainstream way is to inject a P-type doped buried layer at the bottom of the trench, or to form a deep P-type doped base region on both sides of the trench by high-energy ion implantation, so as to reduce the electric field strength at the bottom of the trench and improve the reliability of the SiC trench MOSFET device.

[0004] As shown in FIG. 1, it is a schematic diagram of the prior art of setting a P-type implanted buried layer 10 at the bottom of the trench, Figure 1 As shown in FIG. 2, it is a schematic diagram of the prior art of forming a deep P-type doped base region 12 on both sides of the trench. From Figure 2 and Figure 1 It can be seen that the trench structure and the P-type implanted buried layer 10 or the deep P-type doped base region 12 are in parallel direction, however, when the cell pitch (the repeating distance between the cell trenches and the cell trenches, the smaller the pitch, the higher the channel density, and the smaller the channel resistance) is reduced to reduce the channel resistance, the distance between the P-type implanted buried layers 10 or the distance between the deep P-type doped base regions 12 must be reduced, however, this will cause the conduction path width between the P-type implanted buried layers 10 or the deep P-type doped base regions 12 to be reduced, thereby causing the on-resistance to increase, that is, the resistance of the parasitic JFET structure increases; wherein, the region between the deep P-type doped base regions 12 constitutes the JFET structure, the smaller the distance between the deep P-type doped base regions 12, the smaller the conduction path, but the on-resistance increases. Figure 2

[0005] ​For the implementation case of using deep P-type doped base region 12, when the pitch is reduced to the rear, the deep P-type doped base region 12 is also closer to the channel. When the pitch is small enough, due to the influence of the deep P-type doped base region 12 on the channel, the channel resistance will increase sharply, and due to the large channel electron mobility of the SiC MOSFET device, the channel resistance is high, and in order to further reduce the channel resistance, high-density channel design is necessary. Therefore, it can be seen that for the implementation case of using deep P doped base region 12, the way to reduce the channel resistance by increasing the channel density (reducing the pitch) will be limited by the minimum width of the pitch, which is due to the excessive resistance of the parasitic JFET structure. Because the channel mobility of the silicon carbide MOSFET is generally only 50cm 2 *V -1 S -1 Left and right, the channel resistance accounts for a large proportion, thereby causing the optimization space of the on-resistance of the prior art to be limited, which is caused by the design limitation itself rather than the process capability limitation.

[0006] In summary, for SiC trench type power semiconductor devices, how to ensure the trench bottom gate oxide layer under the condition of reducing the on-resistance by increasing the trench density is a technical problem that needs to be solved urgently at present. SUMMARY

[0007] The purpose of the present application is to overcome the shortcomings in the prior art, provide a high-reliability SiC trench type power semiconductor device and a preparation method, which can effectively reduce the electric field at the bottom of the cell trench, ensure the reliability of the gate oxide layer at the bottom of the cell trench, reduce the channel on-resistance, and be compatible with the existing process and safe and reliable.

[0008] According to the technical scheme provided by the present application, the high-reliability SiC trench type power semiconductor device comprises a SiC semiconductor substrate of a first conductivity type and a cell region prepared in the center region of the SiC semiconductor substrate, the cell region comprises a plurality of parallel distributed cells, and the cells in the cell region adopt a trench structure;

[0009] On the top view plane of the power semiconductor device, a plurality of second conductivity type doped buried layers transversing the cell region are arranged in the cell region, the second conductivity type doped buried layers are arranged in sequence and parallel to each other in the cell region; the cell trenches in the cell region are long strip-shaped and parallel to each other, and the length direction of the cell trenches is perpendicular to the length direction of the second conductivity type doped buried layers;

[0010] On the cross-section of the power semiconductor device, the second conductivity type doped buried layer includes a first buried layer main surface and a second buried layer main surface corresponding to the first buried layer main surface, wherein the second buried layer main surface corresponds to the back side of the SiC semiconductor substrate, and the depth of the second buried layer main surface of the second conductivity type doped buried layer is not less than the bottom depth of the cell trench.

[0011] On the top view of the power semiconductor device, the width of the second conductivity type doped buried layer is 0.5 μm to 5 μm.

[0012] On the top view plane of the power semiconductor device, the spacing between adjacent second conductivity type doped buried layers is 0.5 μm to 5 μm.

[0013] A second conductivity type base region is provided within the cell region, which is transverse to the cell region. A cell trench penetrates the second conductivity type base region, and the bottom of the cell trench is located below the second conductivity type base region.

[0014] On the cross-section of the power semiconductor device, a second conductivity type base region is located on both sides of a cell trench and is in contact with the outer wall of the cell trench; a first conductivity type source region is disposed in the second conductivity type base region on both sides of the cell trench, and the first conductivity type source region is in contact with the outer wall of the cell trench; a trench gate unit is disposed in the cell trench, and the first conductivity type source region and the second conductivity type base region are electrically connected to the source metal on the front side of the SiC semiconductor substrate.

[0015] The second conductivity type base region is located above the first main surface of the buried layer of the second conductivity type doped buried layer, or the second conductivity type base region is in contact with the second conductivity type doped buried layer.

[0016] The trench gate cell includes gate conductive polysilicon filled in the cell trench. The gate conductive polysilicon is insulated from the sidewalls and bottom wall of the cell trench by a gate oxide layer covering the inner sidewalls and bottom wall of the cell trench. The gate conductive polysilicon is insulated from the source metal by an insulating dielectric layer covering the trench opening.

[0017] It also includes a back electrode structure fabricated on the back side of a SiC semiconductor substrate, so that the power semiconductor device formed is a MOSFET device or an IGBT device.

[0018] The SiC semiconductor substrate includes a first conductivity type drift region and a first conductivity type substrate adjacent to the first conductivity type drift region. The back side of the SiC semiconductor substrate is formed using the corresponding surface of the first conductivity type substrate, and the front side corresponding to the back side of the SiC semiconductor substrate is formed using the corresponding surface of the first conductivity type drift region. The cell region corresponds to the first conductivity type drift region.

[0019] A method for fabricating a high-reliability SiC trench power semiconductor device, the method comprising the following steps:

[0020] Step 1: Provide a SiC semiconductor substrate of a first conductivity type, wherein the SiC semiconductor substrate includes a plurality of doped buried layers of a second conductivity type, the doped buried layers of the second conductivity type correspond to the cell regions of the SiC semiconductor substrate, and the doped buried layers of the second conductivity type are arranged sequentially and parallel to each other in the cell regions.

[0021] Step 2: Prepare the required front cell structure in the cell region of the SiC semiconductor substrate. The cells of the front cell structure adopt a trench structure. The cell trenches in the cell region are elongated and parallel to each other. The length direction of the cell trenches is perpendicular to the length direction of the second conductivity type doped buried layer.

[0022] On the cross section where the front cell structure is prepared, the second conductivity type doped buried layer includes a first buried layer main surface and a second buried layer main surface that corresponds to the first buried layer main surface. The second buried layer main surface corresponds to the back side of the SiC semiconductor substrate, and the depth of the second buried layer main surface of the second conductivity type doped buried layer is not less than the bottom depth of the cell trench.

[0023] The second type of conductivity doped buried layer is prepared by epitaxial growth process or by implantation of second type of conductivity impurity ions.

[0024] For N-type power semiconductor devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type. For P-type power semiconductor devices, the first conductivity type and the second conductivity type refer to the opposite types as those for N-type semiconductor devices.

[0025] Advantages of this invention: The length direction of the second conductivity type doped buried layer is perpendicular to the length direction of the cell trench. The depth of the second conductivity type doped buried layer in the drift region of the first conductivity type is not less than the depth of the cell trench. The doped buried layer can protect the cell trench, preventing a high electric field from appearing at the bottom of the cell trench. The front cell structure above the second conductivity type doped buried layer can be the same as that of existing SiC trench power semiconductor devices. Therefore, the cross-section of the channel conduction path of the formed power semiconductor device is not affected. The spacing between the second conductivity type doped buried layers and the pitch between the cell trenches are independent, allowing for increased channel density by reducing the pitch, thereby reducing channel resistance. This meets the high reliability design requirements of low electric field strength at the bottom of the cell trench, is compatible with existing processes, and is safe and reliable. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of an existing SiC trench power MOSFET device.

[0027] Figure 2 This is a schematic diagram of another existing SiC trench power MOSFET device.

[0028] Figure 3 This is a top view of the cell region of the present invention.

[0029] Figure 4 for Figure 3 Sectional view along line AB.

[0030] Figure 5 for Figure 3 The CD-direction section view.

[0031] Explanation of reference numerals in the attached figures: 1-N-type drift region, 2-N+ substrate, 3-cell trench, 4-gate oxide layer, 5-gate conductive polysilicon, 6-P-type base region, 7-insulating dielectric layer, 8-source metal, 9-N+ source region, 10-P-type implanted buried layer, 11-drain metal layer, 12-deep P-type doped base region, 13-P-type doped buried layer. Detailed Implementation

[0032] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0033] like Figure 3 , Figure 4 and Figure 5 As shown: In order to effectively reduce the electric field at the bottom of the cell trench, ensure the reliability of the gate oxide layer at the bottom of the cell trench, and reduce the channel on-resistance, taking an N-type power semiconductor device as an example, the present invention includes an N-type SiC semiconductor substrate and a cell region prepared in the central region of the SiC semiconductor substrate. The cell region includes a plurality of parallel distributed cells, and the cells in the cell region adopt a trench structure.

[0034] On the top view of the power semiconductor device, a plurality of P-type doped buried layers 13 are disposed in the cell region, which are arranged in sequence and parallel to each other in the cell region; the cell trenches 3 in the cell region are elongated and parallel to each other, and the length direction of the cell trenches 3 is perpendicular to the length direction of the P-type doped buried layers 13.

[0035] On the cross-section of the power semiconductor device, the P-type doped buried layer 13 includes a first main surface of the buried layer and a second main surface of the buried layer that corresponds to the first main surface of the buried layer. The second main surface of the buried layer corresponds to the back side of the SiC semiconductor substrate. The depth of the second main surface of the P-type doped buried layer 13 is not less than the bottom depth of the cell trench 3.

[0036] Specifically, the SiC semiconductor substrate is a substrate made of SiC material, and the specific details of the SiC semiconductor substrate can be consistent with existing ones. Figure 1 , Figure 2 , Figure 4 and Figure 5 The image illustrates a specific embodiment of a SiC semiconductor substrate, wherein the SiC semiconductor substrate includes an N-type drift region 1 and an N+ substrate 2 adjacent to the N-type drift region 1. The back side of the SiC semiconductor substrate is formed using the corresponding surface of the N+ substrate 2, and the front side corresponding to the back side of the SiC semiconductor substrate is formed using the corresponding surface of the N-type drift region 1. The cell regions correspond to the drift regions of the first conductivity type.

[0037] Generally, the doping concentration of the N+ substrate 2 is greater than that of the N-type drift region 1, and the thickness of the N-type drift region 1 is greater than that of the N+ substrate 2. The N+ substrate 2 is adjacent to the N-type drift region 1. After adjacency, the surface of the N-type drift region 1 is used to form the front side of the SiC semiconductor substrate, and the corresponding surface of the N+ substrate 2 is used to form the back side of the SiC semiconductor substrate. The front side and the back side of the SiC semiconductor substrate correspond directly. The cell region is generally fabricated in the N-type drift region 1, and the cell region is located in the central region of the N-type drift region 1.

[0038] In specific implementation, the cell region includes several cells, which are distributed in parallel. The cells in the cell region adopt a trench structure, and the cell trenches are located in the N-type drift region 1. That is, the front cell structure of the power semiconductor device is fabricated in the N-type drift region 1.

[0039] In the top view of the power semiconductor device, in this embodiment of the invention, the cell trenches 3 within the cell region are elongated strips, and multiple elongated cell trenches 3 are parallel to each other. The spacing between adjacent cell trenches 3 can be equal or vary according to a preset distance to meet the actual application scenario, which will not be elaborated here. Specifically, a P-type doped buried layer 13 is also provided within the cell region. The P-type doped buried layer 13 traverses the cell region, that is, the length of the P-type doped buried layer 13 corresponds to the area size of the cell region. Generally, the length of the P-type doped buried layer 13 is consistent with or slightly smaller than the first length direction of the cell region. The length of the cell trenches 3 within the cell region corresponds to the second length direction of the cell region. Generally, the length of the cell trenches 3 is smaller than the second length direction of the cell region. The cell region can be rectangular or square; therefore, the first length direction and the second length direction of the cell region are two mutually perpendicular directions.

[0040] In this embodiment of the invention, P-type doped buried layers 13 are arranged sequentially along the first length direction of the cell region, and the P-type doped buried layers 13 are parallel to each other. Therefore, as can be seen from the above description, the length direction of any cell trench 3 is perpendicular to the length direction of any P-type doped buried layer 13.

[0041] In the cross-section of the power semiconductor device, the P-type doped buried layer 13 has a first buried layer main surface and a second buried layer main surface. The first buried layer main surface and the second buried layer main surface are directly opposite each other, and the direction from the first buried layer main surface to the second buried layer main surface is consistent with the thickness direction of the SiC semiconductor substrate. The first buried layer main surface corresponds to the front side of the SiC semiconductor substrate, and the second buried layer main surface corresponds to the back side of the SiC semiconductor substrate. In a specific implementation, the depth of the second buried layer main surface of the P-type doped buried layer 13 is not less than the bottom depth of the cell trench 3, that is, the second buried layer main surface of the P-type doped buried layer 13 is not located above the bottom of the cell trench 3, so that the second buried layer main surface of the P-type doped buried layer 13 is flush with the bottom of the cell trench 3, or the second buried layer main surface of the P-type doped buried layer 13 is located below the bottom of the cell trench 3. When the second main surface of the P-type doped buried layer 13 is located below the bottom of the cell trench 3, the first main surface of the P-type doped buried layer 13 can also be located below the bottom of the cell trench 3. The specific matching relationship between the P-type doped buried layer 13 and the cell trench 3 can be selected according to the needs, based on the actual application scenario.

[0042] In summary, when the length direction of any P-type doped buried layer 13 is perpendicular to the length direction of the cell trench 3, and the depth of the P-type doped buried layer 13 in the N-type drift region 1 is not less than the depth of the cell trench 3, the P-type doped buried layer 13 can be used to protect the cell trench 3, preventing a high electric field from appearing at the bottom of the cell trench 3. The front cell structure above the P-type doped buried layer 13 can be the same as that of existing SiC trench power semiconductor devices. Therefore, the cross-section of the channel conduction path of the formed power semiconductor device will not be affected. The spacing between the P-type doped buried layers 13 and the pitch between the cell trenches 3 are independent of each other, so the channel density can be increased by reducing the pitch, thereby reducing the channel resistance to meet the high reliability design requirements of low electric field strength at the bottom of the cell trench 3.

[0043] Further, in the top view of the power semiconductor device, the width of the P-type doped buried layer 13 is 0.5 μm to 5 μm. In this embodiment of the invention, the width of the P-type doped buried layer 13 in the top view specifically refers to the width along the length direction of the cell trench 3. In the top view of the power semiconductor device, the spacing between adjacent P-type doped buried layers 13 is 0.5 μm to 5 μm. The spacing between adjacent P-type doped buried layers 13 specifically refers to the distance between adjacent P-type doped buried layers 13 along the length direction of the cell trench 3. In this embodiment of the invention, by adjusting the spacing between the P-type doped buried layers 13, the shielding effect of the JFET structure on the bottom of the cell trench 3 can be effectively adjusted, thereby further reducing the electric field strength at the bottom of the cell trench 3.

[0044] Furthermore, a P-type base region 6 is provided in the cell region, which runs through the cell region, and a cell trench 3 runs through the P-type base region 6, with the bottom of the cell trench 3 located below the P-type base region 6.

[0045] On the cross-section of the power semiconductor device, the P-type base region 6 is located on both sides of the cell trench 3 and is in contact with the outer wall of the cell trench 3; N+ source regions 9 are disposed in the P-type base regions 6 on both sides of the cell trench 3, and the N+ source regions 9 are in contact with the outer wall of the cell trench 3; trench gate units are disposed in the cell trench 3, and the N+ source region 9 and the P-type base region 6 are electrically connected to the source metal 8 on the front side of the SiC semiconductor substrate.

[0046] In this embodiment of the invention, a P-type base region 6 is also provided within the cell region, and the P-type base region 6 also extends transversely through the cell region. The P-type base region 6 generally extends vertically downwards from the front side of the SiC semiconductor substrate. After fabricating the cell trench 3, the cell trench 3 penetrates the P-type base region 6, and the bottom of the cell trench 3 is located below the P-type base region 6. Furthermore, an N+ source region 9 is provided within each of the P-type base regions 6 on both sides of the cell trench 3. Both the N+ source region 9 and the P-type base region 6 are in contact with the outer wall of the cell trench 3. Generally, the P-type base region 6 fills the cell region, or the length direction of the P-type base region 6 is consistent with the corresponding length direction of the cell trench 3.

[0047] In specific implementation, the N+ source region 9 and the P-type base region 6 are electrically connected to the source metal 8 on the front side of the SiC semiconductor substrate. The source electrode of the power semiconductor device is formed through the electrical connection between the source metal 8 and the N+ source region 9 and the P-type base region 6. The gate electrode of the power semiconductor device is formed by electrically connecting the trench gate unit within the cell trench 3 to the gate metal on the upper front side of the SiC semiconductor substrate. The specific methods for forming the gate electrode and source electrode can be consistent with existing methods and can be selected and determined according to actual needs; these will not be elaborated further here.

[0048] Figure 1 , Figure 2 , Figure 4 andFigure 5 This illustration shows a specific embodiment of a trench gate cell. Specifically, the trench gate cell includes a gate conductive polysilicon 5 filled within a cell trench 3. The gate conductive polysilicon 5 is insulated from the sidewalls and bottom wall of the cell trench 3 by a gate oxide layer 4 covering the inner sidewalls and bottom wall of the cell trench 5. The gate conductive polysilicon 5 is also insulated from the source metal 8 by an insulating dielectric layer 7 covering the opening of the cell trench 3. Of course, in specific implementations, the trench gate cell can also adopt other forms, such as a shielded gate, which can be selected according to needs to meet the requirements of the actual application scenario.

[0049] Furthermore, the P-type base region 6 is located above the first main surface of the P-type doped buried layer 13, or the P-type base region 6 is in contact with the P-type doped buried layer 13. In this embodiment of the invention, when the P-type base region 6 is located above the first main surface of the P-type doped buried layer 13, the P-type base region 6 and the P-type doped buried layer 13 do not contact each other. Of course, in specific implementations, the P-type base region 6 may contact the P-type doped buried layer 13. When the P-type doped buried layer 13 and the P-type base region 6 do not contact each other, the channel resistance of the power semiconductor device is the lowest and the performance is the best. That is, in specific implementations, it is preferable that the P-type doped buried layer 13 and the P-type base region 6 do not contact each other.

[0050] Furthermore, it also includes a back electrode structure fabricated on the back side of the SiC semiconductor substrate, so that the power semiconductor device formed is a MOSFET device or an IGBT device.

[0051] In this embodiment of the invention, the back electrode structure is fabricated on the back side of the SiC semiconductor substrate, i.e., it is adapted and connected to the N+ substrate 2. Depending on the back electrode structure, the power semiconductor device can be a MOSFET device or an IGBT device. Figure 1 , Figure 2 , Figure 4 and Figure 5 The diagram illustrates one specific implementation of the back electrode structure, in which the back electrode structure includes a drain metal layer 11 that has a 2-ohm contact with the N+ substrate. In this case, the formed power semiconductor device is a MOSFET device. When an IGBT device needs to be formed, the back electrode structure can be adjusted, which will not be described in detail here.

[0052] The trench-type power semiconductor device described above can be fabricated using the following process steps. Specifically, the fabrication method of the power semiconductor device includes the following steps:

[0053] Step 1: Provide an N-type SiC semiconductor substrate, wherein the SiC semiconductor substrate includes a plurality of P-type doped buried layers 13, the P-type doped buried layers 13 correspond to the cell regions of the SiC semiconductor substrate, and the P-type doped buried layers 13 are arranged sequentially and parallel to each other in the cell regions.

[0054] Specifically, the SiC semiconductor substrate includes an N+ substrate 2 and an N-type drift region 1 located above the N+ substrate 2, with a P-type doped buried layer 13 located within the N-type drift region 1. In practice, the P-type doped buried layer 13 is prepared by epitaxial growth or by implanting P-type impurity ions. The specific process conditions and procedures for epitaxial growth and P-type impurity ion implantation can be consistent with existing methods, aiming to form the required number of P-type doped buried layers 13. Specific process conditions and procedures will not be elaborated here.

[0055] Regardless of whether epitaxial growth or P-type impurity ion implantation is used, the specific details of the resulting P-type doped buried layer 13 can be found in the above description and will not be repeated here.

[0056] Step 2: Prepare the required front cell structure in the cell region of the above-mentioned SiC semiconductor substrate. The cells of the front cell structure adopt a trench structure. The cell trenches 3 in the cell region are elongated and parallel to each other. The length direction of the cell trenches 3 is perpendicular to the length direction of the P-type doped buried layer 13.

[0057] On the cross section where the front cell structure is prepared, the P-type doped buried layer 13 includes a first main buried surface and a second main buried surface that corresponds to the first main buried surface. The second main buried surface corresponds to the back side of the SiC semiconductor substrate, and the depth of the second main buried surface of the P-type doped buried layer 13 is not less than the bottom depth of the cell trench 3.

[0058] Specifically, the frontal cell structure can be prepared by the technical means commonly used in this field, that is, the desired cell can be obtained. The cell includes cell trench 3. The specific details of cell trench 3 and its relationship with the P-type doped buried layer 13 can be referred to the above description, and will not be repeated here.

[0059] In addition, in specific implementation, the formed front cell structure also includes source metal 8, etc. After the front cell structure is prepared, a back electrode process is performed on the back side of the SiC semiconductor substrate to prepare the required back electrode structure. The specific details of the back electrode structure can be referred to the above description, and will not be repeated here.

Claims

1. A high-reliability SiC trench power semiconductor device, comprising a SiC semiconductor substrate of a first conductivity type and a cell region prepared in a central region of the SiC semiconductor substrate, the cell region comprising a plurality of parallelly distributed cells, the cells in the cell region being in a trench structure; characterized in that: on a top plane of the power semiconductor device, a plurality of second-conductivity-type doped buried layers are arranged in the cell region and cross the cell region, the second-conductivity-type doped buried layers are arranged in sequence and parallel to each other in the cell region, the cell trenches in the cell region are in a strip shape and parallel to each other, and the length direction of the cell trenches is perpendicular to the length direction of the second-conductivity-type doped buried layers; on a cross section of the power semiconductor device, the second-conductivity-type doped buried layer comprises a buried layer first main surface and a buried layer second main surface opposite to the buried layer first main surface, wherein the buried layer second main surface is opposite to the back surface of the SiC semiconductor substrate, and the depth of the buried layer second main surface of the second-conductivity-type doped buried layer is not less than the depth of the bottom of the cell trench; on the top plane of the power semiconductor device, the width of the second-conductivity-type doped buried layer is 0.5 μm to 5 μm; a second-conductivity-type base region is arranged in the cell region and crosses the cell region, the cell trench penetrates the second-conductivity-type base region, and the bottom of the cell trench is below the second-conductivity-type base region; on the cross section of the power semiconductor device, the second-conductivity-type base region is located on both sides of the cell trench and in contact with the outer side wall of the cell trench; a first-conductivity-type source region is arranged in the second-conductivity-type base region on both sides of the cell trench and in contact with the outer side wall of the cell trench; a trench gate unit is arranged in the cell trench, the first-conductivity-type source region and the second-conductivity-type base region are electrically connected to the source metal on the front surface of the SiC semiconductor substrate; and the second-conductivity-type base region is above the buried layer first main surface of the second-conductivity-type doped buried layer. On the top plane of the power semiconductor device, the spacing between adjacent second-conductivity-type doped buried layers is 0.5 μm to 5 μm. The trench gate unit comprises gate-conducting polysilicon filled in the cell trench, the gate-conducting polysilicon is insulated and separated from the side wall and bottom wall of the cell trench by a gate oxide layer covering the side wall and bottom wall of the cell trench, and the gate-conducting polysilicon is insulated and separated from the source metal by an insulating dielectric layer covering the opening of the cell trench. Further comprising a back electrode structure prepared on the back surface of the SiC semiconductor substrate, so that the formed power semiconductor device is a MOSFET device or an IGBT device by using the back electrode structure. The SiC semiconductor substrate comprises a first-conductivity-type drift region and a first-conductivity-type substrate adjacent to the first-conductivity-type drift region, the back surface of the SiC semiconductor substrate is formed by using the corresponding surface of the first-conductivity-type substrate, the front surface opposite to the back surface of the SiC semiconductor substrate is formed by using the corresponding surface of the first-conductivity-type drift region, and the cell region is opposite to the first-conductivity-type drift region. The preparation method of the power semiconductor device in the above claim 1 comprises the following steps: ​ 2. The high-reliability SiC trench power semiconductor device of claim 1, wherein: ​ 3. The high-reliability SiC trench power semiconductor device of claim 1, wherein: ​ 4. The high-reliability SiC trench power semiconductor device according to any one of claims 1 to 2, characterized by: ​ 5. The high-reliability SiC trench power semiconductor device according to any one of claims 1 to 2, characterized by: ​ 6. A method of manufacturing a high-reliability SiC trench power semiconductor device, characterized by comprising: ​ ​ Step 1, providing a SiC semiconductor substrate of a first conductive type, wherein the SiC semiconductor substrate comprises a plurality of second conductive type doped buried layers, the second conductive type doped buried layers correspond to cell regions of the SiC semiconductor substrate, the second conductive type doped buried layers are arranged in sequence and parallel to each other in the cell regions; Step 2, preparing a required front cell structure in the cell regions of the SiC semiconductor substrate, wherein the cells of the front cell structure adopt a trench structure, the cell trenches in the cell regions are in a strip shape and parallel to each other, and the length direction of the cell trenches is perpendicular to the length direction of the second conductive type doped buried layers; In the cross section of the prepared front cell structure, the second conductive type doped buried layer comprises a buried layer first main surface and a buried layer second main surface corresponding to the buried layer first main surface, wherein the buried layer second main surface corresponds to the back surface of the SiC semiconductor substrate, and the depth of the buried layer second main surface of the second conductive type doped buried layer is not less than the bottom depth of the cell trench.

7. The method of claim 6, wherein the method further comprises: The second conductive type doped buried layer is prepared by an epitaxial growth process or by implanting second conductive type impurity ions. ​

Images