Memory structure and its formation method

Abstract

A memory structure and a method for forming the same are disclosed. The memory structure includes: a substrate; a word line structure on the substrate; gate structures on both sides of the word line structure, the gate structures including a floating gate structure and a control gate structure on the floating gate structure; and a first metal silicide layer on the top surface of the control gate structure. The first metal silicide layer on the top surface of the control gate structure effectively reduces the resistance of the control gate structure, thereby reducing the number of conductive plugs, resulting in a smaller area of ​​the final memory structure and improved device integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and its formation method. Background Technology

[0002] NOR flash memory, developed based on Intel's ETOX architecture, is a type of non-volatile memory, meaning it retains its data even after power is off. NOR flash memory is also a voltage-controlled device, using hot electron injection to write data and tunneling to erase it. A significant characteristic is its high random access speed. As a non-volatile memory, NOR flash memory offers advantages such as non-volatility, high device density, low power consumption, and electrical rewritability, making it widely used in portable electronic products such as mobile phones, digital cameras, and smart cards.

[0003] Flash memory cells have a structure similar to MOS devices, storing charge through floating gates and dielectric layers. The access of electrons in the floating gate causes a change in the device's threshold voltage, thus representing the state of the Flash memory cell. NorFlash arrays are connected together by horizontal gates, called word lines. The drains are connected to vertical metal lines through contact holes, called bit lines. The sources of two adjacent devices are connected together, forming horizontal source lines.

[0004] However, existing Nor Flash devices still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a memory structure and a method for forming the same, so as to reduce the resistance of the control gate structure, thereby reducing the number of conductive plugs, reducing the area of ​​the final memory structure, and improving the integration of the device.

[0006] To address the aforementioned problems, the present invention provides a memory structure comprising: a substrate; a word line structure located on the substrate; gate structures located on both sides of the word line structure, the gate structure comprising a floating gate structure and a control gate structure located on the floating gate structure; and a first metal silicide layer located on the top surface of the control gate structure.

[0007] Optionally, it may also include a second metal silicide layer located on the top surface of the word line structure.

[0008] Optionally, the material of the first metal silicide layer includes nickel silicide or platinum silicide; the material of the second metal silicide layer includes nickel silicide or platinum silicide.

[0009] Optionally, it further includes: a sidewall layer located on the control gate structure, the sidewall layer exposing a portion of the top surface of the control gate structure; the first metal silicide layer located on the exposed top surface of the control gate structure.

[0010] Optionally, the floating gate structure includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewall of the floating gate layer.

[0011] Optionally, the control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewall of the control gate layer.

[0012] Optionally, the first gate dielectric layer and the second gate dielectric layer are single-layer structures or multi-layer structures.

[0013] Optionally, when the first gate dielectric layer and the second gate dielectric layer are multilayer structures, the first gate dielectric layer and the second gate dielectric layer respectively include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0014] Optionally, the material of the word line structure is a semiconductor material, including polycrystalline silicon.

[0015] Accordingly, the present invention also provides a method for forming a memory structure, comprising: providing a substrate; forming a word line structure and gate structures located on both sides of the word line structure on the substrate, the gate structure including a floating gate structure and a control gate structure located on the floating gate structure, the gate structure having a sidewall layer; etching the sidewall layer using an anisotropic dry etching process to expose the top surface of the control gate structure; and forming a first metal silicide layer on the top surface of the control gate structure.

[0016] Optionally, during the process of forming the first metal silicide layer on the top surface of the control gate structure, the method further includes forming a second metal silicide layer on the top surface of the word line structure.

[0017] Optionally, the floating gate structure includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewall of the floating gate layer.

[0018] Optionally, the control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewall of the control gate layer.

[0019] Optionally, the method for forming the word line structure and the gate structures located on both sides of the word line structure includes: forming a floating gate material layer on the substrate; forming a control gate material layer on the floating gate material layer; forming a patterned layer on the control gate material layer, the patterned layer having a patterned opening that exposes a portion of the control gate material layer; forming a sidewall layer on the sidewall of the patterned opening; etching the control gate material layer using the patterned layer and the sidewall layer as a mask until the top surface of the floating gate material layer is exposed, forming two initial control gate structures, with an initial second opening between the two initial control gate structures; and forming a sidewall layer on the sidewall of the initial control gate structure exposed by the initial second opening. A second gate dielectric layer is formed to form two control gate structures, such that the initial second opening forms the second opening; after forming the control gate structures, the floating gate material layer is etched using the patterning layer, sidewall layer, and second gate dielectric layer as masks until the top surface of the substrate is exposed, forming two initial floating gate structures with an initial first opening between them; a second tunneling oxide layer is formed on the sidewall of the initial floating gate structure exposed by the initial first opening and on the top surface of the substrate, forming two floating gate structures, such that the initial first opening forms the first opening; the word line structure is formed within the first opening and the second opening.

[0020] Optionally, after forming the word line structure and before forming the first metal silicide layer, the method further includes: removing the patterning layer, and etching the control gate structure and the floating gate structure using the sidewall layer and the word line structure as a mask until the top surface of the substrate is exposed.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the memory structure of the present invention, the resistance of the control gate structure can be effectively reduced by the first metal silicide layer located on the top surface of the control gate structure, thereby reducing the number of conductive plugs, reducing the area of ​​the final memory structure, and improving the integration of the device.

[0023] Furthermore, it also includes a second metal silicide layer located on the top surface of the word line structure. The second metal silicide layer can effectively reduce the resistance of the word line structure, thereby improving the electrical performance of the final memory structure.

[0024] In the method for forming a memory structure according to the technical solution of the present invention, by forming a first metal silicide layer on the top surface of the control gate structure, the resistance of the control gate structure can be effectively reduced, thereby reducing the number of conductive plugs, resulting in a smaller area of ​​the final memory structure and improving the integration of the device.

[0025] Furthermore, using an anisotropic dry etching process to etch the sidewall layer, combined with a photomask, allows for more precise removal of the sidewall layer located on the control gate structure. In contrast, wet etching is isotropic, which can cause etching damage to the sidewalls of the floating gate structure, such as lateral hollowing out the first tunneling oxide layer, leading to increased leakage current and a shift in device performance. Moreover, the anisotropic dry etching process, combined with a photomask, can etch only the memory region without affecting the logic region, minimizing the impact on the device.

[0026] Furthermore, during the process of forming the first metal silicide layer on the top surface of the control gate structure, the method further includes forming a second metal silicide layer on the top surface of the word line structure. The second metal silicide layer effectively reduces the resistance of the word line structure, thereby improving the electrical performance of the final memory structure. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a memory structure.

[0028] Figures 2 to 11 This is a schematic diagram of the steps in the method for forming the memory structure in an embodiment of the present invention;

[0029] Figures 12 to 13 This is a schematic diagram of the steps in the method for forming a memory structure according to another embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, existing Nor Flash devices still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of a memory structure.

[0032] Please refer to Figure 1In a segmented-gate flash memory device, each word line structure (not shown) has a control gate structure (not shown) on both sides. To reduce resistance while ensuring transmission efficiency, a conductive plug 100 is required every 128 bits to connect the control gate structure. However, as the number of conductive plugs 100 increases, they occupy a large area, approximately 13% of the 128-bit area, resulting in a large area occupied by the final segmented-gate flash memory device and affecting the device's integration density.

[0033] Based on this, the present invention provides a memory structure and its formation method. By using a first metal silicide layer located on the top surface of the control gate structure, the resistance of the control gate structure can be effectively reduced, thereby reducing the number of conductive plugs and resulting in a smaller area of ​​the final memory structure, improving device integration. Furthermore, an anisotropic dry etching process is used to etch the sidewall layer, and with the help of a photomask, the sidewall layer on the control gate structure can be removed more precisely. In contrast, wet etching is isotropic, which can cause etching damage to the sidewalls of the floating gate structure, such as causing side penetration of the first tunneling oxide layer of the floating gate structure, leading to increased leakage current and a shift in device performance. Moreover, the anisotropic dry etching process, combined with a photomask, can only etch the memory region without affecting the logic region, minimizing the impact on the device.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 11 This is a schematic diagram of the steps in the method for forming the memory structure in an embodiment of the present invention.

[0036] Please refer to Figure 2 Substrate 200 is provided.

[0037] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0038] In this embodiment, after providing the substrate 200, the method further includes: forming a word line structure and gate structures located on both sides of the word line structure on the substrate 200. The gate structure includes a floating gate structure and a control gate structure located on the floating gate structure, and the gate structure has a sidewall layer. For a detailed formation process, please refer to [reference needed]. Figures 3 to 9 .

[0039] Please refer to Figure 3 A floating gate material layer 201 is formed on the substrate 200; a control gate material layer 202 is formed on the floating gate material layer 201.

[0040] In this embodiment, the floating gate material layer 201 is formed using an atomic layer deposition process.

[0041] In this embodiment, the control gate material layer 202 is formed using an atomic layer deposition process.

[0042] In this embodiment, the floating gate material layer 201 and the control gate material layer 202 are used to subsequently form the floating gate structure and the control gate structure through patterning processing.

[0043] Please refer to Figure 4 A patterned layer 203 is formed on the control gate material layer 202, and the patterned layer 206 has a patterned opening 204 that exposes a portion of the control gate material layer 202.

[0044] In this embodiment, the patterned layer 203 includes: a first mask layer (not shown) and a second mask layer (not shown) located on the first mask layer, wherein the first mask layer and the second mask layer have the patterned opening 204.

[0045] In this embodiment, the first mask layer is made of silicon nitride, and the second mask layer is made of silicon oxide.

[0046] Please refer to Figure 5 The sidewall layer 205 is formed on the sidewall of the patterned opening 204.

[0047] In this embodiment, the method for forming the sidewall layer 205 includes: forming a sidewall material layer (not shown) on the sidewall and bottom surface of the patterned opening 204 and the patterned layer 203; and etching the sidewall material layer back until the top surface of the patterned layer 203 and the control gate material layer 202 is exposed, thereby forming the sidewall layer 205.

[0048] In this embodiment, the sidewall layer 205 is made of silicon oxide.

[0049] Please refer to Figure 6 Using the patterning layer 203 and the sidewall layer 205 as masks, the control gate material layer 202 is etched until the top surface of the floating gate material layer 201 is exposed, forming two initial control gate structures (not shown). An initial second opening (not shown) is formed between the two initial control gate structures. A second gate dielectric layer (not shown) is formed on the sidewall of the initial control gate structure exposed by the initial second opening, forming two control gate structures 206, and the initial second opening forms the second opening 207.

[0050] In this embodiment, the control gate structure 206 includes: a first gate dielectric layer (not shown), a control gate layer (not shown) located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewall of the control gate layer.

[0051] In this embodiment, the first gate dielectric layer and the second gate dielectric layer are multilayer structures. Specifically, the first gate dielectric layer and the second gate dielectric layer each include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0052] The first silicon oxide layer and the second silicon oxide layer can bond well with the base crystal, while the silicon nitride layer is in the middle and can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0053] In other embodiments, the first gate dielectric layer and the second gate dielectric layer may also be a single-layer structure.

[0054] In this embodiment, the process of etching the control gate material layer 202 using the patterned layer 203 and the sidewall layer 205 as masks is a wet etching process; in other embodiments, the process of etching the control gate material layer using the patterned layer and the sidewall layer as masks can also be a dry etching process.

[0055] Please refer to Figure 7 After forming the control gate structure 206, the floating gate material layer 201 is etched using the patterning layer 203, sidewall layer 205, and second gate dielectric layer as masks until the top surface of the substrate 200 is exposed, forming two initial floating gate structures (not shown). An initial first opening (not shown) is formed between the two initial floating gate structures. A second tunneling oxide layer (not shown) is formed on the sidewall of the initial floating gate structure exposed by the initial first opening and on the top surface of the substrate 200, forming two floating gate structures 208, and causing the initial first opening to form the first opening 209.

[0056] In this embodiment, the floating gate structure 208 includes: a first tunneling oxide layer (not shown), a floating gate layer (not shown) located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewall of the floating gate layer;

[0057] In this embodiment, the process of etching the floating gate material layer 201 using the patterning layer 203, sidewall layer 205, and second gate dielectric layer as masks is a wet etching process; in other embodiments, the process of etching the floating gate material layer using the patterning layer, sidewall layer, and second gate dielectric layer as masks can also be a dry etching process.

[0058] Please refer to Figure 8 A character line structure 210 is formed within the first opening 209 and the second opening 207.

[0059] In this embodiment, the method for forming the character line structure 210 includes: forming a character line material layer (not shown) in the first opening 209 and the second opening 207 and on the patterning layer 203; and planarizing the character line material layer until the top surface of the patterning layer 203 is exposed, thereby forming the character line structure 210.

[0060] In this embodiment, the word line structure 210 is made of a semiconductor material. Specifically, the semiconductor material is polycrystalline silicon.

[0061] In this embodiment, the planarization process employs a chemical mechanical masking process.

[0062] Please refer to Figure 9 Remove the patterning layer 203, and etch the control gate structure 206 and the floating gate structure 208 using the sidewall layer 205 and the word line structure 210 as masks until the top surface of the substrate 200 is exposed.

[0063] In this embodiment, the process of etching the control gate structure 206 and the floating gate structure 208 using the sidewall layer 205 and the word line structure 210 as masks is a dry etching process.

[0064] Please refer to Figure 10 The sidewall layer 205 is etched using an anisotropic dry etching process to expose the top surface of the control gate structure 206.

[0065] In this embodiment, an anisotropic dry etching process is used to etch the sidewall layer 205. Combined with a photomask, this allows for precise removal of the sidewall layer 205 located on the control gate structure 206. In contrast, wet etching is isotropic, which can cause etching damage to the sidewalls of the floating gate structure 208, such as lateral hollowing out the first tunneling oxide layer, leading to increased leakage current and a shift in device performance. Furthermore, the anisotropic dry etching process, combined with a photomask, allows etching only the memory region without affecting the logic region, minimizing the impact on the device.

[0066] In this embodiment, an anisotropic dry etching process is used to remove all of the sidewall layer 205.

[0067] Please refer to Figure 11 A first metal silicide layer 211 is formed on the top surface of the control gate structure 206.

[0068] In this embodiment, by forming a first metal silicide layer 211 on the top surface of the control gate structure 206, the resistance of the control gate structure 206 can be effectively reduced, thereby reducing the number of conductive plugs, resulting in a smaller area of ​​the final memory structure and improved device integration.

[0069] Please continue to refer to this. Figure 11 In this embodiment, during the process of forming the first metal silicide layer 211 on the top surface of the control gate structure 206, the method further includes forming a second metal silicide layer 212 on the top surface of the word line structure 210. The second metal silicide layer 212 can effectively reduce the resistance of the word line structure 210, thereby improving the electrical performance of the final memory structure.

[0070] In this embodiment, the first metal silicide layer 211 is made of nickel silicide, and the second metal silicide layer 212 is also made of nickel silicide. In other embodiments, the first metal silicide layer may also be made of platinum silicide, and the second metal silicide layer may also be made of platinum silicide.

[0071] Accordingly, an embodiment of the present invention also provides a memory structure, please refer to [link / reference needed]. Figure 11 The present invention includes: a substrate 200; a word line structure 210 located on the substrate 200; gate structures located on both sides of the word line structure 210, the gate structures including a floating gate structure 208 and a control gate structure 206 located on the floating gate structure 208; and a first metal silicide layer 211 located on the top surface of the control gate structure 206.

[0072] In this embodiment, the resistance of the control gate structure 206 can be effectively reduced by the first metal silicide layer 211 located on the top surface of the control gate structure 206, thereby reducing the number of conductive plugs, reducing the area of ​​the final memory structure, and improving the integration of the device.

[0073] In this embodiment, a second metal silicide layer 212 is further included on the top surface of the word line structure 210. The second metal silicide layer 212 can effectively reduce the resistance of the word line structure 210, thereby improving the electrical performance of the final memory structure.

[0074] In this embodiment, the first metal silicide layer 211 is made of nickel silicide, and the second metal silicide layer 212 is also made of nickel silicide. In other embodiments, the first metal silicide layer may also be made of platinum silicide, and the second metal silicide layer may also be made of platinum silicide.

[0075] In this embodiment, the control gate structure 206 does not have a sidewall layer 205.

[0076] In this embodiment, the floating gate structure 208 includes: a first tunneling oxide layer, a floating gate layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewall of the floating gate layer.

[0077] In this embodiment, the control gate structure 206 includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewall of the control gate layer.

[0078] In this embodiment, the first gate dielectric layer and the second gate dielectric layer are multilayer structures. Specifically, the first gate dielectric layer and the second gate dielectric layer each include: a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0079] The first silicon oxide layer and the second silicon oxide layer can bond well with the base crystal, while the silicon nitride layer is in the middle and can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement each other.

[0080] In other embodiments, the first gate dielectric layer and the second gate dielectric layer may also be a single-layer structure.

[0081] In other embodiments, the word line structure 210 is made of a semiconductor material, specifically polycrystalline silicon.

[0082] Figures 12 to 13 This is a schematic diagram of the steps in the method for forming a memory structure according to another embodiment of the present invention.

[0083] This embodiment further describes the method for forming the memory structure based on the above embodiments. The difference from the above embodiments is that an anisotropic dry etching process is used to remove part of the sidewall layer 205. The following will provide a detailed description in conjunction with the accompanying drawings.

[0084] Please refer to Figure 12 The sidewall layer 205 is etched using an anisotropic dry etching process to expose the top surface of the control gate structure 206.

[0085] In this embodiment, an anisotropic dry etching process is used to remove part of the sidewall layer 205.

[0086] Please refer to Figure 13 A first metal silicide layer 211 is formed on the top surface of the exposed control gate structure 206.

[0087] Accordingly, an embodiment of the present invention also provides a memory structure, please refer to [link / reference needed]. Figure 13 The rest of the structure is the same as in the above embodiment. The difference is that in this embodiment, it also includes: a sidewall layer 205 located on the control gate structure 206, the sidewall layer 205 exposing part of the top surface of the control gate structure 206; the first metal silicide layer 211 is located on the exposed top surface of the control gate structure 206.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a memory structure, characterized in that, include: Provide substrate; A word line structure and gate structures located on both sides of the word line structure are formed on the substrate. The gate structure includes a floating gate structure and a control gate structure located on the floating gate structure. The gate structure has a sidewall layer. An anisotropic dry etching process, combined with photomask etching, is used to etch the sidewall layer, exposing the top surface of the control gate structure; A first metal silicide layer is formed on the top surface of the control gate structure; wherein... The word line structure and the method for forming the gate structures located on both sides of the word line structure include: forming a floating gate material layer on the substrate; forming a control gate material layer on the floating gate material layer; forming a patterned layer on the control gate material layer, the patterned layer having a patterned opening that exposes a portion of the control gate material layer; forming a sidewall layer on the sidewall of the patterned opening; etching the control gate material layer using the patterned layer and the sidewall layer as a mask until the top surface of the floating gate material layer is exposed, forming two initial control gate structures, with an initial second opening between the two initial control gate structures; and forming a sidewall layer on the sidewall of the initial control gate structure exposed by the initial second opening. A second gate dielectric layer is formed to form two control gate structures, such that the initial second opening forms the second opening; after forming the control gate structures, the floating gate material layer is etched using the patterning layer, sidewall layer, and second gate dielectric layer as masks until the top surface of the substrate is exposed, forming two initial floating gate structures with an initial first opening between them; a second tunneling oxide layer is formed on the sidewall of the initial floating gate structure exposed by the initial first opening and on the top surface of the substrate, forming two floating gate structures, such that the initial first opening forms the first opening; the word line structure is formed within the first opening and the second opening.

2. The method for forming a memory structure as described in claim 1, characterized in that, During the process of forming a first metal silicide layer on the top surface of the control gate structure, the method further includes forming a second metal silicide layer on the top surface of the word line structure.

3. The method for forming a memory structure as described in claim 1, characterized in that, The floating grid structure includes: a first tunneling oxide layer, a floating grid layer located on the first tunneling oxide layer, and a second tunneling oxide layer located on the sidewall of the floating grid layer.

4. The method for forming a memory structure as described in claim 3, characterized in that, The control gate structure includes: a first gate dielectric layer, a control gate layer located on the first gate dielectric layer, and a second gate dielectric layer located on the sidewall of the control gate layer.

5. The method for forming a memory structure as described in claim 1, characterized in that, After forming the word line structure and before forming the first metal silicide layer, the method further includes: removing the patterning layer, and etching the control gate structure and the floating gate structure using the sidewall layer and the word line structure as a mask until the top surface of the substrate is exposed.

Images