Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are characterized by an oxide layer between the metal gate and the channel, resulting in high input resistance. MOSFETs play a crucial role in numerous electronic devices due to their high input impedance, low power consumption, fast switching speed, and ease of integration.

[0003] Figure 1 A schematic diagram of a MOSFET in the prior art is shown. Figure 1 As shown, the MOS transistor includes: a semiconductor substrate 10'; a gate structure 20' located on the semiconductor substrate 10', the gate structure 20' being located in a conductive channel region 11', the gate structure 20' in the conductive channel region 11' being the gate of the MOS transistor to be formed, the gate structure 20' including a gate oxide layer 21' and a gate electrode layer 22' located on the gate oxide layer 21'; doped regions 12' located on both sides of the gate structure 20', the doped regions 12' being the source or drain regions of the MOS transistor to be formed; and a layer covering the doped regions 12' and the gate structure 20'. A metal silicide layer 30' is located on the top surface; a dielectric layer 40' is located above the metal silicide layer 30' and on the sidewall of the gate structure 20', with through-holes on the dielectric layer 40', some of which correspond to the metal silicide layer 30' in the doped region 12' and some of which correspond to the gate structure 20'; metal contacts 50' are located within the contact holes, some of which are electrically connected to the metal silicide layer 30' in the doped region 12' and some of which are electrically connected to the metal silicide layer 30' above the gate structure 20'. The metal silicide layer 30' is used to reduce the resistance of the gate, source, and drain. The metal contacts 50' are used to connect the source or drain region and gate of the MOS transistor to the upper metal wiring to realize logic functions.

[0004] In existing MOS transistors, there is a significant height difference between the gate structure 20' and the doped region 12'. Consequently, the metal silicide layer 30' formed on top of the gate structure 20' and the metal silicide layer 30' formed above the doped region 12' have a certain height difference. Therefore, the depth of the contact hole formed on the dielectric layer 40' and corresponding to the doped region 12' is greater than the depth of the contact hole formed on the dielectric layer 40' and corresponding to the gate structure 20'. As a result, during the existing manufacturing of contact holes, it is easy to over-etch the contact hole corresponding to the gate structure 20, which may penetrate the metal silicide layer 30' and cause an increase in resistance at the gate structure 20'.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of the problems in the prior art, the purpose of this invention is to provide a semiconductor device and its fabrication method, which reduces the abnormality rate during etching of contact holes, increases the process window for etching contact holes, and improves the reliability of semiconductor devices.

[0007] This invention provides a method for fabricating a semiconductor device, comprising:

[0008] A semiconductor substrate is provided, including a conductive channel region;

[0009] A gate structure is formed on the surface of the semiconductor substrate;

[0010] A mask is formed on the side of the gate structure opposite to the semiconductor substrate, and the mask corresponds to the conductive channel region; a first recess is provided on the mask;

[0011] Remove the mask and the gate structures on both sides of the conductive channel region, and form a second recess in the gate structure corresponding to the conductive channel region;

[0012] The semiconductor substrates on both sides of the conductive channel region are doped to form a doped region;

[0013] A metal silicide layer is formed on the side of the gate structure opposite to the semiconductor substrate and on the doped region;

[0014] A dielectric layer is formed on the side of the metal silicide layer opposite to the semiconductor substrate. The dielectric layer has a first contact hole and a second contact hole. The first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recess.

[0015] A first metal contact is formed in the first contact hole, and a second metal contact is formed in the second contact hole.

[0016] In some embodiments, the material of the metal silicide layer includes at least one of cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide, and tantalum silicide.

[0017] In some embodiments, on the vertical projection surface of the semiconductor substrate, the area of ​​the second recess is larger than the area of ​​the second contact hole.

[0018] In some embodiments, at least a portion of the structure of the second metal contact body is located within the second recess.

[0019] In some embodiments, doping the semiconductor substrates on both sides of the conductive channel region includes the following steps:

[0020] The semiconductor substrate is lightly doped to form a well region;

[0021] The well region is heavily doped to form a heavily doped contact region.

[0022] In some embodiments, the dielectric layer is silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, or silicon oxynitride.

[0023] In some embodiments, the gate structure includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer.

[0024] In some embodiments, before forming a dielectric layer on the side of the metal silicide facing away from the semiconductor substrate, the method further includes the step of:

[0025] A sidewall structure is formed on the sidewall of the gate structure in the conductive channel region.

[0026] In some embodiments, forming a first metal contact body in the first contact hole and forming a second metal contact body in the second contact hole includes the steps of:

[0027] A metal contact layer is formed on the side of the dielectric layer opposite to the semiconductor substrate;

[0028] Planarize the metal contact layer until the first metal contact and the second metal contact expose the surface of the dielectric layer.

[0029] In some embodiments, the metal contact layer comprises one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

[0030] This invention also provides a semiconductor device, fabricated using the semiconductor device fabrication method described above, the device comprising:

[0031] The substrate includes the conductive channel region and the doped region;

[0032] A gate structure is located on the surface of the substrate and corresponds to the conductive channel region; the gate structure is provided with a second recess.

[0033] A metal silicide layer is located on the side of the gate structure away from the semiconductor substrate and on the surface of the doped region, and the second recess is filled with the metal silicide layer;

[0034] A dielectric layer is located on the side of the metal silicide layer opposite to the semiconductor substrate; the dielectric layer is provided with a first contact hole and a second contact hole, the first contact hole corresponding to the doped region and the second contact hole corresponding to the second recess;

[0035] The first contact hole is provided with a first metal contact body, and the second contact hole is provided with a second metal contact body.

[0036] The semiconductor device and its fabrication method provided by this invention have the following advantages:

[0037] This technical solution utilizes a mask with a first recess to create a second recess on the top of the gate structure after the mask is removed. This thickens the metal silicide layer on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, reducing the abnormal rate of etching the metal silicide layer during the first contact hole etching. This increases the process window for etching the contact hole, improves the yield of MOSFET devices, and enhances the reliability of semiconductor devices. Attached Figure Description

[0038] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0039] Figure 1 This is a cross-sectional schematic diagram of a MOS transistor in the prior art;

[0040] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0041] Figures 3 to 8 This is a cross-sectional structural schematic diagram of the MOS transistor formation process in one embodiment of the present invention.

[0042] Figure label:

[0043] 10' Substrate 20 Gate Structure in the Prior Art

[0044] 11' The existing conductive channel region 21 gate oxide layer

[0045] 12' Doped region 22 gate electrode layer in the prior art

[0046] 20' Second recess in the gate structure 221 of the prior art

[0047] 21' Gate oxide layer 30 Metal silicide layer in the prior art

[0048] 22' Gate electrode layer 40 dielectric layer in the prior art

[0049] 30' The metal silicide layer 41 in the prior art is the first contact hole

[0050] 40' Dielectric layer 42 in the prior art Second contact hole

[0051] 50' Metal contact body in the prior art 50 Metal contact layer

[0052] 10 Substrate 51 First Contact

[0053] 11 Conductive channel region 52 Second contact

[0054] 12 doped regions, 60 mask layers

[0055] 601 First Depression Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0057] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0058] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0059] It should be further understood that the terms "comprising" or "including" indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only arise when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0060] To address the problems in the prior art, embodiments of the present invention provide a method for fabricating a semiconductor device. Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention is shown. Figure 2 As shown, a semiconductor fabrication method includes: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the side of the gate structure away from the semiconductor substrate, and the mask corresponding to the conductive channel region; having a first recess on the mask; removing the mask and the gate structures on both sides of the conductive channel region, and forming a second recess on the gate structure corresponding to the conductive channel region; doping the semiconductor substrate on both sides of the conductive channel region to form a doped region; forming a metal silicide layer on the side of the gate structure away from the semiconductor substrate and on the doped region; forming a dielectric layer on the side of the metal silicide layer away from the semiconductor substrate, the dielectric layer having a first contact hole and a second contact hole, the first contact hole corresponding to the doped region and the second contact hole corresponding to the second recess; forming a first metal contact in the first contact hole and forming a second metal contact in the second contact hole.

[0061] This technical solution utilizes a mask with a first recess to create a second recess on the top of the gate structure after the mask is removed. This thickens the metal silicide layer on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, reducing the abnormal rate of etching the metal silicide layer during the first contact hole etching. This increases the process window for etching the contact hole, improves the yield of MOSFET devices, and enhances the reliability of semiconductor devices.

[0062] To make the objectives, features and advantages of the present invention more apparent and understandable, reference is made below to the appendix. Figures 2 to 8 The method for fabricating the MOS transistor of the present invention will be described in detail.

[0063] Figures 3 to 8 This is a cross-sectional structural schematic diagram of the semiconductor device formation process in one embodiment of the present invention.

[0064] like Figure 3 As shown, step S100: Provide a semiconductor substrate 10. Specifically, the semiconductor substrate 10 can be at least one of the following materials: Si (silicon), Ge (germanium), SiC (silicon carbide), InP (indium phosphide), or other group III or IV compound semiconductors, wherein the silicon material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor substrate 10 can also be a semiconductor-on-insulator structure, which includes an insulator and a semiconductor material layer located on the insulator. The semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, and indium gallium arsenide.

[0065] Please continue reading. Figure 3 Step S200: A gate structure 20 is formed on the surface of the semiconductor substrate 10. In this embodiment, the gate structure 20 may include a gate dielectric layer 21 located on the surface of the semiconductor substrate 10 and a gate electrode layer 22 located on the surface of the gate dielectric layer 21. The material of the gate dielectric layer 21 may be a composite material layer composed of one or more of silicon oxide, chromium oxide, or silicon oxynitride. The material of the gate electrode layer 22 may be, for example, a polycrystalline silicon layer or a metal material.

[0066] like Figure 4 As shown, in step S300: a mask 60 is formed on the side of the gate structure 20 away from the semiconductor substrate 10, and the mask 60 corresponds to the conductive channel region 11; a first recess 601 is provided on the mask 60.

[0067] Furthermore, such as Figure 5As shown, in step 400: the mask 60 and the gate structures 20 on both sides of the conductive channel region 11 are removed. A second recess 221 is formed on the gate structure 20 corresponding to the conductive channel region 11. When the mask 60 is removed using an etching process, the thickness of the mask 60 at the first recess 601 is small, therefore a groove, i.e., the second recess 221, is etched on the gate structure 20 corresponding to the first recess 601. The gate structure 20 controls the generation and elimination of charge in the conductive channel region. The shape of the first recess 601 is not limited to... Figure 5 The shape shown can be customized by those skilled in the art according to actual needs.

[0068] Furthermore, such as Figure 5 As shown, step 500: doping the semiconductor substrate 10 on both sides of the conductive channel region 11 to form a doped region 12, which is the source region or drain region formed.

[0069] Furthermore, such as Figure 6 As shown, step 600: A metal silicide layer 30 is formed on the side of the gate structure 20 facing away from the semiconductor substrate 10 and on the doped region 12. The metal silicide layer 30 can be used to reduce the contact resistance between the gate structure 20 and the doped region 12. The material of the metal silicide layer 30 includes at least one selected from cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide, and tantalum silicide.

[0070] Furthermore, such as Figure 7 As shown, in step S700: a dielectric layer 40 is formed on the side of the metal silicide layer 30 away from the semiconductor substrate 10. The dielectric layer 40 is provided with a first contact hole 41 and a second contact hole 42. The first contact hole 41 corresponds to the doped region 12, and the second contact hole 42 corresponds to the second recess 221.

[0071] In this embodiment of the invention, on the vertical projection surface of the semiconductor substrate 10, the area of ​​the second recess 221 is larger than the area of ​​the second contact hole 42. This arrangement makes it difficult for the thickness of the metal silicide layer 30 below the second contact hole 42 to be etched, thereby reducing the abnormal rate of etching through the metal silicide layer 30.

[0072] Furthermore, such as Figure 8 As shown, in step S800: a first metal contact 51 is formed in the first contact hole 41, and a second metal contact 52 is formed in the second contact hole 42.

[0073] This technical solution utilizes a mask 60 with a first recessed portion 601 to create a second recessed portion 221 on the top of the gate structure 20 after removing the mask 60. This thickens the metal silicide layer 30 on the surface of the gate structure 20. When etching the first contact hole corresponding to the gate structure 20, the process window for etching the first contact hole can be increased, reducing the abnormal rate of penetrating the metal silicide layer 30 during etching of the first contact hole. This increases the process window for etching the contact hole, improves the yield of MOSFET device fabrication, and enhances the reliability of semiconductor devices.

[0074] Furthermore, in some embodiments of the present invention, the method for forming the metal silicide layer 30 is, for example, to form a metal layer on the surface exposing the doped region 12 and the gate structure 20; and further anneal the metal layer to allow it to chemically react with the silicon elements in the semiconductor substrate 10 and the gate structure 20 in contact with it, thereby generating the metal silicide layer 30. The metal silicide layer 30 can reduce the resistance between the subsequently formed contacts and the doped region 12 and the gate structure 20. The metal layer material is a single metal or alloy of Ni, W, Ti, Ta, Pt, or Co.

[0075] Furthermore, in some embodiments, step S500 involves doping the semiconductor substrate 10 on both sides of the conductive channel region 11, including the following steps:

[0076] Doping is performed on the semiconductor substrate 10 to form a well region;

[0077] Doping is performed in the well region to form a heavily doped contact region.

[0078] The formation of the doped regions employs, for example, a high-density plasma doping process, with N-type or P-type doped ion implantation performed according to the designed doping concentration. In this embodiment of the invention, during the process steps of forming lightly doped and heavily doped regions by performing N-type or P-type doped ion implantation, a specific tilt angle is used for the ion implantation process, and an annealing process can be performed after ion implantation, so that a portion of both the lightly doped and heavily doped regions is located directly below the gate structure 20. The annealing process activates the doped ions, causing them to redistribute within the substrate, and simultaneously repairs the lattice damage to the substrate caused by the ion process.

[0079] In this embodiment of the invention, an NMOS transistor is used as an example of the semiconductor device formed. The implanted ions are N-type ions, specifically P, As, or Sb. In other embodiments, when a PMOS transistor is formed, the implanted ions are P-type ions, specifically B, Ga, or In.

[0080] In some embodiments, prior to the step of forming the dielectric layer 40 on the side of the metal silicide layer 30 facing away from the semiconductor substrate 10, the step further includes:

[0081] A sidewall structure is formed on the sidewall of the gate structure 20 in the conductive channel region 11.

[0082] The sidewall structure is used to limit the lateral current between the gate structure 20 and the source or drain, preventing current from leaking directly from the source or drain and improving the reliability of the semiconductor device. The sidewall structure is made of a composite material layer composed of one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0083] Furthermore, the material of the dielectric layer 40 can be silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbide nitride, or silicon oxynitride. The process for forming the dielectric layer can be, for example, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0084] Further, step S800, which involves forming a first metal contact 51 within the first contact hole 41 and a second metal contact 52 within the second contact hole 42, includes the following steps:

[0085] A metal contact layer 50 is formed on the side of the dielectric layer 40 that is away from the semiconductor substrate 10;

[0086] Planarize the metal contact layer 50 until the first metal contact 51 and the second metal contact 52 are exposed on the surface of the dielectric layer 40.

[0087] The material of the metal contact layer 50 may include one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum. The process for forming the metal contact within the contact hole includes chemical vapor deposition or physical vapor deposition, and planarization of the metal contact layer 50 using a chemical mechanical polishing process.

[0088] This invention also provides a semiconductor device fabricated using the semiconductor device fabrication method described above. The semiconductor device achieves the technical effects of the aforementioned semiconductor device fabrication method, which will not be elaborated further here. Figure 8 As shown, the semiconductor device includes:

[0089] Substrate 10 includes a conductive channel region 11 and a doped region 12;

[0090] The gate structure 20 is located on the surface of the semiconductor substrate 10 and corresponds to the conductive channel region 11; the gate structure 20 is provided with a second recess 221.

[0091] A metal silicide layer 30 is located on the side of the gate structure 20 away from the semiconductor substrate 10 and on the surface of the doped region 12. The metal silicide layer 30 fills the second recess 221.

[0092] The dielectric layer 40 is located on the side of the metal silicide layer 30 that is away from the semiconductor substrate 10; the dielectric layer 40 is provided with a first contact hole 41 and a second contact hole 42, the first contact hole 41 corresponds to the doped region 12, and the second contact hole 42 corresponds to the second recess 221.

[0093] The first contact hole 41 is provided with a first metal contact body 51, and the second contact hole 42 is provided with a second metal contact body 52.

[0094] In summary, the semiconductor device and its fabrication method provided by this invention have the following advantages:

[0095] This technical solution utilizes a mask with a first recess to create a second recess on the top of the gate structure after the mask is removed. This thickens the metal silicide layer on the surface of the gate structure. When etching the first contact hole corresponding to the gate structure, the process window for etching the first contact hole can be increased, reducing the abnormal rate of etching the metal silicide layer during the first contact hole etching. This increases the process window for etching the contact hole, improves the yield of MOSFET devices, and enhances the reliability of semiconductor devices.

[0096] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, including a conductive channel region; A gate structure is formed on the surface of the semiconductor substrate; A mask is formed on the side of the gate structure opposite to the semiconductor substrate, and the mask corresponds to the conductive channel region; a first recess is provided on the mask; Remove the mask and the gate structures on both sides of the conductive channel region, and form a second recess in the gate structure corresponding to the conductive channel region; The semiconductor substrates on both sides of the conductive channel region are doped to form a doped region; A metal silicide layer is formed on the side of the gate structure opposite to the semiconductor substrate and on the doped region; A dielectric layer is formed on the side of the metal silicide layer facing away from the semiconductor substrate. The dielectric layer has a first contact hole and a second contact hole. The first contact hole corresponds to the doped region, and the second contact hole corresponds to the second recess. On the vertical projection plane of the semiconductor substrate, the area of ​​the second recess is larger than the area of ​​the second contact hole. A first metal contact is formed in the first contact hole, and a second metal contact is formed in the second contact hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the metal silicide layer includes at least one of cobalt silicide, tungsten silicide, nickel silicide, platinum silicide, titanium silicide, and tantalum silicide.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of doping the semiconductor substrates on both sides of the conductive channel region includes the following steps: The semiconductor substrate is lightly doped to form a well region; The well region is heavily doped to form a heavily doped contact region.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The dielectric layer is silicon oxide, silicon nitride, silicon carbide nitride, silicon boroide nitride, silicon carbide nitride, or silicon oxynitride.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gate structure includes a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before forming a dielectric layer on the side of the metal silicide facing away from the semiconductor substrate, the method further includes the following steps: A sidewall structure is formed on the sidewall of the gate structure in the conductive channel region.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole includes the following steps: A metal contact layer is formed on the side of the dielectric layer opposite to the semiconductor substrate; Planarize the metal contact layer until the first metal contact and the second metal contact expose the surface of the dielectric layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The metal contact layer comprises one or more of the following: copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.

9. A semiconductor device, characterized in that, The device is prepared by the method of fabrication of a semiconductor device according to any one of claims 1 to 8, wherein the device comprises: The substrate includes the conductive channel region and the doped region; A gate structure is located on the surface of the substrate and corresponds to the conductive channel region; the gate structure is provided with a second recess. A metal silicide layer is located on the side of the gate structure opposite to the semiconductor substrate and on the surface of the doped region; A dielectric layer is located on the side of the metal silicide layer facing away from the semiconductor substrate; the dielectric layer is provided with a first contact hole and a second contact hole, the first contact hole corresponding to the doped region and the second contact hole corresponding to the second recess; on the vertical projection plane of the semiconductor substrate, the area of ​​the second recess is larger than the area of ​​the second contact hole; The first contact hole is provided with a first metal contact body, and the second contact hole is provided with a second metal contact body.

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