Gate drive circuit structure for increasing gate voltage of power MOS tube in bootstrap circuit

Abstract

The present invention relates to a gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit. The structure comprises a primary drive module, a secondary drive module, and a port drive module. The primary drive module, the secondary drive module, and the port drive module are sequentially connected. The primary drive module is responsible for driving the second PMOS tube P2 on and off; the secondary drive module is used to control the on and off of the built-in power tube P1 in the drive circuit; and the port drive module is used to drive an external power MOS tube. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit of the present invention is used. Under the condition of using a thin gate oxide device, the gate drive voltage is increased to reduce the R of driving the external power MOS tube. DS(ON) , improving the overall working efficiency, this structure can be used to drive different power tubes on the high and low sides at the same time. It can adapt to different working voltages by simply adjusting the value of the internal resistance or current reference, and has broad application prospects.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, in particular to the field of bootstrap circuits, and specifically refers to a gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit. Background Art

[0002] MOS (Metal-Oxide-Semiconductor) is increasingly used in applications such as switching voltages and motor drives due to its advantages of high input impedance, low drive current, and fast switching speed. In power drive applications, a dedicated driver integrated circuit (IC) and an external power MOS transistor (MOSFET) are typically used to achieve the required drive requirements. The IC controls signal voltage conversion, gate drive, and protection for the power MOS transistor, while the power MOS transistor provides high-current, high-efficiency output. A power MOS transistor is a voltage-controlled device whose switching state is controlled by the voltage VGS between the gate and source. Within the IC, multiple inverters are used to gradually increase the drive capability. Finally, the inverter is connected to the gate of the external power MOS transistor to output the appropriate VGS voltage. The inverter within the IC typically consists of a P-type MOS transistor and an N-type MOS transistor. This circuit structure is simple, but due to process limitations, the power supply voltage cannot exceed the gate-to-substrate breakdown voltage of the MOS transistor. Therefore, it is used in applications with higher power supply voltages. Furthermore, compared to P-type power MOS transistors, N-type power MOS transistors are more affordable, faster, and have lower on-resistance. Therefore, integrated circuits are mostly designed with a bootstrap boost method to drive two external power NMOS devices. On the one hand, the bootstrap drive method can increase the driving end voltage and expand the application scenarios. On the other hand, instead of using P-type power devices, only N-type power devices are used to improve the overall driving efficiency and reduce the cost of the overall solution. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit with complete functions, stable performance and low circuit cost.

[0004] In order to achieve the above-mentioned object, the gate drive circuit structure for increasing the gate voltage of the power MOS tube in the bootstrap circuit of the present invention is as follows:

[0005] The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit has the following main features: the circuit structure includes a primary drive module, a secondary drive module, and a port drive module; the primary drive module, the secondary drive module, and the port drive module are connected in sequence; the port drive module includes a first PMOS tube; the secondary drive module includes a second PMOS tube; the gate of the first PMOS tube is connected to the drain of the second PMOS tube; the source of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the second PMOS tube is connected to the primary drive module; the primary drive module is responsible for driving the second PMOS tube to turn on and off; the secondary drive module is used to control the turning on and off of the first PMOS tube; and the port drive module is used to drive an external power MOS tube.

[0006] Preferably, the primary driving module includes a first constant current source, a second constant current source, a fifth NMOS transistor, and a first polycrystalline resistor. The gate of the fifth NMOS transistor is connected to the input signal, the source is grounded through the second constant current source, and the drain is connected to the power supply voltage through the first constant current source. One end of the first polycrystalline resistor is connected to the power supply, and the other end of the first polycrystalline resistor is connected to the secondary driving module.

[0007] Preferably, the secondary driving module includes an inverter, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third constant current source, a second PMOS transistor, a second polycrystalline resistor, a fourth polycrystalline resistor, a Zener diode, a third polycrystalline resistor, and a pulse generating circuit;

[0008] The input end of the inverter is connected to the input signal IN, the output end is connected to the gate of the third NMOS transistor, the source of the third NMOS transistor is grounded through a third constant current source, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor; the gate of the fourth NMOS transistor is connected to the digital logic voltage VDD, the drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the drain of the fifth NMOS transistor of the primary drive module, the two ends of the second polycrystalline resistor, the two ends of the series connection of the fourth polycrystalline resistor and the Zener diode, and the source and drain of the second PMOS transistor are all connected in parallel; the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor through a third polycrystalline resistor; the output end of the inverter generates a short pulse through a pulse generating circuit to control the gate of the second NMOS transistor.

[0009] Preferably, the port driver module includes a first PMOS transistor and a first NMOS transistor.

[0010] The gate and drain of the first PMOS transistor are connected in parallel to the two ends of the second polycrystalline resistor, that is, one end of the second polycrystalline resistor R2 is connected to the gate of the first PMOS transistor P1, and the other end of the second polycrystalline resistor R2 is connected to the drain of the first PMOS transistor P1. The gate of the first PMOS transistor is connected to the input signal IN, and the source is grounded. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor and outputs a signal.

[0011] Preferably, the circuit structure further includes a level conversion module, the power supply terminal is connected to the power supply voltage VCC terminal, the level conversion module is connected to the input signal IN and the gate of the first NMOS tube, and the source of the level conversion module and the first NMOS tube are grounded.

[0012] Preferably, the PMOS tube in the circuit structure is a high-voltage device, which is used for voltages above 12V.

[0013] Preferably, the NMOS transistor and the PMOS transistor in the circuit structure both have a thin gate oxide structure, and the thickness of the gate oxide layer of the thin gate oxide structure is 120 angstroms.

[0014] Preferably, the square resistance of the first polycrystalline resistor R1, the second polycrystalline resistor R2, the third polycrystalline resistor R3 or the fourth polycrystalline resistor R4 is between 1000 ohms per square and 4000 ohms per square.

[0015] Preferably, the voltage of the input signal of the gate drive circuit structure is 0-5V, and the voltage of the output signal is 0-10V.

[0016] Preferably, the gate voltage of the second PMOS transistor is less than 5V, and the gate voltage of the first PMOS transistor is less than 6V.

[0017] The gate drive circuit structure of the present invention is used to improve the gate voltage of the power MOS tube in the bootstrap circuit, and a new power tube gate drive structure is proposed. Under the condition of using thin gate oxide devices, the gate drive voltage is increased to reduce the R of the external power MOS tube. DS(ON) , improving overall working efficiency, which is of great significance in terms of energy saving. Moreover, this structure can be used to drive different power tubes on the high and low sides at the same time. By simply adjusting the value of the internal resistance or current reference, it can adapt to different operating voltages. Under the same driving capability, this design can greatly reduce the overall area of the integrated circuit and save circuit costs. The structural principle adopted by the present invention is clear, the function is complete, and it has been verified by mass production circuits. The performance is stable and reliable. It has been widely used in integrated circuit products and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1Schematic diagram of driving an external dual N-type power MOS using a bootstrap boost driving method in one embodiment.

[0019] Figure 2 is a certain NMOS power tube R in an embodiment DS(ON) Schematic diagram of the relationship with gate voltage.

[0020] Figure 3 is a certain NMOS power tube R in an embodiment DS(ON) Schematic diagram of the relationship with the working current.

[0021] Figure 4 This is a commonly used output drive circuit structure for I1 and I2 in one embodiment.

[0022] Figure 5 Schematic diagram of an improved low-side drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit in one embodiment.

[0023] Figure 6 Schematic diagram of a high-side driving structure of a gate driving circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit in an embodiment.

[0024] Figure 7 The figure is a low-side drive simulation waveform diagram of a gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit in one embodiment. DETAILED DESCRIPTION

[0025] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0026] The schematic diagram of the bootstrap drive method is as follows Figure 1 As shown, Figure 1The box contains the internal structure of the integrated circuit, while the remaining components are external. VCC is the power supply voltage, VP is the power drive voltage, D0 is the internal bootstrap diode, C0 is the bootstrap capacitor, I1 is the driver for the high-side MOSFET N1, and I2 is the gate driver for the low-side power transistor N2. Both are constructed by cascading multiple inverters. N1 and N2 are external power NMOS transistors, and IN is the input signal. VCC passes through D0, charging C0 to generate the bootstrap voltage. The low-side driver transistor N2 can be directly driven by the internal driver circuit I2. The high-side transistor N1 requires the input signal to be pre-transmitted through a level shifter circuit, converted to a potential between VB and HB, and then connected to I1. I1 then drives the external high-side transistor N1. When the high-side transistor is turned on, I1 outputs a high level referenced to HB and applies it to the gate of N1. N1 turns on, and the charge in C0 maintains the required turn-on potential. HB outputs a voltage close to VP, and VB is bootstrapped by capacitor C0 to a voltage close to the sum of VP and VCC. In general applications, VCC is 5V. After subtracting the voltage drop across diode D0, the bootstrap voltage is approximately 4.5V. The maximum VP voltage is limited by the withstand voltage of the external power transistor process and the withstand voltage of the integrated circuit HB isolation process. Under current process conditions, a voltage range of 12V to 120V is generally acceptable.

[0027] From the above analysis, it can be seen that after adopting the bootstrap drive method, the integrated circuit can drive two external N-type medium-power MOS tubes, while the integrated circuit can use a lower operating voltage inside, reducing the cost of the overall solution; the power supply at the power output end of the entire solution uses a wide range of voltages to meet the driving requirements of different occasions.

[0028] The above-mentioned drive structure using bootstrap boosting is not perfect and there is room for further optimization.

[0029] 1. There is room for further optimization of MOS tube on-resistance:

[0030] In the above application mode, the power MOS tube works in the switching state, and the overall circuit loss is mainly due to the switching loss and conduction loss of the MOS tube. The former is related to the parasitic capacitance of the power tube gate and other parameters; while the latter is related to the conduction internal resistance R DS(ON) Under the same tube conditions, the greater the internal resistance, the greater the conduction loss. However, for the same MOS tube, its R DS(ON) It is not fixed. Figure 2 R is the value of a certain power MOS tube under different conditions. DS(ON) The numerical value of .

[0031] from Figure 2 It can be seen that the R DS(ON) The parameters are related to its VGS gate-source voltage. Figure 2 The left figure shows that when the VGS gate-source voltage increases, R DS(ON)The maximum VGS gate-source voltage of the MOS tube can reach 10V. Figure 2 The right figure shows that when VGS=4.5V and VGS=10V, R DS(ON) The difference can even exceed 10%. If the VGS gate-source voltage is increased, that is, the Figure 1 The voltage of VCC in the middle, thereby increasing the bootstrap voltage, can further reduce the R of the external power MOS tube. DS(ON) , improve work efficiency.

[0032] 2. Problems caused by increasing VCC voltage:

[0033] Figure 3 It is a multi-stage cascade circuit structure commonly used by I1 and I2. Figure 3 The IN terminal connects to the input control signal, and the OUT terminal connects to the gate of the external power transistor. VH and VL are the reference power supply and reference ground of the circuit. For I2, VH connects to VCC and VL connects to GND; for I1, VH connects to VB and VL connects to HB.

[0034] The use of the inverter cascade drive method mentioned above means that the VGS gate-source voltage and source-drain withstand voltage VDS of these devices are limited by the VCC voltage. Figure 3 The VGS gate-source voltage and VDS withstand voltage of MOS devices must be increased accordingly. Therefore, thick-gate-oxide processes must be used in circuit production, and the gate breakdown voltage must exceed VCC. Thick-gate-oxide devices occupy a much larger physical layout area than thin-gate-oxide devices. Furthermore, thick-gate-oxide devices have higher unit on-resistance than thin-gate-oxide devices. Therefore, to meet the required drive capability, a larger size is required. This undoubtedly places a significant strain on circuit costs.

[0035] The present invention designs a novel gate drive circuit structure for driving an external power MOS tube of an integrated circuit in a bootstrap circuit. By using a high-voltage device with an internal low gate voltage, the voltage driven by the output port is increased, thereby increasing the gate voltage of the external power tube, reducing its on-resistance, and improving efficiency. In the prior art, low voltage generally refers to voltages of 5V and below, and voltages above 5V are high voltage. However, the high voltage of the present invention refers to voltages above 12V. When driving an external power tube, the circuit structure of the present invention does not require the use of thick gate oxide devices with a large unit area and high on-resistance for the internal high-voltage devices of the integrated circuit, but can use thin gate oxide devices with a small unit area and low on-resistance. The thin gate oxide in the specification refers to a gate oxide layer with a thickness of approximately 120 angstroms, that is, 120 meters to the power of 10 to the negative 10th power. In the circuit diagram of the present invention, all MOS device substrates are connected to the device source terminal by default. I1-I3 are constant current sources, N1-N5 are high-voltage NMOS transistors, P1-P2 are thin-gate-oxide high-voltage PMOS transistors, I5 is an inverter composed of low-voltage transistors, I4 is a pulse generator circuit that generates a short pulse signal from the rising edge of the input signal, D1 is a Zener diode, and R1-R4 are polycrystalline high-resistance transistors. P1 and N1 are power output transistors, A, B, C, D, E, and F are all network names, VCC is the power supply voltage, VDD is the low voltage used for internal digital logic, IN is the input signal, and OUT is the output signal.

[0036] The present invention improves the circuit structure of the high and low side drivers I1 and I2. The circuit structure diagram of the low side driver is shown in FIG. Figure 5 As shown, the high-side drive structure is as follows Figure 6 shown.

[0037] The gate drive circuit structure for increasing the gate voltage of the power MOS tube in the bootstrap circuit of the present invention is defined as a primary drive module, a secondary drive module, and a port drive module. The primary drive module, the secondary drive module, and the port drive module are connected in sequence. The primary drive module is responsible for driving the second PMOS tube P2 to turn on and off; the secondary drive module is used to control the turning on and off of the built-in power tube P1 of the drive circuit; and the port drive module is used to drive the external power MOS tube.

[0038] The primary driver module is a pre-driver module responsible for turning the P2 transistor on and off; the secondary driver module is an intermediate driver module responsible for turning the internal power transistor P1 on and off; and the port driver module, composed of P1 and N1, is used to ultimately drive the external power MOS transistor. The primary and secondary driver modules utilize MOS transistors as the primary operating components, corresponding to different production processes, including high-voltage processes based on digital technology. The switching device of the present invention is a MOS device, and a reference current is applied to a resistor to form a turn-on voltage, controlling the turn-on of the MOS device. A current mirror or current sink with a constant current exists in the path, and the current value is relatively small, only tens of microamperes. At the moment of turn-on, the impact on VCC is very small.

[0039] As a preferred embodiment of the present invention, the primary driving module includes a first constant current source I1, a second constant current source I2, a fifth NMOS transistor N5, and a first polycrystalline resistor R1. The gate of the fifth NMOS transistor N5 is connected to the input signal IN, the source is grounded through the second constant current source I2, and the drain is connected to the power supply voltage VCC through the first constant current source I1. The first polycrystalline resistor R1 is connected in parallel with the first constant current source I1 and is connected to the secondary driving module.

[0040] As a preferred embodiment of the present invention, the secondary driving module includes an inverter I5, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a third constant current source I3, a second PMOS transistor P2, a second polycrystalline resistor R2, a fourth polycrystalline resistor R4, a Zener diode D1, a third polycrystalline resistor R3, and a pulse generating circuit;

[0041] The inverter I5 has an input terminal connected to an input signal IN, an output terminal connected to the gate of the third NMOS transistor N3, a source of the third NMOS transistor N3 connected to ground via a third constant current source I3, and a drain of the third NMOS transistor N3 connected to the source of the fourth NMOS transistor N4. The gate of the fourth NMOS transistor N4 is connected to a digital logic voltage VDD, the drain of the fourth NMOS transistor N4 is connected to the drain of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the drain of the fifth NMOS transistor N5 of the primary driver module. Both ends of the second polycrystalline resistor R2, both ends of the series connection of the fourth polycrystalline resistor R4 and the Zener diode D1, and the drain and drain of the second PMOS transistor P2 are all connected in parallel. The drain of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3 via a third polycrystalline resistor R3. The output terminal of the inverter I5 generates a short pulse via a pulse generating circuit to control the gate of the second NMOS transistor N2.

[0042] As a preferred embodiment of the present invention, the port driver module includes a first PMOS transistor P1 and a first NMOS transistor N1.

[0043] The gate and drain of the first PMOS transistor P1 are connected in parallel to the two ends of the second polycrystalline resistor R2. That is, one end of the second polycrystalline resistor R2 is connected to the gate of the first PMOS transistor P1, and the other end of the second polycrystalline resistor R2 is connected to the drain of the first PMOS transistor P1. The gate of the first PMOS transistor P1 is connected to the input signal, and the source is grounded. The source of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and outputs a signal.

[0044] like Figure 5 The circuit structure shown works as follows:

[0045] When the input signal IN is low, after passing through inverter I5, B is high, turning N3 on. Since the gate of N4 is connected to VDD, N4 also turns on. VCC forms a current path to ground through R2-N4-N3-I3, causing the voltage at F to drop, turning P1 on and outputting a high voltage at OUT. The voltage at point F relative to the power supply VCC is the VGS voltage of P1: |VGS(P1)| = I3 × R2. By adjusting the values of R2 or I3, this voltage is designed to be lower than the maximum withstand voltage of P1's gate. This allows P1 to use a thin-gate oxide device and operate within a safe range. High-level B, passing through I4, generates a short pulse that controls the gate of N2. When P1 needs to turn on, N2 turns on instantaneously for a very short time. The instantaneous gate voltage of P1 is approximately the value of the VCC voltage divided by R2 and R3, accelerating the turn-on of P1. R4 and D1 form a clamping circuit to protect the gate of P1, preventing an abnormally high simulated gate voltage from damaging it.

[0046] When the input signal IN is high, A is high, N5 is turned on, and point E is also reduced to the safe operating voltage of the P2 tube gate through R1-N5-I1-I2. The voltage is |VGS(P2)|=(I2-I1)×R1, thereby turning on the P2 tube. At this time, the F potential is increased to VCC, the P1 tube is turned off, and at the same time, point D is high, the N1 tube is turned on, and OUT outputs a low level.

[0047] When used for high-side drive, both P1 and N1 power transistors are in a bootstrapped isolation well. The source terminal of N1 is connected to HB, VCC to VB, and GND to other components. Because the input signal is a low-voltage signal between 0 and VDD, a level shifter circuit is required for the gate of N1.

[0048] As a preferred embodiment of the present invention, the circuit structure further includes a level conversion module, the power supply voltage VCC is connected to the VB signal, the level conversion module is connected to the input signal and the gate of the first NMOS transistor N1, and the source of the level conversion module and the first NMOS transistor N1 are both connected to the HB port.

[0049] In summary, the circuit structure designed in this invention utilizes a thin gate oxide structure for high-voltage devices, enabling high gate drive voltage outputs. The presence of the N2 branch also ensures the turn-on speed of the upper transistor. With adjustments, this structure can also be applied to drive high-side power transistors. The overall simulation circuit functions normally, and the measured values after mass production are comparable to the simulated design values.

[0050] In a specific embodiment of the present invention, when VDD=5V, VCC=10V, GND=0V and load capacitance is 2nF, the transient simulation waveforms of the above-mentioned wire nets correspond to the following: Figure 7 shown. Figure 7 The waveform from top to bottom is IN, A, B, C, D, E, F and OUT.

[0051] from Figure 7 It can be seen that, with the structure designed by the present invention, the maximum gate voltage of the P2 tube is |VGS|=4.893V, and the maximum transient gate voltage of the P1 tube is |VGS|=5.479V. Subsequently, through the action of the current mirror, the VGS voltage is controlled to 3.953V, which is within the safe operating area of the thin-gate oxide device. The input signal is a voltage with an amplitude of 0 to 5V, and the output signal is a voltage with an amplitude of 0 to 10V, which is directly applied to the gate of the external power tube. The gate drive circuit structure for increasing the gate voltage of the power MOS tube is implemented in the bootstrap circuit of the present invention, and a new power tube gate drive structure is proposed. Under the condition of using a thin-gate oxide device, the gate drive voltage is increased to reduce the R of the external power MOS tube. DS(ON) , improving overall working efficiency, which is of great significance in terms of energy saving. Moreover, this structure can be used to drive different power tubes on the high and low sides at the same time. By simply adjusting the value of the internal resistance or current reference, it can adapt to different operating voltages. Under the same driving capability, this design can greatly reduce the overall area of the integrated circuit and save circuit costs. The structural principle adopted by the present invention is clear, the function is complete, and it has been verified by mass production circuits. The performance is stable and reliable. It has been widely used in integrated circuit products and has broad application prospects.

[0052] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit, characterized in that: The circuit structure includes a primary drive module, a secondary drive module, and a port drive module. The primary drive module, the secondary drive module, and the port drive module are connected in sequence. The port drive module includes a first PMOS transistor, and the secondary drive module includes a second PMOS transistor. The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the second PMOS transistor is connected to the primary drive module. The primary drive module is used to control the opening and closing of the second PMOS transistor; the secondary drive module is used to control the opening and closing of the first PMOS transistor; and the port drive module is used to drive an external power MOS transistor. The secondary driving module further includes an inverter, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third constant current source, a second polycrystalline resistor, a fourth polycrystalline resistor, a Zener diode, a third polycrystalline resistor, and a pulse generating circuit; The inverter I5 has an input terminal connected to an input signal, an output terminal connected to the gate of a third NMOS transistor, a source of the third NMOS transistor connected to ground via a third constant current source, and a drain of the third NMOS transistor connected to the source of a fourth NMOS transistor; a gate of the fourth NMOS transistor connected to a digital logic voltage VDD, a drain of the fourth NMOS transistor connected to the drain of a second PMOS transistor, and a gate of the second PMOS transistor connected to the drain of a fifth NMOS transistor of a primary driver module; two ends of the second polycrystalline resistor, two ends of a series connection of a fourth polycrystalline resistor and a Zener diode, and the source and drain of the second PMOS transistor are all connected in parallel; the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor via a third polycrystalline resistor; the output terminal of the inverter generates a short pulse via a pulse generating circuit to control the gate of the second NMOS transistor; the gate of the fifth NMOS transistor of the primary driver module is connected to an input signal, and the source of the first PMOS transistor is the output of a port driver module for driving an external power MOS transistor.

2. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The primary driving module includes a first constant current source, a second constant current source, a fifth NMOS transistor, and a first polycrystalline resistor. The gate of the fifth NMOS transistor is connected to the input signal, the source is grounded through the second constant current source, and the drain is connected to the power supply voltage through the first constant current source. One end of the first polycrystalline resistor is connected to the power supply, and the other end of the first polycrystalline resistor is connected to the secondary driving module.

3. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The port driver module further includes a first NMOS tube; The gate and drain of the first PMOS tube are connected in parallel to the two ends of the second polycrystalline resistor, that is, one end of the second polycrystalline resistor is connected to the gate of the first PMOS tube, and the other end of the second polycrystalline resistor is connected to the drain of the first PMOS tube. The gate of the first PMOS tube is connected to the input signal, and the source is grounded. The source of the first PMOS tube is connected to the drain of the first NMOS tube and outputs a signal.

4. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The circuit structure further includes a level conversion module, the power supply terminal is connected to the power supply voltage VCC terminal, the level conversion module is connected to the input signal and the gate of the first NMOS tube, and the source of the level conversion module and the first NMOS tube are both grounded.

5. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The PMOS tube in the circuit structure is a high-voltage device and is used for voltages above 12V.

6. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 3, characterized in that: The NMOS tube and the PMOS tube in the circuit structure both have a thin gate oxide structure, and the thickness of the gate oxide layer of the thin gate oxide structure is 120 angstroms.

7. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit according to any one of claims 1 or 3, characterized in that: The square resistance of the second polycrystalline resistor, the third polycrystalline resistor or the fourth polycrystalline resistor is between 1000 ohms per square and 4000 ohms per square.

8. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 2, characterized in that: The square resistance of the first polycrystalline resistor is between 1000 ohms per square and 4000 ohms per square.

9. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The voltage of the input signal of the gate drive circuit structure is 0-5V, and the voltage of the output signal is 0-10V.

10. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in the bootstrap circuit according to claim 1, characterized in that: The gate voltage of the second PMOS tube is less than 5V, and the gate voltage of the first PMOS tube is less than 6V.

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