A valley mode DC-DC converter

Abstract

This application discloses a valley-mode DC-DC converter, including a feedback control unit and a conversion unit. The feedback control unit generates a feedback voltage based on the output voltage and a reference voltage. The feedback control unit includes a current detection unit, an NMOS transistor, an error amplifier, and a logic control circuit. The current detection unit detects the on-state current of the NMOS transistor and generates an induced current. The error amplifier generates an error amplification voltage based on the reference voltage and the feedback voltage. The comparator generates a logic control quantity based on the error amplification voltage and the output of the current detection unit. The logic control circuit controls the conversion unit to generate the output voltage based on the logic control quantity and a clock signal. In this invention, the current detection unit only detects the current of the NMOS transistor. After the input signal of the logic control circuit becomes high, the PMOS transistor can be immediately turned off. Therefore, the on-time of the PMOS transistor can be very short, which meets the requirements of applications with small duty cycles.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology and relates to a valley mode DC-DC converter. Background Technology

[0002] A DC-DC converter is a device that converts electrical energy from one voltage value to another in a DC circuit. It only transforms DC parameters and is constructed by assembling small surface-mount integrated circuits and microelectronic components into one unit using microelectronic technology.

[0003] In some applications, DC-DC converters need to operate under conditions of low duty cycles. In this case, if peak mode is used, the on-time of the upper transistor is shorter. However, due to the influence of switching noise, a leading-edge cancellation time must be added to the upper transistor, which means that the upper transistor must have a minimum on-time. Therefore, peak mode limits the application of DC-DC converters at low duty cycles. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a valley-mode DC-DC converter.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A Valley-mode DC-DC converter includes a feedback control unit and a conversion unit;

[0007] The feedback control unit is based on the output voltage V. out and reference voltage V ref Generate feedback voltage V FB ;

[0008] The feedback control unit includes a logic control circuit (Logic), an error amplifier, a voltage divider series resistor unit, a comparator (comp), an NMOS transistor, a current detection unit, and a DC current source (I). DC , Slope current source I SLOPE , resistor and switch S1;

[0009] The current detection unit is used to detect the on-state current of the NMOS transistor and generate an induced current I based on the on-state current of the NMOS transistor. SENSE ;

[0010] The error amplifier is based on a reference voltage V. ref and the feedback voltage V generated by the feedback control unit FB Generate error amplification voltage V EA ;

[0011] The comparator comp is based on the error amplification voltage V.EA The current detection unit outputs Vsum to generate and outputs the logic control quantity Comp to the logic control circuit Logic.

[0012] The conversion unit includes a PMOS transistor, an inductor L, and a capacitor Cout; the PMOS transistor of the conversion unit is controlled by a logic control circuit Logic, which, based on the logic control quantity Comp and the clock signal CLK, controls the conversion unit to generate an output voltage V. out The source of the PMOS transistor is connected to the power supply voltage; one end of the inductor L is connected to the drain of the PMOS transistor, and the other end of the inductor L is connected to the output voltage V. out The inductor L is connected to one end of the voltage divider series resistor unit of the feedback control unit; one end of the capacitor Cout is connected to the output terminal of the converter, and the other end is grounded.

[0013] The present invention further includes the following preferred embodiments:

[0014] Preferably, the negative phase input terminal of the error amplifier is connected to a reference voltage V. ref The non-inverting input terminal is connected to the feedback voltage V generated by the voltage divider series resistor unit in the feedback control unit. FB The output terminal is connected to the negative phase input terminal of comparator comp in the feedback control unit, and outputs an error amplification voltage V to the negative phase input terminal of comparator comp. EA When V FB When V decreases, EA It also decreases accordingly.

[0015] Preferably, the negative input terminal of the comparator comp is connected to an error amplification voltage V. EA The non-inverting input terminal is connected to the output of the current detection unit, and the comparator comp output terminal is connected to the logic control circuit Logic.

[0016] Preferably, the logic control circuit Logic is connected to the clock signal CLK and the output signal Comp of the comparator comp, respectively, and the output signal of the logic control circuit Logic is output to the gate of the PMOS transistor and the NMOS transistor, respectively;

[0017] The source of the NMOS transistor is grounded, and the drain of the NMOS transistor and the PMOS transistor of the switching unit are connected.

[0018] Preferably, the current detection unit is connected to the source and drain of the NMOS transistor and outputs a sensed current based on the source and drain current of the NMOS transistor. The output terminal of the current detection unit is connected to a DC current source I. DC , Slope current source I SLOPE Resistance RSUM One end of switch S1, the other end of the DC current source and the ramp current source are connected to the power supply voltage, and resistor R SUM Both the other end of switch S1 and the other end of switch S1 are grounded.

[0019] Preferably, the voltage divider series resistor unit includes a first voltage divider resistor and a second voltage divider resistor; and,

[0020] The first voltage divider resistor and the second voltage divider resistor form a series circuit. One end of the series circuit is connected to the output terminal Vout of the converter, and the other end is grounded, based on the output voltage Vout. out The feedback voltage V is provided proportionally to the error amplifier. FB .

[0021] Preferably, when the output voltage V of the current detection unit SUM Increase to above the error amplification voltage V EA When the comparator comp flips and outputs a high level, the comparator comp flips and outputs a high level.

[0022] The beneficial effects achieved by this application are:

[0023] Since the current detection unit in this application only detects the current of the NMOS, the PMOS can be turned off immediately as soon as the input signal CLK of the logic control circuit goes high. Therefore, the conduction time of the PMOS can be very short, which can meet the requirements of small duty cycle applications. Attached Figure Description

[0024] Figure 1 This is the circuit schematic diagram of the present invention;

[0025] Figure 2 This is a schematic diagram of the circuit signals of the present invention. Detailed Implementation

[0026] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0027] like Figure 1 As shown, the example is a step-down DC-DC converter.

[0028] The present invention provides a Valley mode DC-DC converter, comprising a feedback control unit and a conversion unit;

[0029] The feedback control unit is based on the output voltage V. out and reference voltage V ref Generate feedback voltage V FB ;

[0030] The feedback control unit includes a logic control circuit (Logic), an error amplifier, a voltage divider series resistor unit, a comparator (comp), an NMOS transistor, a current detection unit, and a DC current source (I). DC , Slope current source I SLOPE , resistor and switch S1;

[0031] The current detection unit is used to detect the on-state current of the NMOS transistor and generate an induced current I based on the on-state current of the NMOS transistor. SENSE ;

[0032] The error amplifier is based on a reference voltage V. ref and the feedback voltage V generated by the feedback control unit FB Generate error amplification voltage V EA ;

[0033] The comparator comp is based on the error amplification voltage V. EA The current detection unit outputs Vsum to generate and outputs the logic control quantity Comp to the logic control circuit Logic.

[0034] The conversion unit includes a PMOS transistor, an inductor L, and a capacitor Cout; the PMOS transistor of the conversion unit is controlled by a logic control circuit Logic, which, based on the logic control quantity Comp and the clock signal CLK, controls the conversion unit to generate an output voltage V. out The source of the PMOS transistor is connected to the power supply voltage; one end of the inductor L is connected to the drain of the PMOS transistor, and the other end of the inductor L is connected to the output voltage V. out The inductor L is connected to one end of the voltage divider series resistor unit of the feedback control unit; one end of the capacitor Cout is connected to the output terminal of the converter, and the other end is grounded.

[0035] In specific implementation, the negative phase input terminal of the error amplifier is connected to a reference voltage V. ref The non-inverting input terminal is connected to the feedback voltage V generated by the voltage divider series resistor unit in the feedback control unit. FB The output terminal is connected to the negative phase input terminal of comparator comp in the feedback control unit, and outputs an error amplification voltage V to the negative phase input terminal of comparator comp. EA .

[0036] When V FB When V decreases, EA It also decreases accordingly.

[0037] The comparator's negative input terminal is connected to an error amplification voltage V. EAThe non-inverting input terminal is connected to the output of the current detection unit, and the comparator comp output terminal is connected to the logic control circuit Logic.

[0038] The logic control circuit Logic is connected to the clock signal CLK and the output signal Comp of the comparator comp respectively. The output signals Pgate and Ngate of the logic control circuit Logic are output to the gates of the PMOS transistor and the NMOS transistor respectively.

[0039] The source of the NMOS transistor is grounded, and the drain of the NMOS transistor and the PMOS transistor of the switching unit are connected.

[0040] When Pgate = low, the PMOS is turned on; when Pgate = high, the PMOS is turned off.

[0041] When Ngate = high, the NMOS is turned on; when Ngate = low, the NMOS is turned off.

[0042] The current detection unit is connected to the source and drain of the NMOS transistor and outputs a sensed current based on the source and drain current of the NMOS transistor. The output terminal of the current detection unit is connected to a DC current source I. DC , Slope current source I SLOPE Resistance R SUM One end of switch S1, the other end of the DC current source and the ramp current source are connected to the power supply voltage, and resistor R SUM Both the other end of switch S1 and the other end of switch S1 are grounded.

[0043] The voltage divider series resistor unit includes a first voltage divider resistor and a second voltage divider resistor; and...

[0044] The first voltage divider resistor and the second voltage divider resistor form a series circuit. One end of the series circuit is connected to the output terminal Vout of the converter, and the other end is grounded, based on the output voltage Vout. out The feedback voltage V is provided proportionally to the error amplifier. FB .

[0045] When the output voltage V of the current detection unit SUM Increase to above the error amplification voltage V EA When the comparator comp flips and outputs a high level, the comparator comp flips and outputs a high level.

[0046] like Figure 2 As shown, when the input signal CLK of the logic control circuit is high, Pgage = high, Ngate = high, the PMOS is turned off, the NMOS is turned on, the current detection unit starts working, and I is generated. SENSE The current flows into the current detection unit;

[0047] When switch S1 is in the open state, the voltage Vsum across Rsum is equal to (I DC +I SLOPE -I SENSE )*Rsum;

[0048] As the current IL in inductor L gradually decreases, I SENSE Gradually decrease, while I SLOPE The voltage at point Vsum gradually increases, so the voltage Vsum at point Vsum will gradually increase. When Vsum increases to a level higher than V... EA When the comparator comp flips, the output signal COMP becomes high. After being processed by the logic control circuit, Pgage = low, Ngate = low, NMOS is turned off, and PMOS is turned on.

[0049] When the load current I of the DC-DC converter load When the voltage increases, the output voltage Vout decreases. FB =Vout*R2 / (R1+R2), therefore V FB It will also get smaller, V EA It will decrease, at which point Vsum is more likely to be higher than V. EA That is, Vsum is higher than V when IL does not decrease significantly. EA When comparator comp flips, its output Comp signal becomes high; the NMOS is turned off and the PMOS is turned on, IL starts to rise, and the energy transferred to Vout increases, making the energy transferred to Vout meet the load current I. load The system will maintain a stable output to meet the demand.

[0050] Since the current sensing unit only detects the current of the NMOS, the PMOS can be turned off immediately after the CLK signal goes high. Therefore, the PMOS conduction time can be very short, which can meet the requirements of small duty cycle applications.

[0051] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A Valley-mode DC-DC converter, comprising a feedback control unit and a conversion unit, characterized in that: The feedback control unit is based on the output voltage V. out Generate feedback voltage V FB ; The feedback control unit includes a logic control circuit (Logic), an error amplifier, a voltage divider series resistor unit, a comparator (comp), an NMOS transistor, a current detection unit, and a DC current source (I). DC , Slope current source I SLOPE Resistance R SUM and switch S1; The current detection unit is used to detect the on-state current of the NMOS transistor and generate an induced current I based on the on-state current of the NMOS transistor. SENSE ; The error amplifier is based on a reference voltage V. ref and the feedback voltage V generated by the feedback control unit FB Generate error amplification voltage V EA ; The comparator comp is based on the error amplification voltage V. EA The current detection unit outputs Vsum to generate and outputs a logic control quantity Comp to the logic control circuit; the negative input terminal of the comparator Comp is connected to the error amplification voltage V. EA The non-inverting input terminal is connected to the output of the current detection unit, and the output terminal of the comparator comp is connected to the logic control circuit Logic; the current detection unit is connected to the source and drain terminals of the NMOS transistor and outputs a sensed current based on the source and drain current of the NMOS transistor; the output terminal of the current detection unit is connected to a DC current source I. DC , Slope current source I SLOPE Resistance R SUM One end of switch S1, the other end of the DC current source and the ramp current source are connected to the power supply voltage, and resistor R SUM Both the other end of switch S1 and the other end of switch S1 are grounded; The conversion unit includes a PMOS transistor, an inductor L, and a capacitor Cout; the PMOS transistor of the conversion unit is controlled by a logic control circuit Logic, which, based on the logic control quantity Comp and the clock signal CLK, controls the conversion unit to generate an output voltage V. out The source of the PMOS transistor is connected to the power supply voltage; one end of the inductor L is connected to the drain of the PMOS transistor, and the other end of the inductor L is connected to the output voltage V. out The inductor L is connected to one end of the voltage divider series resistor unit of the feedback control unit; one end of the capacitor Cout is connected to the output terminal of the converter, and the other end is grounded.

2. The Valley mode DC-DC converter according to claim 1, characterized in that: The negative input terminal of the error amplifier is connected to a reference voltage V. ref The non-inverting input terminal is connected to the feedback voltage V generated by the voltage divider series resistor unit in the feedback control unit. FB The output terminal is connected to the negative phase input terminal of comparator comp in the feedback control unit, and outputs an error amplification voltage V to the negative phase input terminal of comparator comp. EA When V FB When V decreases, EA It also decreases accordingly.

3. The Valley mode DC-DC converter according to claim 1, characterized in that: The logic control circuit Logic is connected to the clock signal CLK and the output signal Comp of the comparator comp, respectively. The output signals of the logic control circuit Logic are output to the... The gates of PMOS and NMOS transistors; The source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the drain of the PMOS transistor in the switching unit.

4. A Valley mode DC-DC converter according to any one of claims 1-3, characterized in that: The voltage divider series resistor unit includes a first voltage divider resistor and a second voltage divider resistor; and... The first voltage divider resistor and the second voltage divider resistor form a series circuit. One end of the series circuit is connected to the output terminal Vout of the converter, and the other end is grounded, based on the output voltage Vout. out The feedback voltage V is provided proportionally to the error amplifier. FB .

5. A Valley mode DC-DC converter according to claim 1, characterized in that: When the output voltage V of the current detection unit SUM Increase to above the error amplification voltage V EA When the comparator comp flips and outputs a high level, the comparator comp flips and outputs a high level.

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