Phase shifting to achieve efficient parallel input and dynamic series transconductance amplifier circuit

Abstract

A parallel-input and dynamic series transconductance amplifier circuit achieves high efficiency through phase shifting. The parallel-input and dynamic series transconductance amplifier circuit includes: a plurality of sub-transconductance amplifier circuits generating a plurality of corresponding transconductance output currents based on a plurality of corresponding differential input voltages; and at least one series capacitor for connecting a first sub-transconductance amplifier circuit and a second sub-transconductance amplifier circuit in series. The second transconductance output current generated by the second sub-transconductance amplifier circuit generates a transient bias current at a common-mode bias node in the first sub-transconductance amplifier circuit through the corresponding series capacitor. When the differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, the transient bias current is provided to a differential pair circuit in the first sub-transconductance amplifier circuit, thereby improving loop bandwidth and response speed during transient conditions.

Description

Technical Field

[0001] The present invention relates to a transconductance amplifier circuit, and more particularly to a parallel input and dynamic series transconductance amplifier circuit that achieves high efficiency by phase shifting. The present invention also relates to a regulating circuit configured with the aforementioned transconductance amplifier circuit. Background Art

[0002] The previous case related to the present application is: "Adaptive Biasing CMOS Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-17 No. 3, pp. 522-528, June 1982, MG Degrauwe (eg Figure 1A and Figure 1B ), and "A Very-High-Slew-Rate CMOS Operational Amplifier, IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, pp. 744-746, June 1989, R. Klinke" (as Figure 1C ).

[0003] Figure 1A A conventional transconductance amplifier circuit 101A is shown. The transconductance amplifier circuit 101A uses two additional differential amplifier pairs 91 and 92 to provide additional current when the differential input voltages Vd at the differential input terminals Vip and Vin are unequal. This increases the common-mode bias current Icb of the main differential amplifier pair 93 during transient conditions to improve loop bandwidth and response speed, and reduces the bias current during steady state to reduce bandwidth and improve stability.

[0004] Figure 1B Another conventional transconductance amplifier circuit 101B is shown. The transconductance amplifier circuit 101B provides additional current through the mirror current of the main differential amplifier pair 94 when the differential input voltage Vd of the differential input terminals Vip and Vin are not equal. Therefore, the bias current of the main differential amplifier pair 94 is increased in transient state to improve the loop bandwidth and response speed, and the bias current is reduced in steady state to reduce the bandwidth and improve stability.

[0005] Figure 1A-1B The transconductance amplifier circuit of the prior art has the disadvantages of being able to provide a limited additional current. Moreover, when this additional current is generated, it still encounters a response speed problem caused by too many current mirrors. Therefore, it is often unable to provide sufficient current in a timely manner, and the goal of improving the loop bandwidth and response speed cannot be achieved.

[0006] Figure 1CAnother conventional transconductance amplifier circuit 101C is shown. The transconductance amplifier circuit 101C is Figure 1A The difference is that the transconductance amplifier circuit 101C further generates additional current through the amplifier transistors MA1 and MA2 with gain, thereby increasing the bias current of the main differential amplifier pair 93 in transient state to improve the loop bandwidth and response speed, and reducing the bias current in steady state to reduce the bandwidth and improve stability.

[0007] Figure 1C A disadvantage of the conventional transconductance amplifier circuit is that the gain stage introduced to increase the bias current also introduces additional stability issues.

[0008] Compared to Figure 1A-1B Compared with the prior art, the transconductance amplifier circuit of the present invention can increase the bias current of the main differential amplifier pair by a larger amplitude during transient state to improve the loop bandwidth and response speed. Figure 1C Compared with the prior art, the transconductance amplifier circuit of the present invention not only increases the bias current of the main differential amplifier pair by a larger margin to improve the loop bandwidth and response speed, but also improves the stability. Summary of the Invention

[0009] From one perspective, the present invention provides a parallel input and dynamic cascade transconductance amplifier circuit, comprising: a plurality of sub-transconductance amplifier circuits, wherein each of the sub-transconductance amplifier circuits generates a corresponding transconductance output current according to a corresponding differential input voltage, the plurality of sub-transconductance amplifier circuits including a first sub-transconductance amplifier circuit and a second sub-transconductance amplifier circuit; and at least one series capacitor, wherein the series capacitor is used to cascade the corresponding two sub-transconductance amplifier circuits, the at least one series capacitor including a first series capacitor, connecting the first sub-transconductance amplifier circuit and the second sub-transconductance amplifier circuit in series; wherein the first series capacitor is connected to the second sub-transconductance amplifier circuit in series. The second transconductance output current corresponding to the second sub-transconductance amplifier circuit passes through the corresponding first series capacitor to generate a transient bias current at a common-mode bias node in the first sub-transconductance amplifier circuit. When the differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, the transient bias current is provided to a differential pair circuit in the first sub-transconductance amplifier circuit, thereby improving the loop bandwidth and response speed in a transient state, and reducing the bias current in a steady state to reduce the bandwidth and improve stability. The differential input voltage corresponding to the first sub-transconductance amplifier circuit is related to the differential input voltage corresponding to the second sub-transconductance amplifier circuit.

[0010] In a preferred embodiment, the pair of differential input terminals of the first sub-transconductance amplifier circuit and the pair of differential input terminals of the second sub-transconductance amplifier circuit are connected in parallel.

[0011] In a preferred embodiment, the transconductance coefficient of the second sub-transconductance amplifier circuit is greater than the transconductance coefficient of the first sub-transconductance amplifier circuit.

[0012] In a preferred embodiment, the parallel input and dynamic series transconductance amplifier circuit also includes a DC bias load coupled to the output end of the second sub-transconductance amplifier circuit and coupled to the first series capacitor, wherein the DC bias load is used to receive the second transconductance output current to provide a corresponding DC bias voltage at the output end of the second sub-transconductance amplifier circuit.

[0013] In a preferred embodiment, the DC bias load includes a MOS diode.

[0014] In a preferred embodiment, each of the sub-transconductance amplifier circuits is configured as a pair of transconductance amplifiers with differential inputs to single-ended outputs, wherein the impedance of the DC bias load corresponding to the second sub-transconductance amplifier circuit is large enough so that the first series capacitor generates a pole at the common-mode bias node in the first sub-transconductance amplifier circuit with a sufficiently low frequency, thereby ensuring that there is a sufficiently large phase difference between the transconductance current Idp and the transconductance current Idn generated by the first sub-transconductance amplifier circuit, thereby ensuring that the parallel input and dynamic series transconductance amplifier circuit has a phase margin greater than or equal to 45 degrees at a unity gain bandwidth.

[0015] In a preferred embodiment, the first series capacitor generates a zero point before the unity gain bandwidth of the first sub-transconductance amplifier circuit so that the parallel input and dynamic series transconductance amplifier circuit has a phase margin greater than or equal to 45 degrees under the unity gain bandwidth.

[0016] In a preferred embodiment, one of the plurality of sub-transconductance amplifier circuits is configured as at least one of the following: (1) a single-stage differential input to single-ended output transconductance amplifier, wherein the single-stage differential input to single-ended output transconductance amplifier includes an in-phase differential transistor and an inverting differential transistor for generating an in-phase transconductance current and an inverting transconductance current according to the corresponding differential input voltage, wherein the in-phase differential transistor is coupled to a MOS diode; (2) a balanced differential input to single-ended output transconductance amplifier, wherein the balanced differential input to single-ended output transconductance amplifier includes an in-phase differential transistor and an inverting differential transistor for generating an in-phase transconductance current and an inverting transconductance current according to the corresponding differential input voltage. A common conduction current and a counter-conduction current are generated according to the corresponding differential input voltage, wherein the common differential transistor and the counter-differential transistor are respectively coupled to their respective corresponding MOS diodes; or (3) a folded cascade differential input to single-ended output transconductance amplifier, wherein the folded cascade differential input to single-ended output transconductance amplifier includes an common differential transistor, an counter-differential transistor and a cascade current mirror circuit, for generating a common conduction current and a counter-conduction current according to the corresponding differential input voltage, wherein the common differential transistor and the counter-differential transistor are respectively coupled to their respective corresponding cascade nodes in the cascade current mirror circuit.

[0017] In a preferred embodiment, the sub-transconductance amplifier circuit includes a current source circuit coupled to the in-phase differential transistor and the inverting differential transistor, wherein the common-mode bias node corresponds to one of the following: (1) the common-mode bias node corresponds to a coupling node between the current source circuit and the in-phase differential transistor and the inverting differential transistor; (2) the common-mode bias node corresponds to a control terminal of the current source circuit; or (3) the common-mode bias node corresponds to a cascade node of the current source circuit, wherein the current source circuit is configured as a cascade current source circuit.

[0018] In a preferred embodiment, the first sub-transconductance amplifier circuit also receives another transient bias current at another common-mode bias node through another series capacitor, so that when the differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, the other transient bias current is provided to the differential pair circuit in the first sub-transconductance amplifier circuit, thereby improving the loop bandwidth and response speed in a transient state, and reducing the bias current in a steady state to reduce the bandwidth and improve stability, wherein the other transient bias current is generated by one of the following configurations: (1) the second sub-transconductance amplifier circuit also generates the other transient bias current; or (2) the multiple sub-transconductance amplifier circuits include another third sub-transconductance amplifier circuit, wherein the third transconductance output current corresponding to the third sub-transconductance amplifier circuit generates the other transient bias current at the other common-mode bias node in the first sub-transconductance amplifier circuit through the corresponding another series capacitor, wherein the differential input voltage corresponding to the first sub-transconductance amplifier circuit is related to the differential input voltage corresponding to the third sub-transconductance amplifier circuit.

[0019] In a preferred embodiment, the first sub-transconductance amplifier circuit further includes a current source circuit for coupling to the differential pair circuit of the first sub-transconductance amplifier circuit, wherein the common-mode bias node corresponds to a coupling node between the current source circuit and the differential pair circuit, and the other common-mode bias node corresponds to a stacking node of the current source circuit, wherein the current source circuit is configured as a stacked current source circuit.

[0020] In a preferred embodiment, the first sub-transconductance amplifier circuit also receives another transient bias current through the common-mode bias node, so that when the differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, the other transient bias current is provided to the differential pair circuit in the first sub-transconductance amplifier circuit, thereby improving the loop bandwidth and response speed in a transient state, and reducing the bias current in a steady state to reduce the bandwidth and improve stability, wherein the other transient bias current is generated by one of the following configurations: (1) the second sub-transconductance amplifier circuit also generates the other transient bias current; or (2) the multiple sub-transconductance amplifier circuits include another third sub-transconductance amplifier circuit, wherein the third sub-transconductance amplifier circuit generates the other transient bias current at the common-mode bias node in the first sub-transconductance amplifier circuit corresponding to the third transconductance output current generated, wherein the differential input voltage corresponding to the first sub-transconductance amplifier circuit is related to the differential input voltage corresponding to the third sub-transconductance amplifier circuit.

[0021] In a preferred embodiment, the first sub-transconductance amplifier circuit further includes a current source circuit coupled to the differential pair circuit of the first sub-transconductance amplifier circuit, wherein the common-mode bias node corresponds to a coupling node between the current source circuit and the differential pair circuit, wherein another common-mode bias node corresponds to a stacking node of the current source circuit, wherein the current source circuit is configured as a stacked current source circuit; wherein the first sub-transconductance amplifier circuit further receives another transient bias current through the another common-mode bias node, so as to provide the another transient bias current to the differential pair circuit in the first sub-transconductance amplifier circuit when a transient change occurs in the differential input voltage corresponding to the first sub-transconductance amplifier circuit. circuit, thereby improving the loop bandwidth and response speed in transient state, and reducing the bias current in steady state to reduce the bandwidth to improve stability, wherein the other transient bias current is generated by one of the following configurations: (1) the second sub-transconductance amplifier circuit also generates the other transient bias current; or (2) the multiple sub-transconductance amplifier circuits include another third sub-transconductance amplifier circuit, wherein the third sub-transconductance amplifier circuit generates the other transient bias current at the other common-mode bias node in the first sub-transconductance amplifier circuit corresponding to the third transconductance output current generated, wherein the differential input voltage corresponding to the first sub-transconductance amplifier circuit is related to the differential input voltage corresponding to the third sub-transconductance amplifier circuit.

[0022] From another perspective, the present invention also provides a regulator circuit, comprising: the parallel input and dynamic series transconductance amplifier circuit as described above; an output transistor; and a feedback circuit, wherein one end of the differential input terminal corresponding to the first sub-transconductance amplifier circuit is coupled to a first reference signal, and the other end of the differential input terminal corresponding to the first sub-transconductance amplifier circuit is used to receive the feedback signal to regulate the output signal to a target value, wherein the target value is related to the first reference signal; wherein one end of the differential input terminal corresponding to the second sub-transconductance amplifier circuit is coupled to a second reference signal, and the other end of the differential input terminal corresponding to the second sub-transconductance amplifier circuit is used to receive the output signal, wherein the ratio of the second reference signal to the first reference signal is related to a feedback gain of the feedback circuit.

[0023] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1A to 1C A transconductance amplifier circuit of the prior art is shown.

[0025] Figure 2A-2B A block diagram and a schematic diagram of an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention are shown.

[0026] Figure 2C A schematic diagram showing a specific embodiment of a DC bias load in the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0027] Figure 3A-3B Two block diagrams showing two embodiments of the parallel input and dynamic series transconductance amplifier circuit and the linear voltage regulator circuit of the present invention.

[0028] Figures 4A to 4C Schematic diagrams showing several specific embodiments of sub-transconductance amplifier circuits in the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0029] Figure 5 An open-loop frequency response curve corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown.

[0030] Figure 6 A closed-loop transient response waveform diagram corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown.

[0031] Figure 7 The open-loop small signal transient response waveform diagram corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown.

[0032] Figures 8A to 8D Schematic diagrams showing several specific embodiments of a current source for providing a static bias current Ibq in the parallel-input and dynamic series transconductance amplifier circuit of the present invention.

[0033] Figures 9A and 9B A block diagram showing an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0034] Figure 9C A schematic diagram showing a specific embodiment of a sub-transconductance amplifier circuit in the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0035] Figures 10A and 10B Schematic diagrams showing two specific embodiments of a sub-transconductance amplifier circuit and a current source for providing a static bias current in the parallel-input and dynamic series transconductance amplifier circuit of the present invention.

[0036] Figure 11 A schematic diagram showing a specific embodiment of a sub-transconductance amplifier circuit and a current source for providing a bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0037] Figures 12A to 12C Schematic diagrams showing several specific embodiments of the sub-transconductance amplifier circuit and the current source for providing bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention.

[0038] Explanation of symbols in the figure

[0039] 100_1~100_n, 100_m, 100-2': Sub-transduction amplifier circuit

[0040] 101A, 101B, 101C: Transconductance amplifier circuit

[0041] 104A~104C: Sub-transduction amplifier circuit

[0042] 109A~109B, 1002, 1003A, 1003B: Transconductance amplifier circuit

[0043] 91, 92, 93, 94: Differential amplifier pair

[0044] 114A, 114B, 114C, 118, 1110: differential amplifier pairs

[0045] 120: Current Mirror

[0046] 121, 122, 123, 123': Current mirror circuit

[0047] 125: Stacked Current Mirror

[0048] 130, 1310, 1310', 1311, 1312A, 1312B, 1312C, 1312C': Current source

[0049] 138A~138D:current source

[0050] 300A, 300B: Linear voltage regulator circuit

[0051] Cc, Cc_1~Cc_[n-1]: Series capacitors

[0052] gm_1~gm_n:transduction coefficient

[0053] Ibq: Quiescent bias current

[0054] Ibtr_1~Ibtr_[n-1], Ibtr': transient bias current

[0055] Icb: common mode bias current

[0056] Ido_2~Ido_n, Ido_m, Ido_2a, Ido_2b: transduction output current

[0057] Idp, Idn, Idn': transduction current

[0058] Ido: transduction output current

[0059] MA1, MA2: Amplifying transistors

[0060] Mc1, Mc1': stacked transistors

[0061] Mm1, Mm1': mirror transistors

[0062] MN1 and MN2: MOS diodes

[0063] MP1, MP24: Differential transistors

[0064] Mz: MOS transistor

[0065] ncm1, ncm2, ncm3, ncm3': common-mode bias nodes

[0066] ncp, ncn: overlapping nodes

[0067] Vbc, Vbc': bias voltage

[0068] Vd, Vd_1~Vd_n: differential input voltage

[0069] VFB: Feedback voltage

[0070] Vip, Vin, Vip_1, Vin_1~Vip_n, Vin_n: differential input terminals

[0071] VREG: Regulates output voltage

[0072] VREF, VREF1, VREF2: reference voltage

[0073] Z_1~Z_[n-1]:DC bias load DETAILED DESCRIPTION

[0074] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0075] Figure 2A-2B A block diagram and a schematic diagram of an embodiment of a parallel input and dynamic series transconductance amplifier circuit of the present invention (transconductance amplifier circuit 1002) are shown. In one embodiment, as Figure 2A and Figure 2B As shown, the transconductance amplifier circuit 1002 has multiple pairs of differential input terminals (Vip_1, Vin_1) to (Vip_n, Vin_n), where n is a positive integer greater than 1, and generates an amplified output voltage Vo_1 and a transconductance output current Ido_1 according to differential input voltages Vd_1 to Vd_n, where the differential input voltages Vd_1 to Vd_n correspond to the voltage differences of the differential input terminals (Vd_1 = Vip_1 - Vin_1, ... Vd_n = Vip_n - Vin_n), respectively.

[0076] like Figure 2B As shown, in this embodiment, the transconductance amplifier circuit 1002 includes multiple sub-transconductance amplifier circuits 100_1~100_n. The sub-transconductance amplifier circuits 100_1~100_n each have a corresponding transconductance coefficient gm_1~gm_n. In this embodiment, the amplified output voltage of the transconductance amplifier circuit 1002 corresponds to the sub-output voltage Vo_1 of the sub-transconductance amplifier circuit 100_1.

[0077] In this embodiment, according to the present invention, at least two of the plurality of sub-transconductance amplifier circuits 100_1-100_n are cascaded with each other via a series capacitor. Specifically, for example, the sub-transconductance amplifier circuits 100_1-100_2 are cascaded with each other via a series capacitor Cc_1. The transconductance output current Ido_2 of the sub-transconductance amplifier circuit 100_2 generates a transient bias current Ibtr_1 at a common-mode bias node in the sub-transconductance amplifier circuit 100_1 via the series capacitor Cc_1. When the differential input voltage Vd_1 of the sub-transconductance amplifier circuit 100_1 changes, the transient bias current is provided to the differential pair circuit in the sub-transconductance amplifier circuit 100_1. This improves loop bandwidth and response speed during transient conditions, and reduces the bias current to lower bandwidth and enhance stability during steady-state conditions.

[0078] In one aspect, when the differential input voltage (e.g., Vd_1, Vd_2) changes, the series capacitor Cc_1 feeds the AC component of the transconductance output current Ido_2 of the sub-transconductance amplifier circuit 100_2 to at least one common-mode bias node in the sub-transconductance amplifier circuit 100_1, thereby generating the aforementioned transient bias current (Ibtr_1).

[0079] Please continue reading Figure 2B In one embodiment, as Figure 2B As shown, the output ends of the front-stage sub-transconductance amplifier circuits (100_2~100_n) for generating the above-mentioned transient bias current are respectively coupled to corresponding DC bias loads Z_1~Z_[n-1], wherein the DC bias loads Z_1~Z_[n-1] are used to respectively determine the DC bias voltage (i.e., sub-output voltages Vo_2~Vo_n) of the front-stage sub-transconductance amplifier circuits (100_2~100_n) according to the transconductance output currents Ido_2~Ido_n.

[0080] Specifically, if Figure 2C As shown, in one embodiment, the DC bias load Z (corresponding to the aforementioned Z_1 to Z_[n-1]) each includes a MOS diode, thereby determining the aforementioned DC bias. It should be noted that the MOS diode, for example Figure 2CAs shown, a MOS transistor Mz is coupled in the form of a diode, and its drain and source are short-circuited or coupled in phase, and the same applies below.

[0081] It is noteworthy that when the differential input voltage changes, all differential input voltages of the plurality of sub-transconductance amplifier circuits 100_1-100_n are correlated with one another. In other words, when the differential input voltage Vd_1 of the sub-transconductance amplifier circuit 100_1 changes, the differential input voltages Vd_2-Vd_n of the other sub-transconductance amplifier circuits 100_2-100_n also change in a correlated manner. In a preferred embodiment, when the differential input voltage Vd_1 of the sub-transconductance amplifier circuit 100_1 changes, the differential input voltages Vd_2-Vd_n of the other sub-transconductance amplifier circuits 100_2-100_n also change in a positively correlated manner.

[0082] Figure 3A A block diagram of an embodiment of the present invention is shown as follows (transconductance amplifier circuit 1003A, linear voltage regulator circuit 300A) of a parallel input and dynamic series transconductance amplifier circuit and a linear voltage regulator circuit. Figure 3A As shown, all pairs of differential input terminals (Vip_1, Vin_1) through (Vip_n, Vin_n) of transconductance amplifier circuit 1003A are connected in parallel. Specifically, in this embodiment, all in-phase differential input terminals (Vip_1 through Vip_n) are directly electrically connected to one another, and all inverting differential input terminals (Vin_1 through Vin_n) are also directly electrically connected to one another. In other words, the differential input voltages Vd_1 through Vd_n of this embodiment are identical.

[0083] In this embodiment, Figure 3A As shown, the transconductance amplifier circuit 1003A is configured as a linear voltage regulator circuit 300A with a gain of A=1+R1 / R2 in a negative feedback manner to generate a regulated output voltage VREG, wherein all the in-phase differential input terminals (Vip_1 to Vip_n) are directly electrically connected to the reference voltage VREF, and all the inverting differential input terminals (Vin_1 to Vin_n) are directly electrically connected to the feedback voltage VFB. Therefore, when the feedback voltage VFB is transiently different from the reference voltage VREF due to, for example, a load change, When a voltage difference occurs, the sub-transconductance amplifier circuits 100_2 to 100_n generate transient bias currents Ibtr_1 to Ibtr_[n-1] according to the transient voltage difference between the reference voltage VREF and the feedback voltage VFB through the series capacitors Cc_1 to Cc_[n-1], respectively, and provide them to the differential pair circuits in the sub-transconductance amplifier circuits 100_1 to 100_[n-1]. This improves the loop bandwidth and response speed during transient conditions, and reduces the bias current to reduce the bandwidth and improve stability during steady-state conditions.

[0084] Figure 3B A block diagram of an embodiment of a parallel-input and dynamically serially connected transconductance amplifier circuit and a linear regulator circuit (transconductance amplifier circuit 1003B, linear regulator circuit 300B) of the present invention is shown. The linear regulator circuit 300B of this embodiment is similar to the linear regulator circuit 300A of the aforementioned embodiment, except that in this embodiment, the differential input voltage Vd_1 of the transconductance amplifier circuit 1003B corresponds to the voltage difference between the reference voltage VREF1 and the feedback voltage VFB of the linear regulator circuit 300B, while the differential input voltages Vd_2 to Vd_n of the transconductance amplifier circuit 1003B correspond to the voltage difference between the reference voltage VREF2 and the regulated output voltage VREG of the linear regulator circuit 300B. The reference voltage VREF2 to the reference voltage VREF1 corresponds to the ratio of the regulated output voltage VREG to the feedback voltage VFB, i.e., this ratio is equal to the aforementioned gain A=1+R1 / R2.

[0085] Please also see Figure 2B In one embodiment, in the preceding transconductance amplifier circuits connected in series, the transconductance coefficient of the preceding sub-transconductance amplifier circuit is greater than the transconductance coefficient of the succeeding sub-transconductance amplifier circuit. Taking the sub-transconductance amplifier circuits 100_1 to 100_2 as an example, in one embodiment, the transconductance coefficient gm_2 is greater than the transconductance coefficient gm_1. As a result, when the differential input voltage changes, the preceding sub-transconductance amplifier circuit (such as the sub-transconductance amplifier circuit 100_2) can provide the aforementioned transient bias current to the succeeding sub-transconductance amplifier circuit (such as the sub-transconductance amplifier circuit 100_1) in a more timely manner.

[0086] Figures 4A to 4C Schematic diagrams showing several specific embodiments of sub-transconductance amplifier circuits (sub-transconductance amplifier circuits 104A-104C) in the parallel input and dynamic series transconductance amplifier circuit of the present invention. In one embodiment, Figure 4A As shown, the sub-transconductance amplifier circuit 104A is configured as a single-stage transconductance amplifier with differential input to single-ended output. The in-phase differential transistor MP1 and the inverting differential transistor MP2 in the differential amplifier pair 114A generate a transconductance current Idn and a transconductance current Idp, respectively, in response to the differential input voltage Vd, thereby generating a transconductance output current Ido. Specifically, the transconductance output current Ido is the difference between the transconductance current Idp and the transconductance current Idn. The transconductance output current Ido is equal to the product of the differential input voltage Vd and the transconductance coefficient gm of the sub-transconductance amplifier circuit 104A, i.e., Ido = Vd * gm. It should be noted that the transconductance output current Ido herein specifically refers to the output current related to the differential input voltage Vd.

[0087] In one embodiment, if Figure 4A As shown, the aforementioned transient bias current Ibtr is input to the common-mode bias node ncm1 of the sub-transconductance amplifier circuit 104A, where the current source 130 also provides a static bias current Ibq via the common-mode bias node ncm1. When a transient voltage difference occurs in the differential input voltage Vd, the transient bias current Ibtr generated by the series-connected preceding sub-transconductance amplifier circuit increases the total bias current of the differential amplifier pair 114A, thereby improving the loop bandwidth and response speed during the transient state. Conversely, when the transient state ends and the circuit enters a steady state, the transient bias current Ibtr gradually approaches zero, thereby reducing the total bias current and lowering the bandwidth to improve stability.

[0088] It should be noted that the common-mode bias node ncm1 described above is only one example. When the aforementioned transient bias current Ibtr is input through the common-mode bias node, the bias currents of the in-phase differential transistor MP1 and the inverting differential transistor MP2 can be increased in the low-frequency component, and the low-frequency components of the transduction current Idp and the transduction current Idn can also be increased. Therefore, for DC or low-frequency components, a node with such characteristics can be used as a "common-mode bias node." Other embodiments of the common-mode bias node will be described in detail later.

[0089] From one perspective, the present invention also improves loop bandwidth and response speed during transient conditions according to the following configuration. In one embodiment, the sub-transconductance amplifier circuit of the front stage (such as Figure 2B The impedance of the DC bias load (Z_1) corresponding to the sub-transconductance amplifier circuit 100_2 is large enough so that the corresponding series capacitor Cc_1 generates a pole Pl_1 at the common-mode bias node (e.g., ncm1) in the sub-transconductance amplifier circuit 100_1. This pole is sufficiently low-frequency, thereby ensuring a sufficiently large phase difference (at least within the unity-gain bandwidth) between the transconductance current Idp and the transconductance current Idn generated by the sub-transconductance amplifier circuit 100_1. This results in a larger net output current during transient conditions, thereby effectively improving the loop bandwidth and response speed.

[0090] Furthermore, it is worth noting that in this embodiment, the inverting differential transistor MP2 directly generates the transconductance current Idp in response to the differential input voltage Vd, while the non-inverting differential transistor MP1 generates the transconductance current Idn' in response to the differential input voltage Vd, which then passes through a first-stage current mirror 120 before generating the transconductance current Idn. Therefore, based on the foregoing aspects of the present invention, when the sub-transconductance amplifier circuit 104A is configured as a single-stage transconductance amplifier with differential input to single-ended output (such as the sub-transconductance amplifier circuit 104A), a further phase difference can be created between the transconductance current Idp and the transconductance current Idn during transient conditions.

[0091] See also Figure 4BIn one embodiment, as Figure 4B As shown, the sub-transconductance amplifier circuit 104B is similar to the sub-transconductance amplifier circuit 104A, except that the in-phase differential transistor MP1 and the inverting differential transistor MP2 in the differential amplifier pair 114B are respectively coupled to MOS diodes MN1 and MN2 with the same impedance, and then generate a transconductance current Idp and a transconductance current Idn through the current mirror circuit (121, 122, 123), thereby generating a transconductance output current Ido.

[0092] In one embodiment, if Figure 4C As shown, the sub-transconductance amplifier circuit 104C is configured as a folded cascode transconductance amplifier. The in-phase differential transistor MP1 and the inverting differential transistor MP2 in the differential amplifier pair 114C respectively generate a transconductance current Idp and a transconductance current Idn″ according to the differential input voltage Vd, which are respectively injected into the cascade nodes ncp and ncn of the cascaded current mirror 125, wherein the cascaded current mirror 125 receives the transconductance current Idn″ and generates a transconductance current Idn.

[0093] and Figure 4A Similar, such as Figure 4B and Figure 4C As shown, in these embodiments, the aforementioned transient bias current Ibtr is input to the common-mode bias node ncm1 of the sub-transconductance amplifier circuit 104B or 104C, wherein the current source 130 also provides a static bias current Ibq through the common-mode bias node ncm1.

[0094] Figure 5 The open-loop frequency response curve corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown as follows: Figure 5 As shown, compared to the open-loop characteristic (dashed line) of the transconductance amplifier circuit without the transient bias current Ibtr, the embodiment of the present invention in which the transient bias current Ibtr is introduced by connecting a series capacitor (solid line) has a similar unity gain bandwidth, that is, there is no loss of bandwidth due to the series capacitor. In addition, in the embodiment of the present invention in which the transient bias current Ibtr is introduced (solid line), the phase margin is higher, that is, more stable. Specifically, taking the sub-transconductance amplifier circuit 100_1 as an example, the series capacitor corresponding to the previous stage (such as Figure 2B), generates a zero Zr_1 before the unity-gain bandwidth of sub-transconductance amplifier circuit 100_1, thereby improving the phase margin of the sub-transconductance amplifier circuit. In other words, from a time-domain perspective, when a transient voltage difference occurs in the differential input voltage Vd and gradually approaches zero due to feedback, the transient bias current Ibtr also gradually approaches zero. At this point, in addition to improving stability by reducing the bandwidth due to the return to a lower quiescent bias current Ibq, the aforementioned series capacitor (e.g., Cc_1) also continues to provide compensation or loop stabilization. It should be noted that the aforementioned zero Zr_1 = Pl_1 / N_1, where N_1 is a real number greater than 1. In one embodiment, appropriately selecting N_1 can achieve a phase margin of 45 degrees or greater for sub-transconductance amplifier circuit 100_1. In another embodiment, appropriately selecting N_1 can achieve a phase margin of 60 degrees or greater for sub-transconductance amplifier circuit 100_1.

[0095] Figure 6 The closed-loop transient response waveform corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown as follows: Figure 6 As shown, compared with the transient response of the transconductance amplifier circuit without the transient bias current Ibtr (dashed line), the embodiment of the present invention in which the transient bias current Ibtr is introduced by connecting a capacitor in series (solid line) can return to stability in a shorter time.

[0096] Figure 7 The open-loop small signal transient response waveform corresponding to an embodiment of the parallel input and dynamic series transconductance amplifier circuit of the present invention is shown as follows: Figure 7 As shown, compared with the open-loop small-signal transient response of the transconductance amplifier circuit without the transient bias current Ibtr (dashed line), the embodiment of the present invention in which the transient bias current Ibtr is introduced by connecting a capacitor in series (solid line) can generate larger transconductance currents Idp and Idn. Moreover, since the transconductance current difference (Idp-Idn) has a smaller phase delay, the small-signal output voltage also exhibits a higher phase margin.

[0097] Figures 8A to 8D Schematic diagrams showing several specific embodiments of current sources (current sources 138A-138D) for providing static bias current Ibq in the parallel input and dynamic series transconductance amplifier circuit of the present invention. In one embodiment, Figure 8AAs shown, the current source 138A includes a mirror transistor Mm1 for mirroring current, whose current output terminal is coupled to the common-mode bias node ncm1 to generate a static bias current Ibq. In this embodiment, a series capacitor Cc is electrically coupled to the current output terminal of the mirror transistor Mm1, that is, the common-mode bias node ncm1, to receive the transconductance output current (such as Ido_2) of the previous stage and provide a transient bias current Ibtr to the differential amplifier pair 118 at the common-mode bias node ncm1.

[0098] In one embodiment, if Figure 8B As shown, current source 138B includes a mirror transistor Mm1 for mirroring current. Its current output terminal is coupled to the common-mode bias node ncm1 to generate a static bias current Ibq. In this embodiment, a series capacitor Cc is electrically coupled to the control terminal (gate) of mirror transistor Mm1, i.e., the common-mode bias node ncm2. In this embodiment, the transient bias current Ibtr controls the mirror transistor Mm1 via the common-mode bias node ncm2 to generate a transient bias current Ibtr' for the differential amplifier pair 118. In other words, the mirror transistor Mm1 simultaneously mirrors the static bias current Ibq and simultaneously controls the control terminal of the mirror transistor Mm1 to generate a transient bias current Ibtr' by coupling the transconductance output current (e.g., Ido_2) of the preceding stage via the series capacitor Cc. Both are then provided to the differential amplifier pair 118. Of course, in this embodiment, the non-inverting and inverting input terminals of the preceding sub-transconductance amplifier circuit need to be adaptively adjusted.

[0099] In one embodiment, if Figure 8C As shown, the current source 138C includes a mirror transistor Mm1 for mirroring current and a cascade transistor Mc1 for increasing output impedance. The mirror transistor Mm1 and the cascade transistor Mc1 are cascaded between the supply voltage and the common-mode bias node ncm1 (i.e., cascaded at node ncm3). The cascade transistor Mc1 is biased by the cascade bias voltage Vbc. In this embodiment, the series capacitor Cc is electrically coupled to the current output terminal of the cascade transistor Mc1, i.e., the common-mode bias node ncm1, to provide a transient bias current Ibtr to the differential amplifier pair 118 at the common-mode bias node ncm1.

[0100] In one embodiment, if Figure 8DAs shown, the current source 138D includes a mirror transistor Mm1 for mirroring current and a cascade transistor Mc1 for increasing output impedance. The mirror transistor Mm1 and the cascade transistor Mc1 are cascaded between a supply voltage and a common-mode bias node ncm1. The cascade transistor Mc1 is biased by the cascade bias voltage. In this embodiment, a series capacitor Cc is electrically coupled to the node where the mirror transistor Mm1 and the cascade transistor Mc1 are cascaded, i.e., the common-mode bias node ncm3, to provide a transient bias current Ibtr to the differential amplifier pair 118 at the common-mode bias node ncm3 (also via the common-mode bias node ncm1).

[0101] Figures 9A and 9B A block diagram of an embodiment of a parallel-input and dynamically cascaded transconductance amplifier circuit according to the present invention (transconductance amplifier circuits 109A-109B) is shown. According to the present invention, transient bias currents are not limited to being injected into a single common-mode bias node of a sub-transconductance amplifier circuit. In one embodiment, a sub-transconductance amplifier circuit within the transconductance amplifier circuit can receive multiple transient bias currents at multiple common-mode bias nodes of the sub-transconductance amplifier circuit via multiple series capacitors.

[0102] In one embodiment, if Figure 9A As shown, the sub-transconductance amplifier circuit 100_1 receives transient bias currents Ibtr_2 and Ibtr_3 from different preceding sub-transconductance amplifier circuits 100_2 and 100_3 at a plurality of common-mode bias nodes. Figure 9B As shown, the sub-transconductance amplifier circuit 100_1 receives transient bias currents Ibtr_2a and Ibtr_2b from the sub-transconductance amplifier circuit 100_2′ at multiple common-mode bias nodes via capacitors Cc_2a and Cc_2b connected in series. In this embodiment, the sub-transconductance amplifier circuit 100_2′ outputs independently adjustable transconductance output currents Ido_2a and Ido_2b. Thus, the current ratio and the impedance values ​​of Z_2a and Z_2b can be individually adjusted to design different pole and zero positions without affecting each other.

[0103] Figure 9C A schematic diagram of a specific embodiment of a sub-transconductance amplifier circuit (sub-transconductance amplifier circuit 100_2′) in the parallel-input and dynamic series transconductance amplifier circuit of the present invention is shown. In this embodiment, the front-stage sub-transconductance amplifier circuit 100_2′ generates independently adjusted transconductance output currents Ido_2a and Ido_2b through the current mirror circuit 123′.

[0104] Figure 10AA schematic diagram showing a specific embodiment of a sub-transconductance amplifier circuit and a current source therein for providing a static bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention (current source 1310) is shown. In one embodiment, the current source (1310) of the sub-transconductance amplifier circuit 100 is configured as the aforementioned stacked current source, such as Figure 10A As shown, the current source 1310 includes a mirror transistor Mm1 for mirroring current and a cascade transistor Mc1 for increasing output impedance. The mirror transistor Mm1 and the cascade transistor Mc1 are cascaded between the supply voltage and the common-mode bias node ncm1. The cascade transistor Mc1 is biased by the cascade bias voltage Vbc. In this embodiment, the common-mode bias node receives transient bias currents Ibtr_a and Ibtr_b from different series capacitors Cc_a and Cc_b, wherein the series capacitor Cc_a is electrically The capacitor Cc_b is coupled to the node where the mirror transistor Mm1 and the cascade transistor Mc1 are cascaded, i.e., the common-mode bias node ncm3, to provide a transient bias current Ibtr_a to the differential amplifier pair 1110 at the common-mode bias node ncm3 (which also flows through the common-mode bias node ncm1). The series capacitor Cc_b is electrically coupled to the current output node of the cascade transistor Mc1, i.e., the common-mode bias node ncm1, to provide a transient bias current Ibtr_b to the differential amplifier pair 1110 at the common-mode bias node ncm1. The transient bias currents Ibtr_a and Ibtr_b may correspond to the aforementioned Figure 9A The transient bias currents Ibtr_2 and Ibtr_3 in the embodiment correspond to the aforementioned Figure 9B The transient bias currents Ibtr_2a and Ibtr_2b in the embodiment.

[0105] Figure 10B A schematic diagram showing another embodiment of a sub-transconductance amplifier circuit and a current source therein for providing a static bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention (current sources 1310, 1310') is provided. In one embodiment, the current sources (1310, 1310') of the sub-transconductance amplifier circuit 100' are configured as the aforementioned stacked current sources, such as Figure 10BAs shown, current sources 1310 and 1310' respectively include mirror transistors Mm1 and Mm1' for mirroring current, and cascade transistors Mc1 and Mc1' for increasing output impedance. Mirror transistor Mm1 and cascade transistor Mc1 are cascaded between the supply voltage and the common-mode bias node ncm1. Mirror transistor Mm1' and cascade transistor Mc1' are cascaded between the supply voltage and the common-mode bias node ncm1. Cascade transistor Mc1 and cascade transistor Mc1' are biased by cascade bias voltages Vbc and Vbc', respectively. In this embodiment, the common-mode bias node receives voltages from different series capacitors Cc_a. The series capacitor Cc_a is electrically coupled to the node where the mirror transistor Mm1 and the cascade transistor Mc1 are cascaded, i.e., the common-mode bias node ncm3, to provide the transient bias current Ibtr_a to the differential amplifier pair 1110 at the common-mode bias node ncm3 (also flowing through the common-mode bias node ncm1). The series capacitor Cc_b is electrically coupled to the bias node ncm3' to provide the transient bias current Ibtr_b to the differential amplifier pair 1110 at the common-mode bias node ncm3' (also flowing through the common-mode bias node ncm1).

[0106] It is noteworthy that during transient conditions, differential amplifier pair 1110 actually receives the sum of transient bias current Ibtr_a and transient bias current Ibtr_b. Therefore, loop bandwidth and response speed can be more effectively improved during transient conditions. During steady-state conditions, bias current is reduced to lower bandwidth and improve stability. Furthermore, because transient bias current Ibtr_a and transient bias current Ibtr_b are respectively injected into the terminals of cascade transistor Mc1, cascade transistor Mc1 or Mc1' also provides an impedance buffer between series capacitor Cc_a and series capacitor Cc_b.

[0107] Figure 11 A schematic diagram showing a specific embodiment of a sub-transconductance amplifier circuit and a current source for providing a bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention (current source 1311). Figure 11 As shown, the transconductance amplifier circuit 1011 further includes another sub-transconductance amplifier circuit 100_m, where m is a positive integer not equal to 1-n. The sub-transconductance amplifier circuit 100_m is similar to the aforementioned sub-transconductance amplifier circuits 100_1-100_n, except that the transconductance output current Ido_m of the sub-transconductance amplifier circuit 100_m is directly electrically coupled to, for example, Figure 11 The common-mode bias node nm1 of the sub-transconductance amplifier circuit 100_1 is shown.

[0108] In other words, in this embodiment, the transconductance output current Ido_m of the sub-transconductance amplifier circuit 100_m and the transconductance output current Ido_2 of the sub-transconductance amplifier circuit 100_2 are respectively injected into the two ends of the series capacitor Cc_2. In this case, the two ends of the series capacitor Cc_2 simultaneously receive currents of the same phase and similar magnitude. From one perspective, the series capacitor Cc_2 does not cause a loading effect on the transconductance output current Ido_2. That is, it does not respond to common-mode signals, but only to differential-mode signals. This allows the aforementioned effects to be more effectively achieved.

[0109] Figure 12A and Figure 12B Schematic diagrams showing two specific embodiments of the sub-transconductance amplifier circuit and the current source therein for providing bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention (current source 1312A and current source 1312B). Figure 11 Similar to the embodiment, the transconductance amplifier circuit 1012A or 1012B further includes another sub-transconductance amplifier circuit 100_m, the difference being that the transconductance output current Ido_m of the sub-transconductance amplifier circuit 100_m and the transconductance output current Ido_2 of the sub-transconductance amplifier circuit 100_2 are respectively injected into the common-mode bias node ncm1 and the common-mode bias node ncm3 of the sub-transconductance amplifier circuit 100_1, or respectively injected into the common-mode bias node ncm3 and the common-mode bias node ncm1 of the sub-transconductance amplifier circuit 100_1.

[0110] Figure 12C A schematic diagram showing another embodiment of a sub-transconductance amplifier circuit and a current source for providing bias current in the parallel input and dynamic series transconductance amplifier circuit of the present invention (current source 1312C). This embodiment is similar to Figure 12B The difference between the embodiments is that the transconductance output current Ido_2 of the sub-transconductance amplifier circuit 100_2 is first injected into the common-mode bias node ncm3' of the current source 1312C' and then injected into the common-mode bias node ncm1 through the cascaded transistor Mc1', so that the transconductance output current Ido_m and the transconductance output current Ido_2 can be effectively isolated and independently designed without affecting each other.

[0111] Of course, in other embodiments, the common-mode bias node into which the transconductance output current Ido_m and the transconductance output current Ido_2 are injected may also be exchanged, which will not be described in detail here.

[0112] The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be applied in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A parallel input and dynamic series transconductance amplifier circuit comprising: a plurality of sub-transconductance amplifier circuits, wherein each of the sub-transconductance amplifier circuits generates a corresponding transconductance output current according to a differential input voltage linearly coupled to the plurality of sub-transconductance amplifier circuits, the plurality of sub-transconductance amplifier circuits including a first sub-transconductance amplifier circuit and a second sub-transconductance amplifier circuit; and At least one series capacitor, wherein the series capacitor is used to connect the corresponding two sub-transconductance amplifier circuits in series, and the at least one series capacitor includes a first series capacitor connected in series with the first sub-transconductance amplifier circuit and the second sub-transconductance amplifier circuit; A second transconductance output current corresponding to the second sub-transconductance amplifier circuit is AC-coupled through the corresponding first series capacitor to generate a transient bias current at a common-mode bias node in the first sub-transconductance amplifier circuit. When a transient state occurs in a differential input voltage corresponding to the first sub-transconductance amplifier circuit, the transient bias current is provided to a common-phase transconductance current and a counter-phase transconductance current of a differential pair circuit in the first sub-transconductance amplifier circuit. During the transient state, a phase difference between the common-phase transconductance current and the counter-phase transconductance current is sufficiently large to enhance a transconductance output current output by the differential pair circuit, thereby improving loop bandwidth and response speed during the transient state. In a steady state, the transient bias current is reduced to reduce bandwidth and improve stability.

2. The parallel-input and dynamic series transconductance amplifier circuit as claimed in claim 1, wherein the pair of differential input terminals of the first sub-transconductance amplifier circuit and the pair of differential input terminals of the second sub-transconductance amplifier circuit are connected in parallel.

3. The parallel-input and dynamic series transconductance amplifier circuit as described in claim 1 , wherein the transconductance coefficient of the second sub-transconductance amplifier circuit is greater than the transconductance coefficient of the first sub-transconductance amplifier circuit, so that the phase difference between the in-phase transconductance current and the anti-phase transconductance current in the first sub-transconductance amplifier circuit is sufficiently large in the transient state.

4. The parallel-input and dynamic series transconductance amplifier circuit as described in claim 1 further includes a DC bias load coupled to the output terminal of the second sub-transconductance amplifier circuit and coupled to the first series capacitor, wherein the DC bias load is used to receive the second transconductance output current to provide a corresponding DC bias voltage at the output terminal of the second sub-transconductance amplifier circuit. 5 . The parallel-input and dynamic series transconductance amplifier circuit as claimed in claim 4 , wherein the DC bias load comprises a MOS diode.

6. The parallel-input and dynamic series transconductance amplifier circuit of claim 4 , wherein each of the sub-transconductance amplifier circuits is configured as a pair of transconductance amplifiers with differential inputs to single-ended outputs, wherein the impedance of the DC bias load corresponding to the second sub-transconductance amplifier circuit is large enough so that the first series capacitor generates a pole at the common-mode bias node in the first sub-transconductance amplifier circuit at a sufficiently low frequency, so that the phase difference is large enough to enhance the transconductance output current, and / or the parallel-input and dynamic series transconductance amplifier circuit has a phase margin greater than or equal to 45 degrees at a unity-gain bandwidth.

7. The parallel-input and dynamic series transconductance amplifier circuit as claimed in claim 6 , wherein the first series capacitor generates a zero point before the unity gain bandwidth of the first sub-transconductance amplifier circuit, thereby enabling the parallel-input and dynamic series transconductance amplifier circuit to have a phase margin greater than or equal to 45 degrees under the unity gain bandwidth.

8. The parallel-input and dynamic series transconductance amplifier circuit of claim 1 , wherein one of the plurality of sub-transconductance amplifier circuits is configured as at least one of the following: (1) A single-stage differential input to single-ended output transconductance amplifier, wherein the single-stage differential input to single-ended output transconductance amplifier includes an in-phase differential transistor and an inverting differential transistor for generating an in-phase transconductance current and an inverting transconductance current according to the corresponding differential input voltage, wherein the in-phase differential transistor is coupled to a MOS diode; (2) a balanced differential input to single-ended output transconductance amplifier, wherein the balanced differential input to single-ended output transconductance amplifier includes an in-phase differential transistor and an inverting differential transistor for generating an in-phase transconductance current and an inverting transconductance current according to the corresponding differential input voltage, wherein the in-phase differential transistor and the inverting differential transistor are respectively coupled to corresponding MOS diodes; or (3) A folded differential input to single-ended output transconductance amplifier, wherein the folded differential input to single-ended output transconductance amplifier includes an in-phase differential transistor, an inverting differential transistor, and a folded current mirror circuit for generating an in-phase transconductance current and an inverting transconductance current according to the corresponding differential input voltage, wherein the in-phase differential transistor and the inverting differential transistor are respectively coupled to corresponding folding nodes in the folded current mirror circuit.

9. The parallel-input and dynamic series transconductance amplifier circuit of claim 8 , wherein the sub-transconductance amplifier circuit comprises a current source circuit coupled to the in-phase differential transistor and an inverting differential transistor, wherein the common-mode bias node corresponds to one of the following: (1) The common-mode bias node corresponds to a coupling node between the current source circuit, the in-phase differential transistor, and the inverting differential transistor; (2) the common-mode bias node corresponds to a control terminal of the current source circuit; or (3) The common-mode bias node corresponds to a cascade node of the current source circuit, wherein the current source circuit is configured as a cascade current source circuit.

10. The parallel-input and dynamic series transconductance amplifier circuit of claim 1 , wherein the first sub-transconductance amplifier circuit further receives another transient bias current at another common-mode bias node via a second series capacitor, and provides the other transient bias current to the differential pair circuit in the first sub-transconductance amplifier circuit during a transient state in which a differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, thereby improving loop bandwidth and response speed during the transient state and reducing the bias current to reduce bandwidth and improve stability during a steady state. The other transient bias current is generated by one of the following configurations: (1) The second sub-transconductance amplifier circuit further generates the other transient bias current; or (2) The plurality of sub-transconductance amplifier circuits include a third sub-transconductance amplifier circuit, wherein a third transconductance output current corresponding to the third sub-transconductance amplifier circuit passes through the corresponding second series capacitor to generate the other transient bias current at the other common-mode bias node in the first sub-transconductance amplifier circuit.

11. The parallel-input and dynamic series transconductance amplifier circuit of claim 10 , wherein the first sub-transconductance amplifier circuit further comprises a current source circuit coupled to the differential pair circuit of the first sub-transconductance amplifier circuit, wherein the common-mode bias node corresponds to a coupling node between the current source circuit and the differential pair circuit, and the other common-mode bias node corresponds to a cascade node of the current source circuit, wherein the current source circuit is configured as a cascade current source circuit.

12. The parallel-input and dynamic series transconductance amplifier circuit of claim 1 , wherein the first sub-transconductance amplifier circuit further receives another transient bias current through the common-mode bias node, and provides the another transient bias current to the differential pair circuit in the first sub-transconductance amplifier circuit during a transient state when a differential input voltage corresponding to the first sub-transconductance amplifier circuit undergoes a transient change, thereby improving loop bandwidth and response speed during the transient state, and reducing the bias current to reduce bandwidth and improve stability during a steady state, wherein the another transient bias current is generated by one of the following configurations: (1) The second sub-transconductance amplifier circuit further generates the other transient bias current; or (2) The plurality of sub-transconductance amplifier circuits include a third sub-transconductance amplifier circuit, wherein the third sub-transconductance amplifier circuit generates another transient bias current at the common-mode bias node in the first sub-transconductance amplifier circuit in response to a third transconductance output current generated by the third sub-transconductance amplifier circuit.

13. The parallel-input and dynamic series transconductance amplifier circuit of claim 1 , wherein the first sub-transconductance amplifier circuit further comprises a current source circuit coupled to the differential pair circuit of the first sub-transconductance amplifier circuit, wherein the common-mode bias node corresponds to a coupling node between the current source circuit and the differential pair circuit, wherein another common-mode bias node corresponds to a cascade node of the current source circuit, and wherein the current source circuit is configured as a cascade current source circuit; wherein the first sub-transconductance amplifier circuit further receives another transient bias current through the another common-mode bias node, and provides the another transient bias current to the differential pair circuit of the first sub-transconductance amplifier circuit when a transient change occurs in a differential input voltage corresponding to the first sub-transconductance amplifier circuit, thereby improving loop bandwidth and response speed in the transient state, and reducing the bias current in the steady state to reduce bandwidth and improve stability, wherein the another transient bias current is generated by one of the following configurations: (1) The second sub-transconductance amplifier circuit further generates the other transient bias current; or (2) The plurality of sub-transconductance amplifier circuits include a third sub-transconductance amplifier circuit, wherein the third sub-transconductance amplifier circuit generates another transient bias current at the other common-mode bias node in the first sub-transconductance amplifier circuit in response to a third transconductance output current generated by the third sub-transconductance amplifier circuit.

14. A regulating circuit comprising: The parallel input and dynamic series transconductance amplifier circuit according to any one of claims 1 to 13; an output transistor; and A feedback circuit, wherein one end of the differential input terminal corresponding to the first sub-transconductance amplifier circuit is coupled to a first reference signal, and the other end of the differential input terminal corresponding to the first sub-transconductance amplifier circuit is used to receive the feedback signal to adjust the output signal to a target value, wherein the target value is related to the first reference signal; The second sub-transconductance amplifier circuit is configured as one of the following: One end of the differential input terminal corresponding to the second sub-transconductance amplifier circuit is coupled to a second reference signal, and the other end of the differential input terminal corresponding to the second sub-transconductance amplifier circuit is used to receive the output signal, wherein a ratio of the second reference signal to the first reference signal is related to a feedback gain of the feedback circuit; or A pair of differential input terminals of the second sub-transconductance amplifier circuit is coupled in parallel with a pair of differential input terminals of the first sub-transconductance amplifier circuit.

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