Data storage method based on reconfigurable processor and reconfigurable processor

Abstract

The present application relates to a data storage method based on a reconfigurable processor, a reconfigurable processor, a computer device, a storage medium and a computer program product. The method comprises: determining the target data containing multiple sub-data required by the computing task, and in the data import unit, dividing each sub-data in the target data by a preset data partitioning algorithm and the data simultaneous access conditions corresponding to the computing task to obtain a read address transformation parameter; according to the external memory address of each sub-data and the read address transformation parameter, respectively calculating the target address of each sub-data in the memory block, and storing the target data to the target address. By using the method provided in the embodiment of the present invention to import data from the external memory, access conflicts can be avoided and the processing performance of the reconfigurable processor can be guaranteed.

Description

Technical Field

[0001] The present application relates to the technical field of reconfigurable processors, and in particular to a data storage method based on a reconfigurable processor and a reconfigurable processor. Background Art

[0002] Reconfigurable processor is a new type of general computing architecture. By utilizing parallelism in multiple dimensions such as instruction-level parallelism and data-level parallelism, it has significant advantages over traditional dedicated custom circuits, general-purpose processors, and field programmable logic arrays in many application fields. Reconfigurable processor has the following characteristics:

[0003] First, the reconfigurable processor has a large number of processing elements (PE). Each processing element can usually perform a variety of arithmetic operations under configuration instructions. By changing the configuration instructions, the functions performed by each processing element can be dynamically changed. The configuration can be changed by upper-level software control in as short as a few clock cycles, so it has significant advantages in flexibility compared to custom circuits and field programmable logic arrays; at the same time, because PE usually performs multi-bit arithmetic operations, the amount of configuration instruction data is significantly lower than that of field programmable logic arrays that need to control single-bit operations;

[0004] Secondly, the processing units of the reconfigurable processor are connected by programmable interconnects. Data is directly transferred from its producer (the processing unit that generates data) to its consumer (the processing unit that uses data) through a pipeline, forming a hardware pipeline similar to a dedicated integrated circuit, which has a significant improvement in computing energy efficiency compared to the register file (RF) method of general-purpose processors.

[0005] In order to speed up the calculation as much as possible, it is usually hoped to make full use of the many processing units in the reconfigurable processor. To achieve this goal, it is usually necessary to explore more computational parallelism through loop unrolling, coarse-grained pipelining, etc. during the task compilation phase. However, due to the constraints of the computing task itself, the parallelism discovered by the above method may cause a simultaneous increase in the on-chip memory access bandwidth, thus also placing higher requirements on the on-chip bandwidth of the architecture itself.

[0006] In order to increase the on-chip bandwidth provided by the memory, the reconfigurable processor is designed with memory blocks in the related art. Each memory block has independent read and write ports. The on-chip bandwidth provided by all memory blocks can be increased synchronously with the number of memory blocks, and the data is also stored in sequence on multiple memory blocks. However, if the data that the array needs to access simultaneously comes from different addresses of the same memory block after the memory block is divided, it will cause access conflicts, resulting in the performance loss of the array. Summary of the invention

[0007] Based on this, it is necessary to provide a data storage method based on a reconfigurable processor, a reconfigurable processor, a computer device, a computer-readable storage medium and a computer program product that can avoid access conflicts caused by accessing different data on the same memory block in order to address the above technical problems.

[0008] In a first aspect, the present application provides a data storage method based on a reconfigurable processor. The reconfigurable processor includes a data import unit and an internal memory, the internal memory includes a plurality of memory blocks, and the method includes:

[0009] Obtaining a computing task, and determining target data required by the computing task, wherein the target data includes a plurality of sub-data;

[0010] In the data import unit, each sub-data in the target data is divided by a preset data division algorithm and a data simultaneous access condition corresponding to the computing task to obtain a read address transformation parameter;

[0011] According to the external memory address of each sub-data and the read address conversion parameter, the target address of each sub-data in the memory block is calculated respectively, and the target data is stored in the target address.

[0012] In one of the embodiments, the data simultaneous access condition includes a read data mode;

[0013] In the data import unit, each sub-data in the target data is divided by a preset data division algorithm and a data simultaneous access condition corresponding to the computing task to obtain an address transformation parameter, including:

[0014] In the data import unit, according to the preset data partitioning algorithm and the read data mode corresponding to the calculation task, a linear transformation calculation is performed on each sub-data in the target data to obtain a read address transformation parameter.

[0015] In one embodiment, the reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of read modules; the method further includes:

[0016] Obtaining the external memory address of the target data through the reading module;

[0017] Calculating a target address according to the external memory address and a read address conversion parameter;

[0018] Based on the target address, data is read from the internal memory.

[0019] In one of the embodiments, the processing unit array further comprises a plurality of write modules, and the data simultaneous access condition further comprises a write data mode;

[0020] By means of the writing module, according to the preset data partitioning algorithm and the writing data mode corresponding to the computing task, each sub-data in the target data is subjected to linear transformation calculation to obtain the writing address transformation parameter, and the external memory address of the target data is obtained;

[0021] Calculating a target address according to the external memory address and the write address conversion parameter;

[0022] Based on the target address, the target data is stored in the internal memory.

[0023] In one embodiment, the reconfigurable processor includes a data export unit; the method further includes:

[0024] Obtaining, by the data export unit, a target address of the target data on the internal memory;

[0025] According to the reverse address transformation parameter corresponding to the write address transformation parameter, the target address is reversely transformed to obtain the external memory address of the target data;

[0026] Based on the external memory address, the target data is stored in the external memory.

[0027] In a second aspect, the present application provides a reconfigurable processor, the reconfigurable processor comprising a data import unit and an internal memory, the internal memory comprising a plurality of memory blocks, wherein:

[0028] The data import unit is used to obtain a computing task and determine the target data required for the computing task, wherein the target data includes multiple sub-data; the sub-data in the target data are divided by a preset data partitioning algorithm and the data simultaneous access conditions corresponding to the computing task to obtain a read address transformation parameter; the target address of each sub-data in the memory block is calculated according to the external memory address of each sub-data and the read address transformation parameter, and the target data is stored in the target address.

[0029] In one embodiment, the reconfigurable processor includes a processing unit array, the processing unit array includes a processing unit, a plurality of read modules and a plurality of write modules, and the data simultaneous access condition further includes a write data mode, wherein:

[0030] The read module is used to obtain the external memory address of the target data; the processing unit is used to calculate the target address according to the external memory address and the read address transformation parameter; the read module is also used to read data in the internal memory based on the target address;

[0031] The write module is used to obtain the external memory address of the target data; the processing unit is also used to perform linear transformation calculations on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and calculate the target address according to the external memory address and the write address transformation parameters; the write module is also used to store the target data in the internal memory.

[0032] In one embodiment, the reconfigurable processor includes a processing unit array, the processing unit array includes a plurality of read modules and a plurality of write modules, the write module includes a first forward address conversion unit and a read unit, the write module includes a second forward address conversion unit and a write unit, the data simultaneous access condition also includes a write data mode, wherein:

[0033] The first forward address conversion unit is used to obtain the external memory address of the target data, and calculate the target address according to the external memory address and the read address conversion parameter;

[0034] The reading unit is used to read data in the internal memory based on the target address;

[0035] The second forward address transformation unit is used to perform linear transformation calculation on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and obtain the external memory address of the target data, and calculate the target address according to the external memory address and the write address transformation parameters;

[0036] The writing unit is used to store the target data into the internal memory.

[0037] In one embodiment, the reconfigurable processor includes a data export unit, and the data export unit includes a reverse address change subunit and a export subunit; wherein:

[0038] The reverse address change subunit is used to obtain the target address of the target data on the internal memory; perform reverse address transformation on the target address according to the reverse address transformation parameter corresponding to the write address transformation parameter to obtain the external memory address of the target data;

[0039] The export subunit is used to store the target data in the external memory based on the external memory address.

[0040] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps described in the above embodiment are implemented.

[0041] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps described in the above embodiment are implemented.

[0042] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps described in the above embodiment are implemented.

[0043] The above-mentioned data storage method based on a reconfigurable processor, reconfigurable processor, computer device, storage medium and computer program product, by determining the target data containing multiple sub-data required by the computing task, in the data import unit, by using a preset data partitioning algorithm and the data simultaneous access conditions corresponding to the computing task, the sub-data in the target data are partitioned to obtain a read address transformation parameter; according to the external memory address of each sub-data and the address transformation parameter, the target address of each sub-data in the memory block is calculated respectively, and the target data is stored in the target address. By using the method provided by the embodiment of the present invention to import data from the external memory, access conflicts can be avoided and the performance of the reconfigurable processor can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic diagram of the structure of a reconfigurable processor in one embodiment;

[0045] Figure 2 A schematic diagram of a flow chart of a data storage method based on a reconfigurable processor in one embodiment;

[0046] Figure 3 Schematic diagram of the storage structure of the A data matrix in one embodiment;

[0047] Figure 4 A schematic diagram of a flow chart of a step of reading data by a reading module in an embodiment;

[0048] Figure 5 A schematic diagram of a flow chart of a step of writing data by a writing module in one embodiment;

[0049] Figure 6A schematic diagram of a flow chart of a data exporting step of a data exporting unit in one embodiment;

[0050] Figure 7 Schematic diagram of the storage structure of the B data matrix in one embodiment;

[0051] Figure 8 A schematic diagram of a storage structure in which a data matrix A in an embodiment is stored in an internal memory after using the method described in an embodiment of the present invention;

[0052] Fig. 9 A schematic diagram of a storage structure in which a data matrix B in an embodiment is stored in an internal memory using the method described in an embodiment of the present invention;

[0053] Fig.10 A schematic diagram of the structure of a reconfigurable processor in another embodiment;

[0054] Fig.11 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] The data storage method based on a reconfigurable processor provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the external memory 500 is connected to the reconfigurable processor 10, and the reconfigurable processor 10 includes a data import unit 200, a processing unit array 100, an internal memory 300 and a data export unit 400. The external memory 500 is connected to the data import unit 200, and the data import unit 200 is connected to the internal memory 300. In this way, the data import unit 200 can store the data in the external memory 500 into the internal memory 300 in the reconfigurable processor 10 through the method provided by the embodiment of the present invention. The internal memory 300 is connected to the processing unit array 100, and the internal memory 300 is also connected to the data export unit 400, and the data export unit 400 is connected to the external memory 500. By adopting the method described in the embodiment of the present invention, the target data in the internal memory 300 can be exported to the external memory 500.

[0057] In one embodiment, Figure 2As shown, a data storage method based on a reconfigurable processor is provided. This embodiment takes the method applied to a reconfigurable processor as an example. The reconfigurable processor includes a data import unit and an internal memory. The internal memory includes multiple memory blocks. In this embodiment, the data storage method based on the reconfigurable processor includes the following steps:

[0058] Step 102, obtaining a computing task and determining target data required for the computing task.

[0059] The target data includes multiple sub-data.

[0060] Specifically, the computing task refers to a program or application that needs to be executed on the reconfigurable processor, and the target data can be the data required for the computing task when it is executed. For example, the computing task can be an image processing program, etc. The target data required by the computing task is the image data that needs to be processed, and the multiple sub-data contained in the target data can be multiple pixel value data contained in the image. In this way, after determining the computing task that needs to be executed, the reconfigurable processor can obtain the target data required to execute the computing task through the data import unit.

[0061] Step 104, in the data import unit, each sub-data in the target data is divided by a preset data division algorithm and a data simultaneous access condition corresponding to the computing task to obtain a read address transformation parameter.

[0062] Specifically, the data import unit may include an address transformation subunit. The reconfigurable processor determines the data simultaneous access condition through the address transformation subunit in the data import unit according to the data reading method of the target data required by the computing task in the internal memory. In this way, the reconfigurable processor can perform linear transformation on each sub-data in the target data through a preset data partitioning algorithm to obtain the read address transformation parameters corresponding to the target data.

[0063] In a possible implementation, the reconfigurable processor generates one or more sets of linear transformation coefficients by using a data partitioning algorithm according to the pattern of data access by the computing task and the principle of linear transformation, and the number of sets of linear transformation coefficients is the same as the number of inputs of the computing task. For example, if the target data required by the computing task is in the form of multiplication of two matrices, then the generated address transformation parameters are two sets, corresponding to the two matrices respectively.

[0064] Step 106 , respectively calculating the target address of each sub-data in the memory block according to the external memory address of each sub-data and the read address conversion parameter, and storing the target data at the target address.

[0065] Specifically, for each sub-data, the reconfigurable processor performs address mapping calculation according to the address transformation parameters and the external memory address of the sub-data through the address transformation sub-unit in the data import unit, and obtains the target address of the sub-data in the memory block of the internal memory. In this way, the data import unit can store the sub-data at the target address based on the target address. Each sub-data will be stored at the target address corresponding to each sub-data, and each target address can ensure that the computing task running on the reconfigurable processor, when accessing the target data on the internal memory, the data that needs to be accessed simultaneously will not be in the same memory block, that is, the computing task does not need to access the data in the same memory block at the same time.

[0066] In the above-mentioned data storage method based on a reconfigurable processor, by determining the target data containing multiple sub-data required by the computing task, and in the data import unit, by using a preset data partitioning algorithm and the data simultaneous access conditions corresponding to the computing task, each sub-data in the target data is divided to obtain an address transformation parameter. According to the external memory address of each sub-data and the address transformation parameter, the target address of each sub-data in the memory block is calculated respectively, and the target data is stored in the target address. By using the method provided by the embodiment of the present invention to import data from the external memory, access conflicts can be avoided and the performance of the reconfigurable processor can be guaranteed.

[0067] In one embodiment, the specific processing of step 104 "in the data import unit, by using a preset data partitioning algorithm and a data simultaneous access condition corresponding to the computing task, each sub-data in the target data is partitioned to obtain a read address transformation parameter" includes:

[0068] In the data import unit, according to the preset data partitioning algorithm and the read data mode corresponding to the calculation task, a linear transformation calculation is performed on each sub-data in the target data to obtain a read address transformation parameter.

[0069] In one example, the simultaneous data access conditions corresponding to the computing task may include the data reading mode of the computing task, that is, when the computing task is running on a reconfigurable processor, a mode of reading data from an internal memory through a read module in the processing unit array. The data import unit can calculate through the data reading mode, the arrangement of each sub-data contained in the target data, and the linear transformation principle to obtain a linear transformation coefficient, that is, a read address transformation parameter.

[0070] In another example, the simultaneous access conditions for data corresponding to the computing task may also include the write data mode (write data mode) of the computing task. Specifically, when the computing task is running on a reconfigurable processor, when the data in the processing unit array (computing task) is written into the internal memory through the write module in the processing unit array, the terminal can perform calculations based on the write data mode corresponding to the computing task, the arrangement of each sub-data contained in the target data, and the linear transformation principle to obtain the address transformation parameters.

[0071] Optionally, the input of the computing task is a 64*64 matrix, and the output is a 122*122 matrix. The computing process is executed 62 times in a row and column loop, for a total of 62*62 times. Each time, the pixels in the 5 input matrices are read in a cross shape. Each time the reading position is shifted to the right by 1, until the edge of the matrix is ​​moved down by 1 and read again from the left, and the pixels in the 4 output matrices are calculated. Each time the calculation result is written, the position is shifted to the right by 2, until the edge of the matrix is ​​moved down by 2 and written again from the left. The specific computing task is optional, and the reading data mode and the writing data mode of each computing task can be different or the same for the data matrix, and the modes can be the same or different.

[0072] In this way, the reconfigurable processor can determine the mode of reading data of the computing task as follows: Figure 3 As shown, Figure 3 The data in A and its arrangement in the external memory are shown in the figure, where x0 corresponds to the column coordinate of the A matrix and x1 corresponds to the row coordinate of the A matrix. The numbers in the circle are the addresses in the external memory, which are arranged in the order of intra-row and inter-row. If each row of the matrix corresponds to an on-chip memory block, when the computing task accesses data 64, 65, and 66, there will be an access conflict because data 64, 65, and 66 all come from memory block 1.

[0073] Through the linear transformation algorithm, the reconfigurable processor can obtain that the storage input data matrix A (the data matrix that needs to be read by the computing task) uses at least 5 on-chip memory blocks, and the linear transformation formula f(i,j)=(67x1+x0)mod5, g(i,j)=(67x1+x0) / 5 is used for calculation, where f is used to calculate the memory block number and g is used to calculate the offset within the memory block. If the maximum data dimension that needs to support remapping is 2 dimensions, the parameters (address transformation parameters) that need to be saved in the input mapping are <67,1,5>, that is, <coefficient 1, coefficient 0, number of memory blocks>.

[0074] In one embodiment, the reconfigurable processor includes a processing unit array, which includes multiple read modules. The multiple read modules included in the processing unit array can be calculated in parallel, that is, the multiple read modules can access different memory blocks in the internal memory at the same time.

[0075] Accordingly, if Figure 4 As shown, the data storage method based on the reconfigurable processor also includes:

[0076] Step 202: Obtain the external memory address of the target data through the reading module.

[0077] Specifically, the computing task is executed on the reconfigurable processor, and it needs to obtain data from the internal memory to run the computing task. The data is the target data required by the computing task. The address of the target data stored in the reconfigurable processor is the address of the external memory. Therefore, when the reconfigurable processor reads the target data through the reading module, it needs to query the external memory address of the target data first.

[0078] Step 204, calculating the target address according to the external memory address and the read address transformation parameter.

[0079] In one example, the read module may include a first forward address conversion unit, and after the data import unit obtains the read address conversion parameter by the method described in the above embodiment, the read address conversion parameter corresponding to the calculation task may be synchronized to the first forward address conversion unit in the processing unit array. The first forward address conversion unit may perform address mapping calculation according to the received read address conversion parameter and the external memory address of the target data to obtain the target address of the target data, that is, the address stored in the internal memory.

[0080] In another example, the processing unit array may include multiple read modules and processing units. After the data import unit obtains the read address transformation parameters by the method described in the above embodiment, the read address transformation parameters corresponding to the calculation task may be synchronized to the processing units in the processing unit array. The processing unit may perform address mapping calculation based on the received read address transformation parameters and the external memory address of the target data, obtain the target address of the target data, that is, the address stored in the internal memory, and return the target address to the read module.

[0081] Step 206, reading data from the internal memory based on the target address.

[0082] Specifically, the reading module may read the target data at a corresponding location in the internal memory based on the target address.

[0083] In one example, the target data may include 100 sub-data, and the external memory addresses of the 100 sub-data may be 1, 2, ..., 100 respectively; after address mapping is performed through the steps described in the above embodiment, the calculated internal memory addresses (target addresses) are addr1, ..., addr100 respectively; when the computing task is executed on the reconfigurable processor, all or part of the above target data is required, that is, all or part of these numbers need to be read, and the address storing the above data in the computing task is the external memory address, so that when the computing task reads the above data through the reading module, the external memory address of the above data needs to be mapped (calculated according to the external memory address and the read address transformation parameter) to obtain the target address, that is, the addresses 1, 2, ..., 100 are mapped and converted into addr1, ..., addr100.

[0084] In this embodiment, by adding a configurable address conversion unit to the hardware structure of the reconfigurable processor, it is ensured that the mapping mode can be changed through software configuration, thereby ensuring the programmability of the reconfigurable processor.

[0085] In one embodiment, the processing unit array further includes a plurality of writing modules, and the data simultaneous access condition further includes a writing data mode. Accordingly, Figure 5 As shown, the data storage method based on the reconfigurable processor also includes:

[0086] Step 302, through the writing module, according to the preset data partitioning algorithm and the writing data mode corresponding to the computing task, linear transformation calculation is performed on each sub-data in the target data to obtain the writing address transformation parameters and the external memory address of the target data.

[0087] Specifically, the address of the target data stored in the reconfigurable processor is the address of the external memory. Therefore, when the reconfigurable processor writes the target data through the writing module, it is necessary to first query the external memory address of the target data.

[0088] Step 304, calculating the target address according to the external memory address and the address transformation parameter.

[0089] In one example, the write module may include a second forward address conversion unit, which may perform calculations based on the write data mode of the computing task, the arrangement of each sub-data included in the target data, and the linear transformation principle to obtain address conversion parameters corresponding to the write data mode. The second forward address conversion unit may perform address mapping calculations based on the calculated write address conversion parameters and the external memory address of the target data to obtain the target address of the target data, that is, the address stored in the internal memory.

[0090] In another example, the processing unit array may include multiple writing modules and processing units, and the processing unit may perform calculations based on the writing data mode of the computing task, the arrangement of each sub-data included in the target data, and the linear transformation principle to obtain the writing address transformation parameters corresponding to the writing data mode. The processing unit may perform address mapping calculations based on the received writing address transformation parameters and the external memory address of the target data to obtain the target address of the target data, that is, the address stored in the internal memory, and return the target address to the writing module.

[0091] Step 306: store the target data into the internal memory based on the target address.

[0092] Specifically, the write module may store the target data at a target location in the internal memory based on the target address.

[0093] In this embodiment, by adding a configurable address conversion unit to the hardware structure of the reconfigurable processor, it is ensured that the mapping mode can be changed through software configuration, thereby ensuring the programmability of the reconfigurable processor.

[0094] In one embodiment, the reconfigurable processor includes a data export unit. Figure 6 As shown, the data storage method based on the reconfigurable processor also includes:

[0095] Step 402, obtaining the target address of the target data in the internal memory through the data export unit.

[0096] Step 404: Perform reverse address transformation on the target address according to the reverse address transformation parameter corresponding to the write address transformation parameter to obtain the external memory address of the target data.

[0097] Step 406: store the target data into the external memory based on the external memory address.

[0098] In an example, the target data may include 100 sub-data, and the internal memory addresses (target addresses) of the 100 sub-data are addr1, ..., addr100 respectively; when the data export unit exports the target data on the internal memory to the external memory, it is necessary to perform a reverse address transformation on the target address according to the reverse address transformation parameters corresponding to the write address transformation parameters to obtain the external memory address corresponding to the target address of the target data, that is, to perform a reverse address transformation on the internal memory addresses (target addresses) of addr1, ..., addr100 respectively to obtain external memory addresses 1, 2, ..., 100.

[0099] The data storage method based on the reconfigurable processor described in the above embodiment is described below in conjunction with a detailed embodiment:

[0100] The computational tasks that need to be run on the reconfigurable processor can be as follows:

[0101] The input of the calculation task is a 64*64 matrix, and the output is a 122*122 matrix. The calculation process is executed 62 times in a row and column loop, for a total of 62*62 times. Each time, the pixels in the 5 input matrices are read in a cross shape. Each time the reading position is shifted to the right by 1, until the edge of the matrix is ​​moved down by 1 and read again from the left, and the pixels in the 4 output matrices are calculated. Each time the calculation result is written, the position is shifted to the right by 2, until the edge of the matrix is ​​moved down by 2 and written again from the left. The specific calculation task is optional, and the reading mode and writing mode of each calculation task can be different.

[0102] In this way, the reconfigurable processor can determine the mode of reading data of the computing task as follows: Figure 3 As shown, Figure 3 The data in the A data matrix (the data matrix that the computing task needs to read) and its arrangement in the external memory are shown in the figure, where x0 corresponds to the column coordinates of the A matrix and x1 corresponds to the row coordinates of the A matrix. The numbers in the circle are the addresses in the external memory, which are arranged in the order of intra-row and inter-row. If each row of the matrix corresponds to an on-chip memory block, when the computing task accesses data 64, 65, and 66, there will be an access conflict because data 64, 65, and 66 all come from memory block 1.

[0103] Optionally, the mode of writing data of the computing task can be as follows Figure 7 As shown, Figure 7 The data matrix B is shown (the data matrix that needs to be written for the computing task). x0 corresponds to the column coordinate of the B matrix, and x1 corresponds to the row coordinate of the B matrix. The numbers in the circle are the addresses in the internal memory, which are arranged in the order of rows within and between rows. If each row of the matrix corresponds to an on-chip memory block, then when accessing data 1, 2 or data 122, 123, they all come from the same memory block, there will be an access conflict.

[0104] In this way, the reconfigurable processor can obtain the minimum use of 5 on-chip memory blocks to store the input data matrix A through the linear transformation algorithm, and calculate it through the linear transformation formula f(i,j)=(67x1+x0)mod5, g(i,j)=(67x1+x0) / 5, where f is used to calculate the memory block number and g is used to calculate the offset within the memory block. If the maximum dimension of the data to be remapped is 2 dimensions, the parameters (address transformation parameters) that need to be saved in the input mapping are <67,1,5>, that is, <coefficient 1, coefficient 0, number of memory blocks>, that is, the calculated address transformation parameters are the address transformation parameters corresponding to the matrix A, that is, the address transformation parameters corresponding to the read data mode of the computing task.

[0105] In this way, after a similar calculation process, it can be obtained that at least 4 on-chip memory blocks are required to store the output data matrix B. Through the linear transformation formula f(x0,x1)=(123x1+x0)mod4, g(x0,x1)=(123x1+x0) / 4, the calculated linear transformation parameters corresponding to the matrix B can be <123,1,4>, which are the address transformation parameters corresponding to the write data mode of the computing task.

[0106] In one embodiment, when the data import unit needs to import the target data into the internal memory, it is necessary to configure the length and address of the transferred data (each sub-data in the target data) in the data import unit, and also to configure the above-mentioned read mapping parameters <67,1,5>. According to the length and address of each sub-data in the target data (external memory address) and the address transformation parameters (read mapping parameters <67,1,5>), the data import unit can calculate the address of each sub-data in the target data after remapping, such as Figure 8 As shown, Figure 8 Each column in the figure corresponds to an on-chip memory block. It can be seen from the figure that although remapping can avoid access conflicts, the data addresses are not stored continuously. The data 64, 65, and 66 that need to be accessed simultaneously have been placed in different memory blocks (64 is placed in memory block 2, 65 is placed in memory block 3, and 66 is placed in memory block 5).

[0107] In this way, the reconfigurable processing can obtain the target address (internal memory address) according to the external memory address (0,1), (1,0), (1,1), (1,2), (2,1) of the target data by mapping and calculating with the address transformation parameters (read mapping parameters <67,1,5>), namely: (1,0), (2,13) ​​(3,13) (4,13) (0,27).

[0108] In one embodiment, the processing unit array in the reconfigurable processor includes a plurality of read modules. When the read module includes a first forward address conversion unit, the read mapping parameter <67,1,5> must be used. When the read module needs to read the target data in the internal memory, the external memory addresses (0,1), (1,0), (1,1), (1,2), (2,1) stored in the array can be used for address mapping calculation to obtain the internal memory addresses (1,0), (2,13) ​​(3,13) (4,13), (0,27). That is, the processing unit array's access to (0,1), (1,0), (1,1), (1,2), (2,1) is converted to access to (1,0), (2,13) ​​(3,13) (4,13), (0,27).

[0109] In one embodiment, the processing unit array in the reconfigurable processor includes a plurality of write modules. When the write module includes a second forward address conversion unit, the write mapping parameter <123,1,4> must be used. When the write module needs to write target data to the internal memory, the external memory addresses (0,1), (0,2), (1,0), (1,1) stored in the array can be used for address mapping calculation to obtain internal memory addresses (1,0), (2,0), (3,30), (0,31). Even if the write mapping parameter <123,1,4> is used, the array access to (0,1), (0,2), (1,0), (1,1) is converted to access to (1,0), (2,0), (3,30), (0,31). The schematic diagram of each address is as follows: Fig. 9 As shown, Fig. 9 Each column in represents an on-chip memory block.

[0110] In one embodiment, in the data export unit, in addition to configuring the length and address of the transferred data (target data), it is also necessary to configure the write inverse mapping parameter <123,1,4,122> to convert the addresses of (1,0), (2,0), (3,30), (0,31) back to (0,1), (0,2), (1,0), (1,1). Note that the inverse transformation of the address mapping needs to be used here. If the transformation is irreversible, this mapping function cannot be used, and the inverse mapping parameters are not exactly the same as the forward mapping parameters. The inverse mapping can be calculated by the following formula:

[0111]

[0112] Among them, x0 corresponds to the column coordinate, x1 corresponds to the row coordinate, and h is the address in the external memory.

[0113] In one embodiment, the address conversion unit in the data import unit requires 2 multipliers (multiplier-accumulators) and 1 division / remainder unit for calculating the mapped address if the dimension of the target data is 2-dimensional, that is, 2 f(i, j) functions and 1 g(i, j) function are required.

[0114] Optionally, the read module in the reconfigurable processor may include a first address conversion unit (linear conversion unit) and a read unit, in which the address conversion may be implemented by using two multipliers and one division / remainder unit, and the read module performs data exchange with the processing unit array.

[0115] Optionally, the reconfigurable processor may include a processing unit array, which includes a processing unit and a plurality of read modules. In this case, the processing unit implements address conversion by using two multipliers and one division / remainder unit. The writing module is similar and will not be described in detail here.

[0116] In one embodiment, the data export module includes a reverse address transformation unit. If the dimension of the data (target data) to be remapped is 2-dimensional, two multipliers (multiplier-accumulators) and one division / remainder unit are required for address calculation of inverse mapping (reverse address transformation).

[0117] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0118] Based on the same inventive concept, the embodiment of the present application also provides a reconfigurable processor for implementing the data storage method based on a reconfigurable processor involved above. The implementation solution provided by the reconfigurable processor to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more reconfigurable processor embodiments provided below can refer to the limitations of the data storage method based on a reconfigurable processor above, and will not be repeated here.

[0119] In one embodiment, Figure 1 As shown, a reconfigurable processor 10 is provided, the reconfigurable processor 10 includes a data import unit 200, an internal memory 300, the internal memory 300 includes a plurality of memory blocks, wherein:

[0120] The data import unit is used to obtain a computing task and determine the target data required for the computing task, wherein the target data includes multiple sub-data; the sub-data in the target data are divided by a preset data partitioning algorithm and the data simultaneous access conditions corresponding to the computing task to obtain a read address transformation parameter; the target address of each sub-data in the memory block is calculated according to the external memory address of each sub-data and the read address transformation parameter, and the target data is stored in the target address.

[0121] In one embodiment, if Fig.10As shown, the reconfigurable processor includes a processing unit array, the processing unit array includes a processing unit, a plurality of read modules and a plurality of write modules, and the data simultaneous access condition also includes a write data mode, wherein:

[0122] The read module is used to obtain the external memory address of the target data; the processing unit is used to calculate the target address according to the external memory address and the read address transformation parameter; the read module is also used to read data in the internal memory based on the target address;

[0123] The write module is used to obtain the external memory address of the target data; the processing unit is also used to perform linear transformation calculations on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and calculate the target address according to the external memory address and the write address transformation parameters; the write module is also used to store the target data in the internal memory.

[0124] In one embodiment, the reconfigurable processor includes a processing unit array, the processing unit array includes a plurality of read modules and a plurality of write modules, the write module includes a first forward address conversion unit and a read unit, the write module includes a second forward address conversion unit and a write unit, the data simultaneous access condition also includes a write data mode, wherein:

[0125] The first forward address conversion unit is used to obtain the external memory address of the target data, and calculate the target address according to the external memory address and the read address conversion parameter;

[0126] The reading unit is used to read data in the internal memory based on the target address;

[0127] The second forward address transformation unit is used to perform linear transformation calculation on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and obtain the external memory address of the target data, and calculate the target address according to the external memory address and the write address transformation parameters;

[0128] The writing unit is used to store the target data into the internal memory.

[0129] In one embodiment, the reconfigurable processor includes a data export unit, and the data export unit includes a reverse address change subunit and a export subunit; wherein:

[0130] The reverse address change subunit is used to obtain the target address of the target data on the internal memory; perform reverse address transformation on the target address according to the reverse address transformation parameter corresponding to the write address transformation parameter to obtain the external memory address of the target data;

[0131] The export subunit is used to store the target data in the external memory based on the external memory address.

[0132] Each module in the above-mentioned reconfigurable processor can be implemented in whole or in part by software, hardware or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0133] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.11 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the address and length of target data, etc. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data storage method based on a reconfigurable processor is implemented.

[0134] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0135] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0136] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0137] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0138] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0139] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data storage method based on a reconfigurable processor, characterized in that: The reconfigurable processor includes a data import unit and an internal memory, wherein the internal memory includes a plurality of memory blocks, and the method includes: Obtaining a computing task, and determining target data required by the computing task, wherein the target data includes a plurality of sub-data; In the data import unit, each sub-data in the target data is divided by a preset data division algorithm and a data simultaneous access condition corresponding to the computing task to obtain a read address transformation parameter, wherein the data simultaneous access condition includes a read data mode; Calculating the target address of each sub-data in the memory block according to the external memory address of each sub-data and the read address conversion parameter, and storing the target data in the target address; In the data import unit, each sub-data in the target data is divided by a preset data division algorithm and a data simultaneous access condition corresponding to the computing task to obtain a read address transformation parameter, including: In the data import unit, according to the preset data partitioning algorithm and the reading data mode corresponding to the calculation task, linear transformation calculation is performed on each sub-data in the target data to obtain read address transformation parameters, and the read address transformation parameters are linear transformation coefficients obtained by linear transformation processing.

2. The method according to claim 1, characterized in that The reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of read modules; the method further includes: Obtaining the external memory address of the target data through the reading module; Calculating a target address according to the external memory address and a read address conversion parameter; Based on the target address, data is read from the internal memory.

3. The method according to claim 2, characterized in that The processing unit array further includes a plurality of writing modules, and the data simultaneous access condition further includes a write data mode; By means of the writing module, according to the preset data partitioning algorithm and the writing data mode corresponding to the computing task, each sub-data in the target data is subjected to linear transformation calculation to obtain the writing address transformation parameter, and the external memory address of the target data is obtained; Calculating a target address according to the external memory address and the write address conversion parameter; Based on the target address, the target data is stored in the internal memory.

4. The method according to claim 3, characterized in that: The reconfigurable processor includes a data export unit; the method further includes: Obtaining, by the data export unit, a target address of the target data on the internal memory; According to the reverse address transformation parameter corresponding to the write address transformation parameter, the target address is reversely transformed to obtain the external memory address of the target data; Based on the external memory address, the target data is stored in the external memory.

5. A reconfigurable processor, characterized in that: The reconfigurable processor includes a data import unit and an internal memory, wherein the internal memory includes a plurality of memory blocks, wherein: The data import unit is used to obtain a computing task and determine target data required by the computing task, wherein the target data includes multiple sub-data; divide each sub-data in the target data by a preset data partitioning algorithm and a data simultaneous access condition corresponding to the computing task to obtain a read address transformation parameter; calculate a target address of each sub-data in the memory block according to an external memory address of each sub-data and the read address transformation parameter, and store the target data in the target address, wherein the data simultaneous access condition includes a read data mode; The data import unit is specifically used to perform linear transformation calculations on each sub-data in the target data according to the preset data partitioning algorithm and the reading data mode corresponding to the calculation task, so as to obtain read address transformation parameters, wherein the read address transformation parameters are linear transformation coefficients obtained by performing linear transformation processing.

6. The reconfigurable processor according to claim 5, characterized in that: The reconfigurable processor includes a processing unit array, the processing unit array includes a processing unit, a plurality of read modules and a plurality of write modules, the data simultaneous access condition also includes a write data mode, wherein: The read module is used to obtain the external memory address of the target data; the processing unit is used to calculate the target address according to the external memory address and the read address transformation parameter; the read module is also used to read data in the internal memory based on the target address; The write module is used to obtain the external memory address of the target data; the processing unit is also used to perform linear transformation calculations on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and calculate the target address according to the external memory address and the write address transformation parameters; the write module is also used to store the target data in the internal memory.

7. The reconfigurable processor according to claim 5, characterized in that: The reconfigurable processor includes a processing unit array, the processing unit array includes a plurality of read modules and a plurality of write modules, the write module includes a first forward address conversion unit and a read unit, the write module includes a second forward address conversion unit and a write unit, the data simultaneous access condition also includes a write data mode, wherein: The first forward address conversion unit is used to obtain the external memory address of the target data, and calculate the target address according to the external memory address and the read address conversion parameter; The reading unit is used to read data in the internal memory based on the target address; The second forward address transformation unit is used to perform linear transformation calculation on each sub-data in the target data according to the preset data partitioning algorithm and the write data mode corresponding to the computing task to obtain write address transformation parameters, and obtain the external memory address of the target data, and calculate the target address according to the external memory address and the write address transformation parameters; The writing unit is used to store the target data into the internal memory.

8. The reconfigurable processor according to claim 7, characterized in that: The reconfigurable processor includes a data export unit, and the data export unit includes a reverse address change subunit and a export subunit; wherein: The reverse address change subunit is used to obtain the target address of the target data on the internal memory; perform reverse address transformation on the target address according to the reverse address transformation parameter corresponding to the write address transformation parameter to obtain the external memory address of the target data; The export subunit is used to store the target data in the external memory based on the external memory address.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

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