Pixel driving circuit, driving method thereof, and display panel

Abstract

The present disclosure relates to the field of display technologies, and provides a pixel driving circuit, a driving method thereof, and a display panel. The pixel driving circuit includes: a driving circuit, a compensation circuit, a data writing circuit, a light emitting control circuit, a signal enhancement circuit, a first storage circuit, a second storage circuit, a first reset circuit, and a second reset circuit. The driving circuit is configured to input a driving current to a second node through a third node according to a signal of a first node; the signal enhancement circuit is configured to connect a first power supply terminal and a fifth node in response to a signal of a second gate driving signal terminal; the first storage circuit is connected between the fifth node and the first node; the second storage circuit is connected between the first node and a fourth node; the first reset circuit is configured to connect a first initial signal terminal and the fourth node in response to a control signal; and the second reset circuit is configured to connect a second initial signal terminal and the fifth node in response to a control signal. The pixel driving circuit can improve the uniformity of display of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display panel. Background Art

[0002] In related technologies, a pixel driving circuit generally includes a driving transistor, which is configured to output a driving current to a light-emitting unit according to a data signal on its gate. However, since the driving current output by the driving transistor is also related to its own threshold voltage, the threshold voltage of the driving transistor will affect the magnitude of the current it outputs. At the same time, since it is difficult to make the threshold voltages of the driving transistors in the display panel exactly the same, under the action of the same data signal, uneven display will occur at different positions of the display panel.

[0003] It should be noted that the information disclosed in the above Background Art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a pixel driving circuit, which includes: a driving circuit, a compensation circuit, a data writing circuit, a light emitting control circuit, a signal enhancing circuit, a first storage circuit, a second storage circuit, a first reset circuit, and a second reset circuit. The driving circuit is connected to a first node, a second node, and a third node, and is configured to input a driving current to the second node through the third node according to the signal of the first node; the compensation circuit is connected to the third node, the first node, and a first enable signal terminal, and is configured to connect the first node and the third node in response to the signal of the first enable signal terminal; the data writing circuit is connected to the second node, a data signal terminal, and a first gate driving signal terminal, and is configured to transmit the signal of the data signal terminal to the second node in response to the signal of the first gate driving signal terminal; the light emitting control circuit is connected to a first power supply terminal, the third node, the second node, a fourth node, a second enable signal terminal, and a third enable signal terminal, and is configured to connect the first power supply terminal and the third node in response to the signal of the second enable signal terminal, and is configured to connect the second node and the fourth node in response to the signal of the third enable signal terminal; the signal enhancing circuit is connected to the first power supply terminal, a fifth node, and a second gate driving signal terminal, and is configured to connect the first power supply terminal and the fifth node in response to the signal of the second gate driving signal terminal; the first storage circuit is connected between the fifth node and the first node; the second storage circuit is connected between the first node and the fourth node; the first reset circuit is connected to the fourth node, a first initial signal terminal, and a reset signal terminal, and is configured to transmit the signal of the first initial signal terminal to the fourth node in response to the signal of the reset signal terminal; the second reset circuit is connected to the fifth node, the first enable signal terminal, and a second initial signal terminal, and is configured to transmit the signal of the second initial signal terminal to the fifth node in response to the signal of the first enable signal terminal.

[0005] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, a first pole of the driving transistor is connected to the third node, a second pole is connected to the second node, and a gate is connected to the first node.

[0006] In an exemplary embodiment of the present disclosure, the compensation circuit includes: a first transistor, a first pole of the first transistor is connected to the third node, a second pole is connected to the first node, and a gate is connected to the first enable signal terminal;

[0007] The data writing circuit includes: a second transistor, a first pole of the second transistor is connected to the data signal terminal, a second pole is connected to the second node, and a gate is connected to the first gate driving signal terminal.

[0008] In an exemplary embodiment of the present disclosure, the light-emitting control circuit includes: a fourth transistor and a fifth transistor. The first pole of the fourth transistor is connected to the first power supply terminal, the second pole is connected to the third node, and the gate is connected to the second enable signal terminal. The first pole of the fifth transistor is connected to the second node, the second pole is connected to the fourth node, and the gate is connected to the third enable signal terminal.

[0009] In an exemplary embodiment of the present disclosure, the signal enhancement circuit includes: a sixth transistor. The first pole of the sixth transistor is connected to the first power supply terminal, the second pole is connected to the fifth node, and the gate is connected to the second gate driving signal terminal. The first storage circuit includes: a first capacitor. The first electrode of the first capacitor is connected to the fifth node, and the second electrode is connected to the first node. The second storage circuit includes: a second capacitor. The first electrode of the second capacitor is connected to the first node, and the second electrode is connected to the fourth node.

[0010] In an exemplary embodiment of the present disclosure, the first reset circuit includes: a seventh transistor. The first pole of the seventh transistor is connected to the first initial signal terminal, the second pole is connected to the fourth node, and the gate is connected to the reset signal terminal. The second reset circuit includes: an eighth transistor. The first pole of the eighth transistor is connected to the second initial signal terminal, the second pole is connected to the fifth node, and the gate is connected to the first enable signal terminal.

[0011] In an exemplary embodiment of the present disclosure, the first initial signal terminal shares the second initial signal terminal.

[0012] In an exemplary embodiment of the present disclosure, the driving transistor is an N-type transistor.

[0013] According to one aspect of the present disclosure, there is provided a method for driving a pixel driving circuit, which is used to drive the above-mentioned pixel driving circuit. The driving method includes:

[0014] In the reset stage, an effective level is input to the reset signal terminal, the second enable signal terminal, and the first enable signal terminal, and an invalid level is input to the first gate driving signal terminal, the second gate driving signal terminal, and the third enable signal terminal;

[0015] In the data writing stage, an effective level is input to the reset signal terminal, the first gate driving signal terminal, and the first enable signal terminal, and an invalid level is input to the second gate driving signal terminal, the second enable signal terminal, and the third enable signal terminal;

[0016] In the data enhancement stage, an effective level is input to the reset signal terminal and the second gate driving signal terminal, and an invalid level is input to the first gate driving signal terminal, the first enable signal terminal, the second enable signal terminal, and the third enable signal terminal;

[0017] In the light-emitting stage, an effective level is input to the second enable signal terminal and the third enable signal terminal, and an ineffective level is input to the reset signal terminal, the first enable signal terminal, the first gate driving signal terminal, and the second gate driving signal terminal.

[0018] According to one aspect of the present disclosure, a display panel is provided, and the display panel includes the above-mentioned pixel driving circuit.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0021] Figure 1 It is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure;

[0022] Figure 2 For Figure 1 It is a timing diagram of control signals in a driving method of the shown pixel driving circuit;

[0023] Figure 3 For Figure 1 It is a state diagram of the shown pixel driving circuit in the reset stage;

[0024] Figure 4 For Figure 1 It is a state diagram of the shown pixel driving circuit in the data writing stage;

[0025] Figure 5 For Figure 1 It is a state diagram of the shown pixel driving circuit in the data enhancement stage;

[0026] Figure 6 For Figure 1 It is a state diagram of the shown pixel driving circuit in the light-emitting stage. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the drawings denote like or similar structures, and thus their detailed descriptions will be omitted.

[0028] The terms "a", "an", and "the" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used in an open-ended inclusive sense and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0029] This exemplary embodiment first provides a pixel driving circuit, as Figure 1 shown, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include: a driving circuit 1, a compensation circuit 2, a data writing circuit 3, a light emitting control circuit 4, a signal enhancing circuit 5, a first storage circuit 8, a second storage circuit 9, a first reset circuit 6, and a second reset circuit 7. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3, and is configured to input a driving current to the second node N2 through the third node N3 according to the signal of the first node N1; the compensation circuit 2 is connected to the third node N3, the first node N1, and a first enable signal terminal EM1, and is configured to connect the first node N1 and the third node N3 in response to the signal of the first enable signal terminal EM1; the data writing circuit 3 is connected to the second node N2, a data signal terminal Data, and a first gate driving signal terminal G1, and is configured to transmit the signal of the data signal terminal Data to the second node N2 in response to the signal of the first gate driving signal terminal G1; the light emitting control circuit 4 is connected to a first power supply terminal VDD, the third node N3, the second node N2, a fourth node N4, a second enable signal terminal EM2, and a third enable signal terminal EM3, and is configured to connect the first power supply terminal VDD and the third node N3 in response to the signal of the second enable signal terminal EM2, and is configured to connect the second node N2 and the fourth node N4 in response to the signal of the third enable signal terminal EM3; the signal enhancing circuit 5 is connected to the first power supply terminal VDD, a fifth node N5, and a second gate driving signal terminal G2, and is configured to connect the first power supply terminal VDD and the fifth node N5 in response to the signal of the second gate driving signal terminal G2; the first storage circuit 8 is connected between the fifth node N5 and the first node N1; the second storage circuit 9 is connected between the first node N1 and the fourth node N4; the first reset circuit 6 is connected to the fourth node N4, a first initial signal terminal Vini1, and a reset signal terminal Reset, and is configured to transmit the signal of the first initial signal terminal Vini1 to the fourth node N4 in response to the signal of the reset signal terminal Reset; the second reset circuit 7 is connected to the fifth node N5, the first enable signal terminal EM1, and a second initial signal terminal Vini2, and is configured to transmit the signal of the second initial signal terminal Vini2 to the fifth node N5 in response to the signal of the first enable signal terminal EM1.

[0030] In this exemplary embodiment, the method for driving the pixel driving circuit may include four stages: a reset stage, a data writing stage, a data enhancement stage, and a light emitting stage. In the reset stage, valid levels may be input to the reset signal terminal Reset, the second enable signal terminal EM2, and the first enable signal terminal EM1, and invalid levels may be input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, and the third enable signal terminal EM3. The first reset circuit 6 conducts the first initial signal terminal Vini1 and the fourth node N4, the light emitting control circuit 4 conducts the first power supply terminal VDD and the third node N3, the compensation circuit 2 conducts the first node N1 and the third node N3, and the second reset circuit 7 conducts the second initial signal terminal Vini2 and the fifth node N5. The first initial signal terminal Vini1 writes a first initial signal to the fourth node N4, the first power supply terminal VDD writes a power supply signal to the first node N1, and the second initial signal terminal Vini2 writes a second initial signal to the fifth node N5. In the data writing stage, valid levels may be input to the reset signal terminal Reset, the first gate driving signal terminal G1, and the first enable signal terminal EM1, and invalid levels may be input to the second gate driving signal terminal G2, the second enable signal terminal EM2, and the third enable signal terminal EM3. The first reset circuit 6 conducts the first initial signal terminal Vini1 and the fourth node N4, the data writing circuit 3 conducts the data signal terminal Data and the second node N2, the compensation circuit 2 conducts the first node N1 and the third node N3, and the second reset circuit 7 conducts the second initial signal terminal Vini2 and the fifth node N5. The first initial signal terminal Vini1 inputs a first initial signal to the fourth node N4, and the second initial signal terminal Vini2 writes a second initial signal to the fifth node N5. The data signal terminal Data writes a voltage Vdata to the second node N2, and the voltages of the first node N1 and the third node N3 become Vdata + Vth, where Vdata is the voltage of the data signal output by the data signal terminal, and Vth is the threshold voltage of the driving circuit 1. In the data enhancement stage, valid levels may be input to the reset signal terminal Reset and the second gate driving signal terminal G2, and invalid levels may be input to the first gate driving signal terminal G1, the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3. The signal enhancement circuit 5 conducts the first power supply terminal VDD and the fifth node N5, and the first reset circuit 6 conducts the first initial signal terminal Vini1 and the fourth node N4. The first initial signal terminal Vini1 inputs a first initial signal to the fourth node N4. The voltage of the fifth node N5 changes from Vini2 to Vdd, where Vini2 is the voltage of the second initial signal and Vdd is the power supply voltage of the first power supply terminal VDD.Based on the principle that the charge of the first node N1 remains unchanged before and after entering the data enhancement stage, the voltage of the first node N1 is raised to Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2), where C1 is the capacitance value of the first storage circuit 8 and C2 is the capacitance value of the second storage circuit 9. In the light-emitting stage, an effective level can be input to the second enable signal terminal EM2 and the third enable signal terminal EM3, and an invalid level can be input to the reset signal terminal Reset, the first enable signal terminal EM1, the first gate drive signal terminal G1, and the second gate drive signal terminal G2. The light-emitting control circuit 4 conducts the first power supply terminal VDD and the third node N3, and conducts the second node N2 and the fourth node N4. The voltage of the fourth node N4 changes from Vini1 to VN4, where Vini1 is the voltage of the first initial signal. The voltage of the first node N1 is coupled to Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2) + (VN4 - Vini1) under the action of the second storage circuit 9. According to the drive transistor output current formula I = (μWCox / 2L)(Vgs - Vth) in the drive circuit 1. 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, Vgs is the gate-source voltage difference of the drive transistor, and Vth is the threshold voltage of the drive transistor. The output current I of the drive circuit 1 in this disclosure is I = (μWCox / 2L)(Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2) + (VN4 - Vini1) - VN4 - Vth) 2 = (μWCox / 2L)(Vdata + (C1 / (C1 + C2))×(Vdd - Vini2) - Vini1) 2 . It can be seen that in this exemplary embodiment, the output current of the pixel drive circuit has nothing to do with the threshold of the drive circuit 1, and this pixel drive circuit can avoid the problem of uneven display of the display panel caused by inconsistent thresholds of the drive circuit 1. At the same time, since the voltage of the first node N1 is raised in the data enhancement stage t3, this pixel drive circuit can output a higher current. Here, the first storage circuit 8 and the second storage circuit 9 can also adjust the output current of the drive circuit, or adjust the voltage range of the data signal when the output current range is certain.

[0031] It should be noted that the effective level is the level that can drive the target circuit. For example, when the target circuit is an N-type transistor, the effective level is a high level, and the logic of the invalid level is opposite to that of the effective level. This drive method has been described in detail in the above content and will not be elaborated here.

[0032] In this exemplary embodiment, as Figure 1As shown, the driving circuit 1 may include: a driving transistor T3, a first pole of the driving transistor T3 is connected to the third node N3, a second pole is connected to the second node N2, and a gate is connected to the first node N1. It should be understood that in other exemplary embodiments, the driving circuit 1 may also have other structures. For example, the driving circuit 1 may include a plurality of driving transistors connected in parallel. The plurality of driving transistors connected in parallel may be connected between the third node N3 and the second node N2, and the gates are all connected to the first node N1. This setting can increase the output current of the driving circuit 1.

[0033] In this exemplary embodiment, as Figure 1 shown, the compensation circuit 2 may include: a first transistor T1, a first pole of the first transistor T1 is connected to the third node N3, a second pole is connected to the first node N1, and a gate is connected to the first enable signal terminal EM1. The data writing circuit 3 may include: a second transistor T2, a first pole of the second transistor T2 is connected to the data signal terminal Data, a second pole is connected to the second node N2, and a gate is connected to the first gate driving signal terminal G1.

[0034] In this exemplary embodiment, as Figure 1 shown, the light emitting control circuit 4 may include: a fourth transistor T4, a fifth transistor T5, a first pole of the fourth transistor T4 is connected to the first power supply terminal VDD, a second pole is connected to the third node N3, and a gate is connected to the second enable signal terminal EM2; a first pole of the fifth transistor T5 is connected to the second node N2, a second pole is connected to the fourth node N4, and a gate is connected to the third enable signal terminal EM3.

[0035] In this exemplary embodiment, as Figure 1 shown, the signal enhancement circuit 5 may include: a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first power supply terminal VDD, a second pole is connected to the fifth node N5, and a gate is connected to the second gate driving signal terminal G2. The first storage circuit 8 may include: a first capacitor C1, a first electrode of the first capacitor C1 is connected to the fifth node N5, and a second electrode is connected to the first node N1. The second storage circuit 9 may include: a second capacitor C2, a first electrode of the second capacitor C2 is connected to the first node N1, and a second electrode is connected to the fourth node N4.

[0036] In this exemplary embodiment, as Figure 1As shown, the first reset circuit 6 may include: a seventh transistor T7, a first pole of the seventh transistor T7 is connected to the first initial signal terminal Vini1, a second pole is connected to the fourth node N4, and a gate is connected to the reset signal terminal Reset. The second reset circuit 7 may include: an eighth transistor T8, a first pole of the eighth transistor T8 is connected to the second initial signal terminal Vini2, a second pole is connected to the fifth node N5, and a gate is connected to the first enable signal terminal EM1.

[0037] As Figure 1 shown, the fourth node N4 of the pixel driving circuit may be used to connect a first electrode of a light emitting unit Oled, and a second electrode of the light emitting unit Oled may be connected to a second power supply terminal VSS. In this exemplary embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may all be N-type transistors. The first power supply terminal VDD may be a high-level power supply terminal, and the second power supply terminal VSS may be a low-level power supply terminal. It should be understood that in other exemplary embodiments, at least some of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may also be P-type transistors. It should be understood that in other exemplary embodiments, the first initial signal terminal Vini1 may also share the second initial signal terminal Vini2.

[0038] As Figure 2 shown, for Figure 1 the timing diagram of control signals in a driving method of the pixel driving circuit shown. Among them, Reset is the timing diagram of the reset signal terminal, G1 is the timing diagram of the first gate driving signal terminal, G2 is the timing diagram of the second gate driving signal terminal, EM1 is the timing diagram of the first enable signal terminal, EM2 is the timing diagram of the second enable signal terminal, and EM3 is the timing diagram of the third enable signal terminal. The driving method of the pixel driving circuit may include: a reset stage t1, a data writing stage t2, a data enhancement stage t3, and a light emitting stage t4.

[0039] In the reset stage t1, as Figure 3 shown, for Figure 1State diagram of the pixel driving circuit shown in the reset stage. Among them, the transistors with crosses are in the off state, and the transistors without crosses are in the on state. In the reset stage, high levels are input to the reset signal terminal Reset, the second enable signal terminal EM2, and the first enable signal terminal EM1, and low levels are input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, and the third enable signal terminal EM3. The first transistor T1, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off. The first initial signal terminal Vini1 inputs a first initial signal to the fourth node N4, and the first power supply terminal VDD inputs a high-level power supply signal to the first node N1 through the fourth transistor T4 and the first transistor T1. The second initial signal terminal Vini2 writes a second initial signal to the fifth node N5.

[0040] In the data writing stage t2, as Figure 4 shown, it is Figure 1 State diagram of the pixel driving circuit shown in the data writing stage. Among them, the transistors with crosses are in the off state, and the transistors without crosses are in the on state. In the data writing stage t2, high levels are input to the reset signal terminal Reset, the first gate driving signal terminal G1, and the first enable signal terminal EM1, and low levels are input to the second gate driving signal terminal G2, the second enable signal terminal EM2, and the third enable signal terminal EM3. The first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first initial signal terminal Vini1 inputs a first initial signal to the fourth node N4, and the second initial signal terminal Vini2 writes a second initial signal to the fifth node N5. The data signal terminal Data writes a voltage Vdata to the second node N2, the driving transistor T3 is turned on, and the voltages of the first node N1 and the third node N3 decrease until the voltages of the first node N1 and the third node N3 become Vdata + Vth, where Vdata is the voltage of the data signal output by the data signal terminal, and Vth is the threshold voltage of the driving transistor T3.

[0041] In the data enhancement stage t3, as Figure 5 shown, it is Figure 1The state diagram of the pixel driving circuit shown during the data boosting stage. Among them, the transistors with a cross mark are in the off state, and the transistors without a cross mark are in the on state. A high level is input to the reset signal terminal Reset and the second gate driving signal terminal G2, and a low level is input to the first gate driving signal terminal G1, the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3. The sixth transistor T6 and the seventh transistor T7 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned off. The first initial signal terminal Vini1 inputs a first initial signal to the fourth node N4. The voltage of the fifth node N5 changes from Vini2 to Vdd, where Vini2 is the voltage of the second initial signal and Vdd is the power supply voltage of the first power supply terminal VDD. Based on the principle that the charge of the first node N1 remains unchanged before and after entering the data boosting stage, the voltage of the first node N1 is pulled up to Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2), where C1 is the capacitance value of the first capacitor C1 and C2 is the capacitance value of the second capacitor C2.

[0042] The light emitting stage t4, as Figure 6 shown, is Figure 1 the state diagram of the pixel driving circuit shown during the light emitting stage. Among them, the transistors with a cross mark are in the off state, and the transistors without a cross mark are in the on state. During the light emitting stage, a high level is input to the second enable signal terminal EM2 and the third enable signal terminal EM3, and a low level is input to the reset signal terminal Reset, the first enable signal terminal EM1, the first gate driving signal terminal G1, and the second gate driving signal terminal G2. The fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The voltage of the fourth node N4 changes from Vini1 to VN4, where Vini1 is the voltage of the first initial signal. The voltage of the first node N1 is coupled to Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2) + (VN4 - Vini1) under the action of the second capacitor C2. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The driving transistor T3 of the present disclosure outputs a current I = (μWCox / 2L)(Vdata + Vth + (C1 / (C1 + C2))×(Vdd - Vini2) + (VN4 - Vini1) - VN4 - Vth) 2= (μWCox / 2L) (Vdata + (C1 / (C1 + C2)) × (Vdd - Vini2) - Vini1) 2 Among them, the voltages of the first initial signal and the second initial signal can be the same.

[0043] It can be seen from this that in this exemplary embodiment, the output current of the pixel driving circuit has nothing to do with the threshold of the driving transistor T3. This pixel driving circuit can avoid the problem of uneven display of the display panel caused by inconsistent thresholds of the driving transistor T3. At the same time, since the voltage of the first node N1 is pulled high during the data enhancement stage t3, this pixel driving circuit can output a higher current. Here, the first capacitor C1 and the second capacitor C2 can also adjust the output current of the driving transistor, or adjust the voltage range of the data signal when the output current range is certain.

[0044] This exemplary embodiment also provides a method for driving a pixel driving circuit. This driving method is used to drive the above-mentioned pixel driving circuit, and the driving method includes:

[0045] In the reset stage, an effective level is input to the reset signal terminal Reset, the second enable signal terminal EM2, and the first enable signal terminal EM1, and an invalid level is input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, and the third enable signal terminal EM3;

[0046] In the data writing stage, an effective level is input to the reset signal terminal Reset, the first gate driving signal terminal G1, and the first enable signal terminal EM1, and an invalid level is input to the second gate driving signal terminal G2, the second enable signal terminal EM2, and the third enable signal terminal EM3;

[0047] In the data enhancement stage, an effective level is input to the reset signal terminal Reset and the second gate driving signal terminal G2, and an invalid level is input to the first gate driving signal terminal G1, the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3;

[0048] In the light emitting stage, an effective level is input to the second enable signal terminal EM2 and the third enable signal terminal EM3, and an invalid level is input to the reset signal terminal Reset, the first enable signal terminal EM1, the first gate driving signal terminal G1, and the second gate driving signal terminal G2.

[0049] Among them, the effective level is the level that can drive the target circuit. For example, when the target circuit is an N-type transistor, the effective level is a high level, and the invalid level is logically opposite to the effective level. This driving method has been described in detail in the above content and will not be elaborated here.

[0050] This exemplary embodiment further provides a display panel, which includes the above-mentioned pixel driving circuit. The display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.

[0051] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0052] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A pixel driving circuit, characterized in that Including: A driving circuit, connected to a first node, a second node, and a third node, for inputting a driving current from the third node to the second node according to a signal of the first node; A compensation circuit, connected to the third node, the first node, and a first enable signal terminal, for connecting the first node and the third node in response to a signal of the first enable signal terminal; A data writing circuit, connected to the second node, a data signal terminal, and a first gate driving signal terminal, for transmitting a signal of the data signal terminal to the second node in response to a signal of the first gate driving signal terminal; A light emitting control circuit, connected to a first power supply terminal, the third node, the second node, a fourth node, a second enable signal terminal, and a third enable signal terminal, for connecting the first power supply terminal and the third node in response to a signal of the second enable signal terminal, and for connecting the second node and the fourth node in response to a signal of the third enable signal terminal; A signal enhancing circuit, connected to the first power supply terminal, a fifth node, and a second gate driving signal terminal, for connecting the first power supply terminal and the fifth node in response to a signal of the second gate driving signal terminal; A first storage circuit, connected between the fifth node and the first node; A second storage circuit, connected between the first node and the fourth node; A first reset circuit, connected to the fourth node, a first initial signal terminal, and a reset signal terminal, for transmitting a signal of the first initial signal terminal to the fourth node in response to a signal of the reset signal terminal; A second reset circuit, connected to the fifth node, the first enable signal terminal, and a second initial signal terminal, for transmitting a signal of the second initial signal terminal to the fifth node in response to a signal of the first enable signal terminal.

2. The pixel driving circuit according to claim 1, wherein The driving circuit includes: A driving transistor, with a first pole connected to the third node, a second pole connected to the second node, and a gate connected to the first node.

3. The pixel driving circuit according to claim 1, wherein The compensation circuit includes: A first transistor, with a first pole connected to the third node, a second pole connected to the first node, and a gate connected to the first enable signal terminal; The data writing circuit includes: A second transistor, with a first pole connected to the data signal terminal, a second pole connected to the second node, and a gate connected to the first gate driving signal terminal.

4. The pixel driving circuit according to claim 1, wherein The light emitting control circuit includes: A fourth transistor, with a first pole connected to the first power supply terminal, a second pole connected to the third node, and a gate connected to the second enable signal terminal; A fifth transistor, with a first pole connected to the second node, a second pole connected to the fourth node, and a gate connected to the third enable signal terminal.

5. The pixel driving circuit according to claim 1, wherein The signal enhancing circuit includes: A sixth transistor, with a first pole connected to the first power supply terminal, a second pole connected to the fifth node, and a gate connected to the second gate driving signal terminal; The first storage circuit includes: A first capacitor, with a first electrode of the first capacitor connected to the fifth node and a second electrode connected to the first node; The second storage circuit includes: A second capacitor, with a first electrode of the second capacitor connected to the first node and a second electrode connected to the fourth node.

6. The pixel driving circuit according to claim 1, wherein The first reset circuit includes: A seventh transistor, having a first pole connected to the first initial signal terminal, a second pole connected to the fourth node, and a gate connected to the reset signal terminal; The second reset circuit includes: An eighth transistor, having a first pole connected to the second initial signal terminal, a second pole connected to the fifth node, and a gate connected to the first enable signal terminal.

7. The pixel driving circuit according to claim 1, wherein The first initial signal terminal shares the second initial signal terminal.

8. The pixel driving circuit according to claim 2, wherein The driving transistor is an N-type transistor.

9. A method for driving a pixel driving circuit, characterized in that For driving the pixel driving circuit according to any one of claims 1-8, the driving method includes: In the reset stage, an effective level is input to the reset signal terminal, the second enable signal terminal, and the first enable signal terminal, and an invalid level is input to the first gate driving signal terminal, the second gate driving signal terminal, and the third enable signal terminal; In the data writing stage, an effective level is input to the reset signal terminal, the first gate driving signal terminal, and the first enable signal terminal, and an invalid level is input to the second gate driving signal terminal, the second enable signal terminal, and the third enable signal terminal; In the data enhancement stage, an effective level is input to the reset signal terminal and the second gate driving signal terminal, and an invalid level is input to the first gate driving signal terminal, the first enable signal terminal, the second enable signal terminal, and the third enable signal terminal; In the light emitting stage, an effective level is input to the second enable signal terminal and the third enable signal terminal, and an invalid level is input to the reset signal terminal, the first enable signal terminal, the first gate driving signal terminal, and the second gate driving signal terminal.

10. A display panel, characterized in that, It includes the pixel driving circuit according to any one of claims 1-8.

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