Image sensor and method of forming image sensor pixel structure

Abstract

The application provides an image sensor and a forming method of an image sensor pixel structure, and is applied to the technical field of semiconductors. In the forming method of the image sensor pixel structure provided by the application, in the process of growing a polysilicon gate structure by using silane in a low-pressure furnace tube of a conventional 55nm image sensor, doped ions with controllable concentration and adsorption effect are simultaneously introduced, so that the metal ion pollution of the gate structure of the small-size image sensor is reduced, and the white pixel of the small-size image sensor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an image sensor and a forming method of image sensor pixel structure. BACKGROUND

[0002] CMOS image sensors have been developed rapidly in the past decade and are widely used in mobile phones, computers, digital cameras and other fields. Generally, an active pixel unit of a CMOS image sensor includes a photo diode (PD) in an epitaxial layer and several transistors. Taking a 4T structure CMOS image sensor as an example, the four transistors specifically include a transfer transistor 110 (Tx), a source follow transistor (SF), a reset transistor (RST) and a row select transistor (RS). The basic working principle of the CMOS image sensor is as follows: before light, the reset transistor and the transfer transistor are turned on to release the original electrons in the photo diode region; during light, all the transistors are turned off to generate charges in the space charge region of the photo diode; during reading, the transfer transistor is turned on to transfer the charges stored in the PD region to the floating diffusion node (FD), and after the transfer, the transfer transistor is turned off and waits for the next light to enter. The charge signal on the floating diffusion node is then used to adjust the source follow transistor to convert the charge into a voltage, and the current is output to the analog-to-digital conversion circuit through the row select transistor.

[0003] At present, with the continuous advancement of standard CMOS process level and the market demand for small size pixels, the pixel size of the CMOS image sensor has gradually decreased from 5.6 mm to 1.0 mm. In order to increase the area of the photo diode region PD, the pixel size has to be reduced, and therefore, the vertical gate oxide process is developed. Specifically, the existing method for forming a vertical gate oxide is to grow polysilicon in a low-pressure furnace tube, and then perform P ion implantation to increase the K value of the polysilicon and thereby reduce the equivalent gate oxide thickness. However, the existing forming method causes metal contamination of the CMOS image sensor product under small size conditions, and thus eventually causes the problem of white pixels. SUMMARY

[0004] The present application aims to provide an image sensor and a forming method of image sensor pixel structure, to propose a new method for forming a vertical gate oxide, and to improve the problem of white pixels of the image sensor.

[0005] In a first aspect, to solve the above technical problems, the present application provides a forming method of image sensor pixel structure, which can at least include the following steps:

[0006] Step S1, providing a semiconductor substrate, wherein a device isolation structure and at least one photodiode region defined by the device isolation structure are formed in the semiconductor substrate;

[0007] Step S2, etching the semiconductor substrate of the photodiode region to form at least one gate trench required for each photodiode region;

[0008] Step S3, forming a doped and patterned gate structure required for each photodiode region by controlling and utilizing a deposition process, and in each photodiode region, the patterned gate structure at least fills the respective gate trench.

[0009] Further, the step S3 of forming the doped and patterned gate structure can include: placing the semiconductor substrate with the gate trench formed in step S2 into a low-pressure furnace tube, and introducing a controllable concentration of silane gas and a doping gas to at least fill the doped and patterned gate structure in the gate trench.

[0010] Further, the doping ions contained in the doped and patterned gate structure formed in step S3 can be phosphorus ions and carbon ions.

[0011] Further, the concentration range of the phosphorus ions can be 1E19-7E21 / cm3.

[0012] Further, the concentration range of the carbon ions can be 1E19-7E21 / cm3.

[0013] Further, the device isolation structure can be a P-type isolation well.

[0014] Further, the step of providing a semiconductor substrate with a device isolation structure and a photodiode region in step S1 can include:

[0015] providing a semiconductor substrate, and forming a patterned hard mask layer on the semiconductor substrate;

[0016] performing P-type ion implantation on the semiconductor substrate with the patterned hard mask layer as a mask to form a P-type isolation well structure, and performing well ion implantation on the semiconductor substrate with ions of a first conductivity type before or after forming the P-type isolation well structure to form a photodiode region;

[0017] performing ion implantation on a surface layer of the photodiode region with ions of a second conductivity type to form a photodiode in the photodiode region.

[0018] Further, before the step of forming the required doped and patterned gate structure of each of the photodiode regions by controlling and using a deposition process in step S3, it can also include the step of forming a gate oxide layer by a thermal oxidation process or a deposition process.

[0019] Further, the doped and patterned gate structure formed in step S3 can also extend to cover the surface of the corresponding semiconductor substrate on both sides of the gate trench.

[0020] In a second aspect, based on the same inventive concept, the present application also provides an image sensor, in particular, the image sensor can include a plurality of pixel structures, wherein each of the pixel structures can be formed by using the method for forming an image sensor pixel structure as described above.

[0021] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0022] In the method for forming an image sensor pixel structure provided by the present application, by simultaneously introducing the doped ions with controllable concentration and adsorption effect into the process of growing the polysilicon gate structure by using silane in the low-pressure furnace tube of the conventional 55nm image sensor, the metal ion pollution of the gate structure of the small-size image sensor is reduced, and the white pixels of the small-size image sensor are improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The figure is a flowchart of the method for forming an image sensor pixel structure in an embodiment of the present application.

[0024] Figures 2a to 2c The figure is a structural schematic diagram of the method for forming an image sensor pixel structure in an embodiment of the present application in its preparation process.

[0025] In the figure, the reference signs are as follows:

[0026] 100 - semiconductor substrate; 101 - device isolation structure (P-type isolation well);

[0027] 102 - gate trench; 110 - photodiode region;

[0028] 120 - patterned gate structure. DETAILED DESCRIPTION

[0029] As described in the background, at present, with the continuous progress of standard CMOS process level, and the market demand for small size pixels, the pixel size of CMOS image sensor has gradually reduced from 5.6mm to 1.0mm. In order to increase the area of photodiode region PD, the pixel size has to be reduced, and therefore, the vertical gate oxide process is developed. Specifically, the existing method for forming vertical gate oxide is to use silane to grow polysilicon in a low pressure furnace tube, and then perform P ion implantation on the surface of the polysilicon layer formed as a gate structure to increase the K value of the polysilicon layer, and thereby reduce the equivalent gate oxide thickness. However, the existing forming method will cause metal contamination of the CMOS image sensor product under small size condition, and thereby eventually cause the problem of white pixels.

[0030] Therefore, the present application provides a forming method of image sensor pixel structure to propose a new method for forming vertical gate oxide, and to improve the problem of white pixels of image sensor.

[0031] Reference Figure 1 , Figure 1 The flowchart of the forming method of image sensor pixel structure provided by the present application is shown in the figure. Specifically, the steps include:

[0032] Step S1, providing a semiconductor substrate, wherein a device isolation structure is formed in the semiconductor substrate, and at least one photodiode region is defined by the device isolation structure;

[0033] Step S2, etching the semiconductor substrate of the photodiode region to form at least one gate trench required for each photodiode region;

[0034] Step S3, forming a doped and patterned gate structure required for each photodiode region by controlling and utilizing deposition process, and in each photodiode region, the patterned gate structure at least fills each gate trench.

[0035] That is, in the forming method of image sensor pixel structure provided by the present application, by simultaneously introducing doped ions with controllable concentration and adsorption effect in the process of growing polysilicon gate structure in a low pressure furnace tube in the conventional 55nm image sensor, the metal ion contamination of the gate structure of the small size image sensor formed is reduced, and the white pixels of the small size image sensor are improved (reduced).

[0036] The image sensor and the forming method of the image sensor pixel structure according to the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are very simplified and are not drawn to scale, and are only used to facilitate and clarify the purpose of illustrating the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

[0037] As shown in the present application and claims, unless the context clearly indicates otherwise, the words "one", "an", "a", and / or "the" do not specify a singular form, but can also include a plural form. Generally, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements. In the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual production.

[0038] wherein, Figures 2a to 2c The forming method of the image sensor pixel structure in an embodiment of the present application is shown in the structural schematic diagram in the preparation process.

[0039] In step S1, referring to Figure 2a As shown, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 is formed with a device isolation structure 101 and at least one photodiode region 110 defined by the device isolation structure 101. The semiconductor substrate 100 can be any suitable substrate known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multi-layer structures formed by these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-silicon-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double-side polished wafers (DSP), ceramic substrates such as aluminum oxide, quartz, or glass substrates, etc. For example, the semiconductor substrate 100 in the present embodiment is a silicon wafer.

[0040] It should be noted that in the embodiment of the present application, the device isolation structure 101 can be a P-type isolation well, of course, the device isolation structure 101 can also be an N-type isolation well, and the type of the formed image sensor can be determined, and the present application does not make a specific limitation.

[0041] In the embodiment, the image sensor is, for example, a CMOS image sensor, and can include a pixel region and a peripheral circuit region (not shown), wherein the pixel region can include a plurality of pixel structures arranged in an array. Each pixel structure is used to convert incident light into an electrical signal output, and thus includes a photodiode having a photoelectric conversion function and a plurality of transistors (not shown) for controlling electronic readout. For example, the pixel structure of the CMOS image sensor in the embodiment of the present application can be a 4-pixel shared floating diffusion pixel structure (not shown). Specifically, all photodiode regions 110 separated by the device isolation structure 101 in the pixel structure can be arranged in an array. A patterned gate structure 120 (as shown in Figure 2c

[0042] It should be noted that in another embodiment, the photodiode region 110 can also be used to connect to a charge-coupled (CCD) image sensor. For a plurality of pixel structures distributed in the pixel region, one of the pixel structures in the embodiment of the present application is described, and the cross-sectional structure of the pixel structure adopts the structure as shown in Figure 2c It can be understood that some of the pixel structures in the pixel region can adopt a design different from the structure described in the present application.

[0043] Optionally, the embodiment of the present application also provides a way to form the device isolation structure 101 and the photodiode region 110 of the semiconductor substrate 100, and specifically includes the following steps:

[0044] First, with reference to Figure 2a , a semiconductor substrate 100 is provided, which can be any suitable substrate material known to those skilled in the art, and can be a bare silicon substrate, a silicon-on-insulator substrate, etc., or a substrate with a doped epitaxial layer on the surface, for example, the semiconductor substrate 100 is composed of a silicon substrate and a silicon germanium epitaxial layer on the surface. A patterned mask layer (not shown) and a protective layer (not shown) are formed on the semiconductor substrate 100, and the protective layer can be a P-type implantation layer;

[0045] Then, with reference to Figure 2a ​P-type ions are implanted into the semiconductor substrate 100 to form a P-type isolation well structure as a device isolation structure 101, and before or after forming the device isolation structure 101, ions of the first conductive type are implanted into the semiconductor substrate 100 to form a photodiode region 110;

[0046] Then, a surface layer of the photodiode region 110 is implanted with ions of the second conductive type to form a photodiode in the photodiode region 110.

[0047] The first conductive type ions can be P-type ions, such as boron ions, and the second conductive type ions can be N-type ions, such as phosphorus ions. In the embodiment, P-type ions are implanted into the semiconductor substrate 100 to form a P-well, and then N-type ions are implanted into a partial region of the P-well to form a photodiode.

[0048] In step S2, referring to FIG. 2, the semiconductor substrate 100 of the photodiode region 110 is etched to form at least one gate trench 102 required for each photodiode region 110. The gate trench 102 can be any polygonal ring allowed by the process, such as a square ring, a pentagonal ring, a pentagonal star ring, a hexagonal ring, etc. Figure 2b

[0049] It should be noted that the gate trench 102 required for each photodiode region 110 can be completely located within the photodiode region 110, and the patterned gate structure required for each photodiode region 110 can be completely located within the photodiode region 110. Of course, the gate trench 102 required for each photodiode region 110 can be partially located within the photodiode region 110, which is not limited in the present application. The etching process for forming the gate trench 102 can be a wet etching process or a dry etching process, or a hybrid process of wet and dry etching processes.

[0050] In step S3, referring to FIG. 3, a doped patterned gate structure 120 required for each photodiode region 110 is formed by controlling and utilizing a deposition process, and the patterned gate structure 120 at least fills each gate trench 102 in each photodiode region 110. Figure 2c

[0051] The doped patterned gate structure 120 formed in step S3 also extends and covers the surface of the semiconductor substrate 100 on both sides of the gate trench 102. ​​

[0052] In the present embodiment, the semiconductor substrate 100 in which the gate trench 102 is formed in step S2 can be placed in a preset low-pressure furnace tube, and a controllable concentration of silane gas and a doping gas can be introduced, and then by controlling the flow of the introduced doping gas, a doped patterned gate structure 120 with a controllable concentration of doping ions at least in the gate trench 102 can be filled. Specifically, the doping ions are exemplarily phosphorus ions and carbon ions. The concentration of the phosphorus ions is exemplarily in the range of 1E19-7E21 / cm3. The concentration of the carbon ions is exemplarily in the range of 1E19-7E21 / cm3.

[0053] In the process of forming the patterned gate structure 120, the phosphorus doping ions are simultaneously introduced to provide the dielectric constant K of the polysilicon material of the patterned gate structure 120, so as to achieve the purpose of reducing the equivalent gate oxide thickness. In the process of forming the patterned gate structure 120, the carbon doping ions are simultaneously introduced to utilize the adsorption of the carbon doping ions to reduce the problem of increasing white pixels caused by metal contamination in the prior art in the process of forming the vertical gate oxide structure (patterned gate structure 120). That is, the forming method of the image sensor provided by the present application can reduce the metal ion contamination of the gate structure of the small-size image sensor and improve the white pixels (reduce the white pixels) of the small-size image sensor.

[0054] Further, before the step of forming the doped patterned gate structure 120 required by each photodiode region 110 in step S3 by controlling and utilizing the deposition process, the forming method provided by the present application can further include forming a gate oxide layer (not shown) by a thermal oxidation process or a deposition process.

[0055] In addition, based on the forming method of the image sensor pixel structure described above, the present embodiment further provides an image sensor, which includes a plurality of pixel structures, wherein each pixel structure can be formed by the forming method of the image sensor pixel structure described above.

[0056] In summary, in the forming method of the image sensor pixel structure provided by the present application, by simultaneously introducing controllable concentration and adsorption doping ions in the process of growing a polysilicon gate structure by silane in a low-pressure furnace tube of a conventional 55nm image sensor, the metal ion contamination of the gate structure of the small-size image sensor is reduced, and the white pixels of the small-size image sensor are improved.

[0057] It should be noted that, although the present application has been described in terms of the preferred embodiments, the embodiments disclosed are not intended to define the scope of the application. Those skilled in the art who pertain to the art will be able to affect changes and modifications to the embodiments disclosed without departing from the scope of the application defined by the claims and their equivalents. It is therefore intended that such changes and modifications be included within the scope of the application.

[0058] It should also be understood that, unless specifically stated otherwise, the terms "first", "second", "third" and the like, in the description do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, and are not necessarily used to denote the order, quantity, or importance of the elements.

[0059] In addition, it is to be appreciated that the terms "comprises", "comprising", "includes", "including", "contains", "containing" or variations thereof do not specify a complete or exclusive inclusion of a process, method, article or apparatus. For example, an article including a composition is not necessarily excluded from having additional composition. It is also to be appreciated that the terms "exemplary" and "for example" are used herein to mean "an example of. " It is to be further appreciated that all junctions mentioned in the specification, including the claims, are inclusive of the conjunctive and disjunctive meanings of "and" and "or" unless specifically stated otherwise. It is also to be appreciated that the terms "another" and "one or more" are used to include "at least one" of something unless specifically stated otherwise.

Claims

1. A method of forming an image sensor pixel structure, characterized by, At least comprising the following steps: Step S1, providing a semiconductor substrate, wherein a device isolation structure and at least one photodiode region defined by the device isolation structure are formed in the semiconductor substrate; Step S2, etching the semiconductor substrate of the photodiode region to form at least one gate trench required for each of the photodiode regions; Step S3, forming a doped and patterned gate structure required for each of the photodiode regions by controlling and utilizing a deposition process, and in each of the photodiode regions, the patterned gate structure at least fills each of the gate trenches; The step S3 of forming the doped and patterned gate structure comprises: placing the semiconductor substrate with the gate trenches formed in step S2 into a low-pressure furnace tube, and introducing a controllable concentration of silane gas and a doping gas to at least fill the doped and patterned gate structure in the gate trenches; And the doping ions contained in the doped and patterned gate structure formed in step S3 are phosphorus ions and carbon ions.

2. The method of forming an image sensor pixel structure of claim 1, wherein, The concentration of the phosphorus ions ranges from 1E19 to 7E21 / cm3.

3. The method of forming a pixel structure of an image sensor according to claim 1, wherein The concentration of the carbon ions ranges from 1E19 to 7E21 / cm3.

4. The method of forming a pixel structure of an image sensor according to claim 1, wherein The device isolation structure is a P-type isolation well.

5. The method for forming an image sensor pixel structure according to claim 4, wherein The step of providing a semiconductor substrate with a device isolation structure and a photodiode region comprises: Providing a semiconductor substrate, and forming a patterned hard mask layer on the semiconductor substrate; Using the patterned hard mask layer as a mask, performing P-type ion implantation on the semiconductor substrate to form a P-type isolation well structure, and before or after forming the P-type isolation well structure, performing well ion implantation on the semiconductor substrate using ions of a first conductivity type to form a photodiode region; Performing ion implantation on the surface layer of the photodiode region using ions of a second conductivity type to form a photodiode in the photodiode region.

6. The method for forming a photo-sensor pixel structure according to claim 1, wherein, Before the step S3 of forming a doped and patterned gate structure required for each of the photodiode regions by controlling and utilizing a deposition process in step S3, it further comprises forming a gate oxide layer by a thermal oxidation process or a deposition process.

7. The method for forming a photo-sensor pixel structure according to claim 1, wherein The doped and patterned gate structure formed in step S3 further extends and covers the surface of the semiconductor substrate corresponding to both sides of the gate trench.

8. An image sensor, comprising: The image sensor comprises a plurality of pixel structures, wherein each of the pixel structures is formed by the forming method of the image sensor pixel structure according to any one of claims 1 to 7.

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