Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application provides a semiconductor device manufacturing method and a semiconductor device. The manufacturing method includes the following steps: processing a fin structure on a substrate layer; processing an oxide layer surrounding the fin structure outside the fin structure; making the fin structure protrude to the surface of the oxide layer; processing a dummy polysilicon gate between the fin structures on the surface of the oxide layer; forming an interlayer dielectric layer between adjacent dummy polysilicon gates; removing the dummy polysilicon gate to expose the oxide layer; injecting ion dopants into the oxide layer to etch the oxide layer downward to a certain depth; and depositing a metal gate on the surface of the etched oxide layer. The manufacturing method can be used to manufacture semiconductor devices, especially fin field effect transistors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] In actual chips, there are situations where multiple semiconductor components are densely arranged, such as transistors, diodes, resistors, and capacitors. As the size of semiconductor components continues to decrease, the integration of electronic components continues to increase, making it possible to integrate more semiconductor components into a given area.

[0003] As the size of semiconductor devices decreases, more leakage current is generated, which affects the normal operation of the components. Therefore, it is necessary to reduce leakage current.

[0004] The fin-shaped structure of the FinFET increases the gate's control area over the channel, significantly enhancing gate control capability. This effectively suppresses the short-channel effect and reduces subthreshold leakage current. Due to the suppression of the short-channel effect and the enhanced gate control capability, FinFETs can use thicker gate oxide than traditional ones, further reducing gate leakage current.

[0005] Furthermore, for fin field-effect transistors, differentiating the fin height of different types of transistor devices can increase the process window for leakage current and further reduce leakage current.

[0006] Patent TWI584478B, Semiconductor and Manufacturing Method Thereof, discloses a semiconductor device. This semiconductor device is a finned field-effect transistor, comprising a first fin and a second fin. The first fin is surrounded by a first isolation region and has a first height relative to the upper surface of the first isolation region. The second fin is surrounded by a second isolation region and has a second height relative to the upper surface of the second isolation region. The upper surfaces of the first and second isolation regions are at different horizontal planes.

[0007] The semiconductor device manufacturing method disclosed in the aforementioned patent involves implanting ions in a first isolation region, etching a first fin, implanting ions in a second isolation region, and etching a second fin. By utilizing different dopants in the implanted isolation regions and varying the etching rate, first and second fins of different heights are formed. After the fin etching is completed, a dummy gate dielectric layer is fabricated, and the dummy gate is etched.

[0008] The aforementioned patent processes the fin layer before the pseudo-polysilicon gate deposition in the semiconductor device, which has the following drawbacks:

[0009] The processing steps of the fin layer are performed before the chemical mechanical polishing (CMP) steps of the interlayer dielectric layer, which leads to an increase in the CMP process window and affects the stability and controllability of the CMP process.

[0010] The fin layer is fabricated before the transistor epitaxy (source epitaxy and drain epitaxy), which makes it difficult to control the uniformity of the epitaxial layer. Summary of the Invention

[0011] The purpose of this invention is to solve one of the above-mentioned technical problems and to provide a method for manufacturing a semiconductor device and a semiconductor device, specifically a method for manufacturing fin field-effect transistors with different fin heights, and a semiconductor device using fin height field-effect transistors.

[0012] To achieve the above objectives, some embodiments of the present invention provide the following technical solutions:

[0013] A method for fabricating a semiconductor device includes the following steps:

[0014] Fabricating a first fin field-effect transistor structure includes a plurality of first fin structures on a substrate layer, fabricating a first oxide layer surrounding the first fin structures, such that the first fin structures extend to the surface of the first oxide layer, and fabricating pseudo polysilicon gates on the surface of the first oxide layer and between the first fin structures, wherein a first interlayer dielectric layer is formed on the surface of the first oxide layer between adjacent pseudo polysilicon gates.

[0015] Remove the pseudo-polysilicon gate until the first oxide layer is exposed;

[0016] Implanting a first ion dopant into the first oxide layer;

[0017] The first oxide layer is etched downwards to a first depth;

[0018] A first metal gate is deposited on the surface of a first oxide layer corresponding to a first depth.

[0019] In some embodiments of the present invention, synchronization further includes the following steps:

[0020] A second fin field-effect transistor structure is fabricated on the same substrate layer as the first fin field-effect transistor structure. The second fin field-effect transistor structure is a semiconductor device that is different from the first fin field-effect transistor structure. It includes a plurality of second fin structures on the substrate layer, a second oxide layer is fabricated around the second fin structures, so that the second fin structures extend to the surface of the second oxide layer, and pseudo polysilicon gates are fabricated on the surface of the second oxide layer and between the second fin structures. A second interlayer dielectric layer is formed on the surface of the second oxide layer between adjacent pseudo polysilicon gates.

[0021] Remove the pseudo-polysilicon gate until the second oxide layer is exposed;

[0022] A second ionic dopant is implanted into the second oxide layer, the second ionic dopant being different from the first ionic dopant.

[0023] The second oxide layer is etched downwards to a second depth;

[0024] A second metal gate is deposited on the surface of the second oxide layer corresponding to the second depth.

[0025] In some embodiments of the present invention, the etching of the first oxide layer and the etching of the second oxide layer are performed simultaneously.

[0026] In some embodiments of the present invention, the manufacturing method further includes the following steps:

[0027] When implanting the first ion dopant into the first oxide layer, a photoresist layer is used to shield the exposed area of ​​the second oxide layer;

[0028] After the first ion dopant implantation is completed, the photoresist layer is removed;

[0029] When implanting the second ion dopant into the second oxide layer, a photoresist layer is used to shield the exposed area of ​​the first oxide layer;

[0030] After the second ion dopant implantation is completed, the photoresist layer is removed.

[0031] In some embodiments of the present invention, the first depth and the second depth are at least 2 nm.

[0032] In some embodiments of the present invention, the height difference between the first depth and the second depth is at least 2 nm.

[0033] In some embodiments of the present invention, the manufacturing method further includes the following steps:

[0034] Before etching the first oxide layer and the second oxide layer, the epitaxial regions of the first fin structure and the second fin structure are processed.

[0035] In some embodiments of the present invention, the manufacturing method further includes the following steps:

[0036] Before removing the pseudo-polysilicon gate, the surfaces of the first interlayer dielectric layer, the second interlayer dielectric layer, and the pseudo-polysilicon gate are subjected to chemical mechanical polishing treatment, so that the top surface of the first interlayer dielectric layer is flush with the top surface of the pseudo-polysilicon gate, and the top surface of the second interlayer dielectric layer is flush with the top surface of the pseudo-polysilicon gate.

[0037] In some embodiments of the present invention, the manufacturing method further includes the following steps:

[0038] The first interlayer dielectric layer, the first metal gate, the second interlayer dielectric layer, and the second metal gate are subjected to chemical mechanical polishing treatment so that the top surface of the first metal gate is flush with the top surface of the first interlayer dielectric layer, and the top surface of the second metal gate is flush with the top surface of the second interlayer dielectric layer.

[0039] Some embodiments of the present invention further provide a fin field-effect transistor, which is fabricated using the fin field-effect transistor fabrication method described above.

[0040] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows:

[0041] 1. Etching of the fin structure after pseudo-polysilicon gate removal (pseudo-polysilicon gate chemical mechanical polishing) can control the chemical mechanical polishing process window, ensuring the stability and controllability of the chemical mechanical polishing process.

[0042] 2. The fin layer processing steps are performed after the transistor epitaxy (source epitaxy and drain epitaxy) and before the epitaxy is formed. The fin height is the same, which can reduce the problem of difficulty in controlling the uniformity of the epitaxy due to different fin heights and improve the controllability of the processing uniformity of the epitaxial layer. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1a This is a first-view structural diagram of a finned field-effect transistor.

[0045] Figure 1b This is a second-view structural diagram of a fin field-effect transistor.

[0046] Figure 1c This is a third-view structural diagram of a fin field-effect transistor.

[0047] Figure 2a A flowchart of the manufacturing method provided for the first embodiment;

[0048] Figure 2b A schematic diagram of the first fin field-effect transistor with a pseudo-polysilicon gate;

[0049] Figure 2c A schematic diagram of the first fin field-effect transistor structure with pseudo-polysilicon gate removed;

[0050] Figure 2d A schematic diagram of the structure for implanting the first ion dopant into the first oxide layer;

[0051] Figure 2e This is a schematic diagram of the structure etched to the first depth.

[0052] Figure 2f A schematic diagram of the first fin field-effect transistor structure after the first metal gate has been fabricated;

[0053] Figure 3a A flowchart of the manufacturing method provided for the second embodiment;

[0054] Figure 3b A schematic diagram of a first fin field-effect transistor structure and a second fin field-effect transistor structure with pseudo-polysilicon gates fabricated on the same substrate.

[0055] Figure 3c A schematic diagram of the pseudo-polysilicon gate structure to remove the first fin field-effect transistor structure and the second fin field-effect transistor structure;

[0056] Figure 3d A schematic diagram of the structure for implanting the first ion dopant into the first oxide layer;

[0057] Figure 3e A schematic diagram of the structure for implanting a second ionic dopant into the second oxide layer;

[0058] Figure 3f This is a schematic diagram of the semiconductor structure after etching the first and second depths.

[0059] Figure 3g This is a schematic diagram of the semiconductor device structure after processing the first metal gate and the second metal gate.

[0060] In the above figures:

[0061] 1-Basal layer;

[0062] 2-Metal gate;

[0063] 3-Pseudo-polycrystalline silicon gate;

[0064] 4-Interlayer dielectric layer;

[0065] 5-Oxide layer;

[0066] 601 - First fin structure, 602 - Second fin structure;

[0067] 701 - First oxide layer, 702 - Second oxide layer;

[0068] 801 - First interlayer dielectric layer; 802 - Second interlayer dielectric layer;

[0069] 901 - First metal gate, 902 - Second metal gate;

[0070] 1001 - First depth, 1002 - Second depth;

[0071] 11-Photoresist layer;

[0072] 12-fin structure;

[0073] 1301 - First ion dopant, 1302 - Second ion dopant. Detailed Implementation

[0074] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0075] refer to Figure 1a , Figure 1b and Figure 1c This is the structure of a fin field-effect transistor in the existing technology.

[0076] The fin field-effect transistor includes a substrate 1, which may be a silicon substrate, or may be other elemental semiconductors, such as germanium, or may include compound semiconductors, such as silicon carbide or gallium arsenide.

[0077] The fin field-effect transistor also includes a number of fin structures 12 spaced apart above the substrate layer 1, which are formed by photolithography or etching and serve as the source and drain of the transistor. The etching process can be dry etching or wet etching.

[0078] An oxide layer 5 is provided around the fin structure as an insulating structure. The height of the fin structure extends above the upper surface of the oxide layer 5, that is, the top height of the fin structure is higher than the surface height of the oxide layer 5.

[0079] The fin field-effect transistor also includes a gate mechanism disposed on the middle portion of the fin structure. According to the fabrication process, a metal gate 2 and a pseudo-polysilicon gate 3 exist. Before fabricating the metal gate 2, a pseudo-polysilicon gate 3 is typically used to assist in constructing the gate structure. An interlayer dielectric layer 4 fills the spaces between the pseudo-polysilicon gates 3. After removing the pseudo-polysilicon gates 3, gate replacement is performed to fabricate the metal gate 2. The metal gate 2 connects the two fin structures of the same transistor and is deposited using a high-dielectric-constant dielectric. For example, the metal gate can be made of TiN, TaN, NiSi, CoSi, Mo, Cu, W, Al, Co, and / or other suitable conductive materials. After removing the pseudo-polysilicon gates 3, the interlayer dielectric layer 4 fills the spaces between the metal gates 2.

[0080] The first embodiment of the present invention provides a method for fabricating a semiconductor device, specifically a method for fabricating the fin height of a fin field-effect transistor.

[0081] The first embodiment of the present invention provides a processing method for a single semiconductor device, referring to... Figure 2aThe flowchart for the method of this embodiment is shown in the figure. Figures 2b to 2f This is a schematic diagram illustrating the implementation steps of the semiconductor device fabrication method provided in this embodiment.

[0082] The invention will first be explained using the structure of an NMOS transistor as an example to illustrate the fabrication method.

[0083] First refer to Figure 2b Before processing the fin structure height, the first fin field-effect transistor structure is first processed (the NMOS transistor in the attached figure is used as an example), which includes several first fin structures 601 on the substrate layer 1. The figure shows two first fin structures 601, which correspond to the source region and drain region of the NMOS transistor, respectively.

[0084] A first oxide layer 701 is processed around the first fin structure 601, such that the first fin structure 601 extends beyond the surface of the first oxide layer 701, i.e., the height of the first fin structure 601 is higher than the height of the surface of the first oxide layer 701. The first oxide layer 701 can be made of a dielectric material such as silicon oxide, high-density plasma (HDP) oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low-k dielectric material, and / or other suitable insulating material.

[0085] A pseudo-polysilicon gate 3 is fabricated on the surface of the first oxide layer 701 and between adjacent first fin structures 601; a first interlayer dielectric layer 801 is formed on the surface of the first oxide layer 701 between adjacent pseudo-polysilicon gates 3. The first interlayer dielectric layer 801 may be made of silicon nitride and / or silicon oxynitride and may be formed by chemical vapor deposition.

[0086] Further reference Figure 2c Remove the pseudo-polysilicon gate 3 to expose the upper surface of the first oxide layer 701.

[0087] refer to Figure 2d A first ionic dopant 1301 is implanted into the first oxide layer 701. A suitable ionic dopant can be selected based on the type of semiconductor device. Taking an NMOS transistor as an example, a P-type implant is performed, and a P-type dopant is implanted into its first oxide layer 701. The P-type dopant includes boron, aluminum, gallium, and indium, and its implantation dose is less than or equal to 10¹³ cm⁻².

[0088] refer to Figure 2e After the first ion dopant implantation is completed, the first oxide layer 701 is etched downward to a first depth 1001 at an etching rate of 35A / min-53A / min.

[0089] Figure 2eThe area indicated by the middle arrow represents the height of the first fin structure 601 formed after the first etching depth of 1001. Specifically, a mask template corresponding to the pattern of the area to be etched in the first fin field-effect transistor structure is designed, and after exposure imaging, etching is performed downwards from the surface of the first oxide layer 701. Dry etching or wet etching techniques can be used, and the etching depth can be controlled by controlling the etching rate and etching time.

[0090] The first depth 1001 is formed by etching the surface of the first oxide layer 701 towards the substrate layer 1, and represents the height difference between the etched surface of the first oxide layer 701 around the first fin structure 601 and the unetched surface of the first oxide layer 701. As shown in the attached figures, the first depth 1001 also represents the distance between the unetched surface of the first oxide layer 701 and the bottom surface of the first interlayer dielectric layer 801. In some embodiments of the present invention, the first depth 1001 is at least 2 nm, and the processing size of the first depth 1001 is selected according to the performance requirements of the semiconductor device.

[0091] refer to Figure 2f A first metal gate 901 is deposited on the surface of the first oxide layer 801 corresponding to the first depth 1001. Furthermore, a high-k dielectric material can be fabricated between the first fin structure 601 and the first metal gate 901, using materials such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba,Sr)TiO3, Al2O3, or other suitable high-k dielectric materials, combinations thereof, or other suitable materials.

[0092] This completes the fabrication of the first fin field-effect transistor (NMOS transistor).

[0093] The second embodiment of the present invention further provides a method for processing multiple semiconductor elements on a substrate layer, and in particular a method for processing fin structures of different heights for each semiconductor element.

[0094] refer to Figure 3a This is a flowchart of the manufacturing method in this embodiment, please refer to... Figures 3b to 3g This is a schematic diagram illustrating the implementation steps of the semiconductor device fabrication method provided in this embodiment.

[0095] refer to Figure 3b A second fin field-effect transistor structure is fabricated on the same substrate layer 1 as the first fin field-effect transistor structure, and the two fin field-effect transistor structures are spaced apart.

[0096] The second fin field-effect transistor structure is a semiconductor device that is different from the first fin field-effect transistor structure (the attached figure uses a PMOS transistor as an example). It includes several second fin structures 602 on the substrate layer 1. The figure shows two second fin structures 602, which correspond to the source region and drain region of the PMOS transistor, respectively.

[0097] Before etching the first oxide layer 701 and the second oxide layer 702, epitaxial regions of the first fin structure 601 and the second fin structure 602 are processed. The epitaxial regions can be made of the same material as the substrate 1, or, in the source and drain regions of the NMOS transistor, epitaxial silicon or epitaxial silicon carbide can be included, and in the source and drain regions of the PMOS transistor, epitaxial silicon germanium or epitaxial germanium can be included.

[0098] A second oxide layer 702 is processed around the second fin structure 602, so that the second fin structure 602 extends to the surface of the second oxide layer 702. A pseudo polysilicon gate 3 is processed on the surface of the second oxide layer 702 and between the second fin structure 602. A second interlayer dielectric layer 802 is formed on the surface of the second oxide layer 702 between adjacent pseudo polysilicon gates 3.

[0099] It should be noted that, for the second fin field-effect transistor structure, the second oxide layer 702 and the second interlayer dielectric layer 802 can be constructed with the same or different compositions as the first oxide layer 701 and the first interlayer dielectric layer 801.

[0100] refer to Figure 3c The pseudo-polysilicon gate 2 of the first fin field-effect transistor structure and the second fin field-effect transistor structure is etched away to expose the upper surfaces of the first oxide layer 701 and the second oxide layer 702.

[0101] A first ionic dopant 1301 is implanted into the first oxide layer 701. Taking an NMOS transistor as an example, a P-type implant is performed on it, and a P-type dopant is implanted into its first oxide layer 701. The P-type dopant includes boron, aluminum, gallium, and indium, and its implantation dose is less than or equal to 10¹³ cm⁻².

[0102] A second ionic dopant 1302 is implanted into the second oxide layer 702. Taking a PMOS transistor as an example, an N-type implantation is performed on it. An N-type dopant is implanted into the second oxide layer 702. The N-type dopant includes nitrogen, phosphorus, arsenic and antimony, and its implantation dose is less than or equal to 10¹³ cm⁻².

[0103] A mask template corresponding to the etchable areas of the first and second fin field-effect transistor structures is designed. After exposure imaging, the mask is etched downwards from the surface of the first oxide layer 701 to a first depth 1001, and downwards from the surface of the second oxide layer 702 to a second depth 1002. The etching rate is 35 A / min-53 A / min.

[0104] The second depth 1002 is formed by etching the surface of the second oxide layer 702 towards the substrate layer 1, and represents the height difference between the etched surface of the second oxide layer 702 around the second fin structure 602 and the unetched surface of the second oxide layer 702. As shown in the attached figures, the second depth 1002 also represents the distance between the unetched surface of the second oxide layer 702 and the bottom surface of the first interlayer dielectric layer 801. In some embodiments of the present invention, the second depth 1002 is at least 2 nm, and the processing size of the second depth 1002 is selected according to the performance requirements of the semiconductor device.

[0105] The etching of the first oxide layer 701 and the second oxide layer 702 can be performed simultaneously, and the etching rate and etching time can be controlled to control the etching depth. Due to the implantation of different types of ion dopants, the first etching depth 1001 and the second etching depth 1002 are different at the same etching rate and etching time, resulting in different fin heights.

[0106] Figure 3d and Figure 3e In some embodiments of the present invention, in order to avoid accidentally injecting the first ion dopant 1301 into the second oxide layer 702, a photoresist layer 11 is used to block the exposed area of ​​the second oxide layer 802 when ion implanting the first oxide layer 701; after the first ion dopant 1301 is implanted, the photoresist layer 11 is removed.

[0107] Similarly, to avoid accidentally injecting the second ion dopant 1302 into the first oxide layer 701, a photoresist layer 11 is used to block the exposed area of ​​the first oxide layer 701 when ion implanting the second oxide layer 702; after the second ion dopant 1302 is implanted, the photoresist layer 11 is removed.

[0108] Furthermore, the second depth 1002 may be the same as or different from the first depth 1001. In a preferred embodiment, the second depth 1002 is different from the first depth 1001, and the height difference between the two is at least 2 nm. (See reference...) Figure 3f The arrows indicate the heights of the first fin structure 601 and the second fin structure 602 formed after etching, respectively. It can be seen that fin structures of different heights are formed.

[0109] refer to Figure 3gAfter the fin structure height is processed, a first metal gate 901 is deposited on the surface of the first oxide layer 701 corresponding to the first depth 1001, and a second metal gate 902 is deposited on the surface of the second oxide layer 702 corresponding to the second depth 1002. Furthermore, gate dielectric layers can be processed between the first fin structure 601 and the first metal gate 901, and between the second fin structure 602 and the second metal gate 902, as described in the aforementioned embodiments, and will not be repeated here.

[0110] Thus, the fabrication of the first fin field-effect transistor (NMOS transistor) and the second fin field-effect transistor (PMOS transistor) with different fin heights was completed.

[0111] In some embodiments of the present invention, in the manufacturing methods described in the first and second embodiments above, the pseudo-polysilicon gate 3 can be planarized by one or more chemical mechanical polishing steps before removal. Therefore, the following steps are further included.

[0112] For the first fin field-effect transistor structure, the surfaces of the first interlayer dielectric layer 801 and the pseudo polysilicon gate 3 are subjected to chemical mechanical polishing treatment to planarize the first interlayer dielectric layer 801, improve the top surface flatness, and make the top surface of the first interlayer dielectric layer 801 flush with the top surface of the pseudo polysilicon gate 3.

[0113] For the second fin field-effect transistor structure, chemical mechanical polishing is performed on the surface of the second interlayer dielectric layer 802 and the surface of the pseudo-polysilicon gate 3 to planarize the second interlayer dielectric layer 802 and improve the top surface flatness. This makes the top surface of the second interlayer dielectric layer 802 flush with the top surface of the pseudo-polysilicon gate 3.

[0114] In some embodiments of the present invention, in the manufacturing methods described in the first and second embodiments above, after the metal gate is processed, the metal gate can be planarized by one or more chemical mechanical polishing steps. The processing method further includes the following steps:

[0115] For the first fin field-effect transistor structure, the surfaces of the first interlayer dielectric layer 801 and the first metal gate 701 are subjected to chemical mechanical polishing treatment so that the top surface of the first interlayer dielectric layer 801 is flush with the top surface of the first metal gate 701.

[0116] For the first fin field-effect transistor structure, the surfaces of the second interlayer dielectric layer 802 and the second metal gate 702 are subjected to chemical mechanical polishing treatment so that the top surface of the second interlayer dielectric layer 802 is flush with the top surface of the second metal gate 702.

[0117] The third embodiment of the present invention provides a semiconductor device that can be fabricated using the semiconductor fabrication method of the first embodiment. This semiconductor device can be a memory device, an input / output device, etc. The semiconductor device integrates a multi-fin field-effect transistor (FFET) structure, wherein the FFET includes transistors, diodes, resistors, capacitors, etc., and the fin structure of different FFETs has different heights.

[0118] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. It should be noted that any modifications, equivalent substitutions, and improvements made by those skilled in the art within the spirit and principles of the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of this patent application should be determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Fabricating a first fin field-effect transistor structure includes a plurality of first fin structures on a substrate layer, fabricating a first oxide layer surrounding the first fin structures, such that the first fin structures extend to the surface of the first oxide layer, and fabricating pseudo polysilicon gates on the surface of the first oxide layer and between the first fin structures, wherein a first interlayer dielectric layer is formed on the surface of the first oxide layer between adjacent pseudo polysilicon gates. Remove the pseudo-polysilicon gate until the first oxide layer is exposed; Implanting a first ion dopant into the first oxide layer; The first oxide layer is etched downwards to a first depth; A first metal gate is deposited on the surface of a first oxide layer corresponding to a first depth; A second fin field-effect transistor structure is fabricated on the same substrate layer as the first fin field-effect transistor structure. The second fin field-effect transistor structure is a semiconductor device that is different from the first fin field-effect transistor structure. It includes a plurality of second fin structures on the substrate layer, a second oxide layer is fabricated around the second fin structures, so that the second fin structures extend to the surface of the second oxide layer, and pseudo polysilicon gates are fabricated on the surface of the second oxide layer and between the second fin structures. A second interlayer dielectric layer is formed on the surface of the second oxide layer between adjacent pseudo polysilicon gates. Remove the pseudo-polysilicon gate until the second oxide layer is exposed; A second ionic dopant is implanted into the second oxide layer, the second ionic dopant being different from the first ionic dopant. The second oxide layer is etched downwards to a second depth; The second depth is different from the first depth; A second metal gate is deposited on the surface of the second oxide layer corresponding to the second depth; The first interlayer dielectric layer, the first metal gate, the second interlayer dielectric layer, and the second metal gate are subjected to chemical mechanical polishing treatment so that the top surface of the first metal gate is flush with the top surface of the first interlayer dielectric layer, and the top surface of the second metal gate is flush with the top surface of the second interlayer dielectric layer.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The etching of the first oxide layer and the etching of the second oxide layer are performed simultaneously.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Further steps include: When implanting the first ion dopant into the first oxide layer, a photoresist layer is used to shield the exposed area of ​​the second oxide layer; After the first ion dopant implantation is completed, the photoresist layer is removed; When implanting the second ion dopant into the second oxide layer, a photoresist layer is used to shield the exposed area of ​​the first oxide layer; After the second ion dopant implantation is completed, the photoresist layer is removed.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first depth and the second depth are at least 2 nm.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The height difference between the first depth and the second depth is at least 2 nm.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Further steps include: Before etching the first oxide layer and the second oxide layer, the epitaxial regions of the first fin structure and the second fin structure are processed.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Further steps include: Before removing the pseudo-polysilicon gate, the surfaces of the first interlayer dielectric layer, the second interlayer dielectric layer, and the pseudo-polysilicon gate are subjected to chemical mechanical polishing treatment, so that the top surface of the first interlayer dielectric layer is flush with the top surface of the pseudo-polysilicon gate, and the top surface of the second interlayer dielectric layer is flush with the top surface of the pseudo-polysilicon gate.

8. A semiconductor device, characterized in that, It is prepared by the method of fabricating the semiconductor device according to any one of claims 1-7.

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