Display panel and display device

Abstract

The application provides a display panel and a display device. In the display panel, a first pixel is electrically connected with a first pixel circuit, and a second pixel is electrically connected with a second pixel circuit. The first pixel circuit has a smaller area in the orthogonal projection of the display panel than the second pixel circuit. The light-emitting layer of the first pixel at least partially overlaps the second pixel circuit, and the light-emitting layer of the second pixel at least partially overlaps the second pixel circuit. In the application, two first pixel circuits and two second pixel circuits with different areas in the pixel unit are used to drive different pixels, so that the display effect of the display panel is improved, the size of each pixel unit is reduced, and the pixel arrangement density of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display panel and a display device. BACKGROUND

[0002] With the continuous development of science and technology, modern society has entered the information age and is developing towards intelligence, and display is a key link to realize information exchange and intelligence. Among the current many display technologies, Micro-LED display technology is considered to be a disruptive next-generation display technology. Micro-LED display technology is a self-luminous display technology, which integrates arrayed micro-LED light-emitting devices on an active driving substrate to realize individual control and lighting to output display images. Micro-LED has the advantages of low power consumption, high brightness, high color saturation, high response speed, long life and high efficiency, and is small in size and high in flexibility, and can be applied to any display application occasion from small size to large size.

[0003] In order to make the light-emitting efficiency and color deviation performance of the Micro-LED light-emitting device reach the best state, it is necessary to use a pixel circuit with a relatively complex circuit structure to drive it. Obviously, the pixel circuit with a relatively complex circuit structure will occupy a larger area in the pixel unit, thereby making the PPI (Pixels Per Inch, pixel arrangement density) of the display panel very low. SUMMARY

[0004] Therefore, in order to solve the above problems, the present application provides a display panel and a display device, and the technical solutions are as follows:

[0005] A display panel, comprising a plurality of pixels, the pixel comprising a light-emitting layer; the pixel comprising a first pixel and a second pixel, the first pixel being electrically connected with a first pixel circuit, the second pixel being electrically connected with a second pixel circuit, the first pixel circuit having a smaller area in the orthogonal projection on the plane of the display panel than the second pixel circuit.

[0006] In the direction perpendicular to the plane of the display panel, the light-emitting layer of the first pixel at least partially overlaps with the second pixel circuit, and the light-emitting layer of the second pixel at least partially overlaps with the second pixel circuit.

[0007] A display device, comprising the above-mentioned display panel.

[0008] Compared with the prior art, the present application has the following advantages:

[0009] The display panel provided by the application comprises a first pixel circuit and a second pixel circuit, the first pixel circuit has a smaller area in a pixel unit than the second pixel circuit, and the first pixel circuit and the second pixel circuit are used to drive different pixels, so that the size of each pixel unit can be greatly reduced, and the pixel arrangement density of the display panel can be improved.

[0010] In addition, in a direction perpendicular to the plane of the display panel, the light-emitting layer of the first pixel at least partially overlaps the second pixel circuit, and the light-emitting layer of the second pixel at least partially overlaps the second pixel circuit, that is, in the direction perpendicular to the plane of the display panel, the second pixel circuit and the first pixel and the second pixel circuit and the second pixel share a part of the area of the pixel unit, so as to further reduce the size of each pixel unit and further improve the pixel arrangement density of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0012] Figure 1 A top view of a display panel provided by the application is shown in the figure.

[0013] Figure 2 A schematic view of a pixel unit in the display panel provided by the application is shown in the figure. Figure 1

[0014] Figure 3 A cross-sectional view of a display panel provided by the application is shown in the figure.

[0015] Figure 4 A circuit structure schematic view of a first pixel circuit provided by the application is shown in the figure.

[0016] Figure 5 A circuit structure schematic view of a second pixel circuit provided by the application is shown in the figure.

[0017] Figure 6 A schematic view of a pixel unit in another display panel provided by the application is shown in the figure.

[0018] ​Figure 7 A schematic view of a pixel unit in a display panel according to the present application;

[0019] Figure 8 A schematic view of a pixel unit in a display panel according to the present application;

[0020] Figure 9 A schematic view of a pixel unit in a display panel according to the present application;

[0021] Figure 10 A schematic view of a pixel unit in a display panel according to the present application;

[0022] Figure 11 A schematic view of a first pixel circuit according to the present application;

[0023] Figure 12 A schematic view of a pixel unit in a display panel according to the present application;

[0024] Figure 13 A schematic view of a display panel according to the present application;

[0025] Figure 14 A schematic view of a pixel unit in a display panel according to the present application;

[0026] Figure 15 A schematic view of a display panel according to the present application;

[0027] Figure 16 A schematic view of a display panel according to the present application;

[0028] Figure 17 A schematic view of pixel brightness color deviation according to the present application;

[0029] Figure 18 A schematic view of a display device according to the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0032] refer to Figure 1 , Figure 1 This is a top view schematic diagram of a display panel provided by the present invention. Figure 1 Multiple pixel units 10 are arranged in an array, where M represents the row direction of the array arrangement and N represents the column direction of the array arrangement. Each pixel unit 10 includes at least two pixels; Reference Figure 2 , Figure 2 for Figure 1 A schematic diagram of a pixel unit shown.

[0033] The display panel includes multiple pixels, each pixel including a light-emitting layer; the pixels include a first pixel 11 and a second pixel 12, the first pixel 11 is electrically connected to a first pixel circuit 13, the second pixel 12 is electrically connected to a second pixel circuit 14, and the orthographic projection area of ​​the first pixel circuit 13 on the plane of the display panel is smaller than the orthographic projection area of ​​the second pixel circuit 14 on the plane of the display panel.

[0034] In the direction perpendicular to the plane of the display panel, the light-emitting layer of the first pixel 11 overlaps at least partially with the second pixel circuit 14, and the light-emitting layer of the second pixel 12 overlaps at least partially with the second pixel circuit 14.

[0035] like Figure 2 As shown, the pixel unit 10 in the display panel includes a first pixel circuit 13 and a second pixel circuit 14. The orthographic projection area of ​​the first pixel circuit 13 on the plane of the display panel is smaller than that of the second pixel circuit 14 on the plane of the display panel. That is to say, the second pixel circuit 14 occupies a larger area in the pixel unit 10, while the first pixel circuit 13 occupies a smaller area in the pixel unit 10. Therefore, in this application, two types of first pixel circuits 13 and second pixel circuits 14, which occupy different areas in the pixel unit 10, are used to drive different pixels. Compared with the method of using the second pixel circuit 14 to drive all pixels, the size of each pixel unit 10 can be greatly reduced, thereby increasing the pixel arrangement density of the display panel.

[0036] Furthermore, in the direction perpendicular to the plane of the display panel, the light-emitting layer of the first pixel 11 overlaps at least partially with the second pixel circuit 14, and the light-emitting layer of the second pixel 12 overlaps at least partially with the second pixel circuit 14. In other words, in the direction perpendicular to the plane of the display panel, the second pixel circuit 14 and the first pixel 11, as well as the second pixel circuit 14 and the second pixel 12, will share a portion of the area of ​​the pixel unit 10, thereby further reducing the size of each pixel unit 10 and further increasing the pixel arrangement density of the display panel.

[0037] Optionally, in another embodiment of the present invention, the first pixel 11 is a quantum dot light-emitting unit; the second pixel 12 is an LED (Light Emitting Diode) light-emitting unit, and optionally the second pixel 12 is a Micro-LED light-emitting unit.

[0038] The first pixel 11 includes a first light-emitting layer, which is used to emit red or green light.

[0039] The second pixel 12 includes a second light-emitting layer, which is used to emit blue light.

[0040] For details, please refer to Figure 3 , Figure 3 for Figure 2 The schematic cross-sectional view of the structure shown along the cutting line AA' indicates that the first pixel 11 (quantum dot light-emitting unit) includes at least: an anode 11a, a light-emitting layer 11b, and a cathode 11c stacked together. The first pixel 11 is located within the pixel opening. In the direction perpendicular to the display panel, the orthographic projection of the light-emitting layer 11b completely covers the orthographic projection of the anode exposed by the pixel opening. The anode 11a is coupled to one electrode of the corresponding thin-film transistor T in the pixel circuit. The cathode 11c is connected to other voltage terminals. Under the action of the electric field, the holes generated by the anode 11a and the electrons generated by the cathode 11c move and migrate to the light-emitting layer 11b. When the holes and electrons meet in the light-emitting layer 11b, they generate excitons, which emit light through radiative transitions.

[0041] The second pixel 12 (LED light-emitting unit or Micro-LED light-emitting unit) includes at least an N electrode 12a, a P electrode 12b, and an epitaxial layer 12c; wherein the N electrode 12a and the P electrode 12b are coupled to one electrode of the corresponding thin film transistor T in the pixel circuit, and the epitaxial layer 12c includes at least an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked together, wherein the second light-emitting layer of the second pixel 12 can be understood as the active layer.

[0042] It should be noted that, Figure 3 The following explanation uses five thin-film transistors T1-T5 as an example. Figure 3 Of the five thin-film transistors T1-T5 shown, the first thin-film transistor T1 to the fourth thin-film transistor T4 are used to form part of the circuit structure of the second pixel circuit 14 that controls the operation of the second pixel 12, and the fifth thin-film transistor T5 is used to form part of the circuit structure of the first pixel circuit 13 that controls the operation of the first pixel 11, as shown. Figure 3As shown, in the direction perpendicular to the plane where the display panel is located, the light-emitting layer of the first pixel 11 at least partially overlaps with the second pixel circuit 14, and the light-emitting layer of the second pixel 12 at least partially overlaps with the second pixel circuit 14. Wherein, QQ is the orthographic projection area of the light-emitting layer of the first pixel 11 on the display panel, EE is the orthographic projection area of the light-emitting layer of the second pixel 12 on the display panel, WW is the orthographic projection area of the second pixel circuit 14 on the display panel, and RR is the orthographic projection area of the first pixel circuit 13 on the display panel.

[0043] The current LED display device or Micro-LED display device has display problems of red light and green light. Specifically, the light-emitting efficiency of the red light emitting unit is very low, and the light-emitting efficiency will decrease sharply with the increase of temperature in the working process, and the power consumption is the highest. The light-emitting peak of the green light emitting unit will shift at low brightness. The display power consumption of the LED light-emitting unit or the Micro-LED light-emitting unit is higher than that of the quantum dot light-emitting unit.

[0044] The current quantum dot light-emitting unit display device has solved the technical problems of the current LED display device or Micro-LED display device, which has display problems of red light and green light. The light-emitting efficiency of the red light LED is low, and the efficiency of the red light LED decreases obviously with the increase of temperature. The light peak of the green light LED will shift at low brightness. Due to the characteristics of the inorganic light-emitting layer of the quantum dot light-emitting unit itself, the working life is even higher than that of the OLED (Organic Light-Emitting Diode) light-emitting unit, but the quantum dot light-emitting unit for emitting blue light has a shorter life.

[0045] Therefore, in the present application, the quantum dot light-emitting unit is used as the first pixel 11 to emit red light or green light, and the LED light-emitting unit or the Micro-LED light-emitting unit is used as the second pixel 12 to emit blue light, that is, the combination display of the quantum dot light-emitting unit and the LED light-emitting unit or the Micro-LED light-emitting unit is realized.

[0046] The color shift problem caused by the deviation of the forward voltage between inorganic light emitting diodes (LEDs) or the size deviation of the driving current is serious. In order to make the light emitting efficiency and the viewing angle of the blue light emitting LED light emitting unit or the Micro-LED light emitting unit reach the best state, the second pixel circuit 14 with the control function of PWM (Pulse Width Modulation) control and PAM (Pulse Amplitude Modulation) control needs to be integrated to drive the second pixel 12. The quantum dot light emitting unit emitting red light or green light only needs to use the first pixel circuit 13 with PWM control or PAM control to drive the first pixel 11.

[0047] For example, the first pixel circuit 13 is a 7T1C pixel circuit with PWM control or PAM control. The second pixel circuit 14 can be a combination of a set of 7T1C pixel circuits with PWM control and a set of 7T1C pixel circuits with PAM control. The first pixel circuit 13 needs 7 thin film transistors to cooperate with other devices to form. Then the second pixel circuit 14 needs more than 7 thin film transistors to cooperate with other devices to form.

[0048] Reference Figure 4 , Figure 4 A circuit structure schematic diagram of a first pixel circuit provided by the application is shown in the figure. The first pixel circuit 13 includes 7 thin film transistors (M1-M7) and a capacitor (Cst). Figure 5 , Figure 5 A circuit structure schematic diagram of a second pixel circuit provided by the application is shown in the figure. The second pixel circuit 14 includes 12 thin film transistors (T1-T12) and two capacitors (C1 and C2).

[0049] It should be noted that Figure 4 The first pixel circuit 13 shown in the figure is only described in the form of an example. It can also be other circuit structures. Similarly Figure 5 The second pixel circuit 14 shown in the figure is only described in the form of an example. It can also be other circuit structures. Compared with Figure 4 and Figure 5 It can be seen that since the second pixel circuit 14 needs more thin film transistors than the first pixel circuit 13, the orthographic projection area of the second pixel circuit 14 on the plane of the display panel will be greater than the orthographic projection area of the first pixel circuit on the plane of the display panel.

[0050] Therefore, in the present application, the pixels in the pixel unit 10 are not all driven and displayed by the second pixel circuit 14 with a larger occupied area, but the driving of the corresponding pixels is realized by the first pixel circuit 13 and the second pixel circuit 14 with different occupied areas in the pixel unit 10. Compared with the driving mode of driving the pixels by the second pixel circuit 14, the size of each pixel unit 10 can be greatly reduced, and the pixel arrangement density of the display panel can be improved.

[0051] In addition, different pixel circuits are used to drive and display different types of pixels, so that the most suitable driving mode is used to drive and display different types of pixels, which can ensure that the luminous efficiency and viewing angle performance of each pixel can reach the best state, thereby greatly improving the display effect of the display panel. The combination of micro LED light emitting units and quantum dot light emitting units in the same panel display improves the light color and efficiency performance of red and green light, and the power consumption is reduced to 1 / 10 of the original; compared with pure quantum dot light emitting unit display, the blue light life is greatly improved.

[0052] Optionally, in another embodiment of the present application, referring to Figure 6 , Figure 6 Another schematic diagram of a pixel unit in a display panel provided by the present application is provided, and the display panel further includes a third pixel 15. The light emission colors of the first pixel 11 and the third pixel 15 are different.

[0053] The third pixel 15 is electrically connected with a third pixel circuit 16. The area of the orthographic projection of the third pixel circuit 16 on the plane of the display panel is smaller than the area of the orthographic projection of the second pixel circuit 14 on the plane of the display panel.

[0054] Specifically, the first pixel 11 is a quantum dot light emitting unit; the second pixel 12 is an LED (Light Emitting Diode, light emitting diode) light emitting unit, and the second pixel 12 is a Micro-LED light emitting unit; and the third pixel 15 is a quantum dot light emitting unit.

[0055] The third pixel 15 includes a third light emitting layer. The light emission colors of the first light emitting layer and the third light emitting layer are different. Assuming that the first pixel 11 is used to emit red light and the third pixel 15 is used to emit green light, the first light emitting layer is used to emit red light, the third light emitting layer is used to emit green light, and the second light emitting layer is used to emit blue light, so as to ensure that the display panel realizes full-color display based on three primary colors.

[0056] The display device of the quantum dot light emitting unit has solved the technical problem of the display problem of red light and green light in the LED display device or the Micro-LED display device. The red light LED has low light emitting efficiency, and the efficiency of the red light LED decreases obviously with the increase of temperature. The green light LED has light peak position offset at low brightness. The quantum dot light emitting unit has the characteristics of the inorganic light emitting layer, and the working life is even higher than that of the OLED light emitting unit. However, the quantum dot light emitting unit for emitting blue light has a short service life.

[0057] Therefore, in the present application, the quantum dot light emitting unit is used as the first pixel 11 for emitting red light, the LED light emitting unit or the Micro-LED light emitting unit is used as the second pixel 12 for emitting blue light, and the quantum dot light emitting unit is used as the third pixel 15 for emitting green light, that is, the combination display of the quantum dot light emitting unit and the LED light emitting unit or the Micro-LED light emitting unit is realized.

[0058] The quantum dot light emitting unit for emitting red light or green light does not have display problems, and only needs to use the third pixel circuit 16 of PWM control or PAM control to drive the third pixel 15.

[0059] For example, the third pixel circuit 16 can be a 7T1C pixel circuit of PWM control or PAM control, that is, the third pixel circuit 16 needs 7 thin film transistors to cooperate with other devices.

[0060] Optionally, the first pixel circuit 13 and the third pixel circuit 16 can be the same or different circuit structures of the 7T1C pixel circuit. In the case that the first pixel circuit 13 and the third pixel circuit 16 are the same, the manufacturing process of the pixel circuit in the display panel can be simplified.

[0061] Therefore, it can be known that not all the pixels in the pixel unit 10 in the present application are driven and displayed by the second pixel circuit 14 with a large occupied area. Instead, the first pixel circuit 13, the second pixel circuit 14 and the third pixel circuit 16 with different occupied areas in the pixel unit are used to drive the corresponding pixels. Compared with the mode that all the pixels are driven by the second pixel circuit 14, the size of each pixel unit can be greatly reduced, and the pixel arrangement density of the display panel can be improved.

[0062] In addition, different pixel circuits are used to drive and display different types of pixels, so that the most suitable driving mode is used to drive and display different types of pixels, so that the light emitting efficiency and the viewing angle offset of each pixel can be in the best state, so that the display effect of the display panel can be improved to the greatest extent.

[0063] Optionally, in another embodiment of the present application, as shown inFigure 6 As shown, in the direction perpendicular to the plane where the display panel is located, the light-emitting layer of the third pixel 15 at least partially overlaps with the second pixel circuit 14.

[0064] Specifically, in the direction perpendicular to the plane where the display panel is located, the light-emitting layer of the first pixel 11 at least partially overlaps with the second pixel circuit 14, the light-emitting layer of the second pixel 12 at least partially overlaps with the second pixel circuit 14, and the light-emitting layer of the third pixel 15 at least partially overlaps with the second pixel circuit 14.

[0065] That is, in the direction perpendicular to the plane where the display panel is located, the second pixel circuit 14 and the first pixel 11, the second pixel circuit 14 and the second pixel 12, and the second pixel circuit 14 and the third pixel 15 respectively share a part of the area of the pixel unit 10, so as to further reduce the size of each pixel unit 10 and further improve the pixel arrangement density of the display panel.

[0066] Optionally, in another embodiment of the present application, as shown in the accompanying drawings, Figure 1 The display panel comprises a plurality of pixel units 10, which are optionally arranged in an array, and is exemplified by 11 rows and 9 columns.

[0067] As shown in the accompanying drawings, Figure 6 One pixel unit 10 comprises one first pixel 11, one second pixel 12 and one third pixel 25.

[0068] In the first direction X, the first pixel 11 and the third pixel 25 are oppositely arranged, and the second pixel 12 is located between the first pixel 11 and the third pixel 25; the first direction X is parallel to the plane where the display panel is located.

[0069] In the direction perpendicular to the plane where the display panel is located, the orthographic projection area of the first pixel 11 and the orthographic projection area of the third pixel 25 are greater than the orthographic projection area of the second pixel 12.

[0070] Specifically, since the first pixel 11 is a quantum dot light emitting unit, the second pixel 12 is a light emitting diode (LED) light emitting unit, and the second pixel 12 is optionally a Micro-LED light emitting unit, and the third pixel 15 is a quantum dot light emitting unit, when the second pixel 12 is a Micro-LED light emitting unit, since the light emitting efficiency of the Micro-LED light emitting unit is high, the size of the Micro-LED light emitting unit does not need to be large to achieve the required light emitting brightness, and the size of the Micro-LED light emitting unit is generally less than 50 μm at present. Under the condition that the size of the Micro-LED light emitting unit is small, the light emitting area of the second pixel 12 is also small, and it can also be understood that the area occupied by the second pixel 12 in the pixel unit 10 is small. Therefore, the light emitting area of the first pixel 11 and the third pixel 15 can be appropriately increased based on the size of the pixel unit 10, so as to improve the light emitting efficiency of the first pixel 11 and the third pixel 15, and reduce the driving current applied to the first pixel 11 and the third pixel 15 under the same light emitting brightness, thereby increasing the display life of the first pixel 11 and the third pixel 15. Moreover, since the area of the blue light LED is small, various pixel arrangement modes can be realized in the arrangement of one pixel, thereby improving the display resolution.

[0071] Optionally, in another embodiment of the present application, referring to Figure 7 , Figure 7 a schematic diagram of a pixel unit in another display panel provided by the present application is provided.

[0072] In the first direction X, the second pixel 12 at least partially overlaps the first pixel 11, and the second pixel 12 at least partially overlaps the third pixel 15.

[0073] In the second direction Y, the second pixel 12 at least partially overlaps the first pixel 11, and the second pixel 12 at least partially overlaps the third pixel 15.

[0074] The first direction X and the second direction Y are perpendicular, and the second direction Y is parallel to the plane in which the display panel is located.

[0075] Specifically, as Figure 7 indicated, taking the first direction X and the second direction Y being perpendicular as an example, based on the structure of the first pixel 11 and the third pixel 15 as Figure 6 indicated, the first pixel 11 and the third pixel 15 are further improved to further increase the light emitting area of the first pixel 11 and the third pixel 15, to maximize the light emitting efficiency of the first pixel 11 and the third pixel 15, and to further reduce the driving current applied to the first pixel 11 and the third pixel 15 under the same light emitting brightness, thereby increasing the display life of the first pixel 11 and the third pixel 15 and improving the display effect of the display panel.

[0076] Optionally, in another embodiment of the present application, referring to Figure 8 , Figure 8 A schematic diagram of a pixel unit in a display panel provided by the present application is shown.

[0077] As shown in Figure 1 , the display panel comprises a plurality of pixel units 10, which are optionally arranged in an array.

[0078] As shown in Figure 8 , the pixel unit 10 comprises two first pixels 11, one second pixel 12 and two third pixels 25.

[0079] The centers of the two first pixels 11 and the centers of the two third pixels 25 form a virtual quadrilateral W.

[0080] The second pixel 12 is located within the virtual quadrilateral W, and the second pixel 12 covers the geometric center of the virtual quadrilateral W.

[0081] Specifically, the center of the first pixel 11 is the geometric center of the first pixel 11. In terms of the first pixel 11 with a rectangular shape, the center of the first pixel 11 is the intersection of the diagonal lines of the rectangle. Similarly, the centers of the second pixel 12 and the third pixel 25 are the geometric centers of the second pixel 12 and the third pixel 25, respectively.

[0082] Since the first pixel 11 is a quantum dot light emitting unit, the second pixel 12 is an LED (Light Emitting Diode) light emitting unit, which is optionally a Micro-LED light emitting unit, and the third pixel 25 is a quantum dot light emitting unit, when the second pixel 12 is a Micro-LED light emitting unit, its own size is generally below 50 μm. Obviously, the light emitting area of the second pixel 12 will also be relatively small, and it can also be understood that the occupied area of the second pixel 12 in the pixel unit 10 will be relatively small, and thus the arrangement of a plurality of other pixels can be realized in the area of the pixel unit 10 other than the second pixel 12, thereby improving the display resolution and display effect of the display panel.

[0083] And by setting the second pixel 12 within the virtual quadrilateral W and covering the geometric center of the virtual quadrilateral W, the center of the second pixel 12 optionally coincides with the geometric center of the virtual quadrilateral W. Then based on one second pixel 12, there will be no problem of weak blue light when any one first pixel 11 and any one third pixel 15 form a full-color display unit, thereby improving the display effect of the display panel.

[0084] Optionally, as shown in Figure 8 , the line connecting the centers of the two first pixels 11 forms one side of the virtual quadrilateral W.

[0085] Or, refer to Figure 9 , Figure 9 A schematic view of a pixel unit in a display panel according to the present application is provided, and a line connecting the centers of two first pixels 11 forms a diagonal line of the virtual quadrangle W.

[0086] Optionally, in another embodiment of the present application, refer to Figure 10 , Figure 10 A schematic view of a pixel unit in a display panel according to the present application is provided, and when two first pixels 11 and two third pixels 15 exist in a pixel unit 10, a first pixel circuit 13 is provided for each first pixel 11, and a third pixel circuit 16 is provided for each third pixel 15, so as to ensure the working performance of each first pixel 11 and each third pixel 15.

[0087] Optionally, in another embodiment of the present application, refer to Figure 11 , Figure 11 A structural schematic view of another first pixel circuit according to the present application is provided.

[0088] The first pixel circuit 13 comprises a driving module 131, which is configured to provide a driving current for the first pixel 11.

[0089] The first pixel circuit 13 further comprises a first switch module 132 and a second switch module 133.

[0090] The first end of the first switch module 132 and the first end of the second switch module 133 are electrically connected to the output end of the driving module 131.

[0091] The second end of the first switch module 132 is connected to a first first pixel 11A, and the second end of the second switch module 133 is connected to a second first pixel 11B.

[0092] The driving module 131 provides a driving current for the first pixel 11, and the first pixel 11 displays in response to the driving current.

[0093] Specifically, in another embodiment of the present application, the driving module 131 of the first pixel circuit 13 is shared by two first pixels 11, and the first switch module 132 and the second switch module 133 are used to control the flow direction of the driving current to the two first pixels 11, respectively.

[0094] For example, when the first switch module 132 is in the on state and the second switch module 133 is in the off state, the driving current generated by the driving module 131 flows to the first first pixel 11A and does not flow to the second first pixel 11B, at this time, the first first pixel 11A displays based on the driving current, and the second first pixel 11B does not display; when the first switch module 132 is in the off state and the second switch module 133 is in the on state, the driving current generated by the driving module 131 flows to the second first pixel 11B and does not flow to the first first pixel 11A, at this time, the first first pixel 11A does not display, and the second first pixel 11B displays based on the driving current; when the first switch module 132 and the second switch module 133 are both in the on state, the driving current generated by the driving module 131 flows to the first first pixel 11A and the second first pixel 11B, respectively, at this time, the first first pixel 11A and the second first pixel 11B display based on the driving current, respectively; when the first switch module 132 and the second switch module 133 are both in the off state, the driving current generated by the driving module 131 does not flow to the first first pixel 11A and the second first pixel 11B, at this time, the first first pixel 11A and the second first pixel 11B do not display.

[0095] Therefore, in the present application, the driving module 131 of the first pixel circuit 13 is shared by two first pixels 11, and the first switch module 132 and the second switch module 133 are combined, so that the circuit structure for controlling the display of the two first pixels 11 can be greatly simplified, and the size of each pixel unit 10 can be greatly reduced, thereby improving the pixel arrangement density of the display panel.

[0096] It should be noted that when the number of first pixels 11 needs to be increased, for example, the number of first pixels 11 is three, then based on the actual circuit load condition, another switch module can be added to control the driving current to flow to the third first pixel.

[0097] It should be noted that, Figure 11 It should be noted that the specific circuit form of the driving module shown is only described in the form of an example, and it can also be other circuit structures as long as it can provide driving current for pixel display.

[0098] It should be noted that the first switch module 132 can be a transistor, the first end of the transistor is electrically connected with the output end of the driving module 131, the second end of the transistor is connected with the first first pixel 11A, and the control end of the transistor receives a switch control signal Sweep1, the switch control signal Sweep1 is used to control the transistor to be in the on state or the off state.

[0099] Similarly, the second switch module 133 can also be a transistor, the first end of the transistor is electrically connected with the output end of the driving module 131, the second end of the transistor is connected with the second first pixel 11B, and the control end of the transistor receives a switch control signal Sweep2, which is used for controlling the transistor to be in a conducting state or a closed state.

[0100] When two third pixels 15 are arranged in one pixel unit 10, the design of the third pixel circuit 16 can be the same as that of the first pixel circuit 13 with two first pixels 11; specifically, the third pixel circuit 16 also includes a driving module, which is used for providing a driving current for the third pixel 15, so that two third pixels 15 can share one driving module of the third pixel circuit 16, and the control of the two third pixels 15 is realized in combination with a switch module.

[0101] Therefore, in the present application, two third pixels 15 share one driving module of the third pixel circuit 16, and in the case that the control of the two third pixels 15 can work normally, the circuit structure for controlling the two third pixels 15 to display can be greatly simplified, and thus the size of each pixel unit 10 can be greatly reduced, and the pixel arrangement density of the display panel can be improved.

[0102] It should be noted that when the number of third pixels 15 needs to be increased, for example, the number of third pixels 15 is three, then based on the actual circuit load condition, another switch module can be additionally arranged, which is used for controlling the circuit state of the driving current flowing to the third third pixel.

[0103] Optionally, in another embodiment of the present application, referring to Figure 12 , Figure 12 Another arrangement diagram of a pixel unit in a display panel provided by the present application is shown.

[0104] As shown in Figure 1 , a plurality of pixel units 10 are arranged in an array; as shown in Figure 12 , in the column direction N of the array arrangement, the pixel unit 10 includes oppositely arranged first and second regions AA and BB, and the first and second regions AA and BB have a gap therebetween.

[0105] The first region AA is provided with the first pixel circuit 13 and the third pixel circuit 16, and the second region BB is provided with the second pixel circuit 14.

[0106] Specifically, by arranging the second pixel circuit 14 on one side of the pixel unit 10 and arranging the first pixel circuit 13 and the third pixel circuit 16 on the other side of the pixel unit 10 in the column direction N of the array arrangement, the second pixel circuit 14 can be wired on the one side of the pixel unit 10 where the second pixel circuit 14 is located, and the first pixel circuit 13 and the third pixel circuit 16 can be wired on the other side of the pixel unit 10 where the first pixel circuit 13 and the third pixel circuit 16 are located.

[0107] That is, based on the distribution of the first pixel circuit 13, the second pixel circuit 14, and the third pixel circuit 16 in the pixel unit 10, the first pixel circuit 13, the second pixel circuit 14, and the third pixel circuit 16 can be wired in different areas, thereby greatly simplifying the wiring difficulty.

[0108] Optionally, as shown in FIG. 1, in the row direction M of the array arrangement, the first pixel circuit 13 and the third pixel circuit 16 are located on the two sides of the second pixel circuit 14, that is, the arrangement areas of the first pixel circuit 13 and the third pixel circuit 16 are as far away from each other as possible. In the case of simplifying the wiring difficulty, the crosstalk problem of the first pixel circuit 13 and the third pixel circuit 16 can be avoided, thereby improving the stability of the signal and the display effect of the display panel. Figure 12

[0109] Referring to FIG. 1, Figure 13 Figure 13 a schematic diagram of a display panel provided by the present application, the display panel further comprising a first gate drive circuit 17 and a second gate drive circuit 18.

[0110] The display panel comprises a first side and a second side oppositely arranged in the row direction M of the array arrangement.

[0111] The first gate drive circuit 17 is located on the first side and is electrically connected with the second pixel circuit 14;

[0112] The second gate drive circuit 18 is located on the second side and is electrically connected with the first pixel circuit 13 and the third pixel circuit 16 respectively.

[0113] Specifically, based on the distribution of the first pixel circuit 13, the second pixel circuit 14, and the third pixel circuit 16 in the pixel unit 10, the first gate drive circuit 17 can wire the second pixel circuit 14 on the one side of the pixel unit 10 where the second pixel circuit 14 is located to realize electrical connection, and the second gate drive circuit 18 can wire the first pixel circuit 13 and the third pixel circuit 16 on the other side of the pixel unit 10 where the first pixel circuit 13 and the third pixel circuit 16 are located to realize electrical connection.

[0114] ​​Therefore, based on the distribution of the first pixel circuit 13, the second pixel circuit 14 and the third pixel circuit 16 in the pixel unit 10, the wiring difficulty of the first gate driving circuit 17 and the second gate driving circuit 18 can be greatly reduced.

[0115] Optionally, in another embodiment of the present application, referring to Figure 14 , Figure 14 In another embodiment of the present application, referring to

[0116] It should be noted that in the actual design process of the display panel, the distribution of the first pixel circuit 13, the second pixel circuit 14 and the third pixel circuit 16 in the pixel unit 10 can be reasonably arranged based on actual needs, which is not limited in the embodiment of the present application.

[0117] Optionally, in another embodiment of the present application, referring to Figure 15 , Figure 15 In another embodiment of the present application, referring to

[0118] The substrate 19; the array layer 20 located on one side of the substrate 19.

[0119] The first pixel 11 and the second pixel 12 located on the side of the array layer 20 away from the substrate 19.

[0120] The encapsulation structure 23 located on the side of the array layer 20 away from the substrate 19, the encapsulation structure 23 is used for encapsulating the second pixel 12.

[0121] Specifically, as Figure 15 shown, the display panel further includes the third pixel 15 located on the side of the array layer 20 away from the substrate 19, the first pixel 11 is a quantum dot light emitting unit, the second pixel 12 is a Micro-LED light emitting unit, and the third pixel 15 is a quantum dot light emitting unit. Taking the first pixel 11 emitting red light, the second pixel 12 emitting blue light and the third pixel 15 emitting green light as an example, based on three primary colors, the display panel realizes full-color display.

[0122] Specifically, the array layer 20 is also called a TFT (Thin Film Transistor) layer, which is used for controlling the working state of the first pixel 11, the second pixel 12 and the third pixel 15.

[0123] As Figure 15As shown in the figure, the array layer 20 comprises a plurality of thin film transistors 201; wherein the thin film transistor 201 comprises an active layer 201a, a gate 201b, a source 201c, and a drain 201d; the array layer 20 further comprises a gate insulating layer 202 arranged between the active layer 201a and the gate 201b, an interlayer insulating layer 203 arranged between the gate 201b and the source 201c and the drain 201d, a passivation layer 204 arranged on the side of the source 201c and the drain 201d away from the interlayer insulating layer 203, and a planarization layer 205 arranged on the side of the passivation layer 204 away from the interlayer insulating layer 203; wherein the side of the planarization layer 205 away from the substrate 19 is provided with a plurality of electrode pad groups composed of a first electrode pad 21 and a second electrode pad 22, and the first electrode pad 21 and the second electrode pad 22 are electrically connected with the electrode terminals of the thin film transistor 201 corresponding thereto.

[0124] It should be noted that the source 201c and the drain 201d are located in the same layer.

[0125] It should be noted that the thin film transistor 201 in the embodiment of the present application can be a P-type thin film transistor or an N-type thin film transistor, and the P-type thin film transistor is taken as an example for description in the embodiment of the present application.

[0126] The specific connection mode is as shown in the figure Figure 15 As shown in the figure, a through hole is formed by etching the planarization layer 205 and the passivation layer 204 to expose the electrode terminals corresponding to the thin film transistor 201, so that the first electrode pad 21 and the second electrode pad 22 are in contact with the electrode terminals corresponding to the thin film transistor 201.

[0127] Optionally, as shown in the figure Figure 15 The display panel can further comprise a base buffer layer 24 between the substrate 19 and the array layer 20.

[0128] The base buffer layer 24 comprises but is not limited to an inorganic material layer or an organic material layer, wherein the material of the inorganic material layer comprises but is not limited to silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or aluminum nitride, etc., and the material of the organic material layer comprises but is not limited to acrylic or PI, etc.

[0129] Since the first pixel 11 is a quantum dot light emitting unit, the second pixel 12 is a Micro-LED light emitting unit, and the third pixel 15 is a quantum dot light emitting unit, in order to solve the limitation of the arrangement of the second pixel 12 on the array layer 20, a plurality of electrode pad groups composed of the first electrode pad 21 and the second electrode pad 22 are arranged on the side of the array layer 20 away from the substrate 19, the second pixel 12 includes a first electrode 121 and a second electrode 122, the first electrode pad 21 is electrically connected with the first electrode 121, and the second electrode pad 22 is electrically connected with the second electrode 122; that is, the array layer 20 can be the same as the array layer of a full Micro-LED display panel.

[0130] It should be noted that the distance between the first electrode pad 21 and the second electrode pad 22 corresponding to the second pixel 12 is D1, the distance between the first electrode pad 21 and the second electrode pad 22 corresponding to the first pixel 11 is D2, and the distance between the first electrode pad 21 and the second electrode pad 22 corresponding to the third pixel 15 is D3, wherein D1=D2=D3.

[0131] Further, as shown in FIG. 2, after the second pixel 12 is transferred to the array layer 20, the second pixel 12 needs to be individually packaged to avoid being damaged in the subsequent film layer manufacturing process. Figure 15

[0132] Optionally, the minimum size of the packaging structure 23 needs to be more than 10 μm larger than the maximum size of the second pixel 12, so as to prevent the packaging structure 23 from damaging the second pixel 12.

[0133] Further, as shown in FIG. 2, after the second pixel 12 is transferred to the array layer 20, the second pixel 12 needs to be individually packaged to avoid being damaged in the subsequent film layer manufacturing process. Figure 15

[0134] Optionally, after the packaging of the second pixel 12 is completed, the first buffer layer 25 is first prepared, and the first electrode pad 21 and the second electrode pad 22 are exposed by photoetching processing, and the patterned auxiliary cathode 28 is formed on the side of the first buffer layer 25 away from the substrate 19, the auxiliary cathode 28 is connected with the second electrode pad 22 through the through hole penetrating the first buffer layer 25; then the second buffer layer 26 is prepared on the side of the first buffer layer 25 away from the substrate 19, and the anode layer of the first pixel 11 and the third pixel 15 is prepared on the side of the second buffer layer 26 away from the substrate 19, the anode layer is connected with the first electrode pad 21 through the through hole penetrating the first buffer layer 25 and the second buffer layer 26; finally, the pixel definition layer 27 is prepared, the pixel definition layer 27 exposes the packaging structure 23 of the second pixel 12, and has a plurality of openings, the openings are used to expose the anode layer of the first pixel 11 and the third pixel 15. ​​

[0135] It should be noted that, in the direction perpendicular to the plane of the display panel, the orthographic projection of the opening overlaps with the orthographic projection of the auxiliary cathode 28.

[0136] Furthermore, light-emitting layers corresponding to the first pixel 11 and the third pixel 15 are formed in the opening, and a cathode layer 29 is formed on the side of the pixel definition layer 27 away from the substrate 19. The cathode layer 29 is connected to the auxiliary cathode 28 through a through hole penetrating the pixel definition layer 27 and the second buffer layer 26, thereby realizing the connection between the cathode layer 29 and the second electrode pad 22, and thus realizing the connection between the cathode layer 29 and the thin film transistor 201.

[0137] Since the first pixel 11 and the third pixel 15 are quantum dot light-emitting units, in order to improve the luminous efficiency of the first pixel 11 and the third pixel 15, the coverage area of ​​their light-emitting layer is relatively large. In the direction perpendicular to the plane of the display panel, the orthographic projection of the light-emitting layer will at least partially cover the orthographic projection of the first electrode pad 21 and the orthographic projection of the second electrode pad 22, such as... Figure 15 As shown, the orthographic projection of the second electrode pad 22 is completely covered by the orthographic projection of the light-emitting layer. Therefore, in this application, in order to realize the connection between the second electrode pad 22 and the cathode layer 29, an auxiliary cathode 28 is provided. In the direction perpendicular to the plane where the display panel is located, the orthographic projection of the anode layer 29 and the orthographic projection of the auxiliary cathode 28 partially overlap, that is, the auxiliary cathode 28 extends beyond the opening area to realize the connection with the cathode layer 29.

[0138] It should be noted that, as Figure 16 As shown, in the direction perpendicular to the plane of the display panel, the orthographic projection of the second pixel 12 on the display panel and the orthographic projection of the cathode layer 29 on the display panel do not overlap, thus ensuring the light emission efficiency of the second pixel 12 and preventing the cathode layer 29 from blocking the light emission of the second pixel 12. Here, CC represents the orthographic projection area of ​​the second pixel 12 on the display panel, and DD represents the area of ​​the cathode layer 29 on the display panel without an orthographic projection, i.e., the area not covered by the cathode layer 29.

[0139] Optionally, in another embodiment of the invention, reference is made to... Figure 16 , Figure 15 This is a cross-sectional schematic diagram of another display panel provided by the present invention.

[0140] Compared Figure 16 Regarding the display panel structure shown, the array layer 20 is completely identical, but the film layer structure on the side of the array layer 20 facing away from the substrate 19 is different, which will be described in detail below:

[0141] like Figure 16 As shown, the display panel also includes a buffer layer 30 located on the side of the array layer 20 facing away from the substrate 19.

[0142] The buffer layer 30 has a first recess 31, and the second pixel 12 and the encapsulation structure 23 are located in the first recess 31.

[0143] The slope angle β of the sidewall of the first recess 31 is 15°-75°.

[0144] Specifically, after the second pixel 12 is transferred to the array layer 20, a patterned auxiliary cathode 28 is formed on the side of the planarization layer 205 away from the substrate 19, the auxiliary cathode 28 is connected with the second electrode pad 22, then the buffer layer 30 of high refractive index material is formed, including but not limited to that the buffer layer 30 is processed by a halftone lithography process to form the first recess 31 and a pit structure for forming the first pixel 11 and the third pixel 15, and the buffer layer 30 of high refractive index material forms the encapsulation structure 23 for encapsulating the second pixel 12 at the second pixel 12 in a high-temperature post-baking process.

[0145] Optionally, the material of the buffer layer 30 is an organic material.

[0146] Optionally, as shown in Figure 17 The end of the encapsulation structure 23 away from the substrate 19 is a curved surface, which is convex in the direction away from the substrate 19, that is, a lens type encapsulation structure 23 is formed to adjust the light path of the light emitted by the second pixel 12, thereby improving the light emission efficiency of the second pixel 12.

[0147] And, in the high-temperature post-baking process of the buffer layer 30 of high refractive index material, the slope angle β of the sidewall of the first recess 31 is controlled to be 15°-75°, and preferably the slope angle β of the sidewall of the first recess 31 is controlled to be 55° by controlling the process parameters.

[0148] Referring to Figure 17 , Figure 17 A schematic diagram of pixel brightness color deviation provided by the present application is shown, in which the abscissa is the viewing angle, the ordinate is the brightness, K1 represents the change curve of the first pixel, K2 represents the change of the third pixel, K3 represents the change curve of the second pixel after the first recess, and K4 represents the change curve of the second pixel; as shown in Figure 17As shown, the luminous brightness of the first pixel 11, the luminous brightness of the second pixel 12 and the luminous brightness of the third pixel 15 are close to each other at 0° viewing angle, but without the first groove 31, the luminous brightness of the second pixel 12 will increase and the luminous brightness of the first pixel 11 and the third pixel 15 will decrease with the change of the viewing angle; then in order to balance the luminous brightness of the first pixel 11, the second pixel 12 and the third pixel 15 at different viewing angles, the first groove 31 is arranged in the present application and the slope angle β of the sidewall of the first groove 31 is 55°, so as to adjust the light emission of the second pixel 12 and ensure that the change trends of the luminous brightness of the first pixel 11, the second pixel 12 and the third pixel 15 are the same under the condition of the change of the viewing angle, that is, as shown Figure 16 the luminous brightness of the first pixel 11, the second pixel 12 and the third pixel 15 all decrease under the condition of the change of the viewing angle, so as to balance the luminance color cast of different pixels on the display panel and further improve the display performance of the display panel.

[0149] The anode layer corresponding to the first pixel 11 and the third pixel 15 is formed in the pit structure, and then the pixel definition layer 27 is prepared, the pixel definition layer 27 has a plurality of openings for exposing the anode layer of the first pixel 11 and the third pixel 15.

[0150] Further, the light-emitting layer corresponding to the first pixel 11 and the third pixel 15 is formed in the opening, the cathode layer 29 is formed on the side of the pixel definition layer 27 away from the substrate 19, the anode layer is connected with the first electrode pad 21 through the via hole penetrating through the buffer layer 30, the cathode layer 29 is connected with the auxiliary cathode 28 through the via hole penetrating through the pixel definition layer 27 and the buffer layer 30, the connection between the cathode layer 29 and the second electrode pad 22 is realized, and further the connection between the cathode layer 29 and the thin film transistor 201 is realized.

[0151] Similarly, since the first pixel 11 and the third pixel 15 are quantum dot light-emitting units, in order to improve the luminous efficiency of the first pixel 11 and the third pixel 15, the coverage area of the light-emitting layer is relatively large, and the orthographic projection of the light-emitting layer at least partially covers the orthographic projection of the first electrode pad 21 and the orthographic projection of the second electrode pad 22 in the direction perpendicular to the plane where the display panel is located, as shown Figure 16 the orthographic projection of the second electrode pad 22 is completely covered by the orthographic projection of the light-emitting layer, therefore the auxiliary cathode 28 is arranged in the present application in order to realize the connection between the second electrode pad 22 and the cathode layer 29, and the orthographic projection of the anode layer and the orthographic projection of the auxiliary cathode 28 partially overlap in the direction perpendicular to the plane where the display panel is located, that is, the auxiliary cathode 28 extends to the area outside the opening to realize the connection with the cathode layer 29.

[0152] It should be noted that, as shown Figure 16As shown, in the direction perpendicular to the plane where the display panel is located, the orthographic projection of the second pixel 12 on the display panel and the orthographic projection of the cathode layer 29 on the display panel do not have an overlapping area, so as to ensure the light emitting efficiency of the second pixel 12 and prevent the cathode layer 29 from shielding the light emitting of the second pixel 12. Wherein, CC is the orthographic projection area of the second pixel 12 on the display panel, and DD is the area on the display panel where the cathode layer 29 has no orthographic projection, i.e. the area not covered by the cathode layer 29.

[0153] Optionally, in another embodiment of the present application, the material of the packaging structure 23 has a refractive index greater than the material of the pixel definition layer 27.

[0154] Specifically, the material of the packaging structure 23 can have a refractive index greater than 1.67, and the material of the pixel definition layer 27 can have a refractive index around 1.5. By using the film layer structure with different refractive indexes, the light path of the light emitted by the second pixel 12 can be adjusted, and thus the light emitting efficiency of the second pixel 12 can be improved.

[0155] Optionally, in another embodiment of the present application, as shown in Figure 18 , the sidewall of the first groove 31 is covered with a reflective layer 32, and the material of the reflective layer 32 includes but is not limited to a metal reflective layer.

[0156] When the reflective layer 32 is a metal reflective layer, it can be prepared in the same process as the anode layer.

[0157] The reflective layer 32 is used to reflect the light incident on the reflective layer 32 from the second pixel 12, so as to adjust the light path of the light emitted by the second pixel 12, and thus improve the light emitting efficiency of the second pixel 12.

[0158] Optionally, in another embodiment of the present application, in the direction perpendicular to the plane where the display panel is located, the distance between the light emitting layer of the first pixel 11 and the substrate 19 is D1, and the distance between the light emitting layer of the second pixel 12 and the substrate 19 is D2.

[0159] Wherein, D1=D2.

[0160] Wherein, in the direction perpendicular to the plane where the display panel is located, the distance between the light emitting layer of the third pixel 15 and the substrate 19 is D3, and D1=D2=D3.

[0161] By making the light emitting layers of the first pixel 11, the second pixel 12 and the third pixel 15 in the same horizontal plane, the uniformity of the light emitting of each pixel can be ensured, color difference can be avoided, and thus the display effect of the display panel can be improved.

[0162] Optionally, based on all the above embodiments of the present application, in another embodiment of the present application, a display device is also provided, which is described with reference to Figure 18 ,​ A structural schematic diagram of a display device provided by the present application is shown in the following.

[0163] The display device 100 comprises the display panel as described in the above embodiments.

[0164] The display device 100 comprises but is not limited to a mobile phone, a tablet computer and the like, and the display device at least has the same technical effects as the display panel.

[0165] The above has described in detail the display panel and the display device provided by the present application, and the principles and implementation manners of the present application have been described by using specific examples; the above description of the embodiments is only used to help understand the method of the present application and the core idea thereof; meanwhile, for the ordinary skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as limiting the present application.

[0166] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment mainly describes the differences from other embodiments, and the same or similar parts between the embodiments can be understood by referring to each other. For the device disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the related parts can be understood by referring to the description of the method part.

[0167] It should also be noted that, in the present specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device inherently includes a series of elements, or further includes the elements inherent to the process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another same element in the process, method, article or device including the element.

[0168] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, The display panel comprises a plurality of pixels, and each pixel comprises a light-emitting layer; the pixels comprise a first pixel and a second pixel, the first pixel is electrically connected with a first pixel circuit, the second pixel is electrically connected with a second pixel circuit, and the first pixel circuit has a smaller area of a projection on a plane where the display panel is located than the second pixel circuit. In a direction perpendicular to the plane where the display panel is located, the light-emitting layer of the first pixel at least partially overlaps the second pixel circuit, and the light-emitting layer of the second pixel at least partially overlaps the second pixel circuit. The display panel further comprises a substrate, an array layer located on one side of the substrate, and a packaging structure located on a side of the array layer away from the substrate, the packaging structure being used for packaging the second pixel; the first pixel and the second pixel are located on a side of the array layer away from the substrate. In a direction perpendicular to the plane where the display panel is located, a distance between the light-emitting layer of the first pixel and the substrate is D1, and a distance between the light-emitting layer of the second pixel and the substrate is D2; D1 = D2; and / or, The display panel further comprises a buffer layer located on a side of the array layer away from the substrate; the buffer layer has a first recess, the second pixel and the packaging structure are located in the first recess; and a slope angle of a sidewall of the first recess is 15°-75°.

2. The display panel of claim 1, wherein, The first pixel comprises a first light-emitting layer, and the first light-emitting layer is used for emitting red light or green light. The second pixel comprises a second light-emitting layer, and the second light-emitting layer is used for emitting blue light.

3. The display panel of claim 2, wherein, The display panel further comprises a third pixel, and the first pixel and the third pixel have different light-emitting colors. The third pixel is electrically connected with a third pixel circuit, and the third pixel circuit has a smaller area of a projection on the plane where the display panel is located than the second pixel circuit.

4. The display panel of claim 3, wherein, In a direction perpendicular to the plane where the display panel is located, the light-emitting layer of the third pixel at least partially overlaps the second pixel circuit.

5. The display panel of claim 3, wherein, The first pixel and the third pixel are quantum dot light-emitting units. The second pixel is an LED light-emitting unit.

6. The display panel of claim 1, wherein, The display panel further comprises a third pixel, and the third pixel is electrically connected with a third pixel circuit, and the third pixel circuit has a smaller area of a projection on the plane where the display panel is located than the second pixel circuit. The display panel comprises a plurality of pixel units, and each pixel unit comprises one first pixel, one second pixel and one third pixel. In a first direction, the first pixel and the third pixel are oppositely arranged, and the second pixel is located between the first pixel and the third pixel. The first direction is parallel to the plane where the display panel is located. In a direction perpendicular to the plane where the display panel is located, the first pixel has a larger area of a projection than the second pixel, and the third pixel has a larger area of a projection than the second pixel.

7. The display panel of claim 6, wherein, In the first direction, the second pixel at least partially overlaps with the first pixel, and the second pixel at least partially overlaps with the third pixel; In the second direction, the second pixel at least partially overlaps with the first pixel, and the second pixel at least partially overlaps with the third pixel; The first direction intersects with the second direction, and the second direction is parallel to the plane where the display panel is located.

8. The display panel of claim 1, wherein, The display panel further comprises a third pixel, and the third pixel is electrically connected with a third pixel circuit, and a projection area of the third pixel circuit on the plane where the display panel is located is smaller than a projection area of the second pixel circuit on the plane where the display panel is located. The display panel comprises a plurality of pixel units, and each pixel unit comprises two first pixels, one second pixel, and two third pixels. Centers of the two first pixels and centers of the two third pixels form a virtual quadrilateral. The second pixel is located in the virtual quadrilateral, and the second pixel covers a geometric center of the virtual quadrilateral.

9. The display panel of claim 8, wherein, A line connecting the centers of the two first pixels forms one side of the virtual quadrilateral. Or, a line connecting the centers of the two first pixels forms one diagonal of the virtual quadrilateral.

10. The display panel of claim 8, wherein, The first pixel circuit comprises a driving module configured to provide a driving current for the first pixel. The first pixel circuit further comprises a first switch module and a second switch module. A first end of the first switch module is electrically connected with an output end of the driving module, and a first end of the second switch module is electrically connected with the output end of the driving module. A second end of the first switch module is connected with a first first pixel, and a second end of the second switch module is connected with a second first pixel.

11. The display panel of claim 6 or 8, wherein, The plurality of pixel units are arranged in an array. In a column direction of the array, the pixel units comprise oppositely arranged first regions and second regions, and the first regions and the second regions have a spacing therebetween. The first regions are provided with the first pixel circuits and the third pixel circuits, and the second regions are provided with the second pixel circuits.

12. The display panel of claim 11, wherein, The display panel further comprises a first gate driving circuit and a second gate driving circuit. The display panel comprises a first side and a second side oppositely arranged in a row direction of the array. The first gate driving circuit is located on the first side and is electrically connected with the second pixel circuit. The second gate driving circuit is located on the second side and is electrically connected with the first pixel circuit and the third pixel circuit, respectively.

13. The display panel of claim 1, wherein, An end of the packaging structure away from the substrate is an arc surface, and the arc surface protrudes in a direction away from the substrate.

14. The display panel of claim 1, wherein, The display panel further comprises a pixel definition layer located on a side of the buffer layer away from the substrate. In a direction perpendicular to the plane where the display panel is located, the pixel definition layer covers the packaging structure, and a material refractive index of the packaging structure is greater than a material refractive index of the pixel definition layer.

15. The display panel of claim 1, wherein, The first pixel comprises an anode layer and a cathode layer located on a side of the anode layer away from the substrate. The display panel further comprises an auxiliary cathode between the anode layer and the substrate, the auxiliary cathode being connected with at least the cathode layer; In a direction perpendicular to a plane in which the display panel lies, a projection of the anode layer partially overlaps a projection of the auxiliary cathode.

16. The display panel of claim 15, wherein, In a direction perpendicular to a plane in which the display panel lies, the cathode layer does not overlap the second pixel.

17. A display device comprising: The display device comprises the display panel of any one of claims 1-16.

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