A signal transmission method and device

Abstract

The application provides a signal transmission method and device, wherein a reference clock signal provided by an external crystal oscillator is spread and multiplied to obtain a first clock signal and a second clock signal, the second clock signal is multiplied to generate a third clock signal, a digital signal to be transmitted is duty cycle modulated based on the first clock signal to obtain a modulated digital signal, a first reverse control signal is generated based on the modulated digital signal, the first reverse control signal is filtered, shaped and amplified to obtain a second reverse control signal, automatic compensation equalization parameter adjustment is performed based on specific training data and the third clock signal, the second reverse control signal is re-timed and sampled to obtain and analyze parallel data, and a feedback signal is transmitted through a main signal channel. In the scheme, a reverse control channel adopting a duty cycle modulation mode is used, so that the purpose of homologous transmission of multiple groups of signals is achieved without the need of designing high requirement clock or external clock source devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal transmission, and in particular to a signal transmission method and device. BACKGROUND

[0002] With the development of vehicle auxiliary driving technology, a vehicle is often equipped with multiple sensors, such as a camera, a radar, etc., and sensor signals need to be transmitted over a long distance before reaching a vehicle-mounted central control.

[0003] In the prior art, in order to ensure the reliability of long-distance signal transmission, a combination link such as FPD-LINK of TI, gigabit multimedia serial link (GMSL) of Maxim, etc. is adopted, in order to achieve the purpose of homologous transmission of multiple groups of signals to reduce the calculation and processing pressure of the vehicle-mounted central control, a reverse control signal of a self-defined coded signal is transmitted by a deserializer, and after the reverse control signal is received by a serializer and the clock is recovered, the other modules are used as reference clock for continuous use, thereby achieving homologous transmission, but this requires a high design requirement for the clock or an external clock source device, resulting in a high application cost. SUMMARY

[0004] Therefore, the embodiments of the present application provide a signal transmission method and device to achieve the purpose of homologous transmission of multiple groups of signals without designing a high requirement clock or external clock source device.

[0005] To achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0006] The first aspect of the embodiments of the present application discloses a signal transmission method applied to a signal transmission device including a serializer and a deserializer, the serializer and the deserializer are connected through a transmission line to form a reverse control channel, and the method comprises:

[0007] The deserializer performs frequency multiplication based on a first reference clock signal provided by an external crystal oscillator source to obtain a first clock signal and a second clock signal;

[0008] The deserializer takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, and performs frequency multiplication processing on the second clock signal to obtain a third clock signal;

[0009] The deserializer performs duty cycle modulation on a digital signal to be sent based on the first clock signal to obtain a modulated digital signal, and the digital signal to be sent is sourced from the deserializer or a vehicle-mounted central control;

[0010] The deserializer generates a first reverse control signal based on the modulated digital signal and sends it to the serializer through the reverse control channel;

[0011] When the serializer receives the first reverse control signal, the first reverse control signal is filtered, shaped, amplified, and a second reverse control signal is obtained;

[0012] When the serializer detects that the second reverse control signal is valid, the second reverse control signal is taken as a reference clock and is re-timed and sampled to obtain parallel data, and a fourth clock signal and a fifth clock signal are generated simultaneously;

[0013] The serializer provides the fourth clock to a previous stage chip, takes the fifth clock signal as a reference clock of a phase-locked loop circuit in the serializer, and sends specific training data to the deserializer immediately after a high-speed clock at the transmitting end of the serializer is generated;

[0014] The deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal;

[0015] The serializer parses the parallel data, and after obtaining the parsing result, sends a feedback signal to the deserializer through a main signal channel, the main signal channel and the reverse control channel share one or two transmission lines, and the main signal is transmitted through the main signal channel.

[0016] Preferably, the deserializer includes a first phase-locked loop circuit and a second phase-locked loop circuit, the first phase-locked loop circuit is connected with the external crystal oscillator, the second phase-locked loop circuit is connected with the first phase-locked loop circuit, the deserializer performs frequency multiplication based on a first reference clock signal provided by the external crystal oscillator to obtain a first clock signal and a second clock signal, including:

[0017] The first phase-locked loop circuit performs frequency spreading and frequency multiplication on the first reference clock signal provided by the external crystal oscillator to a first preset frequency to obtain the first clock signal and the second clock signal;

[0018] The deserializer takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, and performs frequency multiplication on the second clock signal to obtain a third clock signal, including:

[0019] The second phase-locked loop circuit takes the second clock signal as a reference clock, and frequency multiplies the second clock signal to a second preset frequency to obtain the third clock signal.

[0020] Preferably, the deserializer includes a first reverse control unit, the deserializer performs duty cycle modulation on a digital signal to be sent based on the first clock signal to obtain a modulated digital signal, including:

[0021] The first reverse control unit performs duty cycle modulation on the digital signal to be transmitted based on the first clock signal at a modulation ratio X:Y, to obtain a modulated digital signal, wherein X and Y are positive integers and X+Y is greater than 2;

[0022] The frequency of the modulated digital signal is less than or equal to the sum of the frequency of the external crystal oscillator and the modulation ratio.

[0023] The data transmission rate of the main signal is equal to the frequency of the modulated digital signal multiplied by an integer multiple of 10.

[0024] The ratio of the data transmission rate of the main signal to the frequency of the modulated digital signal remains unchanged.

[0025] Preferably, the serializer comprises a third phase-locked loop circuit and a second reverse control unit, the third phase-locked loop circuit and the second reverse control unit are connected, the second reverse control signal is taken as a reference clock and the second reverse control signal is processed by re-timing sampling to obtain parallel data, which comprises:

[0026] The third phase-locked loop circuit takes the second reverse control signal as a second reference clock signal and frequency-multiplies the second reference clock signal to a target frequency to obtain a first fast clock signal.

[0027] The third phase-locked loop circuit generates a second fast clock signal having a phase difference of 180 degrees with the first fast clock, samples the second reverse control signal based on the second fast clock, and converts the sampled second reverse control signal into parallel data, and sends the parallel data to the second reverse control unit.

[0028] Preferably, the serializer comprises a digital unit connected to the second reverse control unit, the serializer parses the parallel data, and after obtaining the parsing result, sends a feedback signal to the deserializer through the main signal channel, which comprises:

[0029] The second reverse control unit parses the parallel data to obtain parsing data and sends the parsing data to the digital unit.

[0030] The digital unit analyzes whether the parsing data is complete, and if so, the digital unit sends a feedback signal to the deserializer through the main signal channel.

[0031] The second aspect of the embodiment of the application discloses a signal transmission device, which comprises a serializer and a deserializer, the serializer and the deserializer are connected through a transmission line, and the deserializer is connected to an external crystal oscillator.

[0032] The deserializer performs frequency multiplication on a reference clock signal provided by the external crystal oscillator to obtain a first clock signal and a second clock signal, takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, performs frequency multiplication on the second clock signal to obtain a third clock signal; performs duty cycle modulation on a digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, the digital signal to be transmitted is sourced from a deserializer or a vehicle-mounted central controller, generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through a reverse control channel, the reverse control channel and the main signal share a transmission line; performs data clock recovery and automatic compensation equalization parameter adjustment based on the third clock signal and specific training data sent by the serializer.

[0033] When the serializer receives the first reverse control signal, the serializer performs filtering, shaping, and amplification on the first reverse control signal to obtain a second reverse control signal, takes the second reverse control signal as a reference clock and performs retiming sampling on the second reverse control signal when the second reverse control signal is detected to be valid to obtain parallel data, simultaneously generates a fourth clock signal and a fifth clock signal, provides the fourth clock to a previous chip for use, takes the fifth clock signal as a reference clock of a phase-locked loop circuit in the serializer, and sends specific training data to the deserializer immediately after generating a high-speed clock at a transmitting end of the serializer; analyzes the parallel data, sends a feedback signal to the deserializer through the main signal channel after obtaining an analysis result, the main signal channel and the reverse control channel share one or two transmission lines, and the main signal is transmitted through the main signal channel.

[0034] Preferably, the deserializer includes a deserializer phase-locked loop and a first reverse control unit, the deserializer phase-locked loop is connected to the first reverse control unit and the external crystal oscillator respectively.

[0035] The deserializer phase-locked loop performs frequency multiplication on a first reference clock signal provided by the external crystal oscillator to obtain a first clock signal and a second clock signal, sends the first clock signal to the first reverse control unit, takes the second clock signal as a reference clock, and performs frequency multiplication on the second clock signal to obtain a third clock signal.

[0036] The first reverse control unit performs duty cycle modulation on a digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through a reverse control channel.

[0037] Preferably, the deserializer comprises a first phase-locked loop circuit, a second phase-locked loop circuit and a first reverse control unit, the first phase-locked loop circuit is connected with the external crystal oscillator, the second phase-locked loop circuit and the first reverse control unit respectively;

[0038] The first phase-locked loop circuit multiplies the first reference clock signal provided by the external crystal oscillator to obtain a first clock signal and a second clock signal, and sends the first clock signal to the first reverse control unit, and the second phase-locked loop circuit takes the second clock signal as a reference clock, multiplies the second clock signal to obtain a third clock signal;

[0039] The first reverse control unit performs duty cycle modulation on the digital signal to be sent based on the first clock signal to obtain a modulated digital signal, generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through a reverse control channel.

[0040] Preferably, the serializer comprises a second reverse control circuit, a serializer phase-locked loop and a second reverse control unit, the second reverse control circuit is connected with the serializer phase-locked loop, and the serializer phase-locked loop is connected with the second reverse control unit;

[0041] The second reverse control circuit performs filtering, shaping and amplifying processing on the first reverse control signal to obtain a second reverse control signal;

[0042] The serializer phase-locked loop takes the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, generates a fourth clock signal and a fifth clock signal based on the second reverse control signal and a known ratio, provides the fourth clock to a previous chip for use, and takes the fifth clock signal as a reference clock of the serializer phase-locked loop;

[0043] The second reverse control unit analyzes the parallel data, and after obtaining the analysis result, sends a feedback signal to the deserializer through the main signal channel.

[0044] Preferably, the serializer comprises a second reverse control circuit, a third phase-locked loop circuit, a fourth phase-locked loop circuit and a second reverse control unit, the second reverse control circuit is connected with the third phase-locked loop circuit, the third phase-locked loop circuit is connected with the fourth phase-locked loop circuit and the second reverse control unit respectively;

[0045] The second reverse control circuit performs filtering, shaping and amplifying processing on the first reverse control signal to obtain a second reverse control signal;

[0046] The third phase-locked loop circuit takes the second reverse control signal as a reference clock and performs retiming sampling processing on the second reverse control signal to obtain parallel data, and simultaneously generates a fourth clock signal and a fifth clock signal, wherein the fourth clock is provided for use by a previous-stage chip, and the fifth clock signal is taken as a reference clock of the fourth phase-locked loop circuit;

[0047] The second reverse control unit analyzes the parallel data, and after obtaining an analysis result, sends a feedback signal to the deserializer through the main signal channel.

[0048] Based on the signal transmission method and device provided in the embodiment of the application, the deserializer performs frequency multiplication on a first reference clock signal provided by an external crystal oscillator to obtain a first clock signal and a second clock signal; the deserializer takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, and performs frequency multiplication processing on the second clock signal to obtain a third clock signal; the deserializer performs duty cycle modulation on a digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, wherein the digital signal to be transmitted is sourced from the deserializer or a vehicle-mounted central control; the deserializer generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through the reverse control channel; when the serializer receives the first reverse control signal, the serializer sends specific training data to the deserializer, and performs filtering, shaping and amplification processing on the first reverse control signal to obtain a second reverse control signal; the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal; when the serializer detects that the second reverse control signal is valid, the serializer performs retiming sampling processing on the second reverse control signal to obtain parallel data, and simultaneously generates a fourth clock signal and a fifth clock signal; the serializer provides the fourth clock for use by a previous-stage chip, and takes the fifth clock signal as a reference clock of a phase-locked loop circuit in the serializer; the serializer analyzes the parallel data, and after obtaining an analysis result, sends a feedback signal to the deserializer through the main signal channel. In this solution, a reverse control channel in a duty cycle modulation mode is adopted, the serializer and the deserializer are connected through a signal transmission line to form the reverse control channel, the deserializer performs duty cycle modulation on a digital signal to generate a reverse control signal and send the reverse control signal to the serializer through the reverse control channel, the serializer sends specific training data to the deserializer after receiving the reverse control signal, the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data, the serializer obtains a clock signal after processing the reverse control signal, and the serializer sends high-speed data to the deserializer based on the clock signal, so that the same-source transmission of multiple groups of signals can be realized without the need for a clock or an external clock source device with high design requirements. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim at the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on the provided drawings.

[0050] Figure 1 A structural diagram of a signal transmission device disclosed in an embodiment of the present application;

[0051] Figure 2 A structural diagram of another signal transmission device disclosed in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of a duty cycle modulated signal disclosed in an embodiment of the present application;

[0053] Figure 4 A flow chart of a signal transmission method disclosed in an embodiment of the present application;

[0054] Figure 5 A flow chart of another signal transmission device disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0056] In the present application, the term “comprising” or “including” or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the sentence “including a…” does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0057] As known from the background, in the existing serializer and deserializer combined link (ADP-LINK), the design requirement for the clock is very high, or an external clock source device needs to be used, resulting in a higher application cost.

[0058] Therefore, the embodiment of the present application discloses a signal transmission method and device, in the present scheme, a duty cycle modulation mode is adopted for the reverse control channel, a serializer and a deserializer are connected through a signal transmission line to form a reverse control channel, the deserializer performs duty cycle modulation on the digital signal from the deserializer or the vehicle-mounted central control, generates a reverse control signal and sends it to the serializer through the reverse control channel, the serializer sends specific training data to the deserializer after receiving the reverse control signal, the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data, the serializer obtains a clock signal after processing the reverse control signal, and the serializer sends high-speed data to the deserializer based on the clock signal, so that the isogenic transmission of multiple groups of signals is realized without the need to design a clock or external clock source device with high requirements.

[0059] As shown in Figure 1 , it is a structure diagram of a signal transmission device disclosed by the embodiment of the present application, which comprises a deserializer 100 and a serializer 200.

[0060] Specifically, the deserializer 100 and the serializer 200 are connected through a signal transmission line to form a reverse control channel, the deserializer 100 is connected with an external crystal oscillator source and a vehicle-mounted central control, and the serializer is connected with a previous-stage chip or a sensor.

[0061] The deserializer 100 is connected with an external crystal oscillator source, and a first reference clock signal provided by the external crystal oscillator source is multiplied to obtain a first clock signal and a second clock signal.

[0062] Preferably, in actual application, the frequency of the first reference clock signal provided by the external crystal oscillator source is selected as 27MHz or 54MHz.

[0063] Preferably, the deserializer 100 performs frequency spreading and frequency multiplication on the reference clock signal provided by the external crystal oscillator source, and the first reference clock signal is multiplied to a first preset frequency with a suitable frequency.

[0064] It should be noted that the frequency spreading of the first reference clock signal makes the entire device have frequency spreading information, which helps to reduce EMI electromagnetic radiation.

[0065] The deserializer 100 takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer 100, and performs frequency multiplication processing on the second clock signal to obtain a third clock signal.

[0066] Preferably, the second clock signal is multiplied to a second preset frequency with a suitable frequency.

[0067] The deserializer 100 performs duty cycle modulation on a digital signal to be sent based on the first clock signal to obtain a modulated digital signal, and the digital signal to be sent is sourced from the deserializer 100 or the vehicle-mounted central control.

[0068] It should be noted that the digital signal to be transmitted can be generated by the deserializer 100.

[0069] The specific implementation process of the duty cycle modulation can be seen in the embodiment shown in Figure 2 The specific implementation process of the duty cycle modulation can be seen in the embodiment shown in

[0070] The deserializer 100 generates a first reverse control signal based on the modulated digital signal and sends it to the serializer 200 through a reverse control channel, which shares one or two transmission lines with the main signal.

[0071] In a specific implementation, the deserializer 100 re-samples the modulated digital signal to generate the first reverse control signal.

[0072] It should be noted that the reverse control channel shares one or two transmission lines with the main signal, which supports full-duplex transmission mode.

[0073] When the serializer 200 receives the first reverse control signal, it sends specific training data to the deserializer 100 and performs filtering, shaping, and amplification processing on the first reverse control signal to obtain a second reverse control signal.

[0074] In a specific implementation, the serializer 200 detects the first reverse control signal after receiving it and only starts sending specific training data to the deserializer 100 when the detection is valid.

[0075] It should be noted that the specific training data is generated based on existing encoding techniques.

[0076] The deserializer 100 performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and a third clock signal.

[0077] It should be noted that the purpose of automatic compensation equalization parameter adjustment is to compensate for the loss of long-distance wire. Specifically, a digital-controlled cyclic scanning mechanism is designed to traverse all parameters in the specific training data, set a reasonable time range, and obtain the bit error rate of the deserializer receiving the specific training data parameters within this time range. If the bit error rate is within a reasonable range, it indicates that the parameter is of good quality.

[0078] When the serializer detects that the second reverse control signal is valid, it uses the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, while generating a fourth clock signal and a fifth clock signal. The serializer 200 provides the fourth clock to the previous chip and uses the fifth clock signal as the reference clock of the phase-locked loop circuit inside the serializer.

[0079] The specific implementation process of the re-timing sampling processing on the second reverse control signal to obtain parallel data can be seen inFigure 2 The embodiment is shown.

[0080] It should be noted that the fourth clock signal is required by the specification of the previous chip; the fifth clock signal is generally restored to an integer multiple of the frequency of the external crystal oscillator source, which is beneficial for the phase-locked loop in the serializer to re-use the restored fifth clock signal after frequency multiplication.

[0081] The serializer 200 parses the parallel data, and after obtaining the parsing result, sends a feedback signal to the deserializer through the main signal channel.

[0082] It should be noted that the main signal channel and the reverse control channel share one or two transmission lines, and the main signal is transmitted through the main signal channel.

[0083] Based on the signal transmission device disclosed in the above embodiment of the application, the signal transmission device comprises a serializer and a deserializer, and the serializer and the deserializer are connected through a signal transmission line to form a reverse control channel. In the present scheme, a reverse control channel adopting a duty cycle modulation mode is used, the serializer and the deserializer are connected through a signal transmission line to form a reverse control channel, the deserializer performs duty cycle modulation on a digital signal from the deserializer or a vehicle-mounted central control, generates a reverse control signal, and sends the reverse control signal to the serializer through the reverse control channel, the serializer sends specific training data to the deserializer after receiving the reverse control signal, the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data, the serializer obtains a clock signal after processing the reverse control signal, and the serializer sends high-speed data to the deserializer based on the clock signal, so that the same-source transmission of multiple groups of signals is realized without the need to design a clock or an external clock source device with high requirements.

[0084] As shown in Figure 2 Another signal transmission device disclosed in the embodiment of the application is shown, which comprises a deserializer 100 and a serializer 200. The deserializer 100 comprises a first phase-locked loop circuit 101, a second phase-locked loop circuit 102, a first reverse control unit 103, a first reverse control circuit 104, a clock recovery unit 105, and a first digital unit 106. The serializer 200 comprises a second reverse control circuit 201, a detection unit 202, a third phase-locked loop circuit 203, a fourth phase-locked loop circuit 204, a second reverse control unit 205, and a second digital unit 206.

[0085] Specifically, the receiving end of the deserializer 100 and the transmitting end of the serializer 200 are connected through a signal transmission line to form a reverse control channel, the first phase-locked loop circuit 101 is connected with an external crystal oscillator source, the second phase-locked loop circuit 102, the first reverse control unit 103 is connected with a vehicle-mounted central control and the first reverse control circuit 104, the second phase-locked loop circuit 102 is connected with the clock recovery unit 105, the clock recovery unit 105 is connected with the receiving end of the deserializer 100 and the first digital unit 106, the first digital unit 106 is connected with the vehicle-mounted central control, the first reverse control circuit 104 is connected with the second reverse control circuit 201 through the reverse control channel, the second reverse control circuit 201 is connected with the detection unit 202 and the third phase-locked loop circuit 203, the detection unit 202 is connected with the third phase-locked loop circuit 203, the third phase-locked loop circuit 203 is connected with a front-end chip, the second reverse control unit 205 and the fourth phase-locked loop circuit, the second reverse control unit 205 is connected with the front-end chip and the second digital unit 206, and the second digital unit 206 and the fourth phase-locked loop circuit 204 are connected with the transmitting end of the serializer 200.

[0086] The first phase-locked loop circuit 101 spreads and multiplies the first reference clock signal provided by the external crystal oscillator source to obtain the first clock signal and the second clock signal, and sends the first clock signal to the first reverse control unit 103 and the first reverse control circuit 104, and sends the second clock signal to the second phase-locked loop circuit 102.

[0087] It should be noted that, in order to make the first reverse control circuit 104 obtain higher serial signal quality, the first clock signal should be sent to the first reverse control circuit 104 first, and then a first clock signal is generated to be sent to the first reverse control unit 103.

[0088] The second phase-locked loop circuit 102 takes the second clock signal as a reference clock, multiplies the second clock signal to a second preset frequency with a suitable frequency to obtain a third clock signal, and sends the third clock signal to the clock recovery unit 105.

[0089] In an embodiment, the first phase-locked loop circuit 101 and the second phase-locked loop circuit 102 are combined into a deserializer phase-locked loop, and the deserializer phase-locked loop is connected with the first reverse control circuit 104, the first reverse control unit 103 and the clock recovery unit 105.

[0090] The phase-locked loop of the deserializer is based on the first reference clock signal provided by the external crystal oscillator to spread the spectrum and multiply the frequency, so as to obtain the first clock signal and the second clock signal, the first clock signal is sent to the first reverse control circuit 104 first, and then a first clock signal is generated and sent to the first reverse control unit 103, and the second clock signal is used as a reference clock, the second clock signal is multiplied to obtain the third clock signal and sent to the clock recovery unit 105.

[0091] The first reverse control unit 103 performs duty cycle modulation on the digital signal to be sent based on the first clock signal, and obtains the modulated digital signal, the digital signal to be sent is derived from the deserializer 100 or the vehicle-mounted central control.

[0092] The modulation ratio of the duty cycle modulation is X:Y, X and Y are positive integers and X+Y is greater than 2, and the embodiment of the application adopts a modulation ratio of 1:3 for illustration.

[0093] The frequency of the modulated digital signal is less than or equal to the ratio of the sum of the modulation ratio to the crystal frequency of the external crystal oscillator.

[0094] Suppose the crystal frequency of the external crystal oscillator is 54MHz, then after duty cycle modulation:

[0095] Fref<=Xtal / M=54 / 4=13.5MHz (1)

[0096] Where Fref is the frequency of the modulated digital signal, Xtal is the crystal frequency of the external crystal oscillator, and M is the sum of the modulation ratio, i.e. M=1+3=4, the value range of M is M>2.

[0097] The data transmission rate of the main signal is equal to the frequency of the modulated digital signal multiplied by an integer multiple of 10, i.e.

[0098] Datarate=Fref*10*N=4.32Gbps (2)

[0099] Where Datarate is the data transmission rate, Fref is 13.5MHz according to formula (1), and N is the ratio of the first clock signal frequency to the transmission rate, here N=32.

[0100] The ratio of the data transmission rate of the main signal to the frequency of the modulated digital signal remains unchanged.

[0101] From formula (2), we have:

[0102] Datarate / Fref=10*N=320 (3)

[0103] It can be understood that the modulated digital signal period is enlarged a times, according to the formula, the frequency is equal to the period of one, then the frequency of the modulated digital signal is reduced to 1 / a of the original, that is, Fref is reduced to 1 / a of the original, and Datarate / Fref remains unchanged according to formula (3), therefore, Datarate is also reduced to 1 / a of the original, which is beneficial to the expansion of the digital signal period by the deserializer 100 to directly change the data transmission rate.

[0104] As Figure 3 shown, it is a schematic diagram of the signal after duty cycle modulation of the embodiment of the application, wherein T represents the period of the modulated digital signal, and idle represents an idle signal. Since the duty cycle modulation is performed in a ratio of 1:3, the modulated digital signal will only appear in three cases of 1000, 1110 and 1100.

[0105] Among them, if 1000 represents 1, then 1110 represents 0, and the other case is that 1000 represents 0, then 1110 represents 1, and 1100 is an idle signal used to balance the DC point drift.

[0106] The first reverse control circuit 104 resamples the modulated digital signal based on the first clock signal, generates a first reverse control signal, and sends it to the second reverse control circuit 201 through the reverse control channel.

[0107] When the second reverse control circuit 201 receives the first reverse control signal, the serializer 200 sends specific training data to the deserializer 100 through the transmitting end, and at the same time, the second reverse control circuit 201 filters, shapes, and amplifies the first reverse control signal to obtain a second reverse control signal and sends it to the detection unit 202 and the third phase-locked loop circuit 203.

[0108] It should be noted that the specific training data is generated based on existing encoding technology.

[0109] The clock recovery unit 105 performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal.

[0110] Among them, the automatic compensation equalization parameter adjustment process please refer to the embodiment shown in Figure 1 , which will not be repeated here.

[0111] The detection unit 202 detects the second reverse control signal after receiving the second reverse control signal, and configures and starts the third phase-locked loop circuit 203 if the detection is valid. The third phase-locked loop circuit 203 takes the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, and at the same time generates a fourth clock signal and a fifth clock signal.

[0112] The re-timing sampling processing is performed by the third phase-locked loop circuit 203, taking the second reverse control signal as a second reference clock signal, and multiplying the second reference clock signal to a target frequency to obtain a first fast clock signal, then generating a second fast clock signal with a phase difference of 180 degrees from the first fast clock, sampling the second reverse control signal based on the second fast clock, and converting the sampled second reverse control signal into parallel data, and sending the parallel data to the second reverse control unit 205.

[0113] The third phase-locked loop circuit 203 sends the fourth clock to the front chip for use, and takes the fifth clock signal as a reference clock of the fourth phase-locked loop circuit 204.

[0114] It should be noted that the fourth clock signal is required by the specification of the front chip, and the fifth clock signal is generally restored to an integer multiple of the frequency of the external crystal oscillator, which is beneficial to the fourth phase-locked loop circuit 204 to re-multiply the restored fifth clock signal for use.

[0115] In an embodiment, the third phase-locked loop circuit 203 and the fourth phase-locked loop circuit 204 are combined into a serializer phase-locked loop, and the serializer phase-locked loop is combined with the detection unit 202, the front chip and the second reverse control unit 205.

[0116] After the detection unit 202 detects that the second reverse control signal is valid, the serializer phase-locked loop is configured and started, and the serializer phase-locked loop takes the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, and generates a fourth clock signal and a fifth clock signal based on the second reverse control signal and a known ratio, and provides the fourth clock to the front chip for use, and takes the fifth clock signal as a reference clock of the serializer phase-locked loop.

[0117] The second reverse control unit 205 analyzes the parallel data to obtain analysis data and sends the analysis data to the second digital unit 206.

[0118] The second digital unit 206 analyzes whether the analysis data is complete, and if so, sends a feedback signal to the receiving end of the deserializer 100 through a main signal channel.

[0119] It should be noted that the main signal channel and the reverse control channel share one or two transmission lines, and the main signal is transmitted through the main signal channel.

[0120] Based on the signal transmission device disclosed in the above embodiment of the present application, in the present scheme, a duty cycle modulation mode is adopted for the reverse control channel, a serializer and a deserializer are connected through a signal transmission line to form the reverse control channel, the deserializer performs duty cycle modulation on the digital signal from the deserializer or the vehicle-mounted central control, generates a reverse control signal and sends it to the second reverse control circuit of the serializer through the reverse control channel, and sends specific training data to the deserializer, the clock recovery unit in the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data, the third phase-locked loop circuit in the serializer processes the reverse control signal to obtain a clock signal, and the serializer sends high-speed data to the deserializer based on the clock signal, so that the isogenic transmission of multiple groups of signals is realized without the need to design a clock or external clock source device with high requirements.

[0121] As shown in Figure 4 the flowchart of the signal transmission method disclosed in the embodiment of the present application, the method is applied to a signal transmission device including a serializer and a deserializer, wherein the serializer and the deserializer are connected through one or more signal transmission lines, and the signal transmission method mainly includes:

[0122] Step S401: The deserializer performs frequency multiplication based on a first reference clock signal provided by an external crystal oscillator to obtain a first clock signal and a second clock signal;

[0123] Preferably, in actual application, the frequency of the reference clock signal provided by the external crystal oscillator is selected as 27MHz or 54MHz.

[0124] Preferably, the deserializer 100 performs frequency spreading and frequency multiplication based on the reference clock signal provided by the external crystal oscillator, and the first reference clock signal is multiplied to a first preset frequency with a suitable frequency.

[0125] Step S402: The deserializer takes the second clock signal as the reference clock of the phase-locked loop circuit in the deserializer, and performs frequency multiplication processing on the second clock signal to obtain a third clock signal;

[0126] In step S402, the second clock signal is multiplied by an integer to a second preset frequency with a suitable frequency to obtain the third clock signal.

[0127] Step S403: The deserializer performs duty cycle modulation on the digital signal to be sent based on the first clock signal to obtain a modulated digital signal, and the digital signal to be sent is sourced from the deserializer or the vehicle-mounted central control;

[0128] The specific implementation process of step S403 is described in detail in the embodiment shown in Figure 2 , please refer to

[0129] Step S404: The deserializer generates the first reverse control signal based on the modulated digital signal and sends it to the serializer through the reverse control channel.

[0130] In step S404, after sampling the modulated digital signal, the first reverse control signal is generated.

[0131] Step S405: When the serializer receives the first reverse control signal, it is filtered, shaped and amplified to obtain the second reverse control signal.

[0132] Step S406: When the serializer detects that the second reverse control signal is valid, it uses the second reverse control signal as the reference clock and re-timing samples the second reverse control signal to obtain parallel data, while generating the fourth and fifth clock signals.

[0133] The detailed implementation process of step S406 is described in detail in the embodiment shown in Figure 2 Please refer to

[0134] Step S407: The serializer provides the fourth clock to the previous chip, uses the fifth clock signal as the reference clock of the phase-locked loop circuit inside the serializer, and sends specific training data to the deserializer immediately after the high-speed clock at the transmitter end of the serializer is generated.

[0135] In step S407, the specific training data is generated based on existing encoding techniques.

[0136] It should be noted that the fourth clock signal is required by the specification of the previous chip; generally, the fifth clock signal is restored to an integer multiple of the frequency of the external crystal oscillator, which is beneficial to the phase-locked loop inside the serializer to re-multiply the restored fifth clock signal to generate a high-speed clock for the transmitter end of the serializer.

[0137] Step S408: The deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal.

[0138] During the execution of step S408, the deserializer can notify the serializer to stop sending specific training data through the reverse control channel according to its own state.

[0139] It should be noted that the specific implementation of automatic compensation equalization parameter adjustment is to design a digital control loop scanning mechanism, traverse all parameters in the specific training data, set a reasonable time range, and obtain the bit error rate of the deserializer receiving the specific training data parameters in this time range. If the bit error rate is within a reasonable range, it indicates that the parameter is of good quality. The purpose of automatic compensation equalization parameter adjustment is to compensate for the loss of long-distance wire.

[0140] Step S409: The serializer parses the parallel data and, after obtaining the parsing result, sends a feedback signal to the deserializer through the main signal channel.

[0141] In step S409, the reverse control channel and the main signal channel share one or two transmission lines. The main signal channel is used to transmit the main signal and supports full-duplex transmission mode.

[0142] During step S409, the serializer parses the parallel data. After obtaining the parsing result, it stops sending specific training data and switches back to the normal data path. At the same time, it sends a feedback signal to the deserializer through the main signal channel. After that, it will continue to send normal data and necessary feedback signals through the main signal channel.

[0143] It should be noted that after step S409, the high-speed signal transmission channel, namely the main signal channel mentioned above, is established, which can carry out normal signal transmission and send necessary feedback signals at the same time.

[0144] Based on the signal transmission method disclosed in the above embodiments of the present invention, this solution employs a reverse control channel with duty cycle modulation. The serializer and deserializer are connected via a signal transmission line to form the reverse control channel. The first reverse control unit in the deserializer performs duty cycle modulation on the digital signal from the deserializer or the vehicle central control unit, generates a reverse control signal, and sends it to the serializer through the reverse control channel. The serializer processes the reverse control signal to obtain a clock signal and sends high-speed data to the deserializer based on the clock signal. Thus, multiple sets of signals can be transmitted from the same source without requiring a clock or external clock source device with high design requirements.

[0145] and Figure 2 Corresponding to the signal transmission device shown, such as Figure 5 The diagram shows a flowchart of another signal transmission method disclosed in an embodiment of the present invention. This signal transmission method mainly includes the following steps:

[0146] Step S501: The first phase-locked loop circuit performs frequency spread-multiplication and frequency multiplication based on the first reference clock signal provided by the external crystal oscillator to obtain the first clock signal and the second clock signal.

[0147] In the specific implementation step S501, the first clock signal is first sent to the first inverting control circuit, and then a first clock signal is generated and sent to the first inverting control unit.

[0148] Step S502: The second phase-locked loop circuit uses the second clock signal as a reference clock, multiplies the second clock signal to the second preset frequency to obtain the third clock signal, and sends the third clock signal to the clock recovery unit.

[0149] Step S503: The first reverse control unit performs duty cycle modulation on the digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, wherein the digital signal to be transmitted is from the deserializer or the vehicle-mounted central control.

[0150] The process of duty cycle modulation is shown in the embodiment of FIG. 8. Figure 2

[0151] Step S504: The first reverse control circuit generates the first reverse control signal from the modulated digital signal and sends the first reverse control signal to the second reverse control circuit through the reverse control channel.

[0152] In step S504, the first reverse control circuit generates the first reverse control signal by sampling the modulated digital signal based on the first clock signal.

[0153] Step S505: When the second reverse control circuit receives the first reverse control signal, the second reverse control circuit performs filtering, shaping and amplifying processing on the first reverse control signal to obtain the second reverse control signal and sends the second reverse control signal to the detection unit and the third phase-locked loop circuit.

[0154] In the implementation of step S505, the clock recovery unit obtains the specific training data through the receiving end of the deserializer.

[0155] Step S506: After the detection unit detects the validity of the second reverse control signal, the third phase-locked loop circuit is configured and started, and the third phase-locked loop circuit performs re-timing sampling processing on the second reverse control signal to obtain the parallel data and generates the fourth clock signal and the fifth clock signal.

[0156] The process of re-timing sampling processing is shown in the embodiment of FIG. 9. Figure 2

[0157] Step S507: The third phase-locked loop circuit sends the fourth clock to the previous chip for use, uses the fifth clock signal as the reference clock of the fourth phase-locked loop circuit, and immediately sends the specific training data from the transmitter of the serializer to the deserializer after frequency multiplication of the fifth clock signal to generate a high-speed clock.

[0158] It should be noted that the fourth clock signal is required by the specification of the previous chip, and the fifth clock signal is generally restored to an integer multiple of the frequency of the external crystal oscillator, which is beneficial to the fourth phase-locked loop circuit to re-multiply the restored fifth clock signal for use.

[0159] It should be further noted that the specific training data is generated based on the existing encoding technology.

[0160] ​​Step S508: The clock recovery unit performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal, and informs the serializer to stop sending the specific training data through the reverse control channel according to the state of the deserializer itself.

[0161] The automatic compensation equalization parameter adjustment process and purpose are described in the above embodiment and will not be repeated here. Figure 1

[0162] Step S509: The second reverse control unit analyzes the parallel data to obtain analysis data and sends the analysis data to the second digital unit.

[0163] Step S510: Stop sending the specific training data and switch back to the normal data path, and the second digital unit analyzes whether the analysis data is complete, and if so, sends a feedback signal to the receiving end of the deserializer through the main signal channel, and also sends a feedback signal to the deserializer through the main signal channel. Thereafter, normal data and necessary feedback signals will be sent through the main signal channel.

[0164] In step S510, the reverse control channel and the main signal channel share one or two transmission lines, and the main signal channel is used to transmit main signals and supports full-duplex transmission mode.

[0165] Based on the signal transmission method disclosed in the above embodiment of the present application, in the present scheme, a reverse control channel using a duty cycle modulation method is adopted, the serializer and the deserializer are connected through a signal transmission line to form the reverse control channel, the deserializer duty cycle modulates the digital signal from the deserializer or the vehicle-mounted central control to generate a reverse control signal and send the reverse control signal to the second reverse control circuit of the serializer through the reverse control channel, and the deserializer sends specific training data to the deserializer. The clock recovery unit in the deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data, the third phase-locked loop circuit in the serializer processes the reverse control signal to obtain a clock signal, and the serializer sends high-speed data to the deserializer based on the clock signal, thereby realizing the same-source transmission of multiple groups of signals without the need to design a clock or external clock source device with high requirements.

[0166] ​The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0167] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0168] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A signal transmission method, characterized by, The application is applied to a signal transmission device including a serializer and a deserializer, the serializer and the deserializer are connected to form a reverse control channel through a transmission line, and the method comprises the following steps: The deserializer performs frequency multiplication on a first reference clock signal provided by an external crystal oscillator to obtain a first clock signal and a second clock signal; The deserializer takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, and performs frequency multiplication on the second clock signal to obtain a third clock signal; The deserializer performs duty cycle modulation on a digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, and the digital signal to be transmitted is derived from the deserializer or a vehicle-mounted central control; The deserializer generates a first reverse control signal based on the modulated digital signal and transmits the first reverse control signal to the serializer through the reverse control channel; When the serializer receives the first reverse control signal, the first reverse control signal is filtered, shaped, amplified, and processed to obtain a second reverse control signal; When the deserializer detects that the second reverse control signal is valid, the deserializer takes the second reverse control signal as a reference clock and performs retiming sampling on the second reverse control signal to obtain parallel data, and simultaneously generates a fourth clock signal and a fifth clock signal; The deserializer takes the fourth clock as a reference clock of a phase-locked loop circuit in the deserializer, and immediately sends specific training data to the deserializer after the high-speed clock at the transmitter end of the serializer is generated; The deserializer performs data clock recovery and automatic compensation equalization parameter adjustment based on the specific training data and the third clock signal; The serializer analyzes the parallel data, and after obtaining the analysis result, sends a feedback signal to the deserializer through a main signal channel, and the main signal channel and the reverse control channel share one or two transmission lines, and the main signal is transmitted through the main signal channel.

2. The method of claim 1, wherein, The deserializer includes a first phase-locked loop circuit and a second phase-locked loop circuit, the first phase-locked loop circuit is connected with the external crystal oscillator, the second phase-locked loop circuit is connected with the first phase-locked loop circuit, and the deserializer performs frequency multiplication on a first reference clock signal provided by an external crystal oscillator to obtain a first clock signal and a second clock signal, which comprises: The first phase-locked loop circuit performs frequency spreading processing on the first reference clock signal provided by the external crystal oscillator and frequency multiplication to a first preset frequency by an integer multiple to obtain a first clock signal and a second clock signal; The deserializer takes the second clock signal as a reference clock of a phase-locked loop circuit in the deserializer, and performs frequency multiplication on the second clock signal to obtain a third clock signal, which comprises: The second phase-locked loop circuit takes the second clock signal as a reference clock, and frequency multiplies the second clock signal to a second preset frequency to obtain a third clock signal.

3. The method of claim 1, wherein, The deserializer includes a first reverse control unit, and the deserializer performs duty cycle modulation on a digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, which comprises: The first reverse control unit duty-cycle modulates the digital signal to be transmitted based on the first clock signal at a modulation ratio X:Y, to obtain a modulated digital signal, X and Y are positive integers and X+Y is greater than 2; Wherein, the frequency of the modulated digital signal is less than or equal to the sum of the frequency of the external crystal oscillator and the modulation ratio; The data transmission rate of the main signal is equal to the frequency of the modulated digital signal multiplied by an integer multiple of 10; The ratio of the data transmission rate of the main signal to the frequency of the modulated digital signal remains unchanged.

4. The method according to any one of claims 1 to 3, characterized in that, The serializer includes a third phase-locked loop circuit and a second reverse control unit, the third phase-locked loop circuit and the second reverse control unit are connected, the second reverse control signal is taken as the reference clock and the second reverse control signal is re-sampled to obtain parallel data, including: The third phase-locked loop circuit takes the second reverse control signal as a second reference clock signal, and frequency-multiplies the second reference clock signal to a target frequency to obtain a first fast clock signal; The third phase-locked loop circuit generates a second fast clock with a phase difference of 180 degrees from the first fast clock, samples the second reverse control signal based on the second fast clock, and converts the sampled second reverse control signal into parallel data, and sends the parallel data to the second reverse control unit.

5. The method of claim 4, wherein, The serializer includes a digital unit connected to the second reverse control unit, and the serializer analyzes the parallel data, and after obtaining the analysis result, sends a feedback signal to the deserializer through the main signal channel, including: The second reverse control unit analyzes the parallel data to obtain analysis data and sends it to the digital unit; The digital unit analyzes whether the analysis data is complete, and if so, the digital unit sends a feedback signal to the deserializer through the main signal channel.

6. A signal transmission device, characterized by comprising: The device includes a serializer and a deserializer connected through a transmission line, and the deserializer is connected to an external crystal oscillator; The deserializer frequency-multiplies the reference clock signal provided by the external crystal oscillator to obtain a first clock signal and a second clock signal, takes the second clock signal as the reference clock of the phase-locked loop circuit in the deserializer, and frequency-multiplies the second clock signal to obtain a third clock signal; duty-cycle modulates the digital signal to be transmitted based on the first clock signal to obtain a modulated digital signal, the digital signal to be transmitted is derived from the deserializer or the vehicle-mounted central control, generates a first reverse control signal based on the modulated digital signal, and sends it to the serializer through a reverse control channel; data clock recovery and automatic compensation equalization parameter adjustment are performed based on the specific training data sent by the serializer and the third clock signal; The serializer receives the first reverse control signal, performs filtering, shaping, amplifying processing on the first reverse control signal to obtain a second reverse control signal, detects that the second reverse control signal is valid, takes the second reverse control signal as a reference clock, and performs retiming sampling processing on the second reverse control signal to obtain parallel data, and simultaneously generates a fourth clock signal and a fifth clock signal, provides the fourth clock to a previous stage chip for use, takes the fifth clock signal as a reference clock of a phase-locked loop circuit in the serializer, and immediately sends specific training data to the deserializer after a high-speed clock at the transmitting end of the serializer is generated; the parallel data is parsed, and after the parsed result is obtained, a feedback signal is sent to the deserializer through a main signal channel, and the main signal channel and the reverse control channel share one or two transmission lines.

7. The apparatus of claim 6, wherein, The deserializer includes a deserializer phase-locked loop and a first reverse control unit, and the deserializer phase-locked loop is connected with the first reverse control unit and the external crystal oscillator source respectively. The deserializer phase-locked loop performs frequency multiplication on a first reference clock signal provided by the external crystal oscillator source to obtain a first clock signal and a second clock signal, sends the first clock signal to the first reverse control unit, takes the second clock signal as a reference clock, performs frequency multiplication processing on the second clock signal to obtain a third clock signal. The first reverse control unit performs duty cycle modulation on a digital signal to be sent based on the first clock signal to obtain a modulated digital signal, generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through a reverse control channel.

8. The apparatus of claim 6, wherein, The deserializer includes a first phase-locked loop circuit, a second phase-locked loop circuit, and a first reverse control unit, and the first phase-locked loop circuit is connected with the external crystal oscillator source, the second phase-locked loop circuit, and the first reverse control unit respectively. The first phase-locked loop circuit performs frequency multiplication on a first reference clock signal provided by the external crystal oscillator source to obtain a first clock signal and a second clock signal, sends the first clock signal to the first reverse control unit, and the second phase-locked loop circuit takes the second clock signal as a reference clock, performs frequency multiplication processing on the second clock signal to obtain a third clock signal. The first reverse control unit performs duty cycle modulation on a digital signal to be sent based on the first clock signal to obtain a modulated digital signal, generates a first reverse control signal based on the modulated digital signal, and sends the first reverse control signal to the serializer through a reverse control channel.

9. The apparatus of any one of claims 6 to 8, wherein, The serializer includes a second reverse control circuit, a serializer phase-locked loop, and a second reverse control unit, the second reverse control circuit is connected with the serializer phase-locked loop, and the serializer phase-locked loop is connected with the second reverse control unit. The second reverse control circuit performs filtering, shaping, and amplifying processing on the first reverse control signal to obtain a second reverse control signal. The serializer phase-locked loop takes the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, and generates a fourth clock signal and a fifth clock signal based on the second reverse control signal and a known ratio, provides the fourth clock to a previous stage chip for use, and takes the fifth clock signal as a reference clock of the serializer phase-locked loop; The second reverse control unit analyzes the parallel data, and after obtaining an analysis result, sends a feedback signal to the deserializer through the main signal channel.

10. The apparatus of any one of claims 6 to 8, wherein, The serializer comprises a second reverse control circuit, a third phase-locked loop circuit, a fourth phase-locked loop circuit and a second reverse control unit, the second reverse control circuit is connected to the third phase-locked loop circuit, the third phase-locked loop circuit is connected to the fourth phase-locked loop circuit and the second reverse control unit respectively; The second reverse control circuit performs filtering, shaping and amplifying processing on the first reverse control signal to obtain a second reverse control signal; The third phase-locked loop circuit takes the second reverse control signal as a reference clock and performs re-timing sampling processing on the second reverse control signal to obtain parallel data, and generates a fourth clock signal and a fifth clock signal, provides the fourth clock to a previous stage chip for use, and takes the fifth clock signal as a reference clock of the fourth phase-locked loop circuit; The second reverse control unit analyzes the parallel data, and after obtaining an analysis result, sends a feedback signal to the deserializer through the main signal channel.

Images