A software fault tolerance and recovery method, device, equipment and storage medium

Abstract

The present application discloses a software fault tolerance recovery method, apparatus, device, and storage medium, which are applied to a system-on-chip connected to an EMMC chip. The method includes: when the EMMC chip is in a working state, if a target access request is obtained, determining whether a historical access request has been completed; if the historical access request has not been completed, saving the content of the EMMC chip accessed in the execution of the historical access request; after completing saving the content of the EMMC chip accessed in the historical access request, restarting the EMMC chip, and executing the historical access request based on the saved content of the EMMC chip accessed in the historical access request; if the historical access request has been completed, executing the target access request to access the EMMC chip. Therefore, by adopting the above method of the present application, when the system-on-chip accesses the EMMC chip with an error, the EMMC chip is restarted for software fault tolerance recovery to keep the system-on-chip working normally, improving the security of the system-on-chip operation.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and more particularly, to a software fault tolerance recovery method, apparatus, device, and storage medium. Background Art

[0002] With the intelligence of automobiles, whether in the field of vehicle control, in-vehicle entertainment, or in the field of vehicle autonomous driving, a large-capacity and high-speed storage system is required to support vehicle intelligence. Currently, the EMMC chip as a storage system for memories has been very common. However, due to the inherent defects of the EMMC storage system, the system connected with the EMMC chip has a problem of low security. Summary of the Invention

[0003] This application proposes a software fault tolerance recovery method, apparatus, device, and storage medium to improve the above problems.

[0004] In a first aspect, an embodiment of this application provides a software fault tolerance recovery method, which is applied to a system-on-chip connected with an EMMC chip. The method includes: when the EMMC chip is in a working state, if a target access request is obtained, determining whether a historical access request has been executed completely, where the historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-on-chip to access the EMMC chip; if the historical access request has not been executed completely, saving the content of the EMMC chip accessed in the execution of the historical access request; after completing saving the content of the EMMC chip accessed in the historical access request, restarting the EMMC chip, and executing the historical access request based on the saved content of the EMMC chip accessed in the historical access request; if the historical access request has been executed completely, executing the target access request to access the EMMC chip.

[0005] Second aspect, an embodiment of the present application further provides a software fault tolerance recovery device, which is applied to a system-on-chip connected to an EMMC chip. The device includes: a target request acquisition unit, an access content storage unit, a fault tolerance recovery unit, and a target request execution unit. Among them, the target request acquisition unit is configured to, when the EMMC chip is in a working state, if a target access request is acquired, determine whether a historical access request has been completed. The historical access request is an access request acquired before the target access request is acquired, and the target access request is used to enable the system-on-chip to access the EMMC chip; the access content storage unit is configured to, if the historical access request has not been completed, save the content of the EMMC chip accessed in the historical access request; the fault tolerance recovery unit is configured to, after completing saving the content of the EMMC chip accessed in the historical access request, restart the EMMC chip, and execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request; the target request execution unit is configured to, if the historical access request has been completed, execute the target access request to access the EMMC chip.

[0006] In one embodiment, the fault tolerance recovery unit is further configured to, after saving the content of the EMMC chip accessed in the historical access request, turn off the power of the EMMC chip for a preset time period and then restart the EMMC chip; after the EMMC chip is started up, execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request.

[0007] In one embodiment, the access content storage unit is further configured to obtain the error type generated when the historical access request has not been completed; create a fault tolerance recovery flag based on the error type; if the historical access request has been completed, determine whether there is a fault tolerance recovery flag; if there is a fault tolerance recovery flag, create a fault tolerance recovery success flag, and obtain a target log according to the fault tolerance recovery flag and the fault tolerance recovery success flag.

[0008] In one embodiment, the access content storage unit is further configured to, after obtaining the target log, clear the fault tolerance recovery flag and the fault tolerance recovery success flag.

[0009] In one embodiment, the fault tolerance recovery unit is further configured to, based on the content of the EMMC chip accessed in the saved historical access request, control the controller in the EMMC chip to send the access address and the access data size corresponding to the historical access request to the memory in the EMMC chip, so that the memory writes the data sent by the system-on-chip into the memory based on the access address and the access data size, or reads the data from the memory based on the access address and the access data size and sends it to the system-on-chip.

[0010] In one embodiment, the target request acquisition unit is further configured to, if a target access request is acquired, parse the target access request to obtain target parsing data of the target access request, where the target parsing data includes the address and data size for reading / writing the EMMC chip in the target access request; the target request execution unit is further configured to, if the execution of the historical access request is completed, control the controller of the EMMC chip to send a target command including the target parsing data to the memory in the EMMC chip, so that the memory responds to the target command to obtain data corresponding to the address and data size for reading the EMMC chip in the target access request and send the data to the system-on-chip, or write the data sent by the system-on-chip to the storage location corresponding to the address and data size for writing the EMMC chip in the target access request in the memory.

[0011] In one embodiment, before the target request acquisition unit executes the operation of determining whether the historical access request has been completed if a target access request is acquired, when it is detected based on a preset access process that a target access request enters the access request queue, the target request acquisition unit is further configured to acquire the target access request.

[0012] In one embodiment, if the execution of the historical access request is not completed, the target request acquisition unit is further configured to block the preset access process, so that the access request queue no longer receives new access requests.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, including: one or more processors, a memory, and one or more application programs. Among them, one or more application programs are stored in the memory and are configured to be executed by one or more processors, and one or more programs are configured to execute to implement the method described in the first aspect above.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which program code is stored, and the program code can be called by a processor to execute the method described in the first aspect above.

[0015] The technical solution provided by this application is applied to a system-on-chip connected to an EMMC chip. When the EMMC chip is in the working state, if a target access request is obtained, it is determined whether the historical access request has been completed. The historical access request is an access request obtained before the target access request, and the target access request is used to enable the system-on-chip to access the EMMC chip. If the historical access request has not been completed, the content of the EMMC chip accessed in the historical access request is saved. After saving the content of the EMMC chip accessed in the historical access request, the EMMC chip is restarted, and the historical access request is executed based on the saved content of the EMMC chip accessed in the historical access request. If the historical access request has been completed, the target access request is executed to access the EMMC chip. Therefore, by adopting the above method of this application, after an error occurs in the system-on-chip when reading / writing the EMMC chip, the EMMC chip is immediately restarted for software fault tolerance recovery operation, which improves the working safety of the system-on-chip. There is no need to restart the system-on-chip, making the user unaware of the error when the system-on-chip reads / writes the EMMC chip, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 FIG. shows a flowchart of a software fault tolerance recovery method provided by an embodiment of this application;

[0018] Figure 2 FIG. shows a flowchart of a software fault tolerance recovery method provided by another embodiment of this application;

[0019] Figure 3 FIG. shows a flowchart of a software fault tolerance recovery method provided by another embodiment of this application;

[0020] Figure 4 FIG. shows a working flowchart of a software fault tolerance recovery device provided by an embodiment of this application;

[0021] Figure 5 FIG. shows a structural block diagram of an electronic device provided by an embodiment of this application;

[0022] Figure 6 FIG. shows a structural block diagram of a computer storage medium provided by an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To enable those skilled in the art to better understand the solution of this application, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the protection scope of this application.

[0024] EMMC (Embedded Multi Media Card) is an embedded memory standard specification established by the MMC Association, mainly for products such as mobile phones or tablet computers. An EMMC integrates a controller in the package, provides a standard interface and manages the flash memory; the EMMC chip has an MMC (Multi Media Card) interface, a flash memory device and a controller, and is packaged in a small BGA; the interface speed of the EMMC chip is up to 400 MBytes per second, and its interface voltage can be 1.8V or 3.3V; the EMMC chip has fast and upgradable performance.

[0025] With the intelligence of automobiles, vehicle storage systems generally begin to use EMMC chips as memories. However, in the related art, in a storage system using an EMMC chip as a memory, the EMMC chip uses 8 data lines for parallel transmission. Once the clock frequency increases, the interference becomes larger and the signal integrity cannot be guaranteed; at the same time, during vehicle driving, due to the influence of temperature and static electricity, the EMMC chip may experience read / write timeouts or CRC (Cyclic Redundancy Check) errors at any time; furthermore, the internal software and hardware systems of the EMMC chip are also very complex. As the EMMC chip, as a storage unit, ages and there are defects in the controller of the EMMC chip, the EMMC storage system has some inherent defects, which are likely to cause system crashes, black screens, file system damage, etc., and further lead to low security in the operation of the system-on-chip connected to the EMMC chip. Therefore, due to the inherent defects of the EMMC storage system, there is a problem of low security in the operation of the system-on-chip connected to the EMMC chip.

[0026] To alleviate the above problems, the inventors of the present application proposed a software fault-tolerant recovery method, apparatus, device, and storage medium provided in an embodiment of the present application, which is applied to a system-on-chip, and the system-on-chip is connected to an EMMC chip. The method includes: when the EMMC chip is in a working state, if a target access request is obtained, determining whether a historical access request has been completed. The historical access request is an access request obtained before the target access request is obtained, and the target access request is used to cause the system-on-chip to access the EMMC chip; if the historical access request has not been completed, saving the content of the EMMC chip accessed during the execution of the historical access request; after completing the saving of the content of the EMMC chip accessed during the historical access request, restarting the EMMC chip, and executing the historical access request based on the saved content of the EMMC chip accessed during the historical access request; if the historical access request has been completed, executing the target access request to access the EMMC chip. Therefore, by using the above method of the present application, after an error occurs when the system-on-chip reads / writes the EMMC chip, the EMMC chip is immediately restarted for software fault-tolerant recovery operations, improving the security of the system-on-chip during operation.

[0027] The following will specifically describe the embodiments of the present application with reference to the accompanying drawings.

[0028] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a software fault-tolerant recovery method shown in an embodiment of the present application. This method can be applied to a system-on-chip, and the system-on-chip is connected to an EMMC chip. The system-on-chip can be applied to terminals such as in-vehicle terminals, robots, computers, smartphones, etc. to implement this solution, and no specific limitation is made here. Referring to Figure 1 as shown, the method at least includes steps S110 to S140.

[0029] Step S110: When the EMMC chip is in a working state, if a target access request is obtained, determine whether a historical access request has been completed. The historical access request is an access request obtained before the target access request is obtained, and the target access request is used to cause the system-on-chip to access the EMMC chip.

[0030] In an embodiment of the present application, there is a system-on-chip (SOC) connected to an EMMC chip. Here, the system-on-chip can be a product, an integrated circuit with a dedicated target, which contains a complete system and all the content of the embedded software. The composition of the system-on-chip can include a system-on-chip control logic module, a microprocessor / microcontroller CPU core module, a digital signal processor DSP module, an embedded memory module, an interface module for communication with the outside, an analog front-end module containing ADC / DAC, a power supply and power consumption management module, etc.; for a wireless SOC, it can also include a radio frequency front-end module, user-defined logic (which can be implemented by FPGA or ASIC), and a microelectromechanical module. More importantly, a SOC chip is embedded with a basic software (implementing a disk operating system or other application software) module or a loadable user software, etc.

[0031] As an implementation manner, when the EMMC chip is in the working state, it can be when the system-on-chip starts up. The system-on-chip powers on the EMMC chip connected to it, initializes the EMMC chip, and initializes the block device through the driver program of the EMMC chip in the embedded software. After that, the EMMC chip is in the powered-on state and the system-on-chip can read data from the EMMC chip or write data into the EMMC chip. Here, the block device is a type of i / o device that stores information in fixed-size blocks, and each block has its own address. A certain length of data can be read from any position of the device (such as a hard disk, a USB flash drive, an SD card, etc.).

[0032] Specifically, the system-on-chip powers on the EMMC chip connected to it and identifies the EMMC chip through the EMMC driver program. The system-on-chip can read the register values and status of the EMMC chip through the EMMC driver program to initialize the EMMC chip. At the same time, the system-on-chip initializes the block device through the EMMC driver program, that is, creates a block device for the system-on-chip to read or write the EMMC chip, preparing for the system-on-chip to read data from the EMMC chip or write data into the EMMC chip.

[0033] As another implementation manner, when the EMMC chip is in the working state, it can be after the EMMC chip is powered on and off multiple times, and the EMMC chip is in the powered-on state and the system-on-chip can read data from the EMMC chip or write data into the EMMC chip.

[0034] It should be understood that when the EMMC chip is in the working state, that is, the EMMC chip is in the powered-on state and can be read or written with data, that is, the EMMC chip can be accessed by the system-on-chip.

[0035] In some embodiments, when the EMMC chip is in the working state, before determining whether the historical access request has been completed after obtaining a target access request, when a target access request enters the access request queue detected based on a preset access process, the target access request is obtained; if the historical access request has not been completed, the preset access process is blocked so that the access request queue no longer receives new access requests.

[0036] In the embodiments of the present application, when the system-on-chip detects that a target access request enters the access request queue based on a preset access process, the target access request is obtained. Among them, the system-on-chip includes a preset access process for specifically accessing the EMMC chip. This preset access process maintains an access request queue and continuously detects whether an access request for accessing the EMMC chip enters the access request queue; if the preset access process detects that a target access request for the system-on-chip to access the EMMC chip enters the access request queue, the target access request is obtained.

[0037] Specifically, when the EMMC chip is in the working state, when a target access request enters the access request queue detected based on a preset access process, the target access request is obtained, and it is determined whether the historical access request has been completed. If the historical access request has not been completed, the preset access process is blocked so that the access request queue no longer receives new access requests.

[0038] That is to say, after the preset access process detects that a target access request enters the access request queue, it determines whether the historical access request has been completed. If not, the preset access process enters the sleep waiting state so that the access request queue no longer receives new access requests; otherwise, the target access request is executed so that the system-on-chip writes data to the EMMC chip or reads data from the EMMC chip.

[0039] It should be understood that the system-on-chip detects whether there is an error in accessing the EMMC chip (read / write operation error) through a dedicated preset access process. After discovering the error, the access request queue no longer receives new access requests, which improves the access (read / write operation) rate of the system-on-chip to the EMMC chip.

[0040] Among them, determining whether the historical access request has been executed can be that the system-on-chip accesses the EMMC chip according to the historical access request, and the historical access request includes a callback function; if the historical access request has not been executed, the system-on-chip calls the callback function to block the preset access process (i.e., enter the sleep waiting state) to wait for the historical access request to be executed, and then execute the target access request and enable the access request queue to receive a new access request; if the historical access request has been executed, the system-on-chip calls the callback function to enable the preset access process to continue to detect whether a new target access request has entered the access request queue, and the system-on-chip executes the target access request to write data to the EMMC chip or read data from the EMMC chip by the system-on-chip.

[0041] It should be understood that in the embodiments of the present application, the system-on-chip accesses the EMMC chip one by one, that is, after the previous access request enables the system-on-chip to complete the read / write data operation on the EMMC chip, the next access request for the system-on-chip to perform the read / write data operation on the EMMC chip is executed.

[0042] Step S120: If the historical access request has not been executed, save the content of the EMMC chip accessed in the historical access request.

[0043] Optionally, the historical access request not being executed can be that the system-on-chip fails to read / write data to the EMMC chip. Specifically, the system-on-chip fails to read / write data to the EMMC chip can be that the system-on-chip times out when reading / writing data to the EMMC chip; it can be a CRC (Cyclic Redundancy Check) error that occurs during data transmission or storage when the system-on-chip reads / writes data to the EMMC chip; it can be an address error when the system-on-chip reads data from the EMMC chip; it can be an address error when the system-on-chip writes data to the EMMC chip; it can be a data size error when the system-on-chip reads data from the EMMC chip; it can be a data size error when the system-on-chip writes data to the EMMC chip, etc., which are not limited here.

[0044] In some embodiments, if the historical access request has not been fully executed, saving the content of the EMMC chip accessed during the execution of the historical access request may be to save the content of the EMMC chip accessed in the historical access request in a data structure initialized by the system chip according to the historical access request. Among them, the saved content of the EMMC chip accessed during the execution of the historical access request may include the address where the historical access request causes the system-level chip to read data from the EMMC chip, the address where the system-level chip writes data to the EMMC chip, and the size of the data that the historical access request causes the system-level chip to read or write to the EMMC chip, etc. Among them, the data structure initialized by the system chip according to the historical access request may be that when a target access request enters the access request queue based on a preset access process, the target access request is obtained; the preset access process obtains the target access request, parses and processes the target access request, and obtains the access purpose of the target access request, that is, whether the target access request causes the system-level chip to read data from the EMMC chip or causes the system-level chip to write data to the EMMC chip; and initializes the data structure corresponding to the data read / written by the system-level chip to the EMMC chip according to the access purpose of the target access request.

[0045] Among them, a data structure is a way for a computer to store and organize data. A data structure refers to a collection of data elements that have one or more specific relationships with each other. Usually, a carefully selected data structure can bring higher running or storage efficiency. A data structure is often related to efficient retrieval algorithms and indexing techniques; a data structure (datastructure) is a collection of data elements with structural characteristics. It studies the logical structure and physical structure of data and their mutual relationships, defines corresponding operations for this structure, designs corresponding algorithms, and ensures that the new structure obtained after these operations still maintains the original structure type.

[0046] It should be noted that saving the content of the EMMC chip accessed during the execution of the historical access request facilitates restoring the access context of the system-level chip to the EMMC chip after the EMMC chip is restarted, that is, restoring the values and states of the registers when the system-level chip accesses the EMMC chip before turning off the power of the EMMC chip, and the commands sent by the controller that controls the EMMC chip when the system-level chip accesses the EMMC chip, including the partition, sector number, Buffer address for reading / writing data, length of the data read / written, etc. of the system-level chip accessing the EMMC chip, so that after the memory of the EMMC chip receives the command, it responds to the command and interacts with the system-level chip for data, making the user unaware of the software fault tolerance recovery process that occurs and improving the user experience.

[0047] Step S130: After completing the saving of the content of the EMMC chip accessed in the historical access request, restart the EMMC chip and execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request.

[0048] In some embodiments, after saving the content of the EMMC chip accessed in the historical access request, restarting the EMMC chip and executing the historical access request based on the current content may be that after saving the content of the EMMC chip accessed in the historical access request, power off the EMMC chip for a preset time period and then restart the EMMC chip again; after the EMMC chip finishes starting up, execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request.

[0049] Among them, the preset time period can be obtained through third-party experimental data or set by the user independently; the preset time period is pre-stored in the driver program of the system-on-chip for the EMMC chip. Exemplarily, the specific size of the preset time period is 2s, 1s, 0.5s, etc.

[0050] It should be understood that the EMMC chip is completely powered off after the power of the EMMC chip is turned off for the preset time period.

[0051] As an implementation manner, if the hardware design of the terminal makes the system-on-chip unable to control the power of the EMMC chip, after completing the saving of the content of the EMMC chip accessed in the historical access request, restarting the EMMC chip may be to use a hardware reset (such as a low-voltage reset, a power-on reset, a power-off reset, etc.) to replace the operation of restarting the EMMC chip.

[0052] As another implementation manner, if the hardware design of the terminal makes the system-on-chip able to control the power of the EMMC chip, after completing the saving of the content of the EMMC chip accessed in the historical access request, restarting the EMMC chip may be to turn off the power of the EMMC chip and then turn on the power of the EMMC chip after the preset time period.

[0053] Among them, after powering on or resetting the EMMC chip again, re-initialize the EMMC chip to make the EMMC chip enter the readable / writable working mode (i.e., the working state). Since this is not the first time the system-on-chip recognizes the EMMC chip when starting up, there is no need to recreate the block device for reading / writing the EMMC chip.

[0054] Specifically, initializing the EMMC chip may be to restore the context content of accessing the EMMC chip in the historical access request based on the content of accessing the EMMC chip in the saved historical access request. For example, initializing the EMMC chip causes the controller of the EMMC chip to issue a command including the partition number, sector number of the data read / written to the memory of the EMMC chip before powering off the EMMC chip, the Buffer address of the read / written data, and the Buffer size, so that the memory of the EMMC chip responds to the command and performs data interaction with the system-on-chip.

[0055] It should be understood that after the EMMC chip is restarted, the historical access request is executed based on the content of the EMMC chip accessed in the saved historical access request, so that after the EMMC chip is restarted, the system-on-chip accesses the EMMC chip based on the historical access request, which is consistent with the context environment in which the system-on-chip accessed the EMMC chip based on the historical access request before the EMMC chip was restarted. Furthermore, the system-on-chip continues to read / write the EMMC chip based on the historical access request, completing software fault tolerance recovery without the user's awareness, thus improving the user experience.

[0056] In some embodiments, executing the historical access request may be to control the controller in the EMMC chip to send the access address and access data size corresponding to the historical access request to the memory in the EMMC chip based on the content of accessing the EMMC chip in the saved historical access request, so that the memory writes the data sent by the system-on-chip to the memory based on the access address and access data size, or reads data from the memory based on the access address and access data size and sends it to the system-on-chip.

[0057] In the embodiments of the present application, if the system-on-chip accesses the EMMC chip according to the historical access request and an error occurs, the preset access process controls the access request queue not to receive new access requests, and the system-on-chip timely performs software fault tolerance recovery processing through the EMMC chip driver to prevent further damage to the file system of the disk partition of the EMMC chip.

[0058] Step S140: If the execution of the historical access request is completed, execute the target access request to access the EMMC chip.

[0059] In some embodiments, if a target access request is obtained, the target access request is parsed to obtain the target parsing data of the target access request, where the target parsing data includes the address of reading / writing the EMMC chip by the target access request and the data size.

[0060] If the execution of the historical access request is completed, executing the target access request to access the EMMC chip may be that, if the execution of the historical access request is completed, the controller controlling the EMMC chip sends a target command including target parsing data to the memory in the EMMC chip, so that the memory obtains data corresponding to the address and data size of the target access request to read the EMMC chip in response to the target command and sends it to the system-on-chip, or writes the data sent by the system-on-chip to the storage location corresponding to the address and data size of the target access request to write the EMMC chip in the memory.

[0061] Among them, executing the target access request to access the EMMC chip may be that the system-on-chip controls the controller in the EMMC chip to send a target command including the address and data size of the target access request to read / write the EMMC chip to the memory in the EMMC chip through the driver of the EMMC chip, and after receiving the response of the memory in the EMMC chip to the target command, writes the data sent by the system-on-chip to the storage location corresponding to the address and data size of the target access request to write the EMMC chip in the memory, or sends the data corresponding to the address and data size of the target access request to read the EMMC chip in the memory of the EMMC chip to the system-on-chip, thereby completing the interaction between the system-on-chip and the EMMC chip.

[0062] The technical solution provided by the embodiments of the present application is applied to a system-on-chip connected to an EMMC chip. When the EMMC chip is in a working state, if a target access request is obtained, it is judged whether the historical access request has been executed. The historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-on-chip to access the EMMC chip; if the execution of the historical access request is not completed, save the content of the EMMC chip accessed in the execution of the historical access request; after completing the saving of the content of the EMMC chip accessed in the historical access request, restart the EMMC chip, and execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request; if the execution of the historical access request is completed, execute the target access request to access the EMMC chip. Therefore, by adopting the above method of the present application, after an error occurs when the system-on-chip accesses the EMMC chip, the EMMC chip is restarted in time to perform software fault tolerance recovery processing of the system chip on the EMMC chip, improving the security of the system-on-chip operation, and completing fault tolerance recovery without the user's perception, improving the user experience.

[0063] Please refer to Figure 2 , Figure 2It is a schematic flowchart of a software fault tolerance and recovery method shown according to an embodiment of the present application. This method can be applied to a system-on-chip, and the system-on-chip is connected to an EMMC chip. The system-on-chip can be applied to terminals, such as in-vehicle terminals, robots, computers, smartphones, etc. to implement this solution, and specific limitations are not made here. Refer to Figure 2 As shown, this method at least includes step S210 to step S250.

[0064] Step S210: When the EMMC chip is in the working state, if a target access request is obtained, determine whether the historical access request has been completed. The historical access request is an access request obtained before the target access request, and the target access request is used to make the system-on-chip access the EMMC chip.

[0065] Step S220: If the historical access request has not been completed, save the content of the EMMC chip accessed during the execution of the historical access request, obtain the error type generated when the historical access request has not been completed, and create a fault tolerance and recovery flag based on the error type.

[0066] In the embodiment of the present application, when the historical access request has not been completed, that is, the historical access request fails to execute, and the failure of the historical access request to execute can occur at each stage when the system-on-chip reads / writes the EMMC chip according to the historical access request. Among them, the reasons for the historical access request not being completed can include timeouts when the system-on-chip reads / writes the EMMC chip, CRC (Cyclic Redundancy Check) errors, etc. Among them, CRC is a channel coding technology that generates a short fixed-length check code according to data such as network data packets or computer files, mainly used to detect or verify possible errors in data transmission or storage. It uses the principle of division and remainder to detect errors.

[0067] In some embodiments, obtaining the error type generated when the historical access request has not been completed can be that the system-on-chip obtains the specific values and statuses of the registers included in the memory of the EMMC chip through the driver of the EMMC chip, and obtains the error type generated when the historical access request has not been completed according to the specific values and statuses of the registers.

[0068] It should be noted that the purpose of obtaining the error type generated when the historical access request has not been completed is to obtain the reason for the failure of the historical access request this time (that is, the reason for this software fault tolerance and recovery process).

[0069] In the embodiment of the present application, the system-on-chip creates a fault tolerance and recovery flag corresponding to the error type based on the error type.

[0070] It should be noted that the system-on-chip creates a fault-tolerant recovery flag corresponding to the error type based on the error type, so that the system-on-chip starts to save the target log based on the fault-tolerant recovery flag.

[0071] Step S230: After completing the saving of the content of the EMMC chip accessed in the historical access request, restart the EMMC chip and execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request.

[0072] Step S240: If the execution of the historical access request is completed, execute the target access request to access the EMMC chip and determine whether there is a fault-tolerant recovery flag.

[0073] In some embodiments, determining whether there is a fault-tolerant recovery flag may be that the system-on-chip obtains the specific values and status of the registers included in the system-on-chip through the driver of the EMMC chip, and determines whether there is a fault-tolerant recovery flag according to the specific values and status of the registers.

[0074] Step S250: If there is a fault-tolerant recovery flag, create a fault-tolerant recovery success flag, and obtain the target log according to the fault-tolerant recovery flag and the fault-tolerant recovery success flag.

[0075] Among them, the target log is the log of the system-on-chip for software fault-tolerant recovery processing of the EMMC chip access error. The target log corresponds to one software fault-tolerant recovery processing, or can also correspond to multiple software fault-tolerant recovery processings; the content of the target log may include the error type of the software fault-tolerant recovery processing, the time when the error occurred, and the time length of the software fault-tolerant recovery processing, etc.

[0076] In some embodiments, after the execution of the historical access request is completed, if the system-on-chip detects a fault-tolerant recovery flag in the memory of the system-on-chip through the driver of the EMMC chip in the system-on-chip, the system-on-chip creates a fault-tolerant recovery success flag corresponding to the fault-tolerant recovery flag.

[0077] Among them, the system-on-chip includes a preset EMMC chip access diagnosis process, which monitors the access status of the system-on-chip to the EMMC chip in real time at the application layer of the system-on-chip. When the preset EMMC chip access diagnosis process detects the fault-tolerant recovery success flag, the preset EMMC chip access diagnosis process saves the corresponding fault-tolerant recovery success flag and the target log corresponding to the fault-tolerant recovery flag in the application layer of the system-on-chip and sends them to the memory of the EMMC chip for storage.

[0078] Exemplarily, the driver of the EMMC chip of the system-on-chip includes an EMMC DIAG process in the application layer of the system-on-chip, which can monitor the access status of the system-on-chip to the EMMC chip in real time; when the EMMC DIAG process detects the fault recovery success flag, the EMMC DIAG process saves the corresponding fault recovery success flag and the target log corresponding to the fault recovery flag in the application layer of the system-on-chip and sends them to the memory of the EMMC chip for storage.

[0079] It should be noted that the purpose of generating the fault recovery success flag is to notify the preset EMMC chip access diagnosis process that software fault recovery has been successfully processed for the system-on-chip to read / write the EMMC chip. As a result, the system-on-chip saves the target log corresponding to the software fault recovery process, and then the error type corresponding to the software fault recovery process can be viewed by checking the saved target log, and the root cause of the error that occurs when the system-on-chip reads / writes the EMMC chip can be analyzed. Among them, since the system-on-chip always generates logs, the target logs of the system-on-chip's read / write faults on the EMMC chip are saved to prevent the logs generated during the long-term operation of the system-on-chip from continuously refreshing and covering the target logs that can analyze the specific reasons for the system-on-chip's read / write faults on the EMMC chip.

[0080] It should be understood that saving the target logs corresponding to the fault recovery flag and the fault recovery success flag can facilitate the analysis of the root cause of the system-on-chip's read / write failure of the EMMC chip, and then the reliability of the EMMC chip and the robustness of the software can be enhanced according to the root cause.

[0081] Exemplarily, the reasons for the system-on-chip's read / write failure of the EMMC chip analyzed according to the target log include that the clock frequency of the EMMC chip is relatively low, which causes the system-on-chip to time out when reading / writing the EMMC chip. Therefore, by increasing the clock frequency of the EMMC chip, the performance of the EMMC chip being read / written can be made faster, and then the reliability of the EMMC chip and the robustness of the software can be enhanced.

[0082] In some embodiments, the vehicle uses the EMMC chip as a memory to form a storage system. During the vehicle's use of OTA (Over-the-Air) technology, a large number of operations for reading / writing the EMMC chip are involved. According to the saved target logs, the root cause of the system-on-chip's read / write failure of the EMMC chip can be analyzed, and then the reliability of the EMMC chip and the robustness of the software can be enhanced according to the root cause, so that during the vehicle's use of OTA (Over-the-Air) technology, the working state of the vehicle is more stable and the risk of OTA (Over-the-Air) upgrade failure of the vehicle is reduced.

[0083] In some embodiments, if there are other chips (such as SIM cards, flash memories, etc.) in addition to the EMMC chip connected to the system-on-chip, the target log can be considered to be saved in other chips, so that the system-on-chip can save the target log immediately in the application layer of the system-on-chip according to the fault tolerance recovery flag before the read / write of the EMMC chip by the driver of the EMMC chip fails and before the fault tolerance recovery process is successfully completed.

[0084] In an implementable manner provided by the embodiments of the present application, considering saving the storage space of the system-on-chip and enabling the system-on-chip to normally save the target log generated by the system-on-chip for the fault tolerance recovery process of the EMMC chip, after saving the target log after a successful software fault tolerance recovery process, the fault tolerance recovery flag and the fault tolerance recovery success flag can be cleared to save resources and specifically save the log generated by the system-on-chip.

[0085] Adopting the technical solution of the present application, which is applied to a system-on-chip connected to an EMMC chip. When the EMMC chip is in a working state, if a target access request is obtained, it is judged whether the historical access request has been completed. The historical access request is an access request obtained before the target access request, and the target access request is used to enable the system-on-chip to access the EMMC chip. If the historical access request has not been completed, the content of the EMMC chip accessed during the execution of the historical access request is saved, the error type generated when the historical access request has not been completed is obtained, and a fault tolerance recovery flag is created based on the error type. After completing the saving of the content of the EMMC chip accessed during the historical access request, the EMMC chip is restarted, and the historical access request is executed based on the saved content of the EMMC chip accessed during the historical access request. If the historical access request has been completed, the target access request is executed to access the EMMC chip, and it is judged whether there is a fault tolerance recovery flag. If there is a fault tolerance recovery flag, a fault tolerance recovery success flag is created, and the target log is obtained according to the fault tolerance recovery flag and the fault tolerance recovery success flag. Therefore, by adopting the above method of the present application, the EMMC chip is immediately restarted for fault tolerance recovery operation after an error occurs in the system-on-chip when reading / writing the EMMC chip, which improves the working safety of the system-on-chip. At the same time, when the system-on-chip performs fault tolerance recovery on reading / writing the EMMC chip, the target log of the system-on-chip for fault tolerance recovery of reading / writing the EMMC chip is saved, which is convenient for analyzing the root cause of the error in the system-on-chip when reading / writing the EMMC chip according to the target log, so that the user can improve the access process of the system-on-chip to the EMMC chip according to the root cause, enhancing the reliability of the EMMC chip and the robustness of the system-on-chip's access to the EMMC chip.

[0086] Please refer to Figure 3, which shows a software fault tolerance recovery device provided by an embodiment of the present application, applied to a system-on-chip connected to an EMMC chip. The device 300 includes: a target request acquisition unit 310, an access content storage unit 320, a fault tolerance recovery unit 330, and a target request execution unit 340. Specifically, the target request acquisition unit 310 is configured to, when the EMMC chip is in a working state, if a target access request is acquired, determine whether a historical access request has been completed. The historical access request is an access request acquired before the target access request. The target access request is used to enable the system-on-chip to access the EMMC chip. The access content storage unit 320 is configured to, if the historical access request has not been completed, save the content of the EMMC chip accessed during the execution of the historical access request. The fault tolerance recovery unit 330 is configured to, after completing saving the content of the EMMC chip accessed in the historical access request, restart the EMMC chip and execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request. The target request execution unit 340 is configured to, if the historical access request has been completed, execute the target access request to access the EMMC chip.

[0087] In one embodiment, the fault tolerance recovery unit 330 is further configured to, after saving the content of the EMMC chip accessed in the historical access request, turn off the power of the EMMC chip for a preset time period and then restart the EMMC chip; after the EMMC chip is started up, execute the historical access request based on the content of the EMMC chip accessed in the saved historical access request.

[0088] In one embodiment, the access content storage unit 320 is further configured to obtain the error type generated when the historical access request has not been completed; create a fault tolerance recovery flag based on the error type; if the historical access request has been completed, determine whether there is a fault tolerance recovery flag; if there is a fault tolerance recovery flag, create a fault tolerance recovery success flag, and obtain a target log according to the fault tolerance recovery flag and the fault tolerance recovery success flag.

[0089] In one embodiment, the access content storage unit 320 is further configured to, after obtaining the target log, clear the fault tolerance recovery flag and the fault tolerance recovery success flag.

[0090] In one embodiment, the fault tolerance recovery unit 330 is further configured to, based on the content of the EMMC chip accessed in the saved historical access request, control the controller in the EMMC chip to send the access address and access data size corresponding to the historical access request to the memory in the EMMC chip, so that the memory writes the data sent by the system-on-chip into the memory based on the access address and access data size, or reads the data from the memory based on the access address and access data size and sends it to the system-on-chip.

[0091] In one embodiment, the target request acquisition unit 310 is further configured to, if a target access request is acquired, parse the target access request to obtain target parsing data of the target access request, where the target parsing data includes the address and data size of the target access request to read / write the EMMC chip; the target request execution unit is further configured to, if the historical access request has been completed, control the controller of the EMMC chip to send a target command including the target parsing data to the memory in the EMMC chip, so that the memory responds to the target command to obtain data corresponding to the address and data size of the target access request to read the EMMC chip and send it to the system-on-chip, or write the data sent by the system-on-chip to the storage location corresponding to the address and data size of the target access request to write the EMMC chip in the memory.

[0092] In one embodiment, before the target request acquisition unit 310 executes the operation of determining whether the historical access request has been completed if the target access request is acquired, when it is detected based on a preset access process that a target access request enters the access request queue, the target access request is acquired.

[0093] In one embodiment, if the historical access request has not been completed, the target request acquisition unit 310 blocks the preset access process, so that the access request queue no longer receives new access requests.

[0094] Please refer to Figure 4 , as an implementation manner, the working process of the software fault tolerance recovery device may include the following steps:

[0095] Step S01: Power on and initialize the EMMC chip and initialize the block device of the system-on-chip.

[0096] The system-on-chip connected to the EMMC chip can power on the EMMC chip through the driver of the EMMC chip, set the values and status of the registers of the EMMC chip to initialize the EMMC chip, and initialize the block device for the system-on-chip to read / write the EMMC chip.

[0097] Step S02: Determine whether the historical access request has been completed.

[0098] If the preset access process included in the system-on-chip detects that a target access request enters the access request queue, the target access request is acquired; the preset access process processes the target access request to obtain the target access request so that the system-on-chip accesses the EMMC chip in a certain way (read / write data), and initializes the data structure for the system-on-chip to read / write data from / to the EMMC chip according to the target access request; at the same time, the preset access process detects whether the historical access request is completed.

[0099] Step S03: Save the content of the EMMC chip accessed in the execution history access request.

[0100] If the execution of the historical access request is not completed, the preset access process controls the access request queue not to receive new target access requests; when the historical access request fails to be accessed successfully, the system-on-chip reads the values and status of the EMMC chip registers through the driver of the EMMC chip, obtains the error type of the historical access request failure to be accessed successfully, creates a fault tolerance recovery flag corresponding to the error type, and saves the EMMC access context, that is, saves the content of the EMMC chip accessed in the execution history access request.

[0101] Step S04: Restart the EMMC chip.

[0102] Turn off the power of the EMMC chip for 2s and then turn on the power of the EMMC chip again; based on the content of the EMMC chip accessed in the saved historical access request, reset the controller of the EMMC chip, and set the values and status of the registers of the EMMC chip through the driver of the EMMC chip to re-initialize the EMMC chip to continue executing the historical access request.

[0103] Step S05: Execute the access request.

[0104] The system-on-chip controls the controller in the EMMC chip to send the access address and access data size corresponding to the historical access request to the memory in the EMMC chip through the driver of the EMMC chip. At the same time, the system-on-chip controls the controller in the EMMC chip to receive the interrupt signal to process irq (emergency event) through the driver of the EMMC chip, that is, to give priority to the system-on-chip's access to the EMMC chip, and update the EMMC access context (the address of the system-on-chip accessing the EMMC chip and the size of the read / write data, etc.), so that the memory writes the data sent by the system-on-chip to the memory based on the access address and access data size, or reads the data from the memory based on the access address and access data size and sends it to the system-on-chip to complete the request to access the EMMC chip in the historical access request.

[0105] Among them, when the system-on-chip executes an access request through the driver of the EMMC chip, it will set the controller of the EMMC chip. If the access request corresponds to the system-on-chip reading data from the EMMC chip, the system-on-chip will set the register corresponding to the data reading method of the controller of the EMMC chip through the driver of the EMMC chip; if the access request corresponds to the system-on-chip writing data to the EMMC chip, the register will be set according to the method of the system-on-chip controlling the controller of the EMMC chip to write data correspondingly; the system-on-chip controls the controller of the EMMC chip to send different read and write commands to the memory of the EMMC through the driver of the EMMC chip. Among them, the commands also include the size of the read / write data, the starting address of the read / write data, etc., all of which are configured by the system-on-chip through the driver of the EMMC chip to control the controller of the EMMC chip.

[0106] Step S06: Save the target log.

[0107] After completing the request to access the EMMC chip in the historical access request, the preset access process detects the completion of the historical access request and controls the access request queue to receive the target access request; the system-on-chip judges whether the fault tolerance recovery flag exists through the driver of the EMMC chip. If it does not exist, it controls the controller of the EMMC chip to send a target command including the target parsed data to the memory in the EMMC chip, so that the memory responds to the target command to obtain the data corresponding to the address and data size of the target access request to read the EMMC chip and send it to the system-on-chip, or writes the data sent by the system-on-chip to the storage location corresponding to the address and data size of the target access request to write the EMMC chip in the memory.

[0108] The system-on-chip judges whether the fault tolerance recovery flag exists through the driver of the EMMC chip. If it exists, it clears the fault tolerance recovery flag and creates a fault tolerance recovery success flag to notify the application layer of the system-on-chip that a fault tolerance has occurred and been successfully recovered. Under the control of the preset diagnosis process (EMMCDIAG process) in the application layer of the system-on-chip, the system-on-chip saves the target log through the driver of the EMMC chip and clears the fault tolerance recovery success flag.

[0109] It should be noted that the various embodiments of this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For device embodiments, since they are basically similar to method embodiments, they are described relatively simply. For the relevant parts, refer to the partial description of the method embodiments. For any processing method described in the method embodiments, it can be implemented by the corresponding processing module in the device embodiments, and will not be elaborated one by one in the device embodiments.

[0110] Please refer to Figure 5 , based on the above software fault tolerance recovery method, the present application also provides another electronic device 400 that can execute the foregoing software fault tolerance recovery method. The electronic device 400 further includes one or more processors 410, a memory 420, and one or more applications. Among them, a program that can execute the content in the foregoing embodiments is stored in the memory 420, and the processor 410 can execute the program stored in the memory 420. Among them, the electronic device 400 can be an intelligent control panel, an intelligent wearable device, a vehicle, an intelligent robot, a tablet computer, a personal computer, etc.

[0111] Among them, the processor 410 may include one or more cores for processing data and a message matrix unit. The processor 410 connects various parts within the entire electronic device through various interfaces and lines. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 420, and by calling data stored in the memory 420, it executes various functions of the electronic device 400 and processes data. Optionally, the processor 410 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 410 may integrate a combination of one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and applications, etc.; the GPU is responsible for rendering and drawing the display content; the modem is used to process wireless communication. It can be understood that the above modem may not be integrated into the processor and may be implemented separately through a communication chip.

[0112] The memory 420 may include an EMMC memory, may also include a Random Access Memory (RAM), and may further include a Read-Only Memory. The memory 420 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 420 may include a program storage area and a data storage area. Among them, the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as when the EMMC chip is in a working state, if a target access request is obtained, determining whether a historical access request has been completed, etc.), instructions for implementing the following various method embodiments, etc. The data storage area may also store data created during the use of the terminal (such as target logs, fault tolerance recovery flags, fault tolerance recovery success flags), etc.

[0113] Please refer to Figure 6 , which shows a structural block diagram of a computer-readable storage medium 500 provided by an embodiment of the present application. Program code 510 is stored in the computer-readable storage medium 500, and the program code 510 can be called by a processor to execute the methods described in the above method embodiments.

[0114] The computer-readable storage medium 500 may be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 500 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 500 has a storage space for the program code 510 that executes any method step in the above methods. These program codes 510 can be read out from or written into one or more computer program products. The program code can be compressed in an appropriate form, for example.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A software fault tolerance recovery method, characterized in that, applied to a system-on-chip, the system-on-chip is connected with an EMMC chip, and the method includes: When the EMMC chip is in a working state, if a target access request is obtained, it is judged whether a historical access request has been executed completely, and the target access request is parsed to obtain the target parsing data of the target access request, wherein the target parsing data includes the address and data size for reading / writing the EMMC chip by the target access request, the historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-on-chip to access the EMMC chip; If the historical access request has not been executed completely, save the content of the EMMC chip accessed in the execution of the historical access request, obtain the error type generated when the historical access request has not been executed completely, and create a fault tolerance recovery flag based on the error type; After saving the content of the EMMC chip accessed in the historical access request, restart the EMMC chip, and based on the content of the EMMC chip accessed in the saved historical access request, control the controller in the EMMC chip to send the access address and access data size corresponding to the historical access request to the memory in the EMMC chip, so that the memory writes the data sent by the system-on-chip into the memory based on the access address and data size, or reads the data from the memory based on the access address and data size and sends it to the system-on-chip; If the historical access request has been executed completely, control the controller of the EMMC chip to send a target command including the target parsing data to the memory in the EMMC chip, so that the memory responds to the target command to obtain the data corresponding to the address and data size for reading the EMMC chip by the target access request and send it to the system-on-chip, or write the data sent by the system-on-chip into the storage location corresponding to the address and data size for writing the EMMC chip by the target access request in the memory, and judge whether there is the fault tolerance recovery flag; If there is the fault tolerance recovery flag, create a fault tolerance recovery success flag, and obtain a target log according to the fault tolerance recovery flag and the fault tolerance recovery success flag, wherein at least the error type, the time when the error occurs, and the time length of the software fault tolerance recovery process are included in the target log.

2. The method according to claim 1, characterized in that, the restarting the EMMC chip after saving the content of the EMMC chip accessed in the historical access request includes: After saving the content of the EMMC chip accessed in the historical access request, turn off the power of the EMMC chip for a preset time period and then restart the EMMC chip.

3. The method according to claim 2, characterized in that, the method further includes: After obtaining the target log, clear the fault tolerance recovery flag and the fault tolerance recovery success flag.

4. The method according to claim 1, wherein, before executing the step of if a target access request is obtained, determining whether the historical access request has been completed, the method further includes: when it is detected based on a preset access process that a target access request enters the access request queue, obtaining the target access request.

5. The method according to claim 4, wherein, the method further includes: if the historical access request has not been completed, blocking the preset access process so that the access request queue does not receive new access requests.

6. A software fault tolerance recovery device, wherein, applied to a system-on-chip, the system-on-chip is connected to an EMMC chip, and the device includes: a target request acquisition unit, configured to, when the EMMC chip is in a working state, if a target access request is obtained, determine whether a historical access request has been completed, and parse the target access request to obtain target parsing data of the target access request, where the target parsing data includes an address for reading / writing the EMMC chip by the target access request and a data size, the historical access request is an access request obtained before the target access request is obtained, and the target access request is used to enable the system-on-chip to access the EMMC chip; an access content storage unit, configured to, if the historical access request has not been completed, save the content of the EMMC chip accessed during the execution of the historical access request, obtain an error type generated when the historical access request has not been completed, and create a fault tolerance recovery flag based on the error type; a fault tolerance recovery unit, configured to, after completing saving the content of the EMMC chip accessed during the historical access request, restart the EMMC chip, and based on the content of the EMMC chip accessed during the saved historical access request, control a controller in the EMMC chip to send an access address and an access data size corresponding to the historical access request to a memory in the EMMC chip, so that the memory writes data sent by the system-on-chip into the memory based on the access address and the data size, or reads data from the memory based on the access address and the data size and sends the data to the system-on-chip; A target request execution unit, which, if the execution of the historical access request is completed, controls the controller of the EMMC chip to send a target command including the target parsing data to the memory in the EMMC chip, so that the memory obtains data corresponding to the address and data size of the target access request to read the EMMC chip in response to the target command and sends the data to the system-on-chip, or writes the data sent by the system-on-chip into the storage location corresponding to the address and data size of the target access request to write the EMMC chip in the memory, and determines whether there is the fault tolerance recovery flag; if there is the fault tolerance recovery flag, creates a fault tolerance recovery success flag, and obtains a target log according to the fault tolerance recovery flag and the fault tolerance recovery success flag, wherein at least the error type, the time when the error occurs, and the time length of the software fault tolerance recovery process are included in the target log.

7. An electronic device, characterized in that it includes: one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs are configured to execute the method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that program code is stored in the computer-readable storage medium, and the program code can be called by a processor to execute the method according to any one of claims 1-5.

Images