A hardware architecture for slice fusion-based aggregation computing of graph neural networks based on FPGA

Abstract

The present invention discloses a hardware architecture for slice fusion-based aggregation computing of graph neural networks based on FPGA. By fusing m 2 slices and deploying them into the computing array, each computing unit is time-division multiplexed by m nodes. The computing units in the same column are connected in a ring, enabling the propagation of node data between the computing units, thereby implementing the aggregation task in GNN. This method only requires 1 / m 2 of the time of the original ring aggregation array, and does not require complex data preprocessing. At the same time, it also has advantages such as regular memory access and strong adaptability.

Description

Technical Field

[0001] The present invention relates to the technical field of machine learning, and more specifically, to a slice fusion-based aggregation computing hardware architecture for graph neural networks based on FPGA. Background Art

[0002] In the past decade, the field of deep learning represented by neural networks has shown good performance in many application scenarios. For example, object detection, semantic segmentation, face recognition, etc. Among them, graph neural networks (GNNs) have gradually received attention in the past two years. Since graph neural networks have unparalleled advantages over other neural networks in processing non-Euclidean data, they are widely used in node classification, natural language processing, recommendation systems, graph clustering, and link prediction fields. Behind the excellent performance of graph neural networks is the high computational cost and the huge challenge to memory access. At present, the performance of CPUs and GPUs is difficult to meet the requirements of graph neural networks with explosive growth in scale and increasingly complex structures. At the same time, existing deep convolutional neural network (DCNN) acceleration structures perform poorly when dealing with the irregular computing patterns of GNNs, so they cannot be directly applied.

[0003] Due to the large number of irregular memory access behaviors in GNN models and the strong sparsity of the involved data, leveraging the characteristics of sparse data to improve computing efficiency has become a research hotspot in academia and industry to break through the GNN acceleration bottleneck. Currently, existing GNN accelerators are mainly deployed on application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Due to the long development cycle of ASICs, their customized characteristics also bring the disadvantage of insufficient flexibility, making GNN accelerators based on this hardware framework difficult to adapt to the characteristics of different data structures in different application scenarios.

[0004] In recent years, commercial high-end FPGAs have rich on-chip storage resources, general logic resources, and computing resources. They can provide powerful parallel computing capabilities, and their logic control is flexible, which can meet the needs of different computing stages in GNN acceleration, including the computationally intensive stage and the irregular memory access intensive stage. The GNN inference process is mainly divided into two stages: combination and aggregation. The combination stage involves intensive matrix multiplication calculations and requires rich computing resources to support a large number of parallel calculations. The computational intensity of the aggregation stage is not high, but it involves a large number of irregular memory accesses, which makes flexible control logic very critical. Compared with the single-instruction single-data-stream of CPUs and the single-instruction multiple-data-stream of GPUs, the multi-instruction multiple-data-stream characteristics of FPGAs enable GNN accelerators to execute different processing stages in parallel. At the same time, FPGAs have lower power consumption and the reconfigurable characteristics that can flexibly adjust circuit configurations.

[0005] In the prior art, a hardware computing system for graph neural networks based on in-memory computing is provided, which includes two in-memory computing modules, two MUX modules, one DMUX module, one control unit, and one Relu module. The two in-memory computing modules are respectively used to complete Laplacian matrix calculation and convolutional calculation of neural networks. The two MUX modules respectively select the input data of the two in-memory computing modules according to the instructions of the control unit. The DMUX module selects the output data direction according to the instructions of the control unit, outputs the data to the outside or conveys it to the MUX module for the next round of calculation. The Relu module performs activation processing on the calculation results of the in-memory computing module to obtain the final result of one-layer neural network calculation, and then sends this result to the subsequent DMUX module. The control unit is used to generate control signals for all other modules and control the entire calculation process.

[0006] The above solution does not improve the GNN aggregation stage, and the existing computing array designs for the GNN aggregation stage are difficult to ensure the regularity of memory access when utilizing the sparsity of the adjacency matrix, which affects the off-chip communication bandwidth. The designs that ensure regularity will lead to the problem of low computing resource utilization, or require complex data preprocessing. Summary of the Invention

[0007] The present invention provides an FPGA-based slice fusion type aggregation calculation hardware architecture for graph neural networks, which improves the utilization rate of computing resources while ensuring regular memory access in the GNN aggregation stage.

[0008] To solve the above technical problems, the technical solution of the present invention is as follows:

[0009] An FPGA-based slice fusion type aggregation calculation hardware architecture for graph neural networks includes a preprocessing module, a memory, a storage control module, a controller, and an aggregation calculation unit array, where:

[0010] The input of the preprocessing module is a graph neural network model and a data set. The preprocessing module generates a control signal flow to the controller according to the graph neural network model and the data set, and at the same time encodes the data in the data set and sends it to the memory for storage.

[0011] The storage control module is used to send the data stored in the memory to the aggregation calculation unit array.

[0012] The controller sends the control signal to the aggregation calculation unit array.

[0013] The aggregation calculation unit array determines whether to perform aggregation calculation according to the control signal flow, and the aggregation calculation unit array performs aggregation calculation according to the data stored in the memory.

[0014] Preferably, the data set is the adjacency matrix of a graph. Both dimensions of the adjacency matrix are used to represent the numbers of all nodes in the graph. When there is a connection between two nodes, the corresponding coordinate point in the adjacency matrix is 1; otherwise, it is 0.

[0015] Preferably, the aggregation calculation unit array includes M×N aggregation calculation units. The M×N aggregation calculation units are arranged in an array, with M rows and N columns in total. Among them, the aggregation calculation units in each row process the aggregation tasks of a group of target vertices. The aggregation calculation units in different columns within the same row process different dimensions of data of the target vertices. The aggregation calculation units in the same column are connected end to end to form a ring structure.

[0016] Preferably, if the dimension of the adjacency matrix is greater than the size of the aggregation calculation unit array, the adjacency matrix needs to be sliced.

[0017] Preferably, when the slice size is Tile_size, Tile_size <= 128, and the number of slice fusions is m 2 When 2 the time required to complete the aggregation of m

[0018]

[0019] slices is Tile_size clock cycles. The time required to complete the single-layer aggregation of the entire graph is:

[0020] In the formula, Vertices_num is the number of vertices in the graph, and clk_period is the clock cycle.

[0020] Preferably, each of the M×N aggregation calculation units includes a group of target node registers. The target node registers receive the control signal stream sent by the controller and determine which source node should be aggregated to the target node at the current time according to the control signal stream.

[0021] Preferably, each clock cycle, each aggregation calculation unit stores the intermediate results of the aggregation calculations of m target vertices, and can receive the feature vectors of m source vertices at the same time. Each target vertex has a group of control flow signals. The aggregation calculation unit will judge according to the control flow signals whether there is an aggregation task at the current time. If so, it will locate the target vertex to be aggregated according to which group of control flow has a valid signal, and obtain the specific source vertex information according to the position of the valid signal in this group of control flow signals, and aggregate it to the corresponding target vertex.

[0022] Preferably, the static priority scheduling strategy is used to solve the calculation task conflict problem that occurs during the slice fusion process. Specifically:

[0023] Judgment is made according to the control flow signal. When there are two or more computing tasks in a certain aggregation computing unit in a certain clock cycle, one of them is executed first, and the remaining computing tasks will be scheduled to be executed when the aggregation computing unit is idle later.

[0024] Preferably, the encoding of the data in the data set is specifically as follows:

[0025] After the adjacency matrix is divided into multiple slices, each slice adopts an improved COO encoding. The slice identifier is divided into a slice group identifier and an intra-group slice identifier. The data within the same slice is stored in ascending order of the relative coordinates within the slice.

[0026] Preferably, the control flow signal is generated by decoding the encoded adjacency matrix using a shift decoder in the preprocessing module, specifically as follows:

[0027] Judgment is made according to the slice group identifier of the data, and the data of one slice group is read;

[0028] If the slice fusion factor is m, each shift decoder needs to generate m 2 streams of control signals in parallel. These streams of control signals are divided into m groups, and each group of m streams of control signals belongs to a target node. Each stream of control signals corresponds to a source node within a slice of the target node;

[0029] The read data is sorted;

[0030] According to the intra-group slice identifier, the data is respectively sent into the corresponding control signal flow registers and waits for the start signal of the control flow generation;

[0031] When the slice size is Tile_size, the control signal flow register is also Tile_size bits. Each bit is used to control the aggregation task in one clock cycle, and the recorder is incremented by 1 every clock cycle;

[0032] When the data at the top of the control signal flow register is equal to the value of the recorder, the data position at the leftmost side of the corresponding control signal flow register is set to 1, and at the same time, the data at the top of the control signal flow register is popped until after Tile_size clock cycles, the decoding is completed;

[0033] After that, when the aggregation starts, the control signal flow register is shifted one bit to the right every clock cycle, and the rightmost data bit of the control signal flow register is used as the control signal, which is used as a flag to judge whether there is an aggregation task.

[0034] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0035] 1) The present invention makes full use of the sparsity of the adjacency matrix, enabling multiple vertices to simultaneously reuse the aggregation computing unit to complete the aggregation task, improving the utilization rate of each aggregation computing unit in the ring array. Compared with the ordinary ring array, when m vertices reuse the aggregation computing unit in this method, the required time is 1 / m of the original time. 2 。

[0036] 2) The memory access of the present invention has regularity. Each time, adjacent m*Tile_size vertex information is read from the memory, making full use of the bandwidth. This also makes the present invention have universality on different data sets, without node rearrangement and complex data scheduling.

[0037] 3) The control logic of the present invention is simple. For each vertex, only a set of control flows is required. Each control flow can be represented by only one bit of data, and the generation of the control flow can be completed by only a set of shift registers, saving the hardware resources required for sparse matrix decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of the hardware architecture of the present invention.

[0039] Figure 2 is the principle of the slice fusion strategy.

[0040] Figure 3 is a schematic diagram of the solution to the computing task conflict.

[0041] Figure 4 is the schematic diagram of the generation principle of the control signal flow. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The drawings are only for illustrative purposes and should not be construed as limitations of this patent;

[0043] For better illustration of this embodiment, some components in the drawings are omitted, enlarged or reduced, which do not represent the dimensions of the actual product;

[0044] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0045] The technical solutions of the present invention will be further described below with reference to the drawings and embodiments.

[0046] Embodiment 1

[0047] This embodiment provides a hardware architecture for slice fusion-based aggregation computing of graph neural networks based on FPGA, as Figure 1 shown. In the figure, APE represents the aggregation computing unit. The array of all aggregation computing units forms an aggregation computing unit array, including a preprocessing module, a memory, a storage control module, a controller, and an aggregation computing unit array, where:

[0048] The input of the preprocessing module is a graph neural network model and a dataset. The preprocessing module generates a control signal and sends it to the controller according to the graph neural network model and the dataset, and encodes the data in the dataset and stores it in the memory.

[0049] The storage control module is used to send the data stored in the memory to the aggregation computing unit array.

[0050] The controller sends the control signal to the aggregation computing unit array.

[0051] The aggregation computing unit array determines whether to perform aggregation computing according to the control signal flow, and performs aggregation computing according to the data stored in the memory.

[0052] Embodiment 2

[0053] On the basis of Embodiment 1, the following content is further disclosed in this embodiment:

[0054] During the GNN inference process, the main task in the aggregation stage is to aggregate the adjacent node information of each node to update the vector representation of each node. Therefore, the hardware needs to be able to perform memory access and computing according to the connection relationship between nodes. The connection relationship between nodes is represented by an adjacency matrix during the computing process. Both dimensions of the adjacency matrix are used to represent the numbers of all nodes in the graph. When there is a connection between two nodes, the corresponding coordinate point in the adjacency matrix is 1, otherwise it is 0. Looking at the whole graph, the adjacent nodes of each node are only a very small part, and the connection relationship is sparse. Therefore, the adjacency matrix is an extremely sparse matrix, and the efficiency of directly performing matrix multiplication on the hardware is very low.

[0055] The dataset is the adjacency matrix of the graph. Both dimensions of the adjacency matrix are used to represent the numbers of all nodes in the graph. When there is a connection between two nodes, the corresponding coordinate point in the adjacency matrix is 1, otherwise it is 0.

[0056] The present invention utilizes the sparsity of the adjacency matrix during the GNN calculation process to design an aggregation computing unit array dedicated to the aggregation stage of GNN. The aggregation computing unit array includes M×N aggregation computing units, and the M×N aggregation computing units are arranged in an array, with a total of M rows and N columns. Among them, the aggregation computing units in each row process the aggregation tasks of a group of target vertices, and the aggregation computing units in different columns within the same row process different-dimensional data of the target vertices. The aggregation computing units in the same column are connected end to end to form a ring structure for the propagation of node data between the aggregation computing units. After the previous calculation is completed, each aggregation computing unit has obtained the required vertex data, and at this time, the aggregation begins. During the aggregation process, in each clock cycle, each aggregation computing unit receives vertex information from the aggregation computing unit upstream in the same ring structure and sends the vertex information to the aggregation computing unit downstream at the same time. The vertex information obtained from the upstream is used as the source vertex information, and it is judged whether an aggregation task needs to be performed through the control flow information input in real time by the aggregation computing unit.

[0057] When the dimension of the adjacency matrix is greater than the size of the aggregation computing unit array, it is necessary to slice the adjacency matrix.

[0058] In this embodiment, the computing array is 128*16, that is, the computing array can process the aggregation tasks of up to 128 groups of target vertices at the same time, and each vertex can process 16-dimensional data.

[0059] When the slice size is Tile_size, Tile_size <= 128, and the number of slice fusions is m 2 When 2 the time required to complete the aggregation of m

[0060]

[0061] slices is Tile_size clock cycles, and the time required to complete the single-layer aggregation of the entire graph is:

[0062] Each of the M×N aggregation computing units includes a group of target node registers. The target node registers receive the control signal flow sent by the controller and judge which source node should be aggregated to the target node at the current time according to the control signal flow.

[0063] In each clock cycle, m intermediate results of the aggregation calculation of target vertices are stored in each aggregation calculation unit, and at the same time, m source vertex feature vectors can be received. Each target vertex has a set of control flow signals. The aggregation calculation unit will judge according to the control flow signals whether there is an aggregation task at present. If so, it will locate the target vertices to be aggregated according to which set of control flow has valid signals, obtain the specific source vertex information according to the positions of the valid signals in this set of control flow signals, and aggregate them to the corresponding target vertices.

[0064] The principle of deploying the slice fusion strategy in this aggregation calculation unit array is as Figure 2 shown. For the convenience of understanding, the example in the figure is the case where the slice size is 8 and the fusion factor is 2. In this example, each slice involves 8 vertex calculations. Directly using the circular calculation structure requires 8 clock cycles to complete the calculation task of one slice. Therefore, it takes 32 clock cycles to complete the 4 slices shown in the figure. However, most of the aggregation calculation units are idle in multiple clock cycles. This embodiment makes full use of the sparsity of the matrix to deploy the aggregation tasks of the 4 slices shown in the figure into the aggregation calculation unit array at the same time. Under the original array size, it takes 8 clock cycles to complete the aggregation tasks of 4 slices.

[0065] First, each aggregation calculation unit in the circular array uses a register to store the target node data that needs to be updated in the current slice. This design expands the target vertex library of each aggregation calculation unit. Each time the vertex data in the aggregation calculation unit is replaced, multiple target vertex data are stored in an aggregation calculation unit. In the figure, the rows of the matrix represent source nodes and the columns represent target nodes. When the fusion factor is 2, each aggregation calculation unit is responsible for updating 2 target nodes. For example, according to Figure 1 the hardware structure of, APE(0,0) is responsible for Figure 2 the aggregation of node 0 and node 8 in, APE(1,0) is responsible for the aggregation of node 1 and node 9, and the other aggregation calculation units are similar. Among the four slices, slice 0 and slice 1 use the same source nodes to update their respective target nodes, while slice 2 and slice 3 respectively have the same target nodes as slice 0 and slice 1, and slice 2 and slice 3 have the same source nodes. Therefore, after slice fusion, each aggregation calculation unit only needs to judge which of the two data sent from the upstream aggregation calculation unit is valid and should be aggregated to which target node according to the control flow when obtaining the source node data in each clock. The 16 node data are divided into two groups of 0-7 and 8-15 and flow in parallel in the circular array. Therefore, it only takes 8 clock cycles to let each target vertex traverse all the source vertices.

[0066] Embodiment 3

[0067] Based on Embodiment 1 and Embodiment 2, this embodiment further discloses the following content:

[0068] During the process of slice fusion, there are cases of data conflicts. The static priority scheduling strategy is used to solve the computational task conflict problem that occurs during the slice fusion process. Specifically:

[0069] Judgment is made according to the control flow signal. When there are two or more computational tasks in a certain aggregation computing unit in a certain clock cycle, one of them is executed first, and the remaining computational tasks will be scheduled to be executed when the aggregation computing unit is idle later.

[0070] Figure 2 The red grids in represent that in the same clock cycle, an APE has multiple computational tasks to execute. Figure 2 The result of deploying the example in to the computing array is as Figure 3 shown. For APE(0,0), in the 2nd clock cycle after the start of the calculation, according to the requirements after slice fusion, it is necessary to complete two computational tasks of aggregating source node 2 to target node 0 and aggregating source node 10 to target node 8. TMR-GCN sets the static priority order according to the slice number. In the clock cycle with computational task conflicts, the computational tasks from the slice with a smaller number are calculated first, and the remaining computational tasks are scheduled to be completed in the subsequent idle clock cycles of this APE. Since in the 3rd clock cycle, APE(0,0) has a computational task to complete, and in the 4th clock cycle APE(0,0) is idle, the task that was not completed in the second clock cycle can be completed at this time.

[0071] Encoding the data in the dataset is specifically as follows:

[0072] After the adjacency matrix is divided into multiple slices, each slice adopts an improved COO encoding, no longer stores the absolute coordinates of non-zero elements, but uses the slice identifier plus the relative coordinates within the slice, which simplifies the decoding process. The slice identifier is divided into a slice group identifier and an intra-group slice identifier. The data within the same slice is stored in ascending order of the relative coordinates within the slice.

[0073] The control flow signal is generated by decoding the encoded adjacency matrix using the shift decoder in the preprocessing module. As Figure 4 shown, all the slices involved in one slice fusion are called a slice group. Specifically:

[0074] Read the data of a slice group from the Edge Bank (Edge Bank is used to store the edge data after COO encoding).

[0075] If the slice fusion factor is m, then each decoding module needs to generate m 2 control flows in parallel. These control flows can be divided into m groups, and each group of m control flows belongs to a target node. Each control flow corresponds to a source node within a slice of this target node.

[0076] Since the data of multiple nodes share an Edge Bank, it is necessary to sort the data read from the Edge Bank.

[0077] In the Sort Module (the Sort Module distributes edge information to the corresponding cache according to the prefix of the input edge data), there is a Buffer for each control flow. The data input to the Sort Module will be sent to the corresponding Buffer (the Buffer is used to store the edge data waiting for decoding) according to its in-group slice identifier, and wait for the start signal generated by the control flow.

[0078] When the slice size is Tile_size, the control flow register is also Tile_size bits, and each bit is used to control the aggregation task for one clock cycle.

[0079] After the start signal arrives, the control flow register shifts one bit to the right every clock cycle. At the same time, the Bit Counter (the BitCounter is used to record the number of the bit currently being decoded in the control flow) increments by 1 every clock cycle.

[0080] When the data at the top of the Buffer is equal to the value of the Bit Counter, the leftmost data position of the corresponding control flow register is set to 1, and at the same time, the data at the top of the Buffer is popped. After Tile_size clock cycles, the decoding is completed.

[0081] After that, when the aggregation starts, the control flow register shifts one bit to the right every clock cycle, and the rightmost data bit of this register is used as a control signal, serving as a flag to judge whether there is an aggregation task.

[0082] The comparison results of the acceleration performance of the present invention on multiple public data sets with other accelerators are shown in Table 1:

[0083] Table 1

[0084]

[0085] The same or similar reference numerals correspond to the same or similar components;

[0086] The terms describing the positional relationship in the drawings are for illustrative purposes only and should not be construed as a limitation of this patent;

[0087] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A slice fusion-based aggregation computing hardware architecture for graph neural networks based on FPGA, characterized in that, It includes a preprocessing module, a memory, a storage control module, a controller, and an aggregation computing unit array, where: The input of the preprocessing module is a graph neural network model and a data set. The preprocessing module generates control signals according to the graph neural network model and the data set and sends them to the controller. At the same time, the data in the data set is encoded and sent to the memory for storage; The storage control module is used to send the data stored in the memory to the aggregation computing unit array; The controller sends control signals to the aggregation computing unit array; The aggregation computing unit array determines whether to perform aggregation computing according to the control signal flow, and the aggregation computing unit array performs aggregation computing according to the data stored in the memory; The data set is the adjacency matrix of the graph. Both dimensions of the adjacency matrix are used to represent the numbers of all nodes in the graph. When there is a connection between two nodes, the corresponding coordinate point of the adjacency matrix is 1, otherwise it is 0; The encoding of the data in the data set is specifically as follows: After the adjacency matrix is divided into multiple slices, each slice uses an improved COO encoding. The slice identifier is divided into a slice group identifier and an intra-group slice identifier. The data within the same slice is stored in ascending order of the relative coordinates within the slice; The control signal flow is generated by decoding the encoded adjacency matrix using a shift decoder in the preprocessing module. Specifically: Judge according to the slice group identifier of the data and read the data of a slice group; If the slicing fusion factor is m, each shift decoder needs to parallelly complete the generation of m 2 streams of control signals. These streams of control signals are divided into m groups, with m streams of control signals in each group belonging to a target node, and each stream of control signals corresponding to a source node within a slice of the target node; Sort the read data; Send the data to the corresponding control signal flow registers according to the intra-group slice identifier and wait for the start signal generated by the control flow; When the slice size is Tile_size, the control signal flow register is also Tile_size bits. Each bit is used to control the aggregation task of one clock cycle, and the recorder is incremented by 1 every clock cycle; When the data at the top of the control signal flow register is equal to the value of the recorder, the data position at the leftmost side of the corresponding control signal flow register is set to 1, and at the same time, the data at the top of the control signal flow register is popped until after Tile_size clock cycles, the decoding is completed; After that, when the aggregation starts, the control signal flow register is shifted one bit to the right every clock cycle. The rightmost data bit of the control signal flow register is used as the control signal and serves as a flag to judge whether there is an aggregation task.

2. The hardware architecture for slice fusion-based aggregation calculation of graph neural network based on FPGA according to claim 1, wherein The aggregation computing unit array includes M×N aggregation computing units. The M×N aggregation computing units are arranged in an array, with a total of M rows and N columns. Among them, the aggregation computing units in each row process the aggregation tasks of a group of target vertices. The aggregation computing units in different columns within the same row process different dimensions of data of the target vertices. The aggregation computing units in the same column are connected end to end to form a ring structure.

3. The hardware architecture for slice fusion-based aggregation calculation of graph neural networks based on FPGA according to claim 2, characterized in that, If the dimension of the adjacency matrix is greater than the size of the aggregation computing unit array, the adjacency matrix needs to be sliced.

4. The hardware architecture for slice fusion-based aggregation calculation of graph neural network based on FPGA according to claim 3, characterized in that, When the slice size is Tile_size, where Tile_size <= 128 and the number of slice fusions is m 2 the time required to complete the aggregation of m 2 slices is Tile_size clock cycles, and the time required to complete the single-layer aggregation of the entire image is: In the formula, Vertices_num is the number of vertices in the graph, and clk_period is the clock cycle.

5. The hardware architecture for slice fusion-based aggregation calculation of graph neural network based on FPGA according to claim 4, characterized in that, Each of the M×N aggregation computing units includes a set of target node registers, and the target node registers receive the control signal stream sent by the controller and determine which source node should be aggregated to the target node at the current time according to the control signal stream.

6. The hardware architecture for slice fusion-based aggregation calculation of graph neural networks based on FPGA according to claim 5, wherein In each clock cycle, each aggregation computing unit stores the intermediate results of the aggregation calculation of m target vertices, and can receive the feature vectors of m source vertices at the same time. Each target vertex has a set of control signal streams. The aggregation computing unit will judge according to the control signal stream whether there is an aggregation task at present. If so, it will locate the target vertex to be aggregated according to which set of control streams has valid signals, and obtain the specific source vertex information according to the position of the valid signals in the set of control signal streams, and aggregate it to the corresponding target vertex.

7. The hardware architecture for slice fusion-based aggregation calculation of graph neural networks based on FPGA according to claim 6, wherein Use the static priority scheduling strategy to solve the calculation task conflict problem that appears in the slicing fusion process. Specifically: Judge according to the control signal stream. When there are two or more calculation tasks in a certain aggregation computing unit in a certain clock cycle, one of them will be executed first, and the remaining calculation tasks will be scheduled to be executed when the aggregation computing unit is idle later.

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