Method of manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided herein. The method includes forming a metal layer in a substrate, and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-fill layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first through hole communicating with the opening in the gap-fill layer, and broadening an upper portion of the opening to form a trench. The method includes performing a third etching step to remove the gap-fill layer located at the bottom of the opening, and deepening the depth of the trench and the opening. The method includes forming a second through hole communicating with the opening in the barrier layer to expose the metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a dual damascene process. Background Art

[0002] In the process of semiconductor devices, in order to connect semiconductor elements to control circuits, an interconnection structure is formed on the semiconductor elements. The interconnection structure is a multi-layer structure, which includes multiple insulating layers and metal layers formed in the insulating layers. In the process of forming the interconnection structure, the insulating layer is usually etched to form vias or trenches. Then, metal is filled into the vias or trenches to form conductive plugs or conductive lines respectively.

[0003] The dual damascene process is often used to form the interconnection structure. According to the formation sequence of vias and trenches, the dual damascene process can be divided into two types: via first and trench first. The size of vias is smaller, and the lithography process for forming vias is more difficult than that for forming trenches. The via first process performs the lithography process for forming vias on a flat plane. Therefore, compared with the trench first process, the via first process has easier process control and a larger process window.

[0004] In order to form an interconnection structure with a multi-layer structure, the dual damascene process can be repeated several times. More specifically, after forming the first layer of metal layer (for example, conductive plugs and / or conductive lines) in the first layer of insulating layer, a barrier layer is formed on the first layer of metal layer. Then, a second layer of insulating layer is formed on the barrier layer. When the second layer of insulating layer is etched to form vias, this barrier layer can be used as an etch stop layer. In other words, this etching process stops after the barrier layer is exposed.

[0005] In the existing via-first process, in order to avoid the leakage of metal in the metal layer during the process and cause contamination, the surface of the metal layer is covered with the above-mentioned barrier layer. However, the coefficient of thermal expansion (CTE) of the barrier layer usually does not match that of the metal layer. When receiving the thermal energy in the process, the stress caused by the CTE mismatch will cause protrusions on the surface of the metal layer, thereby making the surface of the barrier layer covering the metal layer uneven. Moreover, the size, quantity, and position of the protrusions on the metal layer cannot be controlled. Therefore, when performing the existing via-first dual-damascene process, during the etching process of forming vias, the protrusions on the metal layer may be exposed. Furthermore, the barrier layer located on the protrusions of the metal layer may be affected by stress and change the arrangement of its molecules. Therefore, the etching rate of the barrier layer may increase, exposing the underlying metal layer. In this way, the metal (e.g., copper) in the metal layer may leak out and spread in the insulating layer, on the surface of the substrate, in the process chamber, and / or in the gas pipeline, thereby causing uncontrollable contamination and reducing the yield and reliability of the product.

[0006] To solve the above-mentioned contamination problem caused by metal, in the existing dual-damascene process, the following methods are adopted to avoid the formation of protrusions on the metal layer. In some prior arts, before forming the barrier layer, a pretreatment process is performed on the metal layer, e.g., pre-anneal. In some other prior arts, a gas (e.g., hydrogen, nitrogen, or a mixed gas of hydrogen and nitrogen) is added during the pre-anneal of the metal layer. In some other prior arts, before forming the barrier layer, a silicon-containing precursor (e.g., SiH 4 ) is used to treat the surface of the metal layer. However, these methods cannot completely avoid the generation of protrusions on the surface of the metal layer. Even if the number of protrusions can be reduced, these methods may also increase the resistance value of the metal layer, which is not conducive to the operation of the semiconductor device.

[0007] On the other hand, in the existing via-first process, during the etching of forming vias, the insulating layer at the bottom of the via needs to be completely removed. When the barrier layer is removed subsequently, if the insulating layer at the bottom of the via is not completely removed, it may not be possible to completely expose the surface of the metal layer, thereby resulting in too high a resistance value or failure of the conductive plug. To avoid this problem, in the existing via-first process, the insulating layer is usually over-etched to ensure the exposure of the barrier layer. However, to avoid the contamination problem caused by metal, the barrier layer cannot be etched through during the etching of forming vias. Therefore, the control of the etching process is very difficult. When the device is miniaturized (i.e., the thickness of the barrier layer becomes thinner), the control of the etching process will be even more difficult.

[0008] Therefore, in the technical field, there is still a need for semiconductor devices with high yield and high reliability and their manufacturing methods. Summary of the Invention

[0009] An embodiment of the present invention provides a method for manufacturing a semiconductor device, which can avoid the metal contamination problem of the existing via-first process.

[0010] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, including: forming a metal layer in a substrate; forming a barrier layer on the substrate so that the barrier layer covers the metal layer; forming an insulating layer on the barrier layer; performing a first etching step to form an opening in the insulating layer, wherein after the first etching step, the opening does not expose the barrier layer; after the first etching step, forming a gap filling layer on the insulating layer and filling the opening, wherein the gap filling layer has a flat top surface; performing a second etching step to form a first via communicating with the opening in the gap filling layer and removing a part of the insulating layer to widen the upper part of the opening to form a trench, wherein after the second etching step, a part of the gap filling layer is located at the bottom of the opening; performing a third etching step to remove the gap filling layer located at the bottom of the opening and deepen the depth of the trench and the depth of the opening; and forming a second via communicating with the opening in the barrier layer to expose the metal layer.

[0011] In the method for manufacturing a semiconductor device provided by the embodiment of the present invention, by controlling the etching depth in the first etching step, it is possible to avoid exposing the metal layer before performing the third etching step. Therefore, it is possible to avoid the contamination caused by the metal, and thus significantly improve the yield and reliability of the semiconductor device. Brief Description of the Drawings

[0012] Figures 1A to 1E Schematic cross-sectional views of semiconductor devices in various process stages according to some embodiments of the present invention.

[0013] Figures 2A to 2D Schematic cross-sectional views of semiconductor devices in various process stages according to other embodiments of the present invention.

[0014] The reference symbols are as follows:

[0015] 100: Semiconductor device

[0016] 200: Semiconductor device

[0017] 102: Substrate

[0018] 104: Metal layer

[0019] 106: Barrier layer

[0020] 108: Insulating layer

[0021] 112: Gap filling layer

[0022] 114: Mask layer

[0023] 115: Opening

[0024] 115a: First opening

[0025] 115b: Second opening

[0026] 115c: Third opening

[0027] 116: Patterned photoresist layer

[0028] 125: Groove

[0029] 132: Conductive plug

[0030] 134: Conductive line

[0031] 135: First through hole

[0032] 135a: First protrusion

[0033] 135b: Second protrusion

[0034] 145: Second through hole

[0035] D1: First depth

[0036] D2: Second depth

[0037] D3: Third depth

[0038] H1: First height

[0039] H2: Second height

[0040] S1: Shortest distance

[0041] T1: First thickness. Detailed implementation mode

[0042] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following provides preferred embodiments and, in conjunction with the accompanying drawings, makes detailed descriptions as follows. Furthermore, repeated reference symbols and / or words may be used in different examples of the present invention. These repeated symbols or words are for the purpose of simplification and clarity and are not used to limit the relationship between each embodiment and / or the described appearance structure.

[0043] Herein, the terms "about" and "approximately" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The given quantity is an approximate quantity, meaning that the meaning of "about" and "approximately" can still be implied without specific description.

[0044] The present invention provides a method for manufacturing a semiconductor device, Figures 1A to 1ESchematic cross-sectional views of semiconductor device 100 according to some embodiments of the present invention at various stages of the process.

[0045] Please refer to Figure 1A , a metal layer 104 is formed in the substrate 102. More specifically, an opening or trench can be formed in the substrate 102, and then a metal material is filled into this opening or trench. After that, a planarization process (e.g., chemical mechanical polishing process) is performed to remove the excess metal material. After the planarization process, the substrate 102 and the metal layer 104 have a flat top surface.

[0046] The material of the substrate 102 can include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon-on-insulator (SOI), other suitable materials, or a combination of the above materials. In this embodiment, the substrate 102 is a silicon substrate. In some embodiments, other structures can also be formed in the substrate 102, such as isolation structures, p-type implantation regions, or n-type implantation regions (not shown). The material of the metal layer 104 can include copper, aluminum, silver, gold, or other suitable metals. In this embodiment, the metal layer 104 is copper. The metal layer 104 can be formed by a suitable deposition process, such as chemical vapor deposition process, atomic layer deposition process, electroplating process, or a combination of the above processes.

[0047] Next, a barrier layer 106 is formed on the substrate 102, and the barrier layer 106 covers the metal layer 104. After that, an insulating layer 108 is formed on the barrier layer 106. The barrier layer 106 can prevent the metal in the metal layer 104 from leaking out during the process and causing contamination. The material of the barrier layer 106 can include nitrides, carbonitrides, or other suitable barrier materials. In this embodiment, the barrier layer 106 is silicon carbonitride (SiCN). The material of the insulating layer 108 can include oxides, nitrides, oxynitrides, other suitable insulating materials, or a combination of the above. In this embodiment, the insulating layer 108 is silicon oxide. The barrier layer 106 and the insulating layer 108 can be formed independently by a suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, or other suitable deposition processes.

[0048] Next, a first etching step is performed to form an opening 115 in the insulating layer 108. In some embodiments, after the first etching step, the opening 115 does not expose the barrier layer 106, as Figure 1A shown. The first etching step can include an anisotropic etching step. In this embodiment, the first etching step is a dry etching step.

[0049] Please refer to Figure 1B, after the first etching step, a gap-fill layer 112 is formed on the insulating layer 108 to fill the opening 115. The gap-fill layer 112 has a flat top surface. Then, a mask layer 114 is formed on the gap-fill layer 112, and a patterned photoresist layer 116 is formed on the mask layer 114. The position of the opening in the patterned photoresist layer 116 corresponds to the position of the opening 115, and the diameter of the opening in the patterned photoresist layer 116 is larger than the diameter of the opening 115 to expose the mask layer 114 above the gap-fill layer 112 filled in the opening 115. In some embodiments, the gap-fill layer 112 is a material with better fluidity, and the gap-fill layer 112 has a flat top surface. Therefore, the mask layer 114 and the patterned photoresist layer 116 each independently have a substantially uniform thickness. Furthermore, the thickness of the patterned photoresist layer 116 can be the same as that of the photoresist layer in a general lithography process. In this way, the production efficiency can be improved.

[0050] In some embodiments, the gap-fill layer 112, the mask layer 114, and the patterned photoresist layer 116 can be a photoresist stack structure commonly used in the lithography process. For example, the gap-fill layer 112 can include a bottom anti-reflective coating (BARC) material. In some embodiments, the gap-fill layer 112 can be an organic anti-reflective material or an inorganic anti-reflective material, such as silicon oxycarbide (SiOC). For example, the mask layer 114 can be a Si-rich BARC material. In some embodiments, the mask layer 114 can be silicon-rich silicon oxide, silicon-rich silicon oxynitride, or silicon-rich silicon oxycarbide. The patterned photoresist layer 116 can include a general photoresist material. It should be noted that the present invention does not limit the photoresist stack structure to be composed of only three layers, and the number of layers of the mask layer 114 can be adjusted according to the requirements of the lithography process and subsequent etching process.

[0051] Please refer to Figure 1C , using the patterned photoresist layer 116 as a mask to perform a second etching step to remove part of the mask layer 114, the gap-fill layer 112, and the insulating layer 108. After the second etching step, a first through hole 135 communicating with the opening 115 is formed in the gap-fill layer 112, and the upper part of the opening 115 is widened to form a trench 125. Furthermore, after the second etching step is completed, there is still a remaining gap-fill layer 112 at the bottom of the opening 115, and the top surface of the remaining gap-fill layer 112 is lower than the bottom surface of the trench 125. The second etching step can include an anisotropic etching step. In this embodiment, the second etching step is a dry etching step.

[0052] Please refer to Figure 1D, a third etching step is performed to remove the remaining gap-fill layer 112 located at the bottom of the opening 115, and at the same time, to deepen the depth of the bottom surface of the trench 125 and the depth of the bottom surface of the opening 115. Then, the barrier layer 106 exposed by the opening 115 is removed to expose the metal layer 104. After the third etching step, a second through hole 145 communicating with the opening 115 is formed in the barrier layer 106. In this embodiment, while removing the barrier layer 106 exposed by the opening 115, the depth of the bottom surface of the trench 125 can be deepened again. In this way, it is easy to control the depth of the bottom surface of the trench 125 to be the third depth D3. The third etching step may include an anisotropic etching step. In this embodiment, the third etching step is a dry etching step.

[0053] Please refer to Figure 1E , and a metal material is filled into the opening 115 having the trench 125. Then, a planarization process (e.g., chemical mechanical polishing process) is performed to remove the excess metal material. After the planarization process, a conductive line 134 is formed in the trench 125, a conductive plug 132 is formed in the opening 115 below the trench 125, and the top surface of the conductive line 134 is coplanar with the top surface of the insulating layer 108. The materials and formation methods of the conductive plug 132 and the conductive line 134 may be the same as or similar to those of the metal layer 104, and will not be described in detail herein.

[0054] After that, other existing processes may be performed to complete the semiconductor device 100. For example, the process shown in Figures 1A to 1E may be repeated one or more times as required according to the actual situation. In this way, an interconnect structure with a multi-layer structure can be formed.

[0055] In the manufacturing method of the semiconductor device 100 provided in this embodiment, by controlling the etching depth in the first etching step, exposure of the metal layer before the third etching step can be avoided. Such a method can significantly improve the yield and reliability of the semiconductor device, and will not significantly increase the process complexity and production cost.

[0056] Please refer to Figure 1A, after the first etching step, the opening 115 does not expose the barrier layer 106. In this way, even if protrusions are generated on the surface of the metal layer 104, exposure of the metal layer before the third etching step can still be avoided. The depth of the opening 115 can be adjusted by controlling the etching parameters of the first etching step (for example, etching gas, etching time, etching power, etc.). For example, argon, oxygen, nitrogen, carbon monoxide, a gas containing carbon, hydrogen and fluorine, or a combination of the above can be used as the etching gas, and the etching time can be controlled between about 10 seconds and about 300 seconds. In some embodiments, the insulating layer 108 has a first thickness T1, and after the first etching step, the opening 115 has a first depth D1. To make the control of the subsequent third etching step easier, the ratio T1 / D1 of the first thickness T1 to the first depth D1 can be 1.0 - 2.0. In some embodiments, the bottom surface of the opening 115 formed after the first etching step and before the second etching step has a shortest distance S1 from the top surface of the barrier layer 106, and the shortest distance S1 is 50 - 500 nm. To make the control of the subsequent third etching step easier, the ratio T1 / S1 of the first thickness T1 to the shortest distance S1 can be 5.0 - 20.0.

[0057] Please refer to Figure 1C , after the second etching step, a part of the gap filling layer 112 remains at the bottom of the opening 115. In the second etching step, the etching rate of the insulating layer 108 can be the same as or close to the etching rate of the gap filling layer 112. Therefore, the cross-sectional profiles of the opening 115 and the trench 125 can be well controlled. The etching rates of the insulating layer 108 and the gap filling layer 112 can be adjusted by controlling the etching parameters of the second etching step (for example, etching gas, etching time, etching power, etc.). In some embodiments, in the second etching step, the ratio (R1 / R2) of the etching rate R1 of the insulating layer 108 to the etching rate R2 of the gap filling layer 112 is 0.5 - 3.0.

[0058] Please refer to Figure 1D , in this embodiment, after the third etching step, the barrier layer 106 located at the bottom of the opening 115 is removed to expose the metal layer 104. In the third etching step, the etching rate of the insulating layer 108 can be the same as or close to the etching rate of the barrier layer 106. Therefore, the barrier layer 106 located at the bottom of the opening 115 can be completely removed. The etching rates of the insulating layer 108 and the barrier layer 106 can be adjusted by controlling the etching parameters of the third etching step (for example, etching gas, etching time, etching power, etc.). In this embodiment, in the third etching step, the ratio R3 / R4 of the etching rate R3 of the insulating layer 108 to the etching rate R4 of the barrier layer 106 is 0.5 - 3.0.

[0059] In another embodiment not shown, with the barrier layer 106 as the etch stop layer, a third etching step is performed. After the third etching step, the barrier layer 106 at the bottom of the opening 115 is not completely removed. In such an embodiment, after the third etching step, a fourth etching step can be performed to remove the barrier layer 106 at the bottom of the opening 115. After the fourth etching step, the opening 115 exposes the metal layer 104, as Figure 1D shown. In such an embodiment, in the third etching step, the etching rate of the insulating layer 108 can be much greater than that of the barrier layer 106. Therefore, the barrier layer 106 can be used as the etch stop layer for the third etching step. Furthermore, in the fourth etching step, the etching rate of the barrier layer 106 can be much greater than that of the insulating layer 108. Therefore, the cross-sectional profiles of the opening 115 and the trench 125 can be well controlled, and it can be ensured that the barrier layer 106 at the bottom of the opening 115 is completely removed. The etching rates of the insulating layer 108 and the barrier layer 106 can be adjusted by controlling the etching parameters (such as etching gas, etching time, etching power, etc.) of the third etching step and the fourth etching step. In such an embodiment, in the third etching step, the ratio R5 / R6 of the etching rate R5 of the insulating layer 108 to the etching rate R6 of the barrier layer 106 is 3.0 - 20.0, and in the fourth etching step, the ratio R7 / R8 of the etching rate R7 of the barrier layer 106 to the etching rate R8 of the insulating layer 108 is 3.0 - 20.0.

[0060] Please refer to Figure 1C . After the second etching step and before the third etching step, the trench 125 has a second depth D2. Please refer to Figure 1D . After this third etching step, the trench 125 has a third depth D3. In some embodiments, the ratio D3 / D2 of the third depth D3 to the second depth D2 is 1.2 - 2.0. In this way, the cross-sectional profiles of the opening 115 and the trench 125 can be well controlled, and the trench 125 can have a sufficiently large depth such that the resistance value of the conductive line 134 is low.

[0061] Figures 2A to 2D FIG. is a cross-sectional schematic diagram of the semiconductor device 200 according to other embodiments of the present invention at various stages of the process. In Figures 2A to 2D , the same reference numerals are used to denote elements identical to those Figures 1A to 1D shown. For the sake of simplicity, the elements identical to those Figures 1A to 1D shown and their forming process steps are not described in detail herein.

[0062] Figure 2A is similar to Figure 1A , except that Figure 2A the metal layer 104 has two protrusions. In other words,Figures 2A to 2D An embodiment is illustrated in which the metal layer has a plurality of protrusions. In this embodiment, the coefficient of thermal expansion of the barrier layer 106 is less than that of the metal layer 104. In some embodiments, the metal layer 104 has a first coefficient of thermal expansion, the barrier layer 106 has a second coefficient of thermal expansion, and the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is 9.0 - 15.0.

[0063] In some embodiments, referring to Figure 2A , before the first etching step, the first protrusion 135a has a first height H1. The second protrusion 135b has a second height H2, and the second height H2 is less than the first height H1. Then, the first etching step is performed to form a first opening 115a, a second opening 115b, and a third opening 115c in the insulating layer 108. Among them, the first opening 115a is located above the first protrusion 135a, and the second opening 115b is located above the second protrusion 135b.

[0064] As Figure 2A shown, the barrier layer 106 conformally formed on the metal layer with protrusions has a non-flat surface. In addition, in one embodiment, the insulating layer 108 also has a non-flat top surface. In the manufacturing method of the semiconductor device provided in the embodiments of the present invention, the depth of the opening formed in the first etching step can be determined according to the height of the protrusion. Therefore, it is possible to avoid exposing the metal layer before the third etching step. More specifically, the height of each protrusion can be measured on one of a plurality of wafers using the same process by a transmission electron microscope, and the maximum height can be determined. Then, the depth of the opening after the first etching step is determined according to the maximum height of the protrusion.

[0065] In this embodiment, after the first etching step, the maximum height of the protrusion is the first height H1, as Figure 2A shown. The bottom surface of the first opening 115a (the second opening 115b or the third opening 115c) has the shortest distance S1 from the top surface of the barrier layer 106. The ratio S1 / H1 of the shortest distance S1 to the maximum height H1 is 0.5 - 5.0. In some embodiments, the shortest distance S1 is 50 - 500 nm. In some embodiments, the insulating layer 108 has a first thickness T1. After the first etching step, the first opening 115a (the second opening 115b or the third opening 115c) has a first depth D1. The ratio T1 / D1 of the first thickness T1 to the first depth D1 is 1.0 - 2.0. The ratio T1 / S1 of the first thickness T1 to the shortest distance S1 can be 5.0 - 20.0. Therefore, the barrier layer 106 is not exposed after the first etching step.

[0066] Figures 2B to 2D respectively withFigures 1B to 1D Similar, the difference is that the position of the opening of the patterned photoresist layer 116 corresponds to the positions of the first opening 115a, the second opening 115b, and the third opening 115c at the same time, and the diameter of the opening of the patterned photoresist layer 116 is larger than the sum of the diameters of the first opening 115a, the second opening 115b, and the third opening 115c.

[0067] Please refer to Figure 2C , and perform a second etching step to form a trench 125 that communicates with the first opening 115a, the second opening 115b, and the third opening 115c at the same time. Furthermore, in the second etching step, the etching rate of the insulating layer 108 can be the same as or similar to the etching rate of the gap filling layer 112. Therefore, in this embodiment, after the second etching step, the top surfaces of the gap filling layer 112 remaining in the first opening 115a, the second opening 115b, and the third opening 115c are coplanar with each other.

[0068] Please refer to Figure 2D , and perform a third etching step to remove the barrier layer 106 located at the bottoms of the first opening 115a, the second opening 115b, and the third opening 115c to expose the metal layer 104.

[0069] In another embodiment, after the third etching step, the barrier layer 106 located in the first opening 115a, the second opening 115b, and the third opening 115c is not removed. Subsequently, a fourth etching step can be performed to remove the barrier layer 106 located at the bottoms of the first opening 115a, the second opening 115b, and the third opening 115c to expose the metal layer 104.

[0070] After that, other existing processes can be performed to complete the semiconductor device 200. For example, the processes shown in Figure 1E can be performed to form conductive plugs and conductive lines. Furthermore, an interconnect structure with a multi-layer structure can also be formed.

[0071] It should be understood that Figure 2A the number, size, and relative positions of the protrusions shown are only for illustration and are not intended to limit the present invention. For example, in other embodiments, one protrusion can be located directly below a plurality of openings (i.e., the area of the protrusion is larger than the area of the opening).

[0072] In summary, in the method for manufacturing a semiconductor device provided by the embodiments of the present invention, by retaining a part of the insulating layer at the bottom of the opening formed in the first etching step, exposure of the metal layer before the third etching step can be avoided. Therefore, contamination caused by the metal can be avoided, and thus the yield and reliability of the semiconductor device can be significantly improved. Furthermore, in the method for manufacturing a semiconductor device provided by the embodiments of the present invention, only the etching depth in the first etching step needs to be adjusted to avoid contamination caused by the metal. In addition, in the method for manufacturing a semiconductor device provided by the embodiments of the present invention, even if the metal layer forms a protrusion, contamination caused by the metal can still be avoided. In other words, before forming the barrier layer, no pretreatment process needs to be performed on the metal layer. Therefore, such a manufacturing method can be easily integrated into the existing process without additional replacement or modification of production equipment. In this way, the complexity and production cost of the process will not be significantly increased.

[0073] Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the claims.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, comprising: forming a metal layer in a substrate; forming a barrier layer on the substrate to cover the metal layer; forming an insulating layer on the barrier layer; performing a first etching step to form an opening in the insulating layer, wherein after the first etching step, the opening does not expose the barrier layer, and wherein after forming the insulating layer, the metal layer has a plurality of protrusions, and the opening is located above at least one of the plurality of protrusions; after the first etching step, forming a gap filling layer on the insulating layer and filling the opening, wherein the gap filling layer has a flat top surface; performing a second etching step to form a first through hole communicating with the opening in the gap filling layer and removing a part of the insulating layer to widen an upper part of the opening to form a trench, wherein after the second etching step, a part of the gap filling layer is located at the bottom of the opening; performing a third etching step to remove the gap filling layer located at the bottom of the opening and deepen the depth of the trench and the depth of the opening; and forming a second through hole communicating with the opening in the barrier layer to expose the metal layer.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, further comprising: forming a patterned photoresist layer on the gap filling layer, wherein the patterned photoresist layer has a photoresist opening, the position of the photoresist opening corresponds to the position of the opening, and the diameter of the photoresist opening is larger than the diameter of the opening, wherein the second etching step uses the patterned photoresist layer as a mask.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, the insulating layer has a first thickness T1, and after the first etching step and before the second etching step, the opening has a first depth D1, and wherein the ratio T1 / D1 of the first thickness T1 to the first depth D1 is 1.0 - 2.

0.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, after the first etching step and before the second etching step, the bottom surface of the opening and the top surface of the barrier layer have a shortest distance S1, and the shortest distance S1 is 50 - 500 nm.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, performing the third etching step includes: after removing the gap filling layer located at the bottom of the opening, using the barrier layer as an etching stop layer to deepen the depth of the bottom surface of the trench and the depth of the bottom surface of the opening at the same time; and removing the barrier layer exposed by the opening to expose the metal layer, wherein when removing the barrier layer, the depth of the bottom surface of the trench is deepened again.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, the metal layer has a first coefficient of thermal expansion, the barrier layer has a second coefficient of thermal expansion, and the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is 9.0 - 15.

0.

7. The manufacturing method of the semiconductor device as described in claim 1, characterized in that, in the third etching step, the second through hole is formed, and the ratio of the etching rate of the insulating layer to the etching rate of the barrier layer is 0.5 - 3.

0.

8. The manufacturing method of the semiconductor device as described in claim 1, characterized in that, the second through hole is formed in a fourth etching step after the third etching step. In the third etching step, the ratio of the etching rate of the insulating layer to the etching rate of the barrier layer is 3.0 - 20.0, and in the fourth etching step, the ratio of the etching rate of the barrier layer to the etching rate of the insulating layer is 3.0 - 20.

0.

9. The manufacturing method of the semiconductor device as described in claim 1, characterized in that, before performing the third etching step, the trench has a second depth D2, after the third etching step, the trench has a third depth D3, and the ratio D3 / D2 of the third depth D3 to the second depth D2 is 1.2 - 2.

0.

10. The manufacturing method of the semiconductor device as described in claim 1, characterized in that, further comprising: after forming the insulating layer, measuring the height of each of the plurality of protrusions, wherein the plurality of protrusions have a maximum height H1; and determining a first depth D1 of the opening after the first etching step according to the maximum height H1.

11. The manufacturing method of the semiconductor device as described in claim 10, characterized in that, after the first etching step, a bottom surface of the opening and a top surface of the barrier layer have a shortest distance S1, and the ratio S1 / H1 of the shortest distance S1 to the maximum height H1 is 0.5 - 5.0.

Images