Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame includes a carrier and a plurality of pins surrounding the carrier. Each pin has a top surface and a first bottom surface relative to each other, an inner end and an outer end. Each pin forms a recess around the first bottom surface, and the recess has an arc-shaped recess surface. The outer end connects the top surface and the first bottom surface with a flat side wall and one side of the arc-shaped recess surface. The chip is arranged on the carrier and electrically connected to the pins. The packaging colloid covers the lead frame and the chip, and its lower surface is exposed and cut flush with the first bottom surface of each pin. The conductive material layer is arranged on the first bottom surface and the arc-shaped recess surface of each pin. The side surface of the packaging colloid is cut flush with the flat side wall of each pin and exposes the conductive material layer on the side of the arc-shaped recess surface of the outer end. The semiconductor packaging structure of the present invention has better bonding strength.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, the pursuit of miniaturized packaging has led to the emergence of Dual Flat No-Lead (DFN) and Quad Flat No-Lead (QFN) packages, both of which offer smaller footprints and superior heat dissipation, quality stability, and electrical performance, making them widely used in various packaging structures.

[0003] Generally speaking, double-sided flat no-lead packages and four-sided flat no-lead packages only use the bottom surface with the pins exposed as the external electrical connection point. In this case, the limited wettable area often cannot provide sufficient bonding strength between the package structure and external components (such as a printed circuit board), which in turn leads to electrical abnormalities or failures. Therefore, the technology of exposing the side walls of the pins and forming wettable flanks with a stepped structure has begun to be applied to increase the wettable area of ​​the pins and improve the bonding strength of the package structure electrically connected to the printed circuit board. However, the above-mentioned stepped wettable flanks are still limited by the area exposed in the package structure and cannot significantly improve the bonding strength of the pins electrically connected to the printed circuit board. Summary of the Invention

[0004] The present invention is directed to a semiconductor packaging structure, the pins of which have better bonding strength.

[0005] The present invention is also directed to a method for manufacturing a semiconductor package structure, which is used to manufacture the above-mentioned semiconductor package structure.

[0006] According to an embodiment of the present invention, a semiconductor packaging structure includes a lead frame, a chip, an encapsulant, and a conductive material layer. The lead frame includes a carrier and a plurality of pins surrounding the carrier. Each pin has a top surface and a first bottom surface opposite to each other, an inner end, and an outer end, wherein the inner end faces the carrier. Each pin forms a recess around the first bottom surface, and the recess has an arc-shaped recess surface. The outer end connects the top surface and the first bottom surface with a flat sidewall and one side of the arc-shaped recess surface. The chip is arranged on the carrier and electrically connected to the pins. The encapsulant covers the lead frame and the chip. The encapsulant has a bottom surface and a side surface, wherein the bottom surface is exposed and aligned with the first bottom surface of each pin, and the encapsulant separates the recesses of the pins. The conductive material layer is arranged on the first bottom surface and the arc-shaped recess surface of each pin, wherein the side surface of the encapsulant is aligned with the flat sidewall of each pin and exposes the conductive material layer on the side of the arc-shaped recess surface of the outer end.

[0007] In the semiconductor package structure according to the embodiment of the present invention, the surface of the arc-shaped recess is a rough surface.

[0008] In the semiconductor package structure according to the embodiment of the present invention, the distance from the arc-shaped recess surface of each lead to the center of each lead gradually increases from the first bottom surface to the top surface.

[0009] In the semiconductor packaging structure according to an embodiment of the present invention, the inner end of each of the above-mentioned pins has a recess at the first bottom surface, and the packaging colloid fills the recess. The inner end connects the top surface and the first bottom surface through the first side wall, the second bottom surface and the other side of the arc-shaped recess surface covered with a conductive material layer.

[0010] In the semiconductor package structure according to the embodiment of the present invention, the conductive material layer is made of lead-free solder.

[0011] According to an embodiment of the present invention, a method for manufacturing a semiconductor package structure includes the following steps: providing a semi-finished package, comprising a lead frame strip, a plurality of chips, and an encapsulant; the lead frame strip having a plurality of lead frame units and a plurality of connecting bars connecting the lead frame units; each lead frame unit including a support seat and a plurality of pins surrounding the support seat; the outer end of each pin being connected to one of the adjacent connecting bars; the pins of two adjacent lead frame units being arranged opposite each other and forming a plurality of connecting portions on one of the corresponding connecting bars; the bottom of each connecting portion having a groove; the chips being respectively arranged on the support seats of the lead frame units and electrically connected to the pins; and the encapsulant covering the chips and the lead frame strip, wherein the encapsulant fills the grooves of the connecting portions, and the lower surface of the encapsulant is exposed and aligned with the first bottom surface of each pin. forming an etching mask in the center of the first bottom surface of each pin, so that the etching mask exposes the periphery of each first bottom surface. performing an etching process on the semi-finished package, so that each pin forms a recess around the first bottom surface; wherein the encapsulant separates the recesses of the pins, and each recess has an arc-shaped recess surface. The encapsulant in the groove is removed to expose the inner surface of each connecting portion. A conductive material layer is formed on the first bottom surface of each pin and in the recess. A singulation process is performed to cut the encapsulant and the connecting portion to form independent semiconductor package structures, wherein each semiconductor package structure includes a lead frame having a carrier and pins surrounding the carrier, each chip, the encapsulant, and a conductive material layer. Each pin has a top surface and a first bottom surface opposite to each other, an inner end, and an outer end, the inner end facing the carrier, the first bottom surface of each pin and the surface of the arc-shaped recess formed around each pin from the first bottom surface are configured with a conductive material layer, the outer end connects the top surface and the first bottom surface with a flat sidewall and one side of the arc-shaped recess surface, and one side surface of the encapsulant is cut flush with the flat sidewall of each pin to expose the conductive material layer on that side of the arc-shaped recess surface of the outer end.

[0012] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the surface of the arc-shaped recess is a rough surface.

[0013] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the distance from the arc-shaped recess surface of each lead to the center of each lead gradually increases from the first bottom surface to the top surface.

[0014] In the method for manufacturing a semiconductor packaging structure according to an embodiment of the present invention, the inner end of each of the above-mentioned pins has a recess at the first bottom surface, and the packaging colloid fills the recess, and the inner end connects the top surface and the first bottom surface through the first side wall, the second bottom surface and the other side of the arc-shaped recess surface covered with a conductive material layer.

[0015] In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the conductive material layer is made of lead-free solder.

[0016] Based on the above, in the design of the semiconductor package structure of the present invention, a recessed cavity is formed around the bottom of the lead, with an arcuate recessed surface. This allows the conductive material layer to be disposed not only on the first bottom surface of the lead but also on the arcuate recessed surface around the bottom of the lead. Therefore, the lead having an arcuate recessed surface around the bottom can increase the bonding area and amount of the conductive material layer, thereby increasing the area and amount of the conductive material layer on the lead exposed to the semiconductor package structure, thereby improving the bonding strength of the semiconductor package structure and the bonding yield with external terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A is a schematic top view of a semi-finished package of a semiconductor package structure according to an embodiment of the present invention;

[0018] Figures 1B to 1F yes Figure 1A A cross-sectional schematic diagram of a method for manufacturing a semiconductor packaging structure;

[0019] Figure 2 yes Figure 1F A bottom view schematic diagram of a semiconductor package structure;

[0020] Figure 3A yes Figure 1F A partial three-dimensional schematic diagram of the pins of the semiconductor package structure;

[0021] Figure 3B FIG. 1 is a partial three-dimensional schematic diagram of pins of a semiconductor package structure according to another embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 10: packaging semi-finished products;

[0024] 20: semiconductor packaging structure;

[0025] 100: conductor frame;

[0026] 110: lead frame unit;

[0027] 110', 110": conductor rack;

[0028] 111: bearing seat;

[0029] 112, 112': pin;

[0030] 112A: Outer end;

[0031] 112B: medial end;

[0032] 120: connecting strip;

[0033] 121: connecting portion;

[0034] 200: chip;

[0035] 300: encapsulation colloid;

[0036] 301: lower surface;

[0037] 302: side surface;

[0038] 400: etching mask;

[0039] 500: conductive material layer;

[0040] 1111: Bottom;

[0041] 1121: first bottom surface;

[0042] 1122: Depression;

[0043] 1123: concave;

[0044] 1124: top surface;

[0045] 1125: plane side wall;

[0046] 1126: first side wall;

[0047] 1127: second bottom surface;

[0048] 1211: Bottom;

[0049] 1212: groove;

[0050] 1213: inner surface;

[0051] S: arc-shaped concave surface;

[0052] S1, S2: side. DETAILED DESCRIPTION

[0053] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0054] Directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply absolute orientation. Unless expressly stated otherwise, any method described herein is in no way intended to be construed as requiring its steps to be performed in a specific order.

[0055] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

[0056] Figure 1A The figure is a top view of a semi-finished package of a semiconductor package structure according to an embodiment of the present invention. Figures 1B to 1F yes Figure 1A A cross-sectional schematic diagram of a method for manufacturing a semiconductor packaging structure. Figure 2 yes Figure 1F A bottom view schematic diagram of a semiconductor package structure. Figure 3A yes Figure 1F A partial three-dimensional schematic diagram of the pins of a semiconductor package structure. Figure 3B FIG. 1 is a partial three-dimensional schematic diagram of the pins of a semiconductor package structure according to another embodiment of the present invention. It should be noted that: Figure 1A The partial top view of the semi-finished package product 10 in the lower right portion omits the encapsulation colloid 300 to clearly illustrate the structure of the semi-finished package product 10 .

[0057] Regarding the manufacturing method of the semiconductor package structure of this embodiment, first, please refer to Figure 1A , providing a package semi-finished product 10. The package semi-finished product 10 includes a lead frame bar 100, a plurality of chips 200 and a packaging gel 300. The lead frame bar 100 has a plurality of lead frame units 110 and a plurality of connecting bars 120 connecting the plurality of lead frame units 110. The lead frame units 110 are arranged in a matrix and separated by the connecting bars 120. Each lead frame unit 110 includes a carrier 111 and a plurality of pins 112 surrounding the carrier 111, wherein the outer end 112A of each pin 112 is connected to an adjacent connecting bar 120, and the pins 112 of two adjacent lead frame units 110 are arranged opposite to each other and form a plurality of connecting portions 121 on the corresponding connected connecting bars 120.

[0058] Next, please also refer to Figure 1A and Figure 1B, the bottom of each connecting portion 121 has a groove 1212. In the present embodiment, the grooves 1212 of each connecting portion 121 are interconnected to form a single elongated groove extending along the connecting bar 120. However, in other embodiments not shown, the grooves 1212 of each connecting portion 121 may be individual grooves, so that a plurality of grooves separated from each other are formed on the connecting bar 120. The present invention does not limit the form and number of the grooves. The chips 200 are respectively arranged on the supporting bases 111 of the lead frame unit 110 and are electrically connected to the pins 112. Here, the chip 200 is electrically connected to the pins 112 by wire bonding, but is not limited to this electrical connection method.

[0059] Next, please refer to Figure 1A and Figure 1B The encapsulant 300 covers the chip 200 and the lead frame strip 100. The inner end 112B of each lead 112 has a recess 1122 on the first bottom surface 1121. The encapsulant 300 fills the recesses 1122 of the lead 112 and the groove 1212 of the connecting portion 121. The lower surface 301 of the encapsulant 300 is exposed and flush with the first bottom surface 1121 of each lead 112. Filling the recesses 1122 of the lead 112 with the encapsulant 300 secures the lead 112 within the encapsulant 300, preventing the lead 112 from falling out of the encapsulant 300. Furthermore, in this embodiment, the lower surface 301 of the encapsulant 300 also exposes the bottom surface 1111 of the carrier 111. However, in other embodiments not shown, the bottom surface 1111 of the carrier 111 may be covered by the encapsulant 300 and not exposed.

[0060] Afterwards, please refer to Figure 1C , forming an etching mask 400 at the center of the first bottom surface 1121 of each pin 112, so that the etching mask 400 exposes the periphery of each first bottom surface 1121. In the present embodiment, the etching mask 400 also covers the bottom surface 1111 of the carrier 111. Here, it should be noted that, in the present embodiment, the etching mask 400 covering the bottom surface 1111 of the carrier 111 and the center of the first bottom surface 1121 of the pin 112 is, for example, an insulating material. In other embodiments, the etching mask 400 covering the bottom surface 1111 of the carrier 111 and the center of the first bottom surface 1121 of the pin 112 may also be a metal material, wherein the metal material is, for example, gold, palladium or other metals that can be selectively etched, but the present invention is not limited thereto.

[0061] Next, please also refer to Figure 1C and Figure 1DThe semi-finished package product 10 is subjected to an etching process, so that the etching solution begins to isotropically etch the periphery of the first bottom surface 1121 of each lead 112 that is not covered by the etching mask 400, thereby forming a cavity 1123 around the first bottom surface 1121 of each lead 112, wherein the encapsulation glue 300 separates these cavities 1123 of these leads 112 (please refer to Figure 2 Here, the etching process, for example, involves placing the semi-finished package product 10 in a copper etching solution, causing the copper etching solution to perform isotropic etching inwardly from the periphery of the first bottom surface 1121 of the lead 112 not covered by the etching mask 400, thereby exposing the periphery of the first bottom surface 1121 of the lead 112 and forming recesses 1123 inwardly of the lead 112. Preferably, each recess 1123 has an arcuate recess surface S, and the arcuate recess surface S is, for example, a rough surface.

[0062] Next, in this embodiment, since the etching mask 400 covering the bottom surface 1111 of the carrier 111 and the center of the first bottom surface 1121 of the pin 112 is made of an insulating material, the etching process ( Figure 1D ) and then forming the conductive material layer 500 in the manufacturing method ( Figure 1E ), the etching mask 400 covering the carrier 111 and the pins 112 is removed. It should be noted that in other embodiments, when the etching mask 400 is made of a metal material, the etching mask 400 can be removed or retained before the conductive material layer 500 is formed, and this still falls within the scope of protection of the present invention.

[0063] Afterwards, please refer to Figure 1E , the encapsulation colloid 300 in the groove 1212 is removed to expose the inner surface 1213 of each connecting portion 121. Next, a conductive material layer 500 is formed on the first bottom surface 1121 of each pin 112 and in the cavity 1123. Here, the conductive material layer 500 is arranged on the surrounding surface surrounding the pin 112 (i.e., the arc-shaped cavity surface S) and the first bottom surface 1121. It should be noted that in this embodiment, the encapsulation colloid 300 in the groove 1212 is removed by laser irradiation, for example, but not limited to this. Here, the material of the conductive material layer 500 is, for example, lead-free solder, but not limited to this. The method of forming the conductive material layer 500 includes electroplating, printing, etc. In this embodiment, the conductive material layer 500 is also formed on the bottom surface 1111 of the carrier 111 and the inner surface 1213 of the connecting portion 121, which still falls within the scope of protection of the present invention. In addition, the rough arc-shaped recessed surface S can make the conductive material layer 500 adhere to the arc-shaped recessed surface S better, and the rough arc-shaped recessed surface S can also reduce the generation of metal burrs during the subsequent singulation process.

[0064] In particular, in this embodiment, since the bottom of each pin 112 is surrounded by a recess 1123, when the conductive material layer 500 is formed on the arc-shaped recess surface S of the pin 112 (for example, by 360-degree tin plating on the side surface of the pin 112), the bonding area of ​​the conductive material layer 500 can be increased, thereby increasing the area and amount of the conductive material layer 500 on the pin 112 exposed to the semiconductor package structure 20, thereby improving the subsequent completion of the semiconductor package structure 20 (please refer to Figure 1F ) The bonding strength of the electrical connection and the bonding yield with the external terminals.

[0065] Finally, please also refer to Figure 1E and Figure 1F , a singulation process is performed to cut the encapsulation body 300 and the connection portion 121 so that a side surface 302 of the encapsulation body 300 is aligned with the plane side wall 1125 of each lead 112 and the conductive material layer 500 on the side S1 of the arc-shaped recess surface S of the outer end 112A is exposed, thereby forming each independent semiconductor package structure (at Figure 1F Only one semiconductor package structure 20 is schematically shown in FIG.

[0066] Regarding the structure, please refer to Figure 1F The semiconductor package structure 20 includes a lead frame 110' having a carrier 111 and a plurality of leads 112 surrounding the carrier 111, a chip 200, an encapsulant 300, and a conductive material layer 500. Each lead 112 has a top surface 1124 and a first bottom surface 1121 facing each other, an inner end 112B, and an outer end 112A. The conductive material layer 500 is disposed on the first bottom surface 1121 of each lead 112 and on an arcuate recessed surface S formed around each lead 112 from the first bottom surface 1121. The outer end 112A connects the top surface 1124 and the first bottom surface 1121 with a planar sidewall 1125 and a side S1 of the arcuate recessed surface S. Inner end 112B faces carrier 111 and connects top surface 1124 and first bottom surface 1121 via first sidewall 1126, second bottom surface 1127, and the other side S2 of arc-shaped recessed surface S covered with conductive material layer 500. Side surface 302 of encapsulant 300 is flush with planar sidewall 1125 of each lead 112, exposing conductive material layer 500 on one side S1 of arc-shaped recessed surface S of outer end 112A.

[0067] In this embodiment, please also refer to Figure 1F and Figure 3A After the etching process, each pin 112 is formed into a funnel-shaped shape, that is, the distance from the arc-shaped concave surface S of each pin 112 to the center of each pin 112 gradually increases from the first bottom surface 1121 to the top surface 1124. However, each pin 112' of the lead frame 110" may also be as Figure 3BThe hourglass shape with an inwardly tapered neck is formed as shown, which is still within the scope of protection of the present invention. Because the semiconductor package structure 20 of this embodiment forms a cavity 1123 around the bottom of the lead 112 and forms a conductive material layer 500 in the cavity 1123, the conductive material layer 500 is disposed on the first surface 1121 of the lead 112 and the surrounding arc-shaped cavity surface S. Compared to conventional lead 112s with a stepped structure, the lead 112 of this embodiment with an arc-shaped cavity surface S can increase the bonding area of ​​the conductive material layer 500 (i.e., increase the wettable area of ​​the lead 112), thereby improving the electrical bonding strength of the semiconductor package structure 20.

[0068] In summary, in the semiconductor package structure of the present invention, a recessed cavity is formed around the bottom of the lead, with an arcuate recessed surface. This allows the conductive material layer to be disposed not only on the first bottom surface of the lead but also on the arcuate recessed surface around the bottom of the lead. Therefore, the lead having an arcuate recessed surface around the bottom can increase the bonding area and amount of the conductive material layer, thereby increasing the area and amount of the conductive material layer on the lead exposed to the semiconductor package structure, thereby improving the bond strength of the semiconductor package structure's electrical connection and the yield rate of bonding with external terminals.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A lead frame comprising a support base and a plurality of pins surrounding the support base, wherein each of the plurality of pins has a top surface and a first bottom surface facing each other, an inner end, and an outer end, wherein the inner end faces the support base, each of the plurality of pins forms a recess around the first bottom surface, and the recess has an arc-shaped recess surface, and the outer end connects the top surface and the first bottom surface with a planar sidewall and one side of the arc-shaped recess surface; A chip is disposed on the carrier and electrically connected to the plurality of pins; an encapsulant covering the lead frame and the chip, the encapsulant having a lower surface and a side surface, wherein the lower surface exposes and is flush with the first bottom surface of each of the plurality of pins, and the encapsulant separates the recess of each of the plurality of pins; as well as A conductive material layer is configured on the first bottom surface and the arc-shaped recess surface of each of the plurality of pins, wherein the side surface of the encapsulant is flush with the planar sidewall of each of the plurality of pins and exposes the conductive material layer on the one side of the arc-shaped recess surface of the outer end, wherein the inner end of each of the plurality of pins has a recess at the first bottom surface, and the encapsulant fills the recess, and the inner end connects the top surface and the first bottom surface with the first sidewall, the second bottom surface, and the other side of the arc-shaped recess surface covered with the conductive material layer.

2. The semiconductor package structure according to claim 1, wherein: The surface of the arc-shaped recess is a rough surface.

3. The semiconductor package structure according to claim 1, wherein: A distance from the arc-shaped recess surface of each of the plurality of pins to the center of each of the plurality of pins gradually increases from the first bottom surface toward the top surface.

4. The semiconductor package structure according to claim 1, wherein: The conductive material layer is made of lead-free solder.

5. A method for manufacturing a semiconductor packaging structure, characterized in that: include: A package semi-finished product is provided, the package semi-finished product comprising a lead frame strip, a plurality of chips, and an encapsulation resin, the lead frame strip having a plurality of lead frame units and a plurality of connecting bars connecting the plurality of lead frame units, each of the plurality of lead frame units comprising a carrier and a plurality of pins surrounding the carrier, an outer end of each of the plurality of pins being connected to one of the adjacent plurality of connecting bars, the plurality of pins of two adjacent plurality of lead frame units being arranged opposite to each other in pairs and forming a plurality of connecting portions on one of the correspondingly connected plurality of connecting bars, the bottom of each of the plurality of connecting portions having a groove, the plurality of chips being respectively arranged on the carrier of each of the plurality of lead frame units and electrically connected to the plurality of pins, and the encapsulation resin covering the plurality of chips and the lead frame strip, wherein the encapsulation resin fills the groove of each of the plurality of connecting portions, and the bottom surface of the encapsulation resin is exposed and flush with the first bottom surface of each of the plurality of pins; forming an etching mask at the center of the first bottom surface of each of the plurality of pins, so that the etching mask exposes the periphery of the first bottom surface; performing an etching process on the semi-finished package product so that each of the plurality of leads forms a cavity around the first bottom surface, wherein the encapsulation colloid separates the cavity of each of the plurality of leads, and the cavity has an arc-shaped cavity surface; removing the encapsulant in the groove to expose an inner surface of each of the plurality of connecting portions; forming a conductive material layer on the first bottom surface of each of the plurality of pins and in the cavity; as well as A singulation process is performed to cut the encapsulant and the plurality of connecting portions to form a plurality of independent semiconductor package structures, wherein each of the plurality of semiconductor package structures includes a lead frame having the carrier and the plurality of pins surrounding the carrier, one of the plurality of chips, the encapsulant, and the conductive material layer, each of the plurality of pins having a top surface and the first bottom surface opposite to each other, an inner end, and the outer end, the inner end facing the carrier, the first bottom surface of each of the plurality of pins and the surface of the arc-shaped recess formed around each of the plurality of pins from the first bottom surface are configured with the conductive material layer, the outer end has a planar sidewall connecting the top surface and the first bottom surface to one side of the arc-shaped recess surface, and a side surface of the encapsulant is aligned with the planar sidewall of each of the plurality of pins and exposes the conductive material layer on the one side of the arc-shaped recess surface of the outer end.

6. The method for manufacturing a semiconductor package structure according to claim 5, wherein: The surface of the arc-shaped recess is a rough surface.

7. The method for manufacturing a semiconductor package structure according to claim 5, wherein: A distance from the arc-shaped recess surface of each of the plurality of pins to the center of each of the plurality of pins gradually increases from the first bottom surface toward the top surface.

8. The method for manufacturing a semiconductor package structure according to claim 5, wherein: The inner end of each of the plurality of pins has a recess at the first bottom surface, and the encapsulation colloid fills the recess. The inner end connects the top surface and the first bottom surface through the first side wall, the second bottom surface, and the other side of the arc-shaped recess surface covered with the conductive material layer.

9. The method for manufacturing a semiconductor package structure according to claim 5, wherein: The conductive material layer is made of lead-free solder.

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