Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a wafer comprising a substrate and a buried power supply rail in the substrate; a via in the substrate at a back surface of the wafer and exposing the buried power supply rail; a capacitor structure in the via, comprising a first electrode on a bottom and a sidewall of the via, a second electrode disposed opposite the sidewall of the first electrode, and a capacitor dielectric layer between the first electrode and the second electrode, the first electrode being in contact with the buried power supply rail; a first power supply line on the back surface of the wafer and electrically connected with the first electrode; and a second power supply line on the back surface of the wafer and electrically connected with the second electrode. The capacitor structure in the via can increase the capacitor density and the capacitor value per unit area, which is conducive to improving the filtering effect of the capacitor structure on the power supply, and the first electrode is in contact with the buried power supply rail, so that the first power supply line can supply power to the buried power supply rail through the first electrode, which is compatible with the back surface power distribution process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] To meet the needs of continuous logic chip miniaturization, when the metal spacing is very close, in order to optimize the power supply capability of the power supply, a current method is to move the power supply rail downward into the substrate to form a buried power rail (BPR). The buried power rail is beneficial to release the wiring resources of the interconnection, and can also provide a lower resistance local current distribution, and in addition, is beneficial to improve the write margin and read speed.

[0003] In a device with a buried power rail, a backside power delivery network (Backside PDN) technology is usually used. The backside power delivery network is built on the back of the wafer, and uses a micro through silicon via (μTSV) conductive structure to connect the power supply network to the buried power rail, and then transmits power to the standard components through the buried power rail. The backside power delivery network technology is beneficial to improve the chip area utilization, reduce the complexity of the back-end-of-line process, and in addition, can improve the problem of IR drop and improve system performance.

[0004] Among them, in the backside power delivery network technology, a MIM (Metal-Insulator-Metal) capacitor is also provided on the back of the wafer, which is used to filter the power supply to improve the stability of the power supply.

[0005] However, the performance of the current device still needs to be improved. SUMMARY

[0006] The problem solved by the embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to increase the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitance structure on the power supply, and is beneficial to compatibility with the backside power delivery process.

[0007] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a wafer comprising opposite front and back surfaces, the wafer comprising a substrate and a buried power rail located in the substrate, the bottom surface of the substrate being the back surface; a via located in the substrate of the back surface of the wafer and exposing the buried power rail; a capacitor structure located in the via, comprising a first electrode located on the bottom and sidewall of the via, a second electrode arranged opposite to the sidewall of the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, the first electrode being in contact with the buried power rail; a first power line located on the back surface of the wafer and electrically connected with the first electrode; and a second power line located on the back surface of the wafer and electrically connected with the second electrode.

[0008] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a wafer comprising opposite front and back surfaces, the wafer comprising a substrate and a buried power rail located in the substrate, the bottom surface of the substrate being the back surface; etching the back surface of the wafer to form a via exposing the buried power rail in the substrate; forming a capacitor structure in the via, comprising a first electrode located on the bottom and sidewall of the via, a second electrode arranged opposite to the sidewall of the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, the first electrode being in contact with the buried power rail; and forming a first power line electrically connected with the first electrode and a second power line electrically connected with the second electrode on the back surface of the wafer.

[0009] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0010] In the semiconductor structure provided by the embodiment of the present application, the capacitor structure is located in the via, and the two electrodes of the capacitor structure are electrically connected with the first power line and the second power line respectively, for filtering the power supply; the capacitor structure is located in the via, and the first electrode and the second electrode extend along the direction of the sidewall of the via, which is conducive to increasing the effective area between the first electrode and the second electrode and improving the chip area utilization rate, and correspondingly increasing the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitor structure on the power supply and further improving the performance of the device; in addition, the capacitor structure is located in the via, and the first electrode is in contact with the buried power rail, so that the first power line can supply power to the buried power rail through the first electrode, which is compatible with the backside power delivery network (Backside PDN) process, thereby improving the process compatibility.

[0011] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming a capacitor structure in the through hole; forming a first power supply line electrically connected with the first electrode and a second power supply line electrically connected with the second electrode; the two electrodes of the capacitor structure are electrically connected with the first power supply line and the second power supply line respectively, and the capacitor structure is used for filtering the power supply. The capacitor structure is formed in the through hole, and the first electrode and the second electrode extend along the direction of the side wall of the through hole, which is beneficial to increase the effective area between the first electrode and the second electrode, improve the chip area utilization rate, increase the capacitance density and the capacitance value on the unit area, and thus improve the filtering effect of the capacitor structure on the power supply, and further improve the performance of the device. In addition, the capacitor structure is formed in the through hole, and the first electrode is in contact with the buried power supply rail, so that the first power supply line can supply power to the buried power supply rail through the first electrode, which is compatible with the back power distribution process, and improves the process compatibility. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 FIG. 1 is a structure schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0013] Figure 2 FIG. 2 is a structure schematic diagram of another semiconductor structure according to an embodiment of the present application;

[0014] Figures 3 to 8 FIG. 3 is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure according to an embodiment of the present application;

[0015] Figures 9 to 12 FIG. 4 is a structure schematic diagram corresponding to each step in a forming method of a semiconductor structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0016] As known from the background, the performance of the device still needs to be improved.

[0017] Specifically, in the back power distribution technology, an MIM capacitor is further arranged on the back of the wafer, and the upper and lower plates of the MIM capacitor are connected with VDD and VSS respectively, which is used for filtering the power supply to improve the stability of the power supply.

[0018] However, the MIM capacitor arranged on the back of the wafer is a planar structure, the effective area between the electrode plates of the MIM capacitor is small, the capacitance density on the unit area is low, and the capacitance value is small, which leads to poor filtering effect of the MIM capacitor, and the performance of the device still needs to be improved.

[0019] To solve the technical problem, the embodiment of the present application provides a semiconductor structure, comprising: a wafer comprising opposite front and back surfaces, the wafer comprising a substrate and a buried power rail located in the substrate, the bottom surface of the substrate being the back surface; a via located in the substrate of the back surface of the wafer and exposing the buried power rail; a capacitor structure located in the via, comprising a first electrode located on the bottom and sidewall of the via, a second electrode located opposite the sidewall of the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, the first electrode being in contact with the buried power rail; a first power line located on the back surface of the wafer and electrically connected to the first electrode; and a second power line located on the back surface of the wafer and electrically connected to the second electrode.

[0020] In the semiconductor structure provided by the embodiment of the present application, the capacitor structure is located in the via, and the two electrodes of the capacitor structure are electrically connected to the first power line and the second power line, respectively, for filtering the power supply; the capacitor structure is located in the via, and the first electrode and the second electrode extend in the direction of the sidewall of the via, which is conducive to increasing the effective area between the first electrode and the second electrode, improving the chip area utilization rate, correspondingly increasing the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitor structure on the power supply and further improving the performance of the device; in addition, the capacitor structure is located in the via, and the first electrode is in contact with the buried power rail, so that the first power line can supply power to the buried power rail through the first electrode, which is compatible with the back surface power distribution process, thereby improving the process compatibility.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings. Reference is made to Figure 1 , Figure 1 (a) is a sectional view, Figure 1 (b) is Figure 1 (a) is a corresponding top view, showing a structure schematic diagram of an embodiment of the semiconductor structure of the present application.

[0022] In the embodiment, the semiconductor structure comprises: a wafer 200 comprising opposite front and back surfaces 21 and 22, the wafer 200 comprising a substrate 100 and a buried power rail 130 located in the substrate 100, the bottom surface of the substrate 100 being the back surface 22; a via 170 (such as a through hole) located in the substrate of the back surface of the wafer and exposing the buried power rail 130; a capacitor structure 150 located in the via 170, comprising a first electrode 151 located on the bottom and sidewall of the via 170, a second electrode 152 located opposite the sidewall of the first electrode 151, and a capacitor dielectric layer 153 located between the first electrode 151 and the second electrode 152, the first electrode 151 being in contact with the buried power rail 130; a first power line 110 located on the back surface of the wafer and electrically connected to the first electrode 151; and a second power line 120 located on the back surface of the wafer and electrically connected to the second electrode 152. Figure 5(a) shown) in the substrate 100 on the back side 22 of the wafer 200 and exposing the buried power rail 130; a capacitor structure 300 in the via 170, including a first electrode 31 on the bottom and sidewall of the via 170, a second electrode 32 disposed opposite the sidewall of the first electrode 31, and a capacitor dielectric layer 33 between the first electrode 31 and the second electrode 32, the first electrode 31 being in contact with the buried power rail 130; a first power line 210 on the back side 22 of the wafer 200 and electrically connected to the first electrode 31; and a second power line 220 on the back side 22 of the wafer 200 and electrically connected to the second electrode 32.

[0023] The back side 22 of the wafer 200 is used to provide a process platform for forming the capacitor structure 300 and the power lines.

[0024] In this embodiment, the wafer 200 is a wafer for completing device fabrication, and therefore, the substrate 100 on the front side 21 of the wafer 200 has a device structure (not shown) formed thereon.

[0025] In this embodiment, the device structure includes a channel structure 110 protruding from the substrate 100 in a direction away from the back side 22, a gate structure (not shown) across the channel structure 110 and covering part of the top surface and part of the sidewall of the channel structure 110, and source / drain doped regions (not shown) in the channel structure 110 on both sides of the gate structure. Taking the device structure as an example of a fin field effect transistor (FinFET), the channel structure 110 corresponds to a fin.

[0026] In this embodiment, the device structure further includes a shallow trench isolation 120 on the exposed substrate 100 of the channel structure 110, covering part of the sidewall of the channel structure 110. The shallow trench isolation 120 is used to achieve isolation between the channel structures 110 and also to achieve isolation between the substrate 100 and the gate structure.

[0027] The device structure can further include other functional structures, such as resistors, inductors, etc.

[0028] The front side 21 of the wafer 200 can also be bonded to another wafer.

[0029] It should be noted that the front side 21 of the wafer 200 can further have an interconnection structure layer (not shown) formed on the device structure, including multiple layers of back-end-of-line metal interconnection lines and conductive plugs for electrically connecting adjacent layers of metal interconnection lines.

[0030] As an example, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0031] In this embodiment, the back surface 22 includes a first region (not shown) for electrically connecting a first power line and a second region (not shown) for electrically connecting a second power line.

[0032] The buried power rails (BPRs) 130 are used to provide power to different components of the chip. In this embodiment, the buried power rails 130 are located in the substrate 100, which helps to free up wiring resources for the back-end interconnects and reduces the height of the standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails 130 also help to provide a lower resistive local current distribution.

[0033] The buried power rail 130 is an elongated structure, parallel to the extending direction of the trench structure 110, and spaced apart from it. As an example, the buried power rail 130 extends longitudinally (e.g., along the longitudinal direction). Figure 1 (b) As shown in the y-direction, the direction perpendicular to the longitudinal direction is the transverse direction (as shown in the y-direction). Figure 1 (b) shows the x-direction).

[0034] In this embodiment, there are multiple buried power rails 130, which extend longitudinally and are arranged at intervals in the transverse direction.

[0035] The buried power rail 130 is made of a conductive material. In this embodiment, the buried power rail 130 is made of a metallic material, such as one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al. By selecting these materials, the resistivity of the buried power rail 130 is low, which is beneficial for improving RC delay and increasing the processing speed of the chip.

[0036] In this embodiment, the buried power rail 130 is located in the substrate 100 and the shallow trench isolation 120.

[0037] In this embodiment, a covering medium layer 150 is also formed in the shallow trench isolation 120 to cover the buried power rail 130 near the front end 21.

[0038] The covering dielectric layer 150 is used to isolate the buried power rail 130 from the gate structure, or to isolate the buried power rail 130 from other conductive structures.

[0039] The material of the covering dielectric layer 150 is a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the covering dielectric layer 150 is made of the same material as the shallow trench isolation 120, which is advantageous for improving process compatibility.

[0040] In this embodiment, an insulating layer 140 is formed between the buried power rail 130 and the substrate 100, between the buried power rail 130 and the shallow trench isolation 120, and between the covering dielectric layer 150 and the shallow trench isolation 120.

[0041] The insulating layer 140 is used to insulate the buried power rail 130 from the substrate 100. Therefore, the material of the insulating layer 140 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0042] In this embodiment, the semiconductor structure further comprises a passivation layer 160 on the back surface 22 of the wafer 200.

[0043] The passivation layer 160 is used to protect the back surface 22 of the wafer 200 and to isolate the substrate 100 from the conductive structure on the back surface 22 of the wafer 200.

[0044] The material of the passivation layer 160 is one or both of silicon oxide and silicon nitride. In this embodiment, the material of the passivation layer 160 is silicon nitride.

[0045] The via 170 is used to provide a spatial position for forming the capacitor structure 300. The via 170 exposes the buried power rail 130, which is used to make the buried power rail 130 contact the first electrode 31, so that the buried power rail 130 is electrically connected to an external circuit through the first electrode 31.

[0046] In this embodiment, the number of vias 170 is multiple, and the multiple vias 170 are arranged in an array. The vias 170 are arranged in an array, and correspondingly, the number of capacitor structures 300 is multiple, and the multiple capacitor structures 300 are arranged in an array, which is advantageous for further improving the density and capacitance of the capacitor structures 300 per unit area, and thus significantly improving the performance of the semiconductor structure.

[0047] Specifically, in this embodiment, the number of buried power rails 130 is multiple, and the multiple buried power rails 130 extend in the longitudinal direction (i.e., the y direction) and are arranged in the lateral direction (i.e., the x direction) with intervals. A plurality of vias 170 are formed on one buried power rail 130.

[0048] In this embodiment, the via 170 is a micro through silicon via (μTSV), and the depth and opening size of the via 170 are relatively small to meet the demand for continuous reduction in device size.

[0049] In this embodiment, the via hole 170 also penetrates the passivation layer 160.

[0050] In this embodiment, the semiconductor structure further comprises an isolation layer 180 between the first electrode 31 and the substrate 100 on the side wall of the via hole 170, and between the first electrode 31 and the substrate 100 on the bottom of the via hole 170. The isolation layer 180 is used to isolate the substrate 100 and the first electrode 31. In this embodiment, the material of the isolation layer 180 is silicon oxide.

[0051] The two electrodes of the capacitor structure 300 are electrically connected with the first power supply line 210 and the second power supply line 220 respectively, for filtering the power supply.

[0052] In this embodiment, the capacitor structure 300 is located in the via hole 170, and the first electrode 31 and the second electrode 32 extend along the direction of the side wall of the via hole 170, which is conducive to increasing the effective area between the first electrode 31 and the second electrode 32, improving the chip area utilization rate, and correspondingly increasing the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitor structure 300 on the power supply, and further improving the performance of the device. In addition, the capacitor structure 300 is located in the via hole 170, and the first electrode 31 is in contact with the buried power supply track 130, so that the first power supply line 210 can supply power to the buried power supply track 130 from the back of the wafer 200 through the first electrode 31, which is compatible with the back power distribution process, thereby improving the process compatibility.

[0053] In this embodiment, the number of capacitor structures 300 is multiple, and the multiple capacitor structures 300 are arranged in an array, which is conducive to increasing the number and density of capacitor structures 300 per unit area, and the capacitance value, and correspondingly further improving the filtering effect of the capacitor structure 300 on the power supply.

[0054] The first electrode 31 is used as the bottom plate of the capacitor, the second electrode 32 is used as the top plate of the capacitor, and the capacitor dielectric layer 33 is used to realize the electrical isolation between the first electrode 31 and the second electrode 32.

[0055] The materials of the first electrode 31 and the second electrode 32 are conductive materials, and the material of the capacitor dielectric layer 33 is a dielectric material.

[0056] In this embodiment, the capacitor structure 300 is a MIM (Metal-Insulator-Metal) capacitor.

[0057] Therefore, the material of the first electrode 31 and the second electrode 32 is a metal material, including one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and AL.

[0058] In this embodiment, the material of the capacitor dielectric layer 33 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. By selecting a high-k dielectric material, the capacitance of the MIM capacitor can be improved, and the capacitance density can be improved accordingly. The high-k dielectric material can be any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0059] Specifically, the capacitor dielectric layer 33 is a high-k dielectric layer formed by stacking, i.e., the capacitor dielectric layer 33 is a high-k composite dielectric layer. After the high-k dielectric layer is formed to a certain thickness, the formation quality is prone to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the capacitor dielectric layer 33 meets the process requirements, and at the same time, the formation quality is good.

[0060] In this embodiment, the capacitor dielectric layer 33 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer and a second ZrO2 layer formed by stacking.

[0061] In other embodiments, according to process requirements, the material of the capacitor dielectric layer can also be one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0062] In this embodiment, the capacitor structure 300 includes the first electrode 31 located on the bottom and sidewall of the via 170, the capacitor dielectric layer 33 located on the first electrode 31, and the second electrode 32 located on the capacitor dielectric layer 33 and filled in the via 170.

[0063] In this embodiment, the first electrode 31 also extends to the first region, and the second electrode 32 also extends to cover the second region, and exposes the first electrode 31 in the first region.

[0064] The first electrode 31 also extends to the first region, and the second electrode 32 exposes the first electrode 31 in the first region, so as to electrically connect the first power supply line 210 and the first electrode 31.

[0065] The second electrode 32 extends to cover the second region, so as to electrically connect the second power supply line 220 and the second electrode 32.

[0066] The first power line 210 and the second power line 220 are used to supply power to the device structure inside the wafer 200.

[0067] In the embodiment, the first power line 210 and the second power line 220 are located on the back surface 22 of the wafer 200, so that the backside power delivery network (Backside PDN) is used, which is beneficial to improve the chip area utilization rate, reduce the complexity of the back-end-of-line process, improve the IR drop problem, and improve the system performance.

[0068] In the embodiment, the first power line 210 and the second power line 220 are respectively electrically connected to the first electrode 31 and the second electrode 32, so that the capacitor structure 300 can filter the power supply.

[0069] In the embodiment, the capacitor structure 300 is located in the via hole 170, which is beneficial to the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitor structure 300 on the power supply. In addition, the first electrode 31 is in contact with the buried power rail 130, so that the first power line 210 can supply power to the buried power rail 130 through the first electrode 31, which is compatible with the backside power delivery process, thereby improving the process compatibility.

[0070] In the embodiment, the material of the first power line 210 and the second power line 220 is a conductive material, for example, one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0071] The power sources accessed by the first power line 210 and the second power line 220 are different. The first power line 210 is a voltage power source VDD, and the second power line 220 is a ground power source VSS. Alternatively, the first power line 210 is a ground power source VSS, and the second power line 220 is a voltage power source VDD.

[0072] Specifically, according to the type of power source required to be accessed by each buried power rail 130, the type of power source accessed by the first power line 210 is determined, and the type of power source accessed by the second power line 220 is determined accordingly. In the embodiment, the types of power sources required to be accessed by the buried power rails 130 located at different positions are different.

[0073] In the embodiment, the first power line 210 is located on the first region and is electrically connected to the first electrode 31, and the second power line 220 is located on the second region and is electrically connected to the second electrode 32.

[0074] In the embodiment, the semiconductor structure further comprises a dielectric layer 230 on the back surface 22 of the wafer 200. Accordingly, the first power line 210 and the second power line 220 are located in the dielectric layer 230.

[0075] The dielectric layer 230 is used to realize the electrical isolation between the first power line 210 and the second power line 220. The material of the dielectric layer 230 is a dielectric material. In the embodiment, the material of the dielectric layer 230 is silicon oxide.

[0076] Figure 2 is a structure schematic diagram of another embodiment of the semiconductor structure of the present application. The same as the foregoing embodiments will not be described here again, and the difference between the present embodiment and the foregoing embodiments is that:

[0077] In the embodiment, the capacitor structure 400 is a vertical stacked structure; the first electrode 41 comprises a bottom electrode 411 located at the bottom of the via hole 170 and in contact with the buried power rail 130, and a plurality of side electrodes 412 protruding from the bottom electrode 411 and arranged in intervals; and the second electrode 42 is located in the gap between the side electrodes 412.

[0078] The capacitor structure 400 is a vertical stacked structure, the number of the side electrodes 412 is multiple, and the number of the second electrodes 42 is also multiple, which is beneficial to further improve the capacitance density and the capacitance value per unit area, thereby significantly improving the performance of the device.

[0079] In the embodiment, the side electrode 412 located at the most edge position is in contact with the sidewall of the via hole 170.

[0080] In the embodiment, part of the first electrode 41 is retained on the back surface 22 of the wafer 200, so as to facilitate the subsequent electrical connection between the first electrode 41 located on the back surface 22 of the wafer 200 and the first power line.

[0081] For the specific description of the semiconductor structure of the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described here again.

[0082] Correspondingly, the present application further provides a forming method of a semiconductor structure. Figures 3 to 8 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0083] The forming method of the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

[0084] Reference Figure 3, a wafer 200 is provided, including opposite front side 21 and back side 22, the wafer 200 including a substrate 100 and a buried power rail 130 within the substrate 100, a bottom surface of the substrate 100 being the back side 22.

[0085] The back side 22 of the wafer 200 is used to provide a process platform for subsequent formation of a capacitor structure and a power line.

[0086] In this embodiment, the wafer 200 is a wafer for completing device fabrication, and thus the substrate 100 on the front side 21 of the wafer 200 has a device structure (not shown) formed thereon.

[0087] In this embodiment, the device structure includes a channel structure 110 protruding from the substrate 100 in a direction away from the back side 22, a gate structure (not shown) across the channel structure 110 and covering part of a top surface and part of a sidewall of the channel structure 110, and source / drain doped regions (not shown) within the channel structure 110 on both sides of the gate structure. Taking the device structure as an example of a fin field effect transistor (FinFET), the channel structure 110 corresponds to a fin.

[0088] In this embodiment, the device structure further includes a shallow trench isolation 120 on the substrate 100 exposed by the channel structure 110, covering part of the sidewall of the channel structure 110. The shallow trench isolation 120 is used to achieve isolation between the channel structures 110 and also to achieve isolation between the substrate 100 and the gate structure.

[0089] The device structure can further include other functional structures, such as resistors, inductors, etc.

[0090] The front side 21 of the wafer 200 can also be bonded to another wafer.

[0091] It should be noted that the front side 21 of the wafer 200 can further have an interconnection structure layer (not shown) formed on the device structure, including multiple layers of back-end-of-line metal interconnection lines and conductive plugs for electrically connecting the metal interconnection lines of adjacent layers.

[0092] As an example, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0093] In this embodiment, the back side 22 includes a first region (not shown) for electrically connecting a first power line and a second region (not shown) for electrically connecting a second power line.

[0094] The first power line and the second power line are used to supply power to the device structures inside the wafer 200.

[0095] The buried power rail 130 is used to supply power to different components of the chip. In this embodiment, the buried power rail is located in the substrate 100, which is advantageous for releasing the wiring resources of the back-end interconnection and for reducing the height of the standard cells to meet the demand for continuous logic chip miniaturization. In addition, the buried power rail is also advantageous for providing a lower resistance local current distribution.

[0096] The buried power rail 130 is in a long strip structure, which is parallel to the extension direction of the channel structure 110, and has a spacing between the buried power rail 130 and the channel structure 110. As an example, the buried power rail 130 extends in the longitudinal direction, and the direction perpendicular to the longitudinal direction is the transverse direction.

[0097] In this embodiment, the number of buried power rails 130 is multiple, and the multiple buried power rails 130 extend in the longitudinal direction and are arranged in the transverse direction with a spacing.

[0098] The material of the buried power rail 130 is a conductive material. In this embodiment, the material of the buried power rail 130 is a metal material, such as one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al. By selecting these materials, the resistivity of the buried power rail 130 is low, which is advantageous for improving RC delay and increasing the processing speed of the chip.

[0099] In this embodiment, the buried power rail 130 is located in the substrate 100 and the shallow trench isolation 120.

[0100] In this embodiment, the shallow trench isolation 120 further forms a covering dielectric layer 150 covering the end face of the buried power rail 130 close to the front surface 21.

[0101] The covering dielectric layer 150 is used to isolate the buried power rail 130 from the gate structure, or to isolate the buried power rail 130 from other conductive structures.

[0102] The material of the covering dielectric layer 150 is a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the material of the covering dielectric layer 150 is the same as that of the shallow trench isolation 120, which is advantageous for improving process compatibility.

[0103] In this embodiment, an insulating layer 140 is formed between the buried power rail 130 and the substrate 100, between the buried power rail 130 and the shallow trench isolation 120, and between the covering dielectric layer 150 and the shallow trench isolation 120.

[0104] The insulating layer 140 is used to realize insulation between the buried power supply rail 130 and the substrate 100. Therefore, the material of the insulating layer 140 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0105] Reference Figure 4 After providing the wafer 200, the method for forming the semiconductor structure further includes: performing thinning processing on the back surface 22 of the wafer 200.

[0106] The thinning processing is performed on the back surface 22 of the wafer 200, so as to reduce the thickness of the back surface 22 of the wafer 200. In the subsequent etching process performed on the back surface 22 of the wafer 200, the depth of the through hole formed in the substrate 100 for exposing the buried power supply rail 130 can be reduced, the process difficulty of forming the through hole is correspondingly reduced, and it is also beneficial to the subsequent formation of the capacitor structure in the through hole.

[0107] In this embodiment, the chemical mechanical polishing process is used to perform the thinning processing on the back surface 22 of the wafer 200.

[0108] In this embodiment, after the thinning processing is performed on the back surface 22 of the wafer 200, the method for forming the semiconductor structure further includes: forming a passivation layer 160 on the back surface 22 of the wafer 200.

[0109] The passivation layer 160 is used to protect the back surface 22 of the wafer 200 and to isolate the substrate 100 from the conductive structure subsequently formed on the back surface 22 of the wafer 200.

[0110] The material of the passivation layer 160 is one or both of silicon oxide and silicon nitride. In this embodiment, the material of the passivation layer 160 is silicon nitride.

[0111] Reference Figure 5 , Figure 5 (a) is a sectional view, Figure 5 (b) is Figure 5 (a) corresponds to a top view, and the back surface 22 of the wafer 200 is etched to form a through hole 170 in the substrate 100 for exposing the buried power supply rail 130.

[0112] The through hole 170 is used to provide a spatial position for the subsequent formation of the capacitor structure. The through hole 170 exposes the buried power supply rail 130, so as to make the buried power supply rail 130 contact the first electrode subsequently formed, thereby realizing the electrical connection between the buried power supply rail 130 and the external circuit through the first electrode.

[0113] In the step of forming the through holes 170, the number of the through holes 170 is multiple, and the multiple through holes 170 are arranged in an array. The through holes 170 are arranged in an array, and accordingly, after the capacitor structures are formed in the through holes 170, the number of the capacitor structures is multiple, and the multiple capacitor structures are arranged in an array, which is beneficial to further improve the density and capacitance value of the capacitor structures per unit area, and further significantly improve the performance of the semiconductor structure.

[0114] Specifically, in the embodiment, the number of the buried power supply tracks 130 is multiple, the multiple buried power supply tracks 130 extend along the longitudinal direction (as indicated by the y direction in (b)) and are arranged in an array along the transverse direction (as indicated by the x direction in (b)), and a plurality of the through holes 170 are formed on one of the buried power supply tracks 130. Figure 5 Figure 5 Specifically, in the embodiment, the number of the buried power supply tracks 130 is multiple, the multiple buried power supply tracks 130 extend along the longitudinal direction (as indicated by the y direction in (b)) and are arranged in an array along the transverse direction (as indicated by the x direction in (b)), and a plurality of the through holes 170 are formed on one of the buried power supply tracks 130.

[0115] In the embodiment, the through holes 170 are micro through silicon vias (μTSV), and the depth and opening size of the through holes 170 are small to meet the demand of continuous reduction of device size.

[0116] In the embodiment, the through holes 170 also penetrate the passivation layer 160.

[0117] In the embodiment, the back surface 22 of the wafer 200 is etched by using an anisotropic dry etching process to form the through holes 170. The anisotropic dry etching process has the characteristic of anisotropic etching, which is beneficial to improve the Profile control of etching, thereby improving the Profile quality of the through holes 170, for example, improving the smoothness and steepness of the sidewall of the through holes 170. Moreover, the etching precision of the anisotropic dry etching process is high, which is beneficial to reduce the damage to the buried power supply tracks 130 and the device structures on the front surface 21 of the wafer 200.

[0118] ​As an example, the anisotropic dry etching process is a reactive-ion etching (RIE) process. In the reactive-ion etching process, a radio frequency voltage is applied between the plate electrodes, and a chemical and physical etching is performed on the layer to be etched by the generated plasma. In the plasma generated by gas discharge, there are a large number of chemically active gas ions, which interact with the material surface to cause chemical reactions of surface atoms, generating volatile products that are discharged from the reaction chamber with the vacuum pumping system; with the cycle of "reaction-stripping-discharge" of the material surface layer, the material is etched layer by layer to the specified depth; in addition to the surface chemical reaction, the energy ion bombardment of the material surface also causes the surface atoms to sputter, producing a certain etching effect. Therefore, by selecting the reactive-ion etching process, it is beneficial to further improve the profile quality of the via hole 170, and also beneficial to accurately control the depth of the via hole 170.

[0119] In this embodiment, the method for forming the semiconductor structure further includes: after forming the via hole 170, forming an isolation layer 180 on the side wall and the bottom of the via hole 170 and the surface of the substrate 100, and the isolation layer 180 exposes the buried power rail 130.

[0120] The isolation layer 180 is used to isolate the substrate 100 and the first electrode formed subsequently.

[0121] In this embodiment, the material of the isolation layer 180 is silicon oxide.

[0122] As an example, the step of forming the isolation layer 180 includes: performing an oxidation treatment on the substrate 100 exposed by the via hole 170, and oxidizing the part of the thickness of the substrate 100 exposed by the via hole 170 into the isolation layer 180.

[0123] The isolation layer 180 is formed by performing an oxidation treatment on the substrate 100, so that the isolation layer 180 will not be formed on the buried power rail 130 exposed by the via hole 170, and accordingly, there is no need to perform the step of removing the isolation layer on the buried power rail, which is beneficial to simplify the process.

[0124] In this embodiment, during the oxidation treatment on the substrate 100 exposed by the via hole 170, the isolation layer 180 is also formed on the passivation layer 160 of the side wall of the via hole 170.

[0125] Reference Figure 6 , Figure 6 (a) is a cross-sectional view, Figure 6 (b) is Figure 6(a) a corresponding top view, a capacitor structure 300 is formed in the via hole 170, including a first electrode 31 located on the bottom and sidewall of the via hole 170, a second electrode 32 located opposite to the sidewall of the first electrode 31, and a capacitor dielectric layer 33 located between the first electrode 31 and the second electrode 32, the first electrode 31 is in contact with the buried power supply rail 130.

[0126] Subsequent steps further include forming a first power supply line electrically connected to the first electrode 31 and a second power supply line electrically connected to the second electrode 32, the two electrodes of the capacitor structure 300 are respectively electrically connected to the first power supply line and the second power supply line for filtering the power supply.

[0127] In the embodiment, the capacitor structure 300 is formed in the via hole 170, and the first electrode 31 and the second electrode 32 can extend in the direction of the sidewall of the via hole 170, which is conducive to increasing the effective area between the first electrode 31 and the second electrode 32, improving the chip area utilization rate, and correspondingly increasing the capacitance density and capacitance value per unit area, thereby improving the filtering effect of the capacitor structure 300 on the power supply, and further improving the performance of the device; in addition, the capacitor structure 300 is formed in the via hole 170, and the first electrode 31 is in contact with the buried power supply rail 130, so that the first power supply line can supply power to the buried power supply rail 130 through the first electrode 31 on the back surface 22 of the wafer 200, which is compatible with the backside power deliver network (Backside PDN) process, thereby improving the process compatibility.

[0128] In the embodiment, the number of capacitor structures 300 is multiple, and the multiple capacitor structures 300 are arranged in an array, which is conducive to increasing the number and density of capacitor structures 300 per unit area, and the capacitance value, and correspondingly further improving the filtering effect of the capacitor structure 300 on the power supply.

[0129] The first electrode 31 is used as a bottom plate of the capacitor, the second electrode 32 is used as a top plate of the capacitor, and the capacitor dielectric layer 33 is used to realize electrical isolation between the first electrode 31 and the second electrode 32.

[0130] The materials of the first electrode 31 and the second electrode 32 are conductive materials, and the material of the capacitor dielectric layer 33 is a dielectric material.

[0131] In the embodiment, the capacitor structure 300 is a MIM capacitor.

[0132] Therefore, the material of the first electrode 31 and the second electrode 32 is a metal material, including one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and AL.

[0133] In this embodiment, the material of the capacitor dielectric layer 33 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. By selecting a high-k dielectric material, the capacitance of the MIM capacitor can be improved, and the capacitance density can be improved accordingly. The high-k dielectric material can be any one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0134] Specifically, the capacitor dielectric layer 33 is a high-k dielectric layer formed by stacking, i.e., the capacitor dielectric layer 33 is a high-k composite dielectric layer. After the high-k dielectric layer is formed to a certain thickness, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the capacitor dielectric layer 33 meets the process requirements while having good formation quality.

[0135] In this embodiment, the capacitor dielectric layer 33 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer and a second ZrO2 layer formed by stacking.

[0136] In other embodiments, according to process requirements, the material of the capacitor dielectric layer can also be one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0137] In this embodiment, in the step of forming the capacitor structure 300, the capacitor structure 300 includes the first electrode 31 on the bottom and sidewall of the via 170, the capacitor dielectric layer 33 on the first electrode 31, and the second electrode 32 on the capacitor dielectric layer 33 and filling the via 170.

[0138] Specifically, the step of forming the capacitor structure 300 includes: forming the first electrode 31 on the bottom and sidewall of the via 170; forming the capacitor dielectric layer 33 on the first electrode 31; and forming the second electrode 32 on the capacitor dielectric layer 33 and filling the via 170.

[0139] In this embodiment, the process of forming the first electrode 31 and the second electrode 32 includes one or both of a physical vapor deposition process and an atomic layer deposition process.

[0140] In this embodiment, the process of forming the capacitor dielectric layer 33 includes one or two of a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.

[0141] In this embodiment, the atomic layer deposition process is used to sequentially form the first electrode 31, the capacitor dielectric layer 33, and the second electrode 32. The atomic layer deposition process is based on a self-limiting reaction process of atomic layer deposition, and the deposited thin film can reach the thickness of a single layer of atoms, which is beneficial to accurately control the thickness of the deposited thin film, thereby accurately controlling the thickness of the first electrode 31, the capacitor dielectric layer 33, and the second electrode 32. In addition, the thin film prepared by the atomic layer deposition process has the advantages of good bonding strength, uniform film thickness, good composition uniformity, and good shape retention, which is beneficial to sequentially depositing the first electrode 31, the capacitor dielectric layer 33, and the second electrode 32 in the via hole 170 with a small opening size, thereby improving the performance of the capacitor structure 300.

[0142] In this embodiment, in the step of forming the capacitor structure 300, the first electrode 31 also extends to cover the back surface 22, and the second electrode 32 is also formed on the first electrode 31 located on the back surface 22.

[0143] Reference Figure 7 In this embodiment, the method for forming the semiconductor structure further includes: after forming the capacitor structure 300, removing the second electrode 32 and the capacitor dielectric layer 33 located in the first region to expose the first electrode 31 located in the first region.

[0144] The first electrode 31 located in the first region is exposed to facilitate the subsequent formation of a first power line electrically connected to the first electrode 31. In the process of removing the second electrode 32 and the capacitor dielectric layer 33 located in the first region, the patterns of the first electrode 31 and the second electrode 32 are also defined.

[0145] Reference Figure 8 A first power line 210 electrically connected to the first electrode 31 and a second power line 220 electrically connected to the second electrode 32 are formed on the back surface 22 of the wafer 200.

[0146] The first power line 210 and the second power line 220 are used to supply power to the device structures inside the wafer 200.

[0147] In the embodiment, the first power line 210 and the second power line 220 are located on the back surface 22 of the wafer 200, so that a backside power delivery network (Backside PDN) is used, which is beneficial to improve the chip area utilization rate, reduce the complexity of the back-end-of-line process, improve the IR drop problem, and improve the system performance.

[0148] In the embodiment, the first power line 210 and the second power line 220 are electrically connected to the first electrode 31 and the second electrode 32 respectively, so that the capacitor structure 300 can filter the power supply.

[0149] In the embodiment, the capacitor structure 300 is formed in the via 170, and the first electrode 31 and the second electrode 32 can extend in the direction of the sidewall of the via 170, thereby improving the capacitance density and the capacitance value per unit area, and improving the filtering effect of the capacitor structure 300 on the power supply. In addition, the capacitor structure 300 is formed in the via 170, and the first electrode 31 is in contact with the buried power rail 130, so that the first power line 210 can supply power to the buried power rail 130 through the first electrode 31, which is compatible with the backside power delivery process, thereby improving the process compatibility.

[0150] In the embodiment, the first power line 210 and the second power line 220 are made of conductive materials, such as one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0151] The power sources connected by the first power line 210 and the second power line 220 are different. The first power line 210 is a voltage power source VDD, and the second power line 220 is a ground power source VSS. Alternatively, the first power line 210 is a ground power source VSS, and the second power line 220 is a voltage power source VDD.

[0152] Specifically, according to the type of power source required by each buried power rail 130, the type of power source connected by the first power line 210 is determined, and the type of power source connected by the second power line 220 is determined accordingly. In the embodiment, the types of power sources required by the buried power rails 130 located at different positions are different.

[0153] In the embodiment, the step of forming the first power line 210 and the second power line 220 includes: forming the first power line 210 electrically connected to the first electrode 31 on the first region, and forming the second power line 220 electrically connected to the second electrode 32 on the second region.

[0154] In this embodiment, before forming the first power line 210 and the second power line 220, the forming method further comprises: forming a dielectric layer 230 on the back surface 22 of the wafer 200. Accordingly, the first power line 210 and the second power line 220 are formed in the dielectric layer 230.

[0155] The dielectric layer 230 is used to realize the electrical isolation between the first power line 210 and the second power line 220. The material of the dielectric layer 230 is a dielectric material. In this embodiment, the material of the dielectric layer 230 is silicon oxide.

[0156] Figures 9 to 12 is a structure diagram corresponding to each step in another embodiment of the forming method of the semiconductor structure of the present application. This embodiment has the same parts as the foregoing embodiments, which will not be described here. The difference between this embodiment and the foregoing embodiments is that:

[0157] Referring to Figures 9 to 12 , in the step of forming the capacitor structure 400, the capacitor structure 400 is a vertical stacked structure; the first electrode 41 (as shown in Figure 12 ) comprises a bottom electrode 411 located at the bottom of the via 170 and in contact with the buried power rail 130, and a plurality of side electrodes 412 protruding from the bottom electrode 411 and arranged in intervals; the second electrode 42 (as shown in Figure 12 ) is located in the gap between the side electrodes 412.

[0158] The capacitor structure 400 is a vertical stacked structure, the number of the side electrodes 412 is a plurality, and the number of the second electrode 42 is also a plurality, which is beneficial to further improve the capacitance density and capacitance value per unit area, thereby significantly improving the performance of the device.

[0159] In this embodiment, the step of forming the capacitor structure 400 comprises:

[0160] As shown in Figure 9 , a plurality of layers of first electrode films 410 located at the bottom and sidewall of the via and stacked in sequence, and a sacrificial dielectric layer 430 located between the sidewalls of the first electrode films 410 are formed, the plurality of layers of first electrode films 410 located at the bottom of the via are in contact with each other to form the bottom electrode 411, and the first electrode films 410 are also formed on the back surface 22 of the wafer 200.

[0161] In this embodiment, the first electrode films 410 are also formed on the back surface 22 of the wafer 200.

[0162] As shown in Figure 10As shown, the first electrode film 410 is planarized to expose the top surface of the sacrificial dielectric layer 430, while retaining the first electrode film 410 protruding from the bottom electrode 411 as a side electrode 412. The sacrificial dielectric layer 430 is exposed to facilitate subsequent removal.

[0163] In this embodiment, during the planarization process of the first electrode film 410, a portion of the first electrode 41 is retained on the back side 22 of the wafer 200 so that an electrical connection can be made between the first electrode 41 located on the back side 22 of the wafer 200 and the first power line.

[0164] In this embodiment, a chemical mechanical polishing process is used to planarize the first electrode film 410.

[0165] like Figure 11 As shown, the sacrificial dielectric layer 430 is removed, and a gap 420 is formed between the side electrodes 412.

[0166] The gap 420 is used to provide space for the formation of the capacitor dielectric layer and the second electrode.

[0167] like Figure 12 As shown, the capacitor dielectric layer 43 is formed on the surface of the first electrode 41 exposed in the gap 440; the second electrode 42 is filled in the gap 440 in which the capacitor dielectric layer 43 is formed.

[0168] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0169] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a wafer comprising opposite front and back surfaces, the wafer comprising a substrate and a buried power rail located in the substrate, a bottom surface of the substrate being the back surface; a via located in the substrate of the back surface of the wafer and exposing the buried power rail; a capacitor structure located in the via, comprising a first electrode located on a bottom and a sidewall of the via, a second electrode located opposite the sidewall of the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, the first electrode being in contact with the buried power rail; a first power line located on the back surface of the wafer and electrically connected to the first electrode; a second power line located on the back surface of the wafer and electrically connected to the second electrode.

2. The semiconductor structure of claim 1, wherein, The number of capacitor structures is multiple, and the multiple capacitor structures are arranged in an array.

3. The semiconductor structure of claim 1, wherein, The capacitor structure comprises a first electrode located on a bottom and a sidewall of the via, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer and filling the via.

4. The semiconductor structure of claim 1, wherein, The capacitor structure is a vertical stacked structure; the first electrode comprises a bottom electrode located on the bottom of the via and in contact with the buried power rail, and a plurality of side electrodes protruding from the bottom electrode and arranged in an interval; the second electrode is located in the gap between the side electrodes.

5. The semiconductor structure of claim 1, wherein, The back surface comprises a first area for electrically connecting the first power line and a second area for electrically connecting the second power line; The first electrode also extends to the first area, the second electrode also extends to cover the second area, and the first electrode located in the first area is exposed; The first power line is located on the first area and electrically connected to the first electrode, and the second power line is located on the second area and electrically connected to the second electrode.

6. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises an isolation layer located between the first electrode and the sidewall of the via, and between the first electrode and the bottom of the via.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a device structure located on the substrate of the front surface of the wafer.

8. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: a wafer comprising opposite front and back surfaces, the wafer comprising a substrate and a buried power rail located in the substrate, a bottom surface of the substrate being the back surface; etching the back surface of the wafer to form a via in the substrate exposing the buried power rail; forming a capacitor structure in the via, comprising a first electrode located on a bottom and a sidewall of the via, a second electrode located opposite the sidewall of the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, the first electrode being in contact with the buried power rail; forming a first power line electrically connected to the first electrode and a second power line electrically connected to the second electrode on the back surface of the wafer.

9. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming the via, the number of vias is multiple, and the multiple vias are arranged in an array.

10. The method of forming a semiconductor structure of claim 8, wherein, In the step of forming the capacitor structure, the capacitor structure comprises a first electrode located on a bottom and a sidewall of the via, a capacitor dielectric layer located on the first electrode, and a second electrode located on the capacitor dielectric layer and filling the via.

11. The method of forming a semiconductor structure of claim 8, wherein, The capacitor structure is a vertical stack structure; the first electrode includes a bottom electrode located at the bottom of the via and in contact with the buried power rail, and a plurality of side electrodes protruding from the bottom electrode and arranged at intervals; and the second electrode is located in the gap between the side electrodes.

12. The method of forming a semiconductor structure of claim 11, wherein, The step of forming the capacitor structure includes forming a plurality of first electrode films sequentially stacked on the bottom and sidewall of the via, and a sacrificial dielectric layer between the sidewalls of the first electrode films, the first electrode films in contact with each other at the bottom of the via to form a bottom electrode, and the first electrode films also formed on the back surface of the wafer. The first electrode films are planarized to expose the top surface of the sacrificial dielectric layer, and the first electrode films protruding from the bottom electrode are retained as side electrodes. The sacrificial dielectric layer is removed to form a gap between the side electrodes. The capacitor dielectric layer is formed on the exposed surface of the first electrode in the gap. The second electrode is filled in the gap with the capacitor dielectric layer.

13. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the capacitor dielectric layer includes one or two of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

14. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the first electrode and the second electrode includes one or two of physical vapor deposition and atomic layer deposition.

15. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the via includes a reactive ion etching process.

16. The method of forming a semiconductor structure of claim 8, wherein, The method of forming the semiconductor structure further includes forming an isolation layer on the sidewall of the via and the substrate surface of the bottom after forming the via and before forming the capacitor structure, the isolation layer exposing the buried power rail.

17. The method of forming a semiconductor structure of claim 8, wherein, The back surface includes a first area for electrically connecting a first power line and a second area for electrically connecting a second power line. In the step of forming the capacitor structure, the first electrode also extends to cover the back surface, and the second electrode is also formed on the first electrode on the back surface. The method of forming the semiconductor structure further includes removing the second electrode and the capacitor dielectric layer in the first area to expose the first electrode in the first area after forming the capacitor structure and before forming the first power line and the second power line. The step of forming the first power line and the second power line includes forming a first power line electrically connected to the first electrode on the first area, and forming a second power line electrically connected to the second electrode on the second area.

18. The method of forming a semiconductor structure of claim 8, wherein, After providing the wafer, the method of forming the semiconductor structure further includes thinning the back surface of the wafer before etching the back surface of the wafer.

19. The method of forming a semiconductor structure of claim 8, wherein, In the step of providing the wafer, a device structure is formed on the substrate of the front surface of the wafer.

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