Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel material pillars are disposed within the memory regions. Memory block regions extend longitudinally across the memory regions and the intermediate region. Stair-step regions are within the intermediate region. Each of the stair-step regions laterally overlaps two of the memory block regions. A first panel region extends longitudinally across at least portions of the stair-step regions. A second panel region extends longitudinally between adjacent memory block regions and provides lateral spacing. The second panel region has a different size laterally from the first panel region and / or is compositionally different from the first panel region. Some embodiments include methods of forming integrated assemblies.

Description

Technical Field

[0001] The present invention relates to methods of forming integrated components, such as integrated memory devices, and the integrated components. Background Art

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory that is widely used in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND may be the basic architecture of flash memory and may be configured to include vertically stacked memory cells.

[0004] Before describing NAND specifically, it may be helpful to more generally describe the relationship of a memory array within an integrated arrangement. FIG1 shows a block diagram of a prior art device 1000 that includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; and access lines 1004 (e.g., word lines for conducting signals WL0 to WLm) and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 can be used to transfer information to and from memory cells 1003. Row decoder 1007 and column decoder 1008 decode address signals A0 to AX on address lines 1009 to determine which of the memory cells 1003 will be accessed. Sense amplifier circuit 1015 is used to determine the value of information read from memory cell 1003. I / O circuitry 1017 communicates information values ​​between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 through DQN on I / O lines 1005 can represent the value of information read from or to be written to memory cells 1003. Other devices can communicate with device 1000 via I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 controls memory operations to be performed on memory cells 1003 using signals on control lines 1020. Device 1000 can receive power supply voltage signals Vcc and Vss on first and second power supply lines 1030 and 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. The selection circuit 1040 can respond to signals CSEL1 through CSELn via the I / O circuit 1017 to select signals on the first data line 1006 and the second data line 1013, which can represent the value of information to be read from or programmed into the memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 through CSELn signals based on address signals A0 through AX on the address line 1009. The selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to enable communication between the memory array 1002 and the I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 of FIG. 1 can be a NAND memory array, and FIG. 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used in the memory array 1002 of FIG. 1 . Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices can include, for example, thirty-two charge storage devices stacked one on top of another, where each charge storage device corresponds to, for example, one of thirty-two rows (e.g., rows 0 through 31). The charge storage devices of corresponding strings can share a common channel region, such as a common channel region formed in a corresponding pillar of semiconductor material (e.g., polysilicon) around which the charge storage device strings are formed. In a second direction (XX'), each of, for example, sixteen first groups of the multiple strings can include, for example, eight strings that share a plurality (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines can couple the charge storage devices within a row. When each charge storage device includes cells capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same bank) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, and so on. In the third direction (Y-Y'), each of, for example, eight second groups of strings in the plurality of strings can include sixteen strings coupled by corresponding data lines in the eight data lines. The size of the memory block can include 1,024 pages and a total of approximately 16 MB (e.g., 16 WLs x 32 banks x 2 bits = 1,024 pages / block, block size = 1,024 pages x 16 KB / page = 16 MB). The number of strings, banks, access lines, data lines, first groups, second groups, and / or pages can be larger or smaller than those shown in FIG.

[0006] 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in the XX′ direction, the memory block including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to FIG. The multi-string memory block 300 can be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as a tile column. I , tile array j and tile arrays K, where each subset (e.g., tile column) includes a "partial block" (sub-block) of the memory block 300. A global drain-side select gate (SGD) line 340 can be coupled to the SGDs of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers from multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 can simultaneously couple or disconnect the SGDs of the strings of the corresponding partial block (e.g., tile column) independently of the SGDs of the strings of other partial blocks. A global source-side select gate (SGS) line 360 ​​can be coupled to the SGSs of multiple strings. For example, a global SGS line 360 ​​can be coupled to a plurality of sub-SGS lines 362, 364, 366 via corresponding sub-SGS drivers from a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a respective subset (e.g., tile columns). Each of the sub-SGS drivers 322, 324, 326 can simultaneously couple or disconnect the SGS of the strings of the corresponding partial block (e.g., tile columns) independently of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 can couple charge storage devices corresponding to respective rows of each string in the plurality of strings. Each global CG line (e.g., global CG line 350) can be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via corresponding sub-string drivers from a plurality of sub-string drivers 312, 314, and 316. Each of the substring drivers can simultaneously couple or disconnect the charge storage devices corresponding to the corresponding partial blocks and / or rows independently of the charge storage devices of other partial blocks and / or rows. The charge storage devices corresponding to the corresponding subset (e.g., partial block) and the corresponding row may include the charge storage devices of a "partial row" (e.g., a single "tile"). The strings corresponding to the corresponding subset (e.g., partial block) can be coupled to corresponding sub-sources of sub-sources 372, 374, and 376 (e.g., "tile sources"), each of which is coupled to a corresponding power supply.

[0007] Instead, the NAND memory device 200 is described with reference to the schematic illustration of FIG. 4 .

[0008] Memory array 200 includes word lines 2021 to 202 N , and bit lines 2281 to 228 M .

[0009] Memory array 200 also includes NAND strings 2061 through 206 M Each NAND string contains charge storage transistors 2081 to 208 NThe charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge-trapping material (eg, silicon nitride, metal nanodots, etc.) to store charge.

[0010] Charge storage transistors 208 are located at the intersections of word lines 202 and strings 206. Charge storage transistors 208 represent nonvolatile memory cells for storing data. The charge storage transistors 208 of each NAND string 206 are connected in series in a source-to-drain fashion between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of a string 206 and a source select line 214, while each drain select device 212 is located at the intersection of a string 206 and a drain select line 215. Select devices 210 and 212 can be any suitable access devices and are generally illustrated by the blocks in FIG4 .

[0011] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select devices 210 are connected to a source select line 214.

[0012] The drain of each drain select device 212 is connected to a bit line (i.e., digit line) 228 at a drain contact. For example, the drain of drain select device 2121 is connected to bit line 2281. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain select device 2121 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 2061. N of the drain.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are commonly coupled to a given word line 202.

[0014] It would be desirable to develop improved methods of forming integrated memories (eg, NAND memories).It would also be desirable to develop improved memory devices. Summary of the Invention

[0015] Aspects of the present disclosure provide an integrated component comprising: a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first memory region and the second memory region; a stack extending across the first and second memory regions and the intermediate region, the stack comprising alternating conductive levels and insulating levels; channel material pillars arranged within the first and second memory regions; a memory block region extending longitudinally across the first and second memory regions and the intermediate region; stepped regions within the intermediate region, each of the stepped regions laterally overlapping with an associated two of the memory block regions; a first panel region extending longitudinally across at least a portion of the stepped regions and laterally between the associated two of the memory block regions; a second panel region extending longitudinally between adjacent regions of the memory block region and providing lateral spacing; and the second panel region having a laterally different size than the first panel region and / or being compositionally different from the first panel region.

[0016] Another aspect of the present disclosure provides an integrated component comprising: a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first memory region and the second memory region; a stack extending across the first and second memory regions and the intermediate region, the stack comprising alternating conductive levels and insulating levels; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; memory block regions extending across the first and second memory regions and the intermediate region, the memory block regions extending longitudinally; each of the memory block regions comprising a first edge region along a terminal edge of the first memory region and comprising a a second edge region; a stepped region within the middle region, each of the stepped regions laterally overlapping with associated two of the memory block regions; a longitudinally extending panel providing lateral spacing between adjacent regions of the memory block region; the longitudinally extending panel including a first longitudinally extending panel extending across the stepped region and including a second longitudinally extending panel extending laterally between the step regions and not across the step regions; a first laterally extending panel along the first edge region and a second laterally extending panel along the second edge region; the first longitudinally extending panel including a first panel region extending completely across the stepped region; the second longitudinally extending panel including only a second panel region; and the first panel region being laterally wider than the second panel region and / or compositionally different from the second panel region.

[0017] Another aspect of the present disclosure provides a method of forming an integrated component, wherein the method includes: forming a structure to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first memory region and the second memory region; a step position is defined in the intermediate region; the structure includes a stack extending across the first memory region, the second memory region, and the intermediate region; the stack includes alternating first and second levels, wherein the first level includes a sacrificial material and the second level includes an insulating material; forming pillars extending through the stack within the first and second memory regions, the pillars including a cell material and a channel material material; forming a first slit opening extending through the stack, wherein at least one of the first slit openings includes a segment extending across one of the step positions; forming a first panel material within the first slit opening; forming a column opening extending through the stack within the middle region; forming a column material within the column opening; after forming the first panel material and the column material, forming a second slit opening through the stack; one or more of the second slit openings extending across the first memory region, the middle region and the second memory region; replacing at least some of the sacrificial material of the first level with a conductive material; and forming a second panel material within the second slit opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 shows a block diagram of a prior art memory device having a memory array of memory cells.

[0019] FIG. 2 shows a 3D NAND memory device in the form of a Figure 1 Prior Art Schematic diagram of a memory device.

[0020] FIG. 3 illustrates a cross-sectional view of the prior art 3D NAND memory device of FIG. 2 in the XX′ direction.

[0021] FIG. 4 is a schematic diagram of a prior art NAND memory array.

[0022] Figure 5-5B is a schematic top-down view of a region showing example integrated components of an example embodiment ( Figure 5 ) and a pair of schematic cross-sectional side views ( Figure 5A and 5B ). Figure 5A and 5B The cross-sectional side views are along Figure 5 The lines AA and BB.

[0023] Figure 6-10 is a schematic top-down view of regions illustrating example integrated components of an example embodiment.

[0024] Figure 11A and 11B are a schematic top-down view and a schematic cross-sectional side view of a region of an example integrated assembly during an example processing phase of an example method. Figure 11B The cross-sectional side view is along Figure 11A Line BB.

[0025] Figure 11C is with Figure 11A At the same processing stage Figure 11A Cross-sectional side view of a region of an assembly.

[0026] Figure 12A and 12B is Figure 11A and 11B 11 and 11B are schematic top-down and schematic cross-sectional side views of a region of an example integrated assembly. Figure 12B The cross-sectional side view is along Figure 12A Line BB.

[0027] Figure 13A and 13B is Figure 12A and 12B 11 and 11B are schematic top-down and cross-sectional side views of a region of an example integrated assembly. Figure 13B The cross-sectional side view is along Figure 13A Line BB.

[0028] Figure 14A and 14B is Figure 13A and 13B 11 and 11B are schematic top-down and schematic cross-sectional side views of a region of an example integrated assembly. Figure 14B The cross-sectional side view is along Figure 14A Line BB.

[0029] Figure 15A and 15B is Figure 14A and 14B 11 and 11B are schematic top-down and schematic cross-sectional side views of a region of an example integrated assembly. Figure 15B The cross-sectional side view is along Figure 15A Line BB.

[0030] Figure 16A and 16B is Figure 15A and 15B11 and 11B are schematic top-down and schematic cross-sectional side views of a region of an example integrated assembly. Figure 16B The cross-sectional side view is along Figure 16A Line BB.

[0031] Figure 17A and 17B is Figure 16A and 16B 11 and 11B are schematic top-down and schematic cross-sectional side views of a region of an example integrated assembly. Figure 17B The cross-sectional side view is along Figure 17A Line BB.

[0032] Figure 17C is with Figure 17A At the same processing stage Figure 17A A schematic cross-sectional side view of the area of ​​the assembly and is taken along the Figure 11C A view of the same cross section as shown. DETAILED DESCRIPTION

[0033] Some embodiments include a method of forming an integrated component. The component may have an intermediate region between a pair of memory regions. A first panel structure may be formed within the intermediate region to provide structural support. Subsequently, slits may be formed to extend into the memory regions and the intermediate region, wherein portions of the slits within the memory regions separate the memory blocks from each other. The slits may be used to provide access to a sacrificial material during a gate replacement method. The slits may be filled with one or more materials to form a second panel structure. Reference Figure 5 -17 describes an example embodiment.

[0034] Figure 5 A top-down view of several example regions along an example integrated assembly 10 is shown. The illustrated regions of assembly 10 include a pair of memory regions (memory array regions) 12a and 12b (array 1 and array 2), and an intermediate region 14 between the memory regions. In some embodiments, memory regions 12a and 12b may be referred to as first regions that are laterally displaced relative to each other (later offset from each other), and intermediate region 14 may be referred to as another region (or as a second region) that is located between the laterally displaced (later offset) first regions. Note that Figure 5A and 5B Cross-sectional side views are shown within the storage region 12a and the intermediate region 14, respectively. Figure 5A It is along Figure 5 The view of line AA, and Figure 5B It is along Figure 5 A view of line BB. Figure 5A and 5BThe view schematically shows the Figure 5 The instance structure is represented in a top-down view of Figure 5 The same ratio is provided.

[0035] Figure 5 Unit material pillars 16 are shown arranged within the memory regions 12a and 12b. The pillars 16 can be substantially identical to one another, the term "substantially identical" meaning identical within reasonable tolerances of manufacturing and measurement. The pillars 16 can be configured in a close-packed arrangement within each of the memory regions 12a and 12b, such as a hexagonal close-packed (HCP) arrangement. There can be hundreds, thousands, millions, hundreds of thousands, etc. of pillars 16 arranged within each of the memory regions 12a and 12b. Figure 5 The support 16 may have any suitable shape. Figure 5 They are shown as circles, but in other embodiments they can be elliptical, polygonal, etc.

[0036] Figure 5A Each of the pillars 16 is shown to include an outer region 18 containing memory cell material, a channel material 20 adjacent to the outer region 18, and an insulating material 22 surrounded by the channel material 20. Figure 5A Stippling is provided within the channel material 20 to help the reader identify the channel material.

[0037] The cell materials within region 18 may include tunneling materials, charge storage materials, and charge blocking materials. The tunneling material (also referred to as a gate dielectric material) may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like. The charge storage material may include any suitable composition and, in some embodiments, may include a floating gate material (e.g., polysilicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, and the like). The charge blocking material may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0038] Channel material 20 comprises a semiconductor material. The semiconductor material may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are legacy nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material may comprise, consist essentially of, or consist of appropriately doped silicon.

[0039] The channel material 20 can be considered to be configured as a channel material pillar 24. In the embodiment shown, the channel material pillar 24 is Figure 5 , wherein such annular ring surrounds the insulating material 22. Such a configuration of the channel material pillars may be considered to correspond to a "hollow" channel configuration, wherein the insulating material 22 is disposed within the hollow body of the channel material pillars. In other embodiments, the channel material 22 may be configured as solid pillars. In some embodiments, the channel material pillars within the memory region 12a may be referred to as first channel material pillars, and the channel material pillars within the memory region 12b may be referred to as second channel material pillars. The channel material pillars may be arranged in any suitable configuration within the first memory region 12a and the second memory region 12b. In some embodiments, the channel material pillars may be arranged in a close-packed configuration, such as a hexagonal close-packed (HCP) configuration.

[0040] The outer region 18 of the unit material is Figure 5 will be annular in a top-down view of the Figure 5 are shown to simplify the drawing.

[0041] Figure 5 and 5A Insulating material 22 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0042] The pillar 26 is arranged within the intermediate region 14 . Figure 5B Each of the pillars 26 is shown to include conductive material 28 laterally surrounded by insulating material 30. The insulating material 30 is not Figure 5B The top-down view is shown to simplify the drawing.

[0043] The pillars 26 may be arranged in any suitable configuration and may or may not be of the same size and composition as one another. Figure 5 In the top-down view of FIG, the column 26 can have any suitable shape. Figure 5 In other embodiments, they may be elliptical, polygonal, etc.

[0044] Conductive material 28 may include any suitable conductive composition, such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 28 may include one or more of tungsten, titanium nitride, and tungsten nitride. For example, conductive material 28 may include a conductive liner including one or both of titanium nitride and tungsten nitride along insulating liner 30, and may include a tungsten filler laterally surrounded by the conductive liner.

[0045] Insulating material 30 is configured as an insulating ring (or alternatively, an insulating liner) surrounding the conductive pillar. Material 30 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0046] In some embodiments, the conductive material 28 of the pillars 26 can be configured as conductive pillars 32. Such conductive pillars can be "live" and thus can serve as electrical interconnects. Alternatively, the pillars can be "dummy" and can serve only to provide structural support. Hundreds, thousands, millions, etc. of conductive pillars 26 can be disposed within the intermediate region 14.

[0047] Intermediate region 14 may include numerous regions associated with integrated memory, including, for example, step regions, summit regions, bridge regions, etc. If conductive pillars 32 are charged pillars, such pillars may be used to interconnect components associated with memory regions 12 a and 12 b to circuitry below the illustrated region of integrated assembly 10. For example, the conductive pillars may be used to connect bit lines to sensing circuitry (e.g., sense amplifier circuitry), to connect SGD devices to control circuitry, etc.

[0048] Figure 5 Memory blocks 34a-34d are shown extending longitudinally across memory regions 12a and 12b and across middle region 14. In the illustrated embodiment, the longitudinal direction of the memory blocks is the y-axis direction shown, which may also be referred to as a first direction. Blocks 34a-d may be similar to the memory blocks described above in the "Background" section of this disclosure.

[0049] Panels 36a-36e extend longitudinally along the lateral edges of memory blocks 34a-34d, and panels 38a and 38b extend transversely (i.e., along the x-axis, or second direction, as shown) along the ends of memory blocks 34a-34d. In some embodiments, longitudinally extending panels 36a-36e may be referred to as first panels, and transversely extending panels 38a and 38b may be referred to as second panels. In some embodiments, each of memory blocks 34 may be considered to include a first edge region along the terminal edge of first memory block 12a and a second edge region 37 along the terminal edge of second memory block 12b. Transversely extending panels 38a and 38b may be considered to be along first edge region 35 and second edge region 37, respectively.

[0050] Figure 5 Schematically, step regions (low-lying regions) 40a and 40b are shown, with dotted lines indicating the approximate boundaries of the step regions. Step region 40 is within intermediate region 14. It is noteworthy that each of step regions 40 laterally overlaps with two of memory block regions 34 (e.g., step region 40a laterally overlaps with memory block regions 34a and 34b). Memory block regions that partially overlap with a step region can be considered to be associated with the step region. Thus, memory block regions 34a and 34b can be considered to be associated with step region 40a, and memory block regions 34c and 34d can be considered to be associated with step region 40b.

[0051] The longitudinally extending panels 36 may be considered to include a first set of longitudinally extending panels (which may be referred to as first longitudinally extending panels) that extend across the step region 40. In the illustrated embodiment, the first longitudinally extending panels are panels 36b and 36d.

[0052] The longitudinally extending panels 36 may be considered to include a second set of longitudinally extending panels (which may be referred to as second longitudinally extending panels) that extend transversely between and not across the step regions 40. In the embodiment shown, the second longitudinally extending panels are panels 36a, 36c, and 36e.

[0053] First panels 36b and 36d include a first panel region 42 and a second panel region 44, with first panel region 42 differing from second panel region 44 in one or both of composition and thickness. In the illustrated embodiment, first panel region 42 is laterally wider (laterally thicker) than second panel region 44. Typically, first panel region 42 will be at least as wide as second panel region 44 along interface 43, where the edges of first panel region 42 and second panel region 44 abut each other (i.e., are immediately adjacent each other).

[0054] The first panel region 42 may extend completely across the step region 40 along the longitudinal (y-axis) direction, as shown in FIG. Figure 5The first panel region 42 can provide structural support during the removal of the sacrificial material (as described below with reference to Figure 16A and 16B ), and may also reduce or eliminate problematic block flexure (i.e., warping, distortion, and / or other undesirable mechanical displacement of the memory block region 34) during manufacture and / or use of the integrated assembly 10. It may be desirable for the first panel region 42 to extend completely across the step region 40 in the longitudinal direction. However, it should be understood that in some embodiments, it may be appropriate for the first panel region 42 to extend only partially across the step region 40 in the longitudinal direction, rather than completely across the step region.

[0055] The first panel regions 42 are laterally located between the memory block regions 34 associated with the respective staircase regions 40. For example, one of the panel regions 42 is laterally located between the memory block regions 34a and 34b associated with the staircase region 40a.

[0056] The second panel regions 44 of the first panels 36b and 36d provide lateral spacing between adjacent memory block regions (eg, the second panel region 44 of the panel 36b provides lateral spacing between adjacent memory block regions 34a and 34b).

[0057] In the illustrated embodiment, the second longitudinally-extending panels 36a , 36c , and 36e include only the second panel region 44 , and the transversely-extending panels 38a and 38b include only the second panel region 44 .

[0058] Figure 5A and 5B Panel regions 42 and 44 are shown as having different compositions relative to each other. Specifically, panel region 44 is a laminate of two different compositions 46 and 48, and panel region 42 includes only a single homogeneous composition 50.

[0059] In some embodiments, composition 46 may include, consist essentially of, or consist of one or more of silicon (e.g., polycrystalline silicon, amorphous silicon, etc.), germanium, silicon dioxide, a metal, etc. In some embodiments, composition 46 may include an undoped semiconductor material, such as undoped silicon. The term "undoped" does not necessarily mean that there is an absolute absence of dopants within the semiconductor material, but rather means that the amount of any dopant present within such semiconductor material is generally understood to be insignificant. For example, depending on the context, undoped silicon may be understood to include less than about 10 16 atoms / cm3, less than about 10 15 atoms / cm3 etc.

[0060] In some embodiments, composition 48 can include, consist essentially of, or consist of silicon nitride.

[0061] In some embodiments, composition 50 can comprise, consist essentially of, or consist of silicon dioxide.

[0062] In some embodiments, panel regions 42 and 44 may be the same composition as one another.

[0063] In some embodiments, the laminate of panel region 44 may include more than two different materials.

[0064] In some embodiments, the material 48 ( Figure 5A ) can be considered as a liner configured as an upwardly open container shape, and material 46 can be considered as a filler material within such an upwardly open container shape. Figure 5 The lining of material 48 is not shown in the top-down view of FIG. 1 to simplify the drawing.

[0065] Figure 5A Component 10 is shown including a source structure 54 comprising a first composition 56 on a second composition 58. First composition 56 may, for example, comprise silicon (and / or other semiconductor material) heavily doped with a suitable conductivity-enhancing dopant (e.g., phosphorus, arsenic, etc.). Second composition 58 may comprise any suitable conductive material; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, second composition 58 may comprise, consist essentially of, or consist of tungsten silicide.

[0066] Source structure 54 is shown coupled to logic circuitry (e.g., CMOS) 52a provided below the source structure. Logic circuitry 52a may include, for example, control circuitry suitable for coupling with source structure 54 and controlling the flow of current along the source structure during read / write operations of the memory cells within memory regions 12a and 12b. Source structure 54 may be similar to the source structures described above with reference to the prior art of Figures 1-4.

[0067] Logic circuitry (e.g., CMOS) may be supported by semiconductor material (not shown). Such semiconductor material may, for example, include, consist essentially of, or consist of single crystal silicon (Si). The semiconductor material may be referred to as a semiconductor base, or as a semiconductor substrate. The term "semiconductor substrate" means any structure comprising semiconductor material, including but not limited to a monolithic semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. The configuration described herein may be referred to as an integrated configuration supported by a semiconductor substrate, and therefore may be considered an integrated assembly.

[0068] Figure 5B Conductive material 58 is shown as being configured as islands 60 in intermediate region 14. The islands are laterally spaced apart from one another by insulating material 62. Insulating material 62 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0069] Figure 5B Logic circuitry (e.g., CMOS) is shown including components 52b and 52c coupled to conductive material 28 of conductive pillars 32 via conductive islands 60. Components 52b and 52c may correspond to, for example, control circuitry and / or sensing circuitry (e.g., sense amplifier circuitry, driver circuitry, etc.).

[0070] A stack 68 is formed on the composition 56, such as Figure 5A and 5B . The stack 68 has alternating first levels 70 and second levels 72. The first levels 70 include conductive material 74 and the second levels 72 include insulating material 76. Although the conductive material 74 is shown as completely filling the first levels 70, in other embodiments, at least some of the material provided within the first levels 70 may be insulating material (e.g., dielectric barrier material).

[0071] Conductive material 74 may comprise any suitable composition and, in some embodiments, may comprise a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material, if present, may comprise any suitable composition and, in some embodiments, may comprise one or more of aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0072] Figure 5A and 5B The stack 68 can be considered to include alternating insulating levels (intermediate levels) 72 and conductive levels 70 .

[0073] Figure 5AThe components of FIG. 6 can be considered as a memory device including a memory cell 64 and a selection device (SGS device) 66. Although only one conductive layer is shown as being incorporated into the SGS device 66 (the bottommost conductive layer), in other embodiments, multiple conductive layers can be incorporated into the SGS device. If multiple conductive layers are incorporated into the SGS device, the conductive layers can be electrically coupled (combined together) to form a long channel SGS device. The layer including the SGS device can be referred to as an SGS layer.

[0074] Memory cells 64 (e.g., NAND memory cells) are stacked vertically on top of each other. Each of the memory cells includes a region of semiconductor material (channel material) 20 and includes a region of conductive layer 70 (control gate region). The region of conductive layer 70 not included by memory cell 64 may be a word line region (wiring region) that couples the control gate region to driver circuitry and / or to other suitable circuitry. Memory cell 64 includes cell materials (e.g., tunneling material, charge storage material, and charge blocking material) within region 18.

[0075] In some embodiments, the conductive level 70 associated with the memory cells 64 can be referred to as a word line / control gate level (or memory cell level) because it includes the word lines and control gates associated with the vertically stacked memory cells of the NAND string. A NAND string can include any suitable number of memory cell levels. For example, a NAND string can have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0076] In some embodiments, the channel material pillars 24 may be considered to represent Figure 5 and 5A The memory regions 12a and 12b extend from a large number of pillars of substantially identical channel material.

[0077] Figure 5B Pillars 26 are shown extending through stack 68 to conductive material 58. Pillars 26 include conductive pillars 32, and in the illustrated embodiment, such conductive pillars are electrically coupled to conductive islands 60 that include conductive material 58. In embodiments where conductive pillars 32 are "live" pillars, pillars 32 can be coupled to CMOS circuitry 62. Alternatively, in embodiments where the conductive pillars are "dummy" configurations provided for structural support rather than for electrical connection, at least some of the conductive pillars 32 may not be coupled to the CMOS circuitry. In embodiments where pillars 26 are dummy configurations (i.e., provided only for structural support), pillars 26 may include only insulating material, without including conductive material 28.

[0078] In the illustrated embodiment, each of the islands 60 supports one of the conductive pillars 32. In other embodiments, at least one of the islands 60 may support two or more of the conductive pillars.

[0079] Figure 5 The top-down view of FIG. 1 shows additional conductive posts outside 78 of panel 38a (i.e., outside the periphery of memory region 12a), and shows additional dummy posts 80 between panel 38a and conductive posts 78. Conductive posts 78 may be "live" posts and may serve, for example, as a means of passing stack 68 ( Figure 5A and 5B In some applications, the channel pillar 24 may be coupled to a bit line (see below). Figure 17C Description), and may be operatively adjacent to the SGD device (also referred to below Figure 17C ), and the conductive pillars 78 may be used to couple one or both of the SGD device and the bit line to the stack 68 ( Figure 5A and 5B ) below the logic circuitry. Pillars 78 are shown as squares to help distinguish them from pillars 26 of intermediate region 14. It should be understood that in some embodiments, pillars 78 and 26 can have the same configuration as one another, and in other embodiments can have different configurations relative to one another.

[0080] Dummy pillars 80 may be used to extend through stack 68 of conductive level 70 ( Figure 5A and 5B ) to reduce stress caused by the high density of conductive material within level 70. In some embodiments, panel 38 may include a material that prevents the formation of conductive material within level 70 in the outer peripheral area of ​​panel 38 (see below). Figure 8 In such embodiments, it may be appropriate to eliminate the dummy post 80. Figure 5 The top-down view of the can be square (as shown), or can include any other suitable shape.

[0081] exist Figure 5 In the top-down view of FIG, dummy posts 80 are shown as having a smaller square than posts 78 so that they can be distinguished from posts 78. However, it should be understood that dummy posts 80 may have any suitable size relative to posts 78 and may be the same size as posts 78, smaller than posts 78, or larger than posts 78.

[0082] To simplify the drawing, pillars 80 and 78 are shown only along one of the peripheral edges of memory block region 34. In other embodiments, additional pillars 80 and 78 may be along the other peripheral edge of memory block region 34 (eg, outside of panel 38b).

[0083] Figure 5 Step connections 82 are shown in step regions 40a and 40b. Step connections 82 may be used to connect the conductive layers 70 ( Figure 5A ) word lines are coupled to driver circuitry and / or any other suitable circuitry. The step connection 82 may include a conductive core region laterally surrounded by an annular ring of insulating material. The insulating material ring is not Figure 5 To simplify the drawing. Figure 5 In a top-down view of (as shown), the step connection may be circular, or may comprise any other suitable shape. Figure 5 In the top-down view of FIG, the step connections 82 are shown with smaller circles than the posts 26 so that they can be distinguished from the posts 26. However, it should be understood that the step connections 82 can have any suitable size relative to the posts 26 and can be the same size as the posts 26, smaller than the posts 26, or larger than the posts 26.

[0084] Figure 5 4. An embodiment is shown in which the first panel region 42 is laterally thicker than the second panel region 44. In other embodiments, the first panel region 42 may have approximately the same lateral thickness as the second panel region 44, at least along the interface 43 where the first and second panel regions abut one another, e.g. Figure 6 As shown. Although Figure 5 and 6 In the embodiment of the present invention, the first panel region 42 is shown as having the same lateral thickness along the entire longitudinal extension of such first panel region, but it should be understood that in some embodiments, the lateral thickness of the first panel region can vary along the longitudinal extension of the panel region. In any case, it is desirable that the first panel region 42 has a lateral thickness (width) that is as great as the lateral thickness (width) of the second panel region 44 at least along the interface 43.

[0085] Figure 6 The first panel region 42 may include a different composition than the second panel region 44. For example, the panel region 42 may include the Figure 5B The composition 50 described, and the panel area 44 may include the above reference Figure 5A Materials 46 and 48 described.

[0086] In some embodiments, the first region 44 may extend longitudinally across only a portion of the step regions 40a and 40b, e.g. Figure 7 shown, rather than extending completely across the stepped area.

[0087] In some embodiments, the laterally extending panels 38a and 38b may include a first panel region 42 such as Figure 8 The illustrated embodiment shows that the laterally extending panels 38a and 38b only include the first panel region 42 and, in the illustrated embodiment, the composition 50.

[0088] If the laterally-extending panels 38a and 38b include a first region 42 (e.g., composition 50), the first region may be formed as a support structure (e.g., a composite material 50) prior to forming the conductive material 74 within the level 70 of the stack 68. Figure 5A and 5B The panel region 42 may protect the portion of the stack outside the panel region from being exposed to conditions where the insulating material within the layer 70 is replaced with a conductive material (see below). Figure 16B ) and thus no conductive material is formed in the stacking region outside of the laterally extending panels 38a and 38b. In some embodiments, this may enable the elimination of dummy pillars 80 ( Figure 5 ), since such dummy pillars are generally used to reduce stress caused by the metal-containing layers 70 in the outer regions of the laterally extending panels 38a and 38b. Figure 8 The embodiment shown is that the live pillar 78 is outside the laterally extending panel 38a and adjacent to the panel 38a, so that there is no intermediate dummy pillar ( Figure 5 Pillar 80).

[0089] Figure 5-8 The embodiment of the longitudinally extending panels 36b and 36d is shown to include a first panel area 42 and a second panel area 44. In other embodiments, the longitudinally extending panels 36b and 36d may include only the first panel area 42, such as Figure 9 and 10 shown. Figure 9 The second panel region 44 is shown to be thinner (narrower) than the first panel region 42, and Figure 10 A first panel region 42 and a second panel region 44 are shown as being approximately the same thickness (width) as each other.

[0090] Figure 5-10 The integrated assembly can be formed by any suitable method. Example methods are described with reference to Figures 11-17. The specific method of Figures 11-17 is specifically designed to manufacture Figure 10 However, it should be understood that similar methods can be used to manufacture integrated components of other embodiments.

[0091] refer to Figure 11A and 11B , regions of the integrated assembly 10 are shown in a top-down view and a cross-sectional side view, respectively. Figure 11B The side view is along Figure 11A Line BB. In addition, Figure 11C An additional cross-sectional side view is provided in FIG. This view is within the memory area 12a. Figure 11A and 11B Different scales of view available Figure 11C ,but Figure 11C and Figure 11A and 11B are at the same stage of processing.

[0092] Figure 11C Source structure 54 is shown including materials 58 and 56 . Figure 11B Material 56 is shown, but material 58 is not shown to simplify the drawing.

[0093] exist Figure 11A -C processing stage to form unit material pillars 16, and Figure 11A and 11C The unit material pillar is schematically shown in FIG.

[0094] The stack 68 includes alternating first and second levels 70 and 72. Figure 11A At processing stage 1-C, level 72 includes insulating material 76, and level 70 includes sacrificial material 84. In some embodiments, material 84 may include, consist essentially of, or consist of silicon nitride; and material 76 may include, consist essentially of, or consist of silicon dioxide.

[0095] The stack 68 may be considered together as part of a construction 86. In the embodiment shown, such a construction includes a first memory region 12a, a second memory region 12b, and an intermediate region 14 laterally between the first and second memory regions.

[0096] Step regions (step locations) 40a and 40b are defined within the intermediate region 14 and correspond to openings etched into the stack 68 (eg, Figure 11B In some embodiments, stepped locations 40a and 40b may be referred to as low-lying locations to better describe the three-dimensional configuration of the locations. Figure 11B The step region is shown partially penetrating into the stack 68. Specifically, the step location does not penetrate to the bottom level 70 (described above with reference to the SGS level) to be incorporated into the SGS level. Figure 5A describes the SGS hierarchy).

[0097] Insulating material 88 is formed within step regions 40 a and 40 b. Insulating material 88 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide, aluminum oxide, carbon-doped silicon oxide, boron-doped silicon oxide, undoped silicon, or the like. In some embodiments, material 88 may comprise one or more liners formed along the material of stack 68. Such liners may comprise any suitable material, including, for example, one or more of undoped silicon, silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0098] refer to Figure 12A and 12B, forming first slit openings 90 extending through stack 68, wherein a pair of slit openings 90 are located within panel locations 36b and 36d and thus have segments extending across step locations 40a and 40b. First panel material 50 is formed within slit openings 90 to form first panel region 42. In some embodiments, panel material 50 may include, consist essentially of, or consist of silicon dioxide.

[0099] refer to Figure 13A and 13B , forming post openings 92 that extend through stack 68 within intermediate region 14 .

[0100] refer to Figure 14A and 14B , a pillar material is formed within pillar opening 92. In the illustrated embodiment, the pillar material comprises conductive material 28 and insulating liner material 30. The pillar material within pillar opening 92 forms pillar 26.

[0101] Although the column opening 92 ( Figure 13A and 13B ) is shown at the slit opening 90 ( Figure 12A and 12B ), but it should be understood that in other embodiments, the post opening 92 can be formed simultaneously with the slit opening 90 or before the slit opening 90.

[0102] refer to Figure 15A and 15B , forming a second slit opening 94 through the stack 68. The second slit opening 94 is shown extending longitudinally across the storage areas 12a and 12b and across the middle area 14. The embodiment shown ultimately forms a similar Figure 10 The configuration of the configuration, and therefore the slit openings 94 are formed to extend longitudinally. In other embodiments, a configuration similar to Figure 5-7 of the components, and thus at least some of the second slit openings 94 may extend laterally.

[0103] refer to Figure 16A and 16B , removing the sacrificial material 84 of the first level 70 ( Figure 15B ) and is replaced with a conductive material 74. Although the conductive material 74 is shown as completely filling the first level 70, in other embodiments, at least some of the material provided within the first level 70 may be an insulating material (e.g., a dielectric barrier material). The conductive material 74 may include any suitable composition and, in some embodiments, may include a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material may include any suitable composition and, in some embodiments, may include one or more of aluminum oxide, hafnium oxide, zirconium oxide, and the like.

[0104] Figure 16A and16B The first level 70 is a conductive level, and the stack 68 can be considered to include alternating insulating levels (intermediate levels) 72 and conductive levels 70 .

[0105] refer to Figure 17A and 17B , in the slit opening 94 ( Figure 16A and 16B ) forms a second panel material 46. The panel material 46 may include the above reference Figure 5 and 5A The composition described. Lining material 48 ( Figure 5A ) may be provided adjacent to the panel material 46 but not in Figure 17A and 17B are shown to simplify the drawing.

[0106] Panel material 46 forms longitudinally extending panels 36a, 36c, and 36e. Memory block regions 34a-d are bounded by longitudinally extending panels 36a-e and transversely extending panels 38a and 38b. In some embodiments, panel material 46 may be considered to form second panel region 44.

[0107] While the panel materials 50 and 46 are shown as being different from one another, it should be understood that in other embodiments, the panel materials 50 and 46 may be the same composition as one another.

[0108] In the embodiment shown in Figures 11-16, first slit openings 90 ( Figure 12A and 12B ) to define the transversely extending slits that are ultimately used to form the transversely extending panels 38a and 38b. In other embodiments, the second slit opening 94 ( Figure 15A and 15B ) can be formed along such outer boundaries and ultimately used to form the transversely extending panels 38a and 38b. If the transversely extending panels 38a and 38b are formed using the first slit opening 90, then Figure 8-10 38a and 38b. Alternatively, if the second slit opening 94 is used to form the transversely extending panels 38a and 38b, the transversely extending panels 38a and 38b will be formed. Figure 5-7 A construction of the type shown is shown in which the material 46 of the second panel region 44 is within the laterally extending panels 38a and 38b.

[0109] Although the slit openings 90 (FIG. 12) and 94 (FIG. 15) are shown as having substantially the same lateral width as one another, it should be understood that in other embodiments, such slit openings may have different lateral widths relative to one another to form a similar configuration. Figure 5 、 7, 8 and 9 configurations.

[0110] Figure 17C Shown in Figure 17A and 17B Additional cross-sectional side views of the assembly 10 at the processing stage of FIG. Figure 17C The view is within the memory area 12a and along the Figure 11C The channel material pillar 24 is coupled to the bit line 98. The SGD device 100 is schematically shown adjacent to the upper region of the pillar 24 and below the bit line 98.

[0111] The bit lines 98 may extend in and out relative to Figure 17C Cross-sectional view of the page.

[0112] Pillar 26, bit line 98, SGD device 100, SGS device 66, and memory cell 64 may together be considered to form a NAND-type configuration similar to that described above with reference to Figures 1-4.

[0113] exist Figure 17C In the view of FIG, the SGD device 100 is indicated as being coupled to the conductive pillar 32 and Figure 17B In the view of FIG, some conductive pillars 32 are indicated as being coupled to the SGD device 100. Thus, in some embodiments, the SGD device 100 associated with the memory region (12a or 12b) can be coupled to the logic circuitry (e.g., Figure 5B 52b and 52c).

[0114] SGD device 100 is an example of a component that may be associated with cell material pillars 16 and coupled to logic circuitry through conductive pillars 32. In other embodiments, other components may be coupled to logic circuitry through one or more of conductive pillars 32, instead of or in addition to SGD device 100. For example, bit line 98 may be coupled to logic circuitry through conductive pillars 32, and in such embodiments, the logic circuitry may include sensing circuitry (e.g., sense amplifier circuitry) coupled to the bit line through conductive pillars 32. In general, one or more components may be operably proximate to cell material pillars 16 (and / or channel material pillars 24) and may be coupled to logic circuitry 52 (e.g., through conductive pillars 32) through conductive pillars 32. Figure 5B ).

[0115] Figure 17BOnly some of the conductive pillars 32 coupled to the SGD device 100 are shown. Such conductive pillars can be considered "live" pillars because they are used to form an electrical connection. The remaining conductive pillars 32 can be "dummy" pillars used only to provide structural support. The dummy pillars may or may not contain conductive material 28. For example, in some embodiments, the dummy pillars can be populated separately from the live pillars, such that the live pillars include the conductive material 28 of the conductive pillars 32, and the dummy pillars include only one or more insulating materials.

[0116] In some embodiments, all pillars 26 within step regions 40a and 40b may be dummy pillars, and the charged pillars may correspond to pillars 78 ( Figure 5 ).

[0117] Step contact 82 ( Figure 5 ). In some embodiments, they may be formed after forming pillars 26. In other embodiments, they may be formed before or during forming pillars 26.

[0118] The components and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0119] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0120] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be used within this disclosure to provide linguistic variance to simplify the premise basis in the following claims, and are not intended to indicate any significant chemical or electrical differences.

[0121] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in other instances may be intended to provide linguistic variation within this disclosure to simplify the underlying basis for the appended claims.

[0122] The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the following claims relate to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the drawings or rotated relative to such orientation.

[0123] Unless otherwise specified, the cross-sectional views of the accompanying figures illustrate only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawing.

[0124] When a structure is referred to as being "on," "adjacent," or "against" another structure, the structure may be directly on the other structure or there may be intervening structures. Conversely, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0125] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to the upper surface of the base.

[0126] Some embodiments include an integrated component having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. A stack extends across the first and second memory regions and the intermediate region. The stack includes alternating conductive and insulating levels. A first channel material pillar is arranged within the first memory region. A second channel material pillar is arranged within the second memory region. A memory block region extends longitudinally across the first and second memory regions and the intermediate region. A stepped region is within the intermediate region. Each of the stepped regions laterally overlaps with an associated two of the memory block regions. A first panel region extends longitudinally across at least a portion of the stepped region and laterally between the associated two of the memory block regions. A second panel region extends longitudinally between adjacent regions of the memory block region and provides lateral spacing. The second panel region has laterally different dimensions than the first panel region and / or is compositionally different from the first panel region.

[0127] Some embodiments include an integrated component comprising a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. A stack extends across the first and second memory regions and the intermediate region. The stack includes alternating conductive and insulating levels. A first channel material pillar is disposed within the first memory region. A second channel material pillar is disposed within the second memory region. A memory block region extends across the first and second memory regions and the intermediate region. The memory block region extends longitudinally. Each of the memory block regions includes a first edge region along a terminal edge of the first memory region and a second edge region along a terminal edge of the second memory region. A step region is within the intermediate region. Each of the step regions laterally overlaps with an associated two of the memory block regions. A longitudinally extending panel provides lateral spacing between adjacent regions of the memory block region. The longitudinally extending panels include a first longitudinally extending panel extending across the step region and a second longitudinally extending panel extending laterally between the step regions but not across the step region. The first laterally extending panel extends along the first edge region, and the second laterally extending panel extends along the second edge region. The first longitudinally extending panel comprises a first panel region extending completely across the step region. The second longitudinally extending panel comprises only a second panel region. The first panel region is laterally wider than the second panel region and / or compositionally different from the second panel region.

[0128] Some embodiments include a method for forming an integrated component. A structure is formed to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions. A stepped location is defined in the intermediate region. The structure includes a stack extending across the first memory region, the second memory region, and the intermediate region. The stack includes alternating first and second levels, wherein the first levels include sacrificial material and the second levels include insulating material. Pillars are formed extending through the stack within the first and second memory regions. The pillars include cell material and channel material. First slit openings are formed extending through the stack, wherein at least one of the first slit openings includes a segment extending across one of the stepped locations. A first panel material is formed within the first slit opening. A column opening is formed extending through the stack within the intermediate region. A column material is formed within the column opening. After forming the first panel material and the column material, a second slit opening is formed through the stack. One or more of the second slit openings extend across the first memory region, the intermediate region, and the second memory region. At least some of the sacrificial material in the first level is replaced with a conductive material. A second panel material is formed within the second slit opening.

[0129] As specified, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a first memory area, a second memory area offset from the first memory area, and an intermediate area between the first memory area and the second memory area; a stack extending across the first and second memory regions and the intermediate region, the stack comprising alternating conductive and insulating levels; a channel material pillar disposed within the first and second memory regions; a memory block region extending longitudinally across the first and second memory regions and the intermediate region; step regions within the middle region, each of the step regions laterally overlapping associated two of the memory block regions; a first panel region extending longitudinally across at least a portion of the staircase region and extending laterally between the associated two of the memory block regions; a second panel region extending longitudinally between adjacent regions of the memory block region and providing lateral spacing; and The second panel region has laterally different dimensions and / or is compositionally different from the first panel region. 2 . The integrated assembly of claim 1 , wherein the first panel region is laterally thicker than the second panel region. 3 . The integrated component of claim 2 , wherein an edge of one of the first panel areas abuts an edge of one of the second panel areas.

4. The integrated assembly of claim 1, wherein the second panel region is compositionally different from the first panel region.

5. The integrated assembly of claim 1, comprising a post disposed within the intermediate region.

6. The integrated assembly of claim 5, wherein at least some of the posts are used to provide electrical connections through the stack.

7. The integrated assembly of claim 6, wherein a component is operably proximate to the channel material pillars and is also coupled to the at least some of the pillars, and wherein the at least some of the pillars are electrically coupled to logic circuitry.

8. An integrated assembly according to claim 7, wherein the component comprises an SGD device.

9. The integrated assembly of claim 5, wherein at least some of the columns are used only for structural support.

10. An integrated assembly comprising: a first memory area, a second memory area offset from the first memory area, and an intermediate area between the first memory area and the second memory area; a stack extending across the first and second memory regions and the intermediate region, the stack comprising alternating conductive and insulating levels; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; a memory block region extending across the first and second memory regions and the middle region, the memory block region extending longitudinally; each of the memory block regions including a first edge region along a terminal edge of the first memory region and including a second edge region along a terminal edge of the second memory region; step regions within the middle region, each of the step regions laterally overlapping associated two of the memory block regions; a longitudinally extending panel providing lateral spacing between adjacent regions of the memory block region; the longitudinally extending panel comprising a first longitudinally extending panel extending across the step region and comprising a second longitudinally extending panel extending laterally between the step regions and not across the step region; a first laterally extending panel along said first edge region and a second laterally extending panel along said second edge region; the first longitudinally extending panel comprising a first panel region extending completely across the step region; the second longitudinally extending panel comprises only a second panel region; and The first panel region is laterally wider than the second panel region and / or compositionally different than the second panel region.

11. The integrated assembly of claim 10, wherein the first longitudinally extending panel comprises only the first panel region.

12. The integrated assembly of claim 10, wherein the first longitudinally extending panel includes the second panel region proximate the first panel region.

13. The integrated assembly of claim 10, wherein the first and second laterally-extending panels comprise only the first panel region.

14. An integrated component according to claim 13, wherein the memory block area is on the inner side of the first and second laterally extending panels, wherein the live contacts are on the outer side of at least one of the first and second laterally extending panels, and wherein there are no virtual contacts between the live contacts and the at least one of the first and second laterally extending panels.

15. The integrated assembly of claim 10, wherein the first and second laterally-extending panels comprise only the second panel region.

16. The integrated assembly of claim 10, wherein the first panel region is laterally thicker than the second panel region.

17. The integrated assembly of claim 10, wherein the first panel region is compositionally different from the second panel region.

18. The integrated assembly of claim 17, wherein the first panel region comprises only a single homogeneous material, and wherein the second panel region comprises a laminate of two or more different materials.

19. The integrated assembly of claim 17, wherein the first panel region consists essentially of silicon dioxide.

20. The integrated component of claim 17, wherein each of the second panel regions comprises a liner comprising silicon nitride, wherein the liner forms an upwardly open container shape, and each of the second panel regions further comprises a filling material within the upwardly open container shape.

21. The integrated assembly of claim 20, wherein the fill material consists essentially of silicon.

22. A method of forming an integrated assembly, comprising: forming a structure to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first memory region and the second memory region; a stepped location defined in the intermediate region; the construction comprising a stack extending across the first memory region, the second memory region, and the intermediate region; the stack comprising alternating first and second levels, wherein the first levels comprise a sacrificial material and the second levels comprise an insulating material; forming pillars extending through the stack within the first and second memory regions, the pillars comprising cell material and channel material; forming first slit openings extending through the stack, wherein at least one of the first slit openings includes a segment extending across one of the step locations; forming a first panel material within the first slit opening; forming a column opening extending through the stack within the intermediate region; forming a post material within the post opening; forming a second slit opening through the stack after forming the first panel material and the pillar material; one or more of the second slit openings extending across the first memory region, the intermediate region, and the second memory region; replacing at least some of the sacrificial material of the first level with a conductive material; as well as A second panel material is formed within the second slit opening.

23. The method of claim 22, wherein the post opening is formed simultaneously with the first slit opening.

24. The method of claim 22, wherein the first and second panel materials are the same composition as one another.

25. The method of claim 22, wherein the first and second panel materials are of different compositions relative to each other.

26. The method of claim 25, wherein the first panel material comprises silicon dioxide.

27. The method of claim 26, wherein the second panel material comprises two or more different compositions.

28. The method of claim 27, wherein the second panel material comprises a first composition comprising silicon nitride and a second composition consisting essentially of silicon.

29. The method of claim 22, wherein: the first memory region comprising a first outer boundary along an opposite side relative to the intermediate region; The second memory region includes a second outer boundary along an opposite side relative to the middle region; and Some of the first slit openings are formed to extend along the first and second outer boundaries.

30. The method of claim 22, wherein: the first memory region comprising a first outer boundary along an opposite side relative to the intermediate region; The second memory region includes a second outer boundary along an opposite side relative to the middle region; and Some of the second slit openings are formed to extend along the first and second outer boundaries.

31. The method of claim 22, wherein the second slit opening extends along a longitudinal direction, and wherein the first slit opening is at least as wide laterally as the second slit opening.

32. The method of claim 22, wherein the second slit opening extends along a longitudinal direction, and wherein the first slit opening is laterally wider than the second slit opening.

33. The method of claim 22, wherein at least one of the second slit openings has an edge directly against the first panel material.

34. The method of claim 22, wherein the first and second slit openings laterally separate memory block regions from each other.

Images