A semiconductor structure based on a ferroelectric Schottky tunneling junction and a preparation method thereof

Abstract

The present invention relates to a semiconductor structure based on a ferroelectric Schottky tunneling junction, comprising: a substrate; a first isolation layer disposed on the upper surface of the substrate; a channel layer disposed on the upper surface of the first isolation layer, including an intrinsic region and a doped region, the upper surface of the doped region being flush with the upper surface of the channel layer; a first electrode layer disposed on the upper surface of the intrinsic region; a second electrode layer disposed on the upper surface of the doped region; a ferroelectric layer disposed between the first electrode layer and the second electrode layer and covering a part of the upper surface of the first electrode layer; and a third electrode layer disposed on the upper surfaces of the ferroelectric layer and the second electrode layer. The semiconductor structure of the present invention utilizes the excellent unidirectional conductivity of the ferroelectric Schottky tunneling junction and realizes the switching and storage of the device by controlling the width of the ferroelectric Schottky tunneling junction through the ferroelectric layer, so that the switching control has good non-volatile impedance characteristics and unidirectional conductivity.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and particularly to a semiconductor structure based on a ferroelectric Schottky tunneling junction and a preparation method thereof. Background Art

[0002] With the advent of the era of "everything interconnected and everything intelligently connected", people have an urgent need for intelligence in various fields of application, and the existing artificial intelligence technologies and corresponding hardware can no longer meet the needs of the era. At present, the in-memory computing neuromorphic chip, as an important hardware support for neuromorphic computing technology, not only has brain-like functions such as large-scale parallel processing, self-organization, and self-learning, but also can break through the limitation of the "memory wall" of the von Neumann architecture through a distributed storage and computing structure, and has an irreplaceable application prospect in fields with high computing power, high energy efficiency, multi-task parallelism, and self-learning function requirements such as comprehensive information processing.

[0003] Inspired by the human brain neural network structure, non-volatile memristors can simulate the behavior of neural synapses and can form an in-memory computing neuromorphic chip with brain-like functions. Currently known non-volatile memristors that can simulate the behavior of neural synapses include: 1T1R units with bidirectional analog resistance modulation behavior, non-volatile phase change memristors, non-volatile ferroelectric tunneling junction memristors, etc. However, the relevant device structures are limited by the resistive bidirectional conduction working mode, resulting in signal bidirectional feedback behavior and system disorder of complex neural network multi-level neurons. Therefore, the relevant devices still do not have the ability to construct a highly energy-efficient and highly stable ultra-large-scale in-memory computing neuromorphic chip.

[0004] Therefore, it is necessary to develop a new semiconductor structure that has both good non-volatile impedance characteristics and excellent unidirectional conductivity. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a semiconductor structure based on a ferroelectric Schottky tunneling junction, which utilizes the excellent unidirectional conductivity of the ferroelectric Schottky tunneling junction and realizes the switching and storage of the device by controlling the width of the ferroelectric Schottky tunneling junction through a ferroelectric layer, so that the switching control has good non-volatile impedance characteristics and unidirectional conductivity.

[0006] Another purpose of the present invention is to provide a preparation method of the semiconductor structure.

[0007] In order to achieve the above purposes, the present invention provides the following technical solutions.

[0008] A semiconductor structure based on a ferroelectric Schottky tunneling junction, comprising:

[0009] A substrate;

[0010] A first isolation layer disposed on the upper surface of the substrate;

[0011] A channel layer is disposed on the upper surface of the first isolation layer and includes an intrinsic region and a doped region. The upper surface of the doped region is flush with the upper surface of the channel layer.

[0012] A first electrode layer is disposed on the upper surface of the intrinsic region;

[0013] A second electrode layer is disposed on the upper surface of the doped region;

[0014] A ferroelectric layer is disposed between the first electrode layer and the second electrode layer and covers a partial upper surface of the first electrode layer; and

[0015] A third electrode layer is disposed on the upper surfaces of the ferroelectric layer and the second electrode layer.

[0016] The present invention also provides a method for manufacturing a semiconductor structure based on a ferroelectric Schottky tunneling junction, including:

[0017] Providing a substrate;

[0018] Forming a first isolation layer and a channel layer on the upper surface of the substrate in sequence from bottom to top;

[0019] Performing ion implantation on a part of the channel layer to form a doped region, wherein the part without ion implantation is an intrinsic region;

[0020] After ion implantation, performing annealing activation treatment on the channel layer;

[0021] Forming a first electrode layer on the upper surface of the intrinsic region and forming a second electrode layer on the upper surface of the doped region;

[0022] Performing annealing treatment on the first electrode layer and the second electrode layer to make them form electrical contact with the channel layer;

[0023] Forming a ferroelectric layer between the first electrode layer and the second electrode layer and making it cover a partial upper surface of the first electrode layer;

[0024] Performing annealing treatment on the ferroelectric layer to activate the ferroelectricity of the ferroelectric layer; and

[0025] Forming a third electrode layer on the upper surfaces of the ferroelectric layer and the second electrode layer.

[0026] Compared with the prior art, the beneficial effects of the present invention:

[0027] The present invention provides a semiconductor structure based on a ferroelectric Schottky tunneling junction. By utilizing the polarization characteristics of the ferroelectric material, stable polarization charges are generated on the surface of the ferroelectric layer after applying a pulse to the ferroelectric layer, and the stable polarization charges are combined with a wide-barrier ferroelectric Schottky tunneling junction formed by a first electrode layer metal with a large work function and a semiconductor with a low doping concentration (i.e., an intrinsic region). By applying different pulse voltages, different types of charges are generated on the surface of the ferroelectric layer, thereby inducing corresponding carriers in the channel layer, and then stably regulating the barrier width of the ferroelectric Schottky tunneling junction to achieve stable switching-state storage. Since the entire stored information exhibits electrical characteristics through the ferroelectric Schottky tunneling junction formed by the semiconductor and the metal, it has the characteristic of unidirectional conduction. With the stable polarization charges, the switching and storage of the device are realized by controlling the width of the ferroelectric Schottky tunneling junction through the ferroelectric layer, making the switching control have stable characteristics and unidirectional conductivity.

[0028] In addition, the carriers in the semiconductor structure of the present invention are transported through tunneling and drift-diffusion methods, so that the semiconductor structure has a large on-state current. Additionally, due to the polarization control of the ferroelectric layer, the barrier width of the ferroelectric Schottky tunneling junction formed by the first electrode layer and the intrinsic region becomes smaller in the on-state and larger in the off-state, so that the semiconductor structure has a very large current on-off ratio.

[0029] Furthermore, ferroelectric Schottky tunneling junctions are formed between the first electrode layer and the intrinsic region, and between the second electrode layer and the doped region of the present invention. Through the bilateral Schottky barriers, a large voltage division is generated during writing, thereby reducing the number of electrodes. At the same time, since the first electrode layer and the second electrode layer can achieve stable writing and reading, the semiconductor structure of the present invention can be highly integrated to realize the construction and simulation of a neural network-like structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0031] Figure 1 is a schematic diagram of the semiconductor structure based on the ferroelectric Schottky tunneling junction of the present invention.

[0032] Figures 2 - 10 is a schematic diagram of the structure obtained in each step of the preparation method provided by the embodiment of the present invention.

[0033] DESCRIPTION OF THE REFERENCE NUMERALS

[0034] 100 is the substrate, 200 is the first isolation layer, 300 is the channel layer, 301 is the intrinsic region, 302 is the doped region, 400 is the first electrode layer, 500 is the second electrode layer, 600 is the ferroelectric layer, 700 is the third electrode layer, 800 is the gate dielectric layer, 900 is the conductive layer, 1000 is the second isolation layer, 1100 is the third isolation layer, 1200 is the fourth isolation layer, 1300 is the fifth isolation layer. Detailed implementation manners

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] Schematic diagrams of various structures according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0037] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element.

[0038] Since existing ferroelectric tunneling junction devices, although having stable switching states, do not have unidirectional conductivity. Therefore, the present invention provides a new semiconductor structure based on a ferroelectric Schottky tunneling junction. The semiconductor structure of the present invention will be further described below with reference to the accompanying drawings.

[0039] Figure 1 A schematic diagram of the semiconductor structure based on the ferroelectric Schottky tunneling junction of the present invention is given. As Figure 1As shown in the figure, the semiconductor structure based on a ferroelectric Schottky tunneling junction of the present invention includes: a substrate 100; a first isolation layer 200 disposed on the upper surface of the substrate 100; a channel layer 300 disposed on the upper surface of the first isolation layer 200, including an intrinsic region 301 and a doped region 302, and the upper surface of the doped region 302 is flush with the upper surface of the channel layer 300; a first electrode layer 400 disposed on the upper surface of the intrinsic region 301; a second electrode layer 500 disposed on the upper surface of the doped region 302; a ferroelectric layer 600 disposed between the first electrode layer 400 and the second electrode layer 500 and covering a part of the upper surface of the first electrode layer 400; and a third electrode layer 700 disposed on the upper surfaces of the ferroelectric layer 600 and the second electrode layer 500.

[0040] Preferably, the substrate 100 can be any one of Si, Ge, SiC, GaN, sapphire, and diamond.

[0041] Preferably, the thickness of the first isolation layer 200 can be 10 - 50 nm, preferably 10 - 20 nm.

[0042] Preferably, the first isolation layer 200 can be any one of SiO2, BPSG, and borosilicate glass.

[0043] Preferably, the thickness of the channel layer 300 can be 5 nm - 50 nm, preferably 5 nm - 20 nm, and more preferably 5 nm - 10 nm.

[0044] Preferably, the channel layer 300 can be any semiconductor material, for example, it can be any one of Si, Ge, SiGe, GaN, GaAs, GaO, and two-dimensional materials. The channel layer 300 includes an intrinsic region 301 and a doped region 302. The impurity concentration of the intrinsic region 301 should be as low as possible. Preferably, the impurity concentration is less than or equal to 1×10 18 cm -3 , and the impurity type is not limited, so as to form a ferroelectric Schottky tunneling junction between the intrinsic region 301 and the first electrode layer 400. The doping concentration of the doped region 302 can be 1×10 18 cm -3 to 1×10 20 cm -3 . The doped region 302 forms a ferroelectric Schottky tunneling junction with the second electrode layer 500, and the barrier width of the ferroelectric Schottky tunneling junction is preferably below 10 nm.

[0045] Preferably, both the first electrode layer 400 and the second electrode layer 500 can be any one of tungsten metal, titanium metal, copper metal, aluminum metal, platinum metal, iridium metal, ruthenium metal, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0046] Preferably, the thicknesses of the first electrode layer 400 and the second electrode layer 500 can both be 3 - 50 nm, preferably 3 - 10 nm.

[0047] Preferably, the ferroelectric layer 600 is a ferroelectric material and a ferroelectric-like material having polarization properties. For example, it can be Hf 0.5 Zr 0.5 O2 (HZO), Hf 1-x Al x O2 (HAO) (x = 0 - 1), HfSiO, Al2O3, HfO2, ZrO2, BaTiO3, Cd2Nb2O7, BiFeO3, SrBi2Ta2O9 (SBT), ZnSnO3 or polyvinylidene fluoride (PVDF). Under the action of an externally applied electric field, the asymmetric electric dipoles contained in the unit cells of the ferroelectric material can undergo directional flipping, and still maintain the directional flipping after the electric field is removed. Due to such characteristics of the ferroelectric material, a certain amount of polarized charge can be generated on the surface of the ferroelectric material, that is, before the polarization degree of the ferroelectric material reaches the saturation polarization intensity, the density of the surface polarized charge is proportional to the applied voltage.

[0048] Preferably, the thickness of the ferroelectric layer 600 can be 3 - 20 nm, preferably 3 - 11 nm.

[0049] In the present invention, the ferroelectric layer 600 covers a part of the upper surface of the first electrode layer 400, and the covering width is not less than 10 nm. The advantage of such a setting is that: the input writing voltage can cause the ferroelectric layer 600 to undergo directional polarization.

[0050] Preferably, the third electrode layer 700 can be any one of tungsten metal, titanium metal, copper metal, aluminum metal, platinum metal, iridium metal, ruthenium metal, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide. The third electrode layer 700 is used to connect the ferroelectric layer 600 and the second electrode layer 500.

[0051] In some embodiments, the semiconductor structure of the present invention further includes: a gate dielectric layer 800 and a conductive layer 900, which are stacked in sequence from bottom to top between the channel layer 300 and the ferroelectric layer 600, and the ferroelectric layer 600, the conductive layer 900, and the gate dielectric layer 800 are conformal. When a write voltage is applied to the device, due to the voltage division of the gate dielectric layer 800, the voltage drop between the third electrode layer 700 and the first electrode layer 400 is evenly distributed across the entire ferroelectric layer 600, making the polarization region area of the ferroelectric layer 600 larger and the polarization more uniform, so that the ferroelectric layer 600 has a larger range of carrier regulation for the channel layer, which is beneficial to improving the switching current ratio of the device and enhancing the stability of the device. The gate dielectric layer 800 and the conductive layer 900 can make the polarization of the ferroelectric layer 600 more uniform, thus facilitating the improvement of the stability of the switching control.

[0052] Preferably, the gate dielectric layer 800 can be SiO2, Si3N4, Ta2O5, TiO2, HfO2, ZrO2, Al2O3, Er2O3, HfSiON, or borosilicate glass.

[0053] Preferably, the thickness of the gate dielectric layer 800 can be 2 - 10 nm, preferably 2 - 5 nm.

[0054] Preferably, the gate dielectric layer 800 covers a part of the upper surface of the second electrode layer 500. Since the ferroelectric layer 600, the conductive layer 900, and the gate dielectric layer 800 are conformal, such an arrangement can prevent the ferroelectric layer 600 from directly contacting the second electrode layer 500, reducing the lateral electric field influence of the electrode 500 on the ferroelectric layer 600 during the application of a write pulse. Therefore, the ferroelectric layer is more controlled by the electric field perpendicular to the channel layer, thereby enhancing the polarization intensity of the ferroelectric layer during the writing process and further improving the current switching ratio.

[0055] Preferably, the conductive layer 900 can be any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0056] Preferably, the thickness of the conductive layer 900 can be 5 - 50 nm.

[0057] In some embodiments, the semiconductor structure of the present invention further includes: a second isolation layer 1000, which covers a part of the upper surface of the first electrode layer 400 and a part of the ferroelectric layer 600; and a third isolation layer 1100, which is disposed between a part of the ferroelectric layer 600 and a part of the third electrode layer 700. In this embodiment, the third electrode layer 700 covers a part of the ferroelectric layer 600, the third isolation layer 1100, and a part of the second electrode layer 500.

[0058] In some embodiments, the semiconductor structure of the present invention further includes: a fourth isolation layer covering a part of the upper surface and the side surface of the first electrode layer; and a fifth isolation layer covering a part of the upper surface and the side surface of the second electrode layer.

[0059] Preferably, each of the second isolation layer 1000, the third isolation layer 1100, the fourth isolation layer 1200, and the fifth isolation layer 1300 can be any one of SiO2, BPSG, and borosilicate glass.

[0060] Preferably, the thickness of each of the second isolation layer 1000, the third isolation layer 1100, the fourth isolation layer 1200, and the fifth isolation layer 1300 can be 10 - 100 nm, preferably 10 - 50 nm. These four isolation layers act as protective layers during the device fabrication process to prevent contamination of the ferroelectric layer and the electrode metal by lithography. The isolation layer 1100 reduces the influence of the lateral electric field of the third electrode layer 700 on the ferroelectric layer, such that during the write pulse process, the electric field direction is perpendicular to the ferroelectric layer.

[0061] The switching control principle of the semiconductor structure of the present invention is as follows.

[0062] A positive pulse voltage is applied to the third electrode layer 700. Since the intrinsic region 301 is not heavily doped and has a high impedance, under the positive pulse, the ferroelectric layer 600 is polarized, causing electrons to be induced in the intrinsic region 301. Thus, a conduction path is formed as the third electrode layer 700 - the second electrode layer 500 - the doped region 302 - the intrinsic region 301 - the first electrode layer 400, which is the on state.

[0063] Based on the above on state, a negative pulse is applied. Since the small ferroelectric Schottky tunneling junction formed by the second electrode layer 500 and the doped region 302 generates a large voltage drop under the reverse voltage, a voltage drop occurs between the position of the intrinsic region 301 and the position of the third electrode layer 700 (plus the overlap formed by the conformal part and the first electrode layer 400). As a result, the polarization of the ferroelectric layer 600 is reversed, causing the intrinsic region 301 to transform from a semiconductor with electrons as the majority carriers to a semiconductor with holes as the majority carriers. Since the metal work function of the first electrode layer 400 is relatively large, the Schottky barrier width formed by the first electrode layer 400 and the intrinsic region 301 is relatively large at this time, and the device is turned off.

[0064] The present invention also provides a method for fabricating the semiconductor structure based on the ferroelectric Schottky tunneling junction, in combination with Figures 2 - 10 , and the specific process is as follows.

[0065] First, a substrate 100 is provided.

[0066] Then, a first isolation layer 200 and a channel layer 300 are sequentially formed on the upper surface of the substrate 100 from bottom to top, and the resulting structure is as Figure 2 shown.

[0067] Preferably, the first isolation layer 200 and the channel layer 300 can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0068] Preferably, after the channel layer 300 is formed and before ion implantation, a sacrificial layer is formed on the upper surface of the channel layer 300, and the resulting structure is as Figure 3 shown. Setting the sacrificial layer can avoid damaging the channel layer 300 during ion implantation.

[0069] Preferably, the sacrificial layer can be formed by chemical vapor deposition.

[0070] Preferably, the sacrificial layer can be SiO2. The thickness of the sacrificial layer can be 10 - 50 nm, preferably 10 - 20 nm.

[0071] After that, part of the channel layer 300 is ion-implanted to form a doped region 302, and the un-implanted part is an intrinsic region 301. The resulting structure is as Figure 4 shown.

[0072] After ion implantation, an annealing activation treatment is performed on the channel layer.

[0073] Preferably, the annealing temperature is 900 - 1100 °C.

[0074] Next, a first electrode layer 400 is formed on the upper surface of the intrinsic region, and a second electrode layer 500 is formed on the upper surface of the doped region.

[0075] In some specific embodiments, a sacrificial layer is formed on the upper surface of the channel layer 300. The forming methods of the first electrode layer 400 and the second electrode layer 500 include: etching the sacrificial layer to form a first groove and a second groove, so as to expose part of the upper surfaces of the intrinsic region 301 and the doped region 302. The resulting structure is as Figure 5 shown; forming the first electrode layer at the first groove and the second electrode layer at the second groove by magnetron sputtering; and removing the remaining sacrificial layer. The resulting structure is as Figure 6 shown.

[0076] Then, an annealing treatment is performed on the first electrode layer 400 and the second electrode layer 500 to make them form electrical contact with the channel layer 300.

[0077] Preferably, the annealing is rapid annealing for 30 - 90 s, and the annealing temperature is 700 - 1100 °C.

[0078] After that, a ferroelectric layer 600 is formed between the first electrode layer 400 and the second electrode layer 500 and covers part of the upper surface of the first electrode layer 400.

[0079] Preferably, the ferroelectric layer 600 can be formed by atomic layer deposition.

[0080] In some specific embodiments, the method for forming the ferroelectric layer 600 includes: forming a ferroelectric material layer by atomic layer deposition to cover the channel layer 300, the first electrode layer 400, and the second electrode layer 500; and removing a part of the ferroelectric material layer, so as to form a ferroelectric layer between the first electrode layer 400 and the second electrode layer 500 and make it cover a part of the upper surface of the first electrode layer 400.

[0081] Preferably, before forming the ferroelectric layer 600, a gate dielectric layer 800 and a conductive layer 900 are sequentially formed from bottom to top between the first electrode layer 400 and the second electrode layer 500, and the ferroelectric layer 600, the conductive layer 900, and the gate dielectric layer 800 are conformal.

[0082] In some specific embodiments, first, a gate dielectric layer 800 is formed by atomic layer deposition to cover the channel layer 300, the first electrode layer 400, and the second electrode layer 500; then, a conductive layer 900 and a ferroelectric layer 600 are sequentially formed from bottom to top on the upper surface of the gate dielectric layer 800 by atomic layer deposition, and the obtained structure is as Figure 7 shown; then, the ferroelectric layer 600, the conductive layer 900, and the gate dielectric layer 800 are etched to make the three layers conformal, and the obtained structure is as Figure 8 shown.

[0083] Next, the ferroelectric layer 600 is annealed to activate the ferroelectricity of the ferroelectric layer 600.

[0084] Preferably, the annealing is rapid annealing for 30 - 90 s, and the annealing temperature is 500 - 800 °C.

[0085] Finally, a third electrode layer 700 is formed on the upper surfaces of the ferroelectric layer 600 and the second electrode layer 500.

[0086] Preferably, the third electrode layer 700 can be formed by magnetron sputtering.

[0087] In some embodiments, after forming the ferroelectric layer 600, first, an isolation material layer is formed to cover the channel layer 300, the first electrode layer 400, the ferroelectric layer 600, and the second electrode layer 500, and the obtained structure is as Figure 9 shown; then, the isolation material layer is etched to form a first window, a second window, a third isolation layer 1100, and a fifth isolation layer 1300, so as to expose a part of the ferroelectric layer 600 and a part of the second electrode layer 500, and the obtained structure is as Figure 10As shown; afterwards, a third electrode layer 700 is formed at the first window and the second window by magnetron sputtering to electrically connect the ferroelectric layer 600 and the second electrode layer 500; finally, a part of the isolation material layer on the upper surface of the first electrode layer 400 is removed, thereby forming a second isolation layer 1000 and a fourth isolation layer 1200, and the resulting structure is as Figure 1 shown.

[0088] Preferably, the isolation material layer can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0089] The present invention will be further described below in conjunction with specific embodiments and drawings.

[0090] Embodiment 1

[0091] A Schottky tunneling junction based on HZO ferroelectric material is fabricated on a Si substrate.

[0092] Step 1: Select a substrate and grow a dielectric isolation layer.

[0093] An SOI substrate composed of Si as the substrate 100, SiO2 as the first isolation layer 200, and Si as the channel layer 300 in sequence is selected, as Figure 2 shown; a 8-nm-thick sacrificial layer is grown by chemical vapor deposition process, and the resulting structure is as Figure 3 shown.

[0094] Step 2: Ion implantation.

[0095] The sacrificial layer is lithographed, and then by using the ion implantation process, P - is used as the ion source, the ion implantation energy is set to 20 keV, and the implantation starts from the surface of the sacrificial layer, and the carrier concentration of the doped region is 1×10 18 cm -3 , and the resulting structure is as Figure 4 shown.

[0096] Step 3: Form the first electrode layer 400 and the second electrode layer 500.

[0097] By using the lithography process and the etching process, holes are formed in the sacrificial layer. The specific steps are as follows: The structure as Figure 4 shown is patterned by the lithography process, then it is soaked in an NH4F solution for 30 s, and then soaked in deionized water for 30 s, and repeated 3 - 5 times, thereby etching holes in the sacrificial layer, and the resulting structure is as Figure 5 shown. Afterwards, the first electrode layer 400 and the second electrode layer 500 are formed by magnetron sputtering technology. The specific steps are as follows: First, the reaction chamber is evacuated by a molecular pump and a cold pump until the vacuum pressure is 8×10 -10Torr, and then under the conditions of a power of 300 W and an Ar pressure of 5 mTorr, Ni was used as the target through-hole for sputtering to form the first electrode layer 400 and the second electrode layer 500. Then, a rapid annealing process was carried out for 50 s at 1000 °C. The annealed structure was immersed in an NH4F solution for 30 s, and then in deionized water for 30 s, and this was repeated 3 - 5 times to remove the remaining sacrificial layer. The resulting structure is as shown in Figure 6 shown.

[0098] Step 4: Grow the gate control layer.

[0099] First, a SiO2 gate dielectric layer 800 was deposited using an ultra-high vacuum chemical vapor deposition process. The specific steps are as follows: SiCl4 was used as the silicon source, H2O was used as the oxygen source, and a 3-nm SiO2 gate dielectric layer 800 was deposited at 500 °C. Then, using magnetron sputtering technology, a 5-nm TiN metal layer 900 was sputter-grown under the condition of an Ar pressure of 7 mTorr. After that, again using a vacuum chemical vapor deposition process, with TEMAHf as the precursor hafnium source, TEMAZr as the precursor zirconium source, O3 as the precursor oxygen source, N2 as the purge gas, and at a reaction temperature of 260 °C, a 10-nm HZO ferroelectric layer 600 was grown. The resulting structure is as shown in Figure 7 shown.

[0100] Step 5: Grow the third electrode layer

[0101] Using an etching process, the gate control region was etched. The resulting structure is as shown in Figure 8 shown. Then, using an ultra-high vacuum chemical vapor deposition process, SiO2 was deposited. The specific steps are as follows: SiCl4 was used as the silicon source, H2O was used as the oxygen source, and 20-nm SiO2 was deposited at 500 °C as the isolation layer. The resulting structure is as shown in Figure 9 shown. After that, an etching process was used to etch out the corresponding holes for forming the third electrode layer 700, as shown in Figure 10 shown. Then, the third electrode layer 700 was formed using magnetron sputtering technology. The specific steps are as follows: First, the reaction chamber was evacuated using a molecular pump and a cold pump until the vacuum pressure was 5×10 -12 Torr, and then under the conditions of a power of 550 W and an Ar pressure of 5 mTorr, Au was used as the target through-hole for sputtering to form the third electrode layer 700. Finally, the isolation layer was etched using an etching process to partially expose the first electrode layer 400. The resulting structure is as shown in Figure 1 shown. The device fabrication is completed.

[0102] Example 2

[0103] A Schottky tunneling junction based on HAO ferroelectric material was fabricated on a Ge substrate.

[0104] Step 1: Select a substrate and grow a dielectric isolation layer.

[0105] Select a GOI substrate composed of Ge as the substrate 100, SiO2 as the first isolation layer 200, and Si as the channel layer 300 in sequence, as Figure 2 shown; use chemical vapor deposition process to grow a 8-nm-thick sacrificial layer, and the obtained structure is as Figure 3 shown.

[0106] Step 2: Ion implantation.

[0107] Perform photolithography on the sacrificial layer, and then use the ion implantation process. Use P - as the ion source, set the ion implantation energy to 15 keV, start implanting from the surface of the sacrificial layer, and the carrier concentration of the doped region is 1×10 18 cm -3 , and the obtained structure is as Figure 4 shown.

[0108] Step 3: Form the first electrode layer 400 and the second electrode layer 500.

[0109] Use photolithography and etching processes to form holes in the sacrificial layer. The specific steps are as follows: Pattern the structure as Figure 4 shown by photolithography, then soak it in NH4F solution for 20 s, and then soak it in deionized water for 25 s, repeat 4 - 6 times, so as to etch holes in the sacrificial layer, and the obtained structure is as Figure 5 shown. After that, use magnetron sputtering technology to form the first electrode layer 400 and the second electrode layer 500. The specific steps are as follows: First, use a molecular pump and a cold pump to evacuate the reaction chamber until the vacuum pressure is 1×10 -11 Torr, then under the conditions of 280 W power and 8 mTorr Ar pressure, use W as the target material through-hole for sputtering, so as to form the first electrode layer 400 and the second electrode layer 500. Then, use rapid annealing process for 50 s at 1000 °C. Soak the annealed structure in NH4F solution for 30 s, and then soak it in deionized water for 30 s, repeat 3 - 5 times, so as to remove the remaining sacrificial layer, and the obtained structure is as Figure 6 shown.

[0110] Step 4: Grow a gate control layer.

[0111] First, use the ultra-high vacuum chemical vapor deposition process to deposit the SiO2 gate dielectric layer 800. The specific steps are as follows: Use SiCl4 as the silicon source and H2O as the oxygen source to deposit a 3nm SiO2 gate dielectric layer 800 at 500°C. Then, use the magnetron sputtering technique to sputter-grow a 5nm TiN metal layer 900 under the condition of an Ar pressure of 7mTorr. After that, use the vacuum chemical vapor deposition process again. Use TEMAHf as the precursor hafnium source, TMA as the precursor aluminum source, O3 as the precursor oxygen source, N2 as the purge gas, and grow an 8nm HAO ferroelectric layer 600 under the condition of a reaction temperature of 270°C. And anneal the device rapidly at 750°C for 30S under N2. The obtained structure is as Figure 7 shown.

[0112] Step 5: Grow the third electrode layer

[0113] Use the etching process to etch out the gate-controlled area. The obtained structure is as Figure 8 shown. Then use the ultra-high vacuum chemical vapor deposition process to deposit SiO2. The specific steps are as follows: Use SiCl4 as the silicon source and H2O as the oxygen source to deposit 20nm SiO2 at 500°C as the isolation layer. The obtained structure is as Figure 9 shown. After that, use the etching process to etch out the corresponding holes for forming the third electrode layer 700, as Figure 10 shown. Then, use the magnetron sputtering technique to form the third electrode layer 700. The specific steps are as follows: First, use a molecular pump and a cold pump to evacuate the reaction chamber until the vacuum pressure is 5×10 -12 Torr. Then, under the conditions of a power of 550W and an Ar pressure of 5mTorr, use Au as the target material to sputter through the holes, thereby forming the third electrode layer 700. Finally, use the etching process to etch the isolation layer to expose part of the first electrode layer 400. The obtained structure is as Figure 1 shown. The device fabrication is completed.

[0114] Example 3

[0115] Fabricate a Schottky tunneling junction based on HfSiO ferroelectric material on an Si substrate.

[0116] Step 1: Select the substrate and grow the dielectric isolation layer.

[0117] Select an SOI substrate composed of Si as the substrate 100, SiO2 as the first isolation layer 200, and Si as the channel layer 300 in sequence, as Figure 2 shown; Use the chemical vapor deposition process to grow a 8nm thick sacrificial layer. The obtained structure is as Figure 3 shown.

[0118] Step 2: Ion implantation.

[0119] Lithography is performed on the sacrificial layer, and then, using the ion implantation process, P - is used as the ion source, the ion implantation energy is set to 20 keV, implantation starts from the surface of the sacrificial layer, and the carrier concentration in the doped region is 1×10 18 cm -3 , and the obtained structure is as Figure 4 shown.

[0120] Step 3: Form the first electrode layer 400 and the second electrode layer 500.

[0121] Using the lithography process and the etching process, holes are formed on the sacrificial layer. The specific steps are as follows: The structure as Figure 4 shown is patterned through the lithography process, then it is soaked in an NH4F solution for 35 s, and then soaked in deionized water for 20 s, repeating 3 - 5 times, so as to etch holes on the sacrificial layer. The obtained structure is as Figure 5 shown. After that, the first electrode layer 400 and the second electrode layer 500 are formed using the magnetron sputtering technique. The specific steps are as follows: First, the reaction chamber is evacuated using a molecular pump and a cold pump until the vacuum pressure is 5×10 -10 Torr. Then, under the conditions of a power of 250 W and an Ar pressure of 8 mTorr, sputtering is performed using Ni as the target material through-hole, so as to form the first electrode layer 400 and the second electrode layer 500. Then, using the rapid annealing process, rapid annealing is carried out at 1000 °C for 50 s. The annealed structure is soaked in an NH4F solution for 30 s, and then soaked in deionized water for 30 s, repeating 3 - 5 times, so as to remove the remaining sacrificial layer. The obtained structure is as Figure 6 shown.

[0122] Step 4: Grow the gate control layer.

[0123] First, using the ultra-high vacuum chemical vapor deposition process, deposit the SiO2 gate dielectric layer 800. The specific steps are as follows: Using SiCl4 as the silicon source and H2O as the oxygen source, deposit a 3-nm SiO2 gate dielectric layer 800 at 500 °C. Then, using the magnetron sputtering technique, sputter and grow a 5-nm TiN metal layer 900 under the condition of an Ar pressure of 7 mTorr. After that, using the vacuum chemical vapor deposition process again, using TEMAHf as the precursor hafnium source, 4DMAS as the precursor silicon source, O3 as the precursor oxygen source, N2 as the purge gas, and under the condition of a reaction temperature of 500 °C, grow a 12-nm HfSiO ferroelectric layer 600, and perform rapid annealing on the device at 700 °C for 60 S under N2. The obtained structure is as Figure 7 shown.

[0124] Step 5: Grow the third electrode layer

[0125] Using an etching process, an etched gate control region is obtained, and the resulting structure is as shown in Figure 8 . Then, using an ultra-high vacuum chemical vapor deposition process, SiO2 is deposited. The specific steps are as follows: Using SiCl4 as the silicon source and H2O as the oxygen source, 20 nm of SiO2 is deposited at 500 °C as the isolation layer, and the resulting structure is as shown in Figure 9 . After that, an etching process is used to etch out the corresponding holes for forming the third electrode layer 700, as shown in Figure 10 . Then, a third electrode layer 700 is formed using a magnetron sputtering technique. The specific steps are as follows: First, the reaction chamber is evacuated using a molecular pump and a cold pump until the vacuum pressure is 5×10 -12 Torr. Then, under the conditions of a power of 550 W and an Ar pressure of 5 mTorr, Au is used as the target material for through-hole sputtering to form the third electrode layer 700. Finally, the isolation layer is etched using an etching process to partially expose the first electrode layer 400, and the resulting structure is as shown in Figure 1 . The device fabrication is completed.

[0126] As described above, only the preferred specific embodiments of the present invention are given, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. For example, in addition to the planar process given in this embodiment, the device process structure also includes three-dimensional Schottky tunneling junctions using Nanowire type, Nanosheet type, and FinFET type structures. These improvements and refinements should also be regarded as within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure based on a ferroelectric Schottky tunneling junction, characterized in that, Comprising: A substrate; A first isolation layer disposed on the upper surface of the substrate; A channel layer disposed on the upper surface of the first isolation layer, including an intrinsic region and a doped region, the upper surface of the doped region being flush with the upper surface of the channel layer; A first electrode layer disposed on the upper surface of the intrinsic region; A second electrode layer disposed on the upper surface of the doped region; A ferroelectric layer disposed between the first electrode layer and the second electrode layer and covering a part of the upper surface of the first electrode layer, the first electrode layer not being connected to the ferroelectric layer; And A third electrode layer disposed on the upper surfaces of the ferroelectric layer and the second electrode layer, and the third electrode layer contacting and connecting the ferroelectric layer and the second electrode layer.

2. The semiconductor structure according to claim 1, characterized in that, Further comprising: A gate dielectric layer and a conductive layer stacked in sequence from bottom to top between the channel layer and the ferroelectric layer, and the ferroelectric layer, the conductive layer and the gate dielectric layer being conformal.

3. The semiconductor structure according to claim 2, characterized in that, The gate dielectric layer covering a part of the upper surface of the second electrode layer.

4. The semiconductor structure according to claim 3, characterized in that, Further comprising: A second isolation layer covering a part of the upper surface of the first electrode layer and covering a part of the ferroelectric layer; And A third isolation layer disposed between a part of the ferroelectric layer and a part of the third electrode layer.

5. The semiconductor structure according to claim 1 or 2, characterized in that, Further comprising: A fourth isolation layer covering a part of the upper surface and the side surface of the first electrode layer; A fifth isolation layer covering a part of the upper surface and the side surface of the second electrode layer.

6. The semiconductor structure according to claim 1 or 2, characterized in that, The thickness of the channel layer is 5 nm - 50 nm.

7. The semiconductor structure according to claim 1 or 2, characterized in that, The doping concentration of the doped region is less than or equal to 1×10 20 cm -3 ; The doped region and the second electrode layer form a ferroelectric Schottky tunneling junction, and the barrier width of the ferroelectric Schottky tunneling junction is below 10 nm.

8. A method for preparing a semiconductor structure based on a ferroelectric Schottky tunneling junction, characterized in that, Comprising: Providing a substrate; Sequentially forming a first isolation layer and a channel layer on the upper surface of the substrate from bottom to top; Performing ion implantation on a part of the channel layer to form a doped region, wherein the part not subjected to ion implantation is the intrinsic region; After ion implantation, performing an annealing activation treatment on the channel layer; Forming a first electrode layer on the upper surface of the intrinsic region and forming a second electrode layer on the upper surface of the doped region; Performing an annealing treatment on the first electrode layer and the second electrode layer to make them form electrical contact with the channel layer; Forming a ferroelectric layer between the first electrode layer and the second electrode layer and making it cover a part of the upper surface of the first electrode layer, the first electrode layer not being connected to the ferroelectric layer; Performing an annealing treatment on the ferroelectric layer to activate the ferroelectricity of the ferroelectric layer; And Forming a third electrode layer on the upper surfaces of the ferroelectric layer and the second electrode layer, and the third electrode layer contacting and connecting the ferroelectric layer and the second electrode layer.

9. The preparation method according to claim 8, characterized in that, Further comprising: Before forming the ferroelectric layer, sequentially forming a gate dielectric layer and a conductive layer between the first electrode layer and the second electrode layer from bottom to top, and making the ferroelectric layer, the conductive layer and the gate dielectric layer conformal.

10. The preparation method according to claim 8 or 9, characterized in that, Further comprising: After forming the ferroelectric layer, forming an isolation material layer to cover the channel layer, the first electrode layer, the ferroelectric layer and the second electrode layer; Etching the isolation material layer to form a first window, a second window, a third isolation layer and a fifth isolation layer, so as to expose a part of the ferroelectric layer and a part of the second electrode layer; Form the third electrode layer at the first window and the second window, and electrically connect the ferroelectric layer and the second electrode layer; and Remove a part of the isolation material layer on the upper surface of the first electrode layer, so as to form a second isolation layer and a fourth isolation layer.

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