A heterojunction trench t-gate power mosfet device and a method of manufacturing the same

Abstract

The application discloses a heterojunction trench T-shaped gate power MOSFET device and a preparation method thereof, which comprises a substrate, a hetero-epitaxial buffer layer, an epitaxial channel layer, a source region heavily doped ohmic contact region, a drain electrode and a gate electrode; the material of the hetero-epitaxial buffer layer is beta-Ga2O3; the source region current blocking layer is arranged in the hetero-epitaxial buffer layer; the epitaxial channel layer is arranged in the hetero-epitaxial buffer layer; the material of the epitaxial channel layer is doped beta-Ga2O3; the trench is arranged on the epitaxial channel layer; the first gate oxide layer is arranged on the epitaxial channel layer and the inner wall of the trench; the surface of the first gate oxide layer is provided with the second gate oxide layer, and the surface of the second gate oxide layer is provided with the third gate oxide layer; the passivation layer is arranged on the hetero-epitaxial buffer layer; the source electrode is arranged on the two sides of the gate electrode; and the source region heavily doped ohmic contact region is connected with the lower end of the source electrode. The application improves the beta-Ga2O3 MOSFET breakdown voltage, reduces the gate leakage current, improves the high-temperature reliability of the device and realizes the enhancement mode MOSFET.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of discrete devices for high-frequency and high-power applications, and particularly relates to a heterojunction trench T-shaped gate power MOSFET device and a preparation method thereof. BACKGROUND

[0002] Power devices based on wide-bandgap semiconductor materials have the advantages of high breakdown field strength, low on-resistance, high temperature resistance, radiation resistance, and small size, and become the preferred material for making power devices. At present, wide-bandgap semiconductor materials and devices represented by SiC and GaN have been developed for many years, and the device performance has gradually approached or exceeded that of silicon-based power devices. However, the difficulty in growing bulk single crystals of SiC and GaN and the high cost limit the application of the latter devices. Ga2O3 material is a new wide-bandgap semiconductor material after SiC and GaN, with a much wider band gap (4.7-4.9 eV) and a much higher theoretical breakdown field (8 MV / cm) than SiC and GaN. It not only has better physical properties such as high temperature resistance, high voltage resistance, and radiation resistance than SiC and GaN, but also has other good material properties such as deep ultraviolet light detection optical properties and high sensitivity gas sensing properties, and has the transparency of sapphire and the conductivity of SiC. It has great application space in high-frequency, high-power devices, ultraviolet light detectors, and transparent conductive films, and has broad application prospects in aerospace, military, and nuclear energy.

[0003] However, the application of beta-Ga2O3 in high-power or high-frequency applications is limited by the insufficient electron transport rate, the low thermal conductivity, and the serious self-heating effect caused by the low thermal conductivity. These problems greatly affect the high-voltage performance of beta-Ga2O3 MOSFET devices. Moreover, due to the presence of oxygen vacancies, natural beta-Ga2O3 only exists in n-type, making it difficult to form an enhancement-type device. SUMMARY

[0004] To solve the above problems in the prior art, the application provides a heterojunction trench T-shaped gate power MOSFET device and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical solutions:

[0005] The first aspect of the embodiment of the application provides a heterojunction trench T-shaped gate power MOSFET device, comprising: a substrate, a heteroepitaxial buffer layer, an epitaxial channel layer, a source region heavily doped ohmic contact region, a drain electrode, and a gate electrode.

[0006] The drain electrode, the substrate, and the heteroepitaxial buffer layer are sequentially arranged from bottom to top.

[0007] The material of the heteroepitaxial buffer layer is beta-Ga2O3.

[0008] Source region current blocking layers are respectively arranged in the two side portions of the heteroepitaxial buffer layer.

[0009] The source region current blocking layer is an L-shaped structure extending in the depth direction and the horizontal direction;

[0010] The part of the source region current blocking layer extending in the depth direction is close to the outer edge of the heteroepitaxial buffer layer and the top is flush with the top of the heteroepitaxial buffer layer;

[0011] The heteroepitaxial buffer layer between the two parts of the source region current blocking layer extending in the depth direction is provided with the epitaxial channel layer; the top of the epitaxial channel layer is flush with the top of the source region current blocking layer; and the material of the epitaxial channel layer is doped β-Ga2O3;

[0012] The epitaxial channel layer is provided with a groove;

[0013] The epitaxial channel layer and the inner wall of the groove are provided with a first gate oxide layer;

[0014] The surface of the first gate oxide layer is provided with a second gate oxide layer, and the surface of the second gate oxide layer is provided with a third gate oxide layer;

[0015] The dielectric constant of the first gate oxide layer is less than 10; the dielectric constant of the second gate oxide layer is greater than 15 and less than 25; and the dielectric constant of the third gate oxide layer is greater than 40;

[0016] The heteroepitaxial buffer layer is provided with a passivation layer;

[0017] The gate electrode is a T-shaped structure, is arranged on the surface of the passivation layer and extends to the lateral surface of the third gate oxide layer;

[0018] The source electrode is arranged on the both sides of the gate electrode; and the source electrode extends to the plane where the top of the epitaxial channel layer is located through the passivation layer;

[0019] The lower end of the source electrode is connected with the source region heavily doped ohmic contact region.

[0020] In an embodiment of the present application, the material of the epitaxial channel layer is β-Ga2O3 doped with Si, Sn or Ge.

[0021] In an embodiment of the present application, the material of the first gate oxide layer is Al2O3 or SiO2;

[0022] The material of the second gate oxide layer is HfO2, Hf x Al 1-x O, Hf x Si 1-x O, Hf x Zr 1-xO, La2O3, Ta2O3, or ZrO2;

[0023] The material of the third gate oxide layer is BaTiO3, SrTiO3, LaMnO3, KTaO3, or BiFeO3.

[0024] In an embodiment of the present application, the material of the source region current blocking layer is Mg-doped β-Ga2O3. 2+ In an embodiment of the present application, the material of the source region current blocking layer is β-Ga2O3.

[0025] In an embodiment of the present application, the material of the gate electrode is a multi-layer metal layer structure formed by at least two different metals selected from Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, and Pb.

[0026] In an embodiment of the present application, the source electrode and the drain electrode are a double-layer metal layer structure formed by two different metals, wherein the metals are Au, Al, and Ti.

[0027] In an embodiment of the present application, the doping element of the source region heavily-doped ohmic contact region is Si, Sn, or Ge-doped β-Ga2O3 material.

[0028] A second aspect of the embodiments of the present application provides a preparation method of a heterojunction trench T-gate power MOSFET device, comprising the following steps:

[0029] Step one, treating the surface of a single crystal material to obtain a substrate;

[0030] Step two, growing β-Ga2O3 on the substrate to form a heteroepitaxial buffer layer;

[0031] Step three, using a first photomask to perform ion implantation on the heteroepitaxial buffer layer corresponding to a first preset region on the first photomask, and performing thermal annealing in a nitrogen atmosphere to form a part of the source region current blocking layer extending in a horizontal direction; wherein the first preset region is located at a position corresponding to a side portion of the heteroepitaxial buffer layer.

[0032] Step four, using a second photomask to perform ion implantation on the heteroepitaxial buffer layer from the top of a second preset region on the second photomask to a part of the source region current blocking layer extending in a horizontal direction, and performing annealing in a nitrogen atmosphere to form a part of the source region current blocking layer extending in a depth direction; the part of the source region current blocking layer extending in the horizontal direction and the part of the source region current blocking layer extending in the depth direction constitute the source region current blocking layer.

[0033] wherein the second preset region is located at a position corresponding to a side portion close to an outer edge of the heteroepitaxial buffer layer.

[0034] Step five, using the third photoetching plate to perform ion implantation on the third preset area on the third photoetching plate corresponding to the hetero-epitaxial buffer layer, to form an epitaxial channel layer; the third preset area is located at a position corresponding to the hetero-epitaxial buffer layer between the portions of the two source region current blocking layers extending in the depth direction;

[0035] Step six, using the fourth photoetching plate to perform ion implantation on the fourth preset area on the fourth photoetching plate corresponding to the surface of the product prepared in step five, to form a source region heavily doped ohmic contact region; the fourth preset area is located at positions corresponding to the two sides of the epitaxial channel layer respectively;

[0036] Step seven, using the fifth mask plate to etch a groove on the epitaxial channel layer corresponding to the fifth preset area on the fifth mask plate; the fifth preset area is located on the epitaxial channel layer;

[0037] Step eight, cleaning the product prepared in step seven;

[0038] Step nine, using a plasma enhanced ALD atomic layer deposition process to grow a first gate oxide layer on the epitaxial channel layer and the inner wall of the groove; the dielectric constant of the first gate oxide layer is less than 10;

[0039] Step ten, using a plasma enhanced ALD atomic layer deposition process to grow a second gate oxide layer on the surface of the first gate oxide layer; the dielectric constant of the second gate oxide layer is greater than 15 and less than 25;

[0040] Step eleven, using a radio frequency magnetron process to sputter and grow a third gate oxide layer on the surface of the second gate oxide layer; the dielectric constant of the third gate oxide layer is greater than 40;

[0041] Step twelve, using the sixth photoetching plate to etch the first gate oxide layer, the second gate oxide layer and the third gate oxide layer corresponding to the sixth preset area on the sixth photoetching plate; the sixth preset area is located at a position corresponding to the edge of the product prepared in step eleven extending from the surface of the source region heavily doped ohmic contact region;

[0042] Step thirteen, using the seventh photoetching plate to grow a source electrode by growing a source metal on the seventh preset area on the seventh photoetching plate; the seventh preset area is located at a position corresponding to the surface of the source region heavily doped ohmic contact region;

[0043] Step fourteen, using the eighth photoetching plate to grow a vertical segment of a T-shaped gate electrode on the eighth preset area on the eighth photoetching plate; the eighth preset area is located at a position corresponding to between the lateral surfaces of the third gate oxide layer;

[0044] Step fifteen, using the ninth photoetching plate to grow a passivation layer on a ninth preset area on the ninth photoetching plate; the ninth preset area is located at a corresponding position outside the source electrode and the gate electrode;

[0045] Step sixteen, using the tenth photoetching plate to grow a horizontal segment of the T-shaped gate electrode on a tenth preset area on the tenth photoetching plate; the tenth preset area is located at a corresponding position between the source electrodes;

[0046] Step seventeen, growing a drain metal on the back of the substrate to form a drain electrode, thereby obtaining the device provided in the first aspect of the embodiment of the present application.

[0047] The present application has the following advantages:

[0048] The device of the present application can improve the breakdown voltage of the β-Ga2O3 MOSFET, reduce the gate-drain current, improve the high-temperature reliability of the device, and realize the enhancement-mode MOSFET. Specifically:

[0049] 1. The β-Ga2O3 / substrate heterojunction structure is adopted to reduce the self-heating effect of the device and improve the channel mobility and electron transmission rate of the device.

[0050] Although the β-Ga2O3 material has a high band gap and a high breakdown field strength (the theoretical breakdown field strength is 8 MV / cm), its thermal conductivity is low, and the self-heating effect is serious, which will cause the device to break down at a certain temperature. By selecting a heterojunction substrate, the self-heating effect of gallium oxide can be dispersed by other materials with high thermal conductivity, the loss of the device caused by heating is reduced, the electrons in the device are less affected by temperature, and the mobility and transmission rate are increased.

[0051] 2. The three-layer trench gate oxide structure with low k, high k, and ultra-high k can realize high breakdown field strength and enhancement-mode MOSFET.

[0052] According to Gauss theorem ε(Ga2O3) * E(Ga2O3) = ε(Oxide) * E(Oxide), the ε (dielectric constant) value of gallium oxide is as high as 10, that is, when the dielectric constant of the oxide layer is relatively low, for example, the dielectric constant of the traditional silicon dioxide (SiO2) is 3.9, the field strength that the gate oxide layer can withstand is about 2.6 times that of gallium oxide, and the uneven distribution of the electric field of the device will cause serious electron and hole tunneling, which will eventually lead to premature breakdown of the device. Selecting a material with a relatively high dielectric constant can improve the uneven distribution of the electric field, increase the breakdown field strength, and higher k value can increase the equivalent oxide layer thickness of the device under the condition of physical reduction of the gate oxide layer, and reduce the quantum effect caused by the reduction of the device size due to Moore's law.

[0053] And the trench structure can also reduce the on-resistance of the device, and has certain effect on realizing higher breakdown field strength.

[0054] 3. The longitudinal device structure is adopted, the longitudinal structure drain is located at the back of the device, the current flows vertically in the device, the breakdown voltage is more affected by the thickness of the drift layer, the chip area can be fully utilized, the on-resistance of the device per unit area is smaller, higher current driving can be realized, and it is very suitable for power devices.

[0055] 4. The L-shaped SCBL (source current blocking layer) structure can provide electrical isolation between the source electrode and the drain electrode, and the electrons transmitted from the source electrode to the drain electrode can enter the drift region to form current only through the conductive opening controlled by the SCBL.

[0056] The application will be further described in detail below in combination with the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 A structure schematic diagram of a heterojunction trench T-gate power MOSFET device provided for an embodiment of the application is shown in the figure.

[0058] Figures 2a-2j A structure schematic diagram of a photoetching plate and a mask plate provided for an embodiment of the application is shown in the figure.

[0059] Explanation of reference signs:

[0060] 1-substrate; 2-heteroepitaxial buffer layer; 3-epitaxial channel layer; 4-source region current blocking layer; 5-source region heavily doped ohmic contact region; 6-first gate oxide layer; 7-second gate oxide layer; 8-third gate oxide layer; 9-passivation layer; 10-gate electrode; 11-source electrode; 12-drain electrode; 13-first photoetching plate; 14-first preset region; 15-second photoetching plate; 16-second preset region; 17-third photoetching plate; 18-third preset region; 19-fourth photoetching plate; 20-fourth preset region; 21-fifth mask plate; 22-fifth preset region; 23-sixth photoetching plate; 24-sixth preset region; 25-seventh photoetching plate; 26-seventh preset region; 27-eighth photoetching plate; 28-eighth preset region; 29-ninth photoetching plate; 30-ninth preset region; 31-tenth photoetching plate; 32-tenth preset region. DETAILED DESCRIPTION

[0061] The application will be further described in detail below in combination with specific embodiments, but the embodiments of the application are not limited thereto.

[0062] Embodiment one

[0063] Please see Figure 1 The first aspect of the present invention provides a heterojunction trench T-gate power MOSFET device, comprising: a substrate 1, a heteroepitaxial buffer layer 2, an epitaxial channel layer 3, a source region heavily doped ohmic contact region 5, a drain electrode 12, and a gate electrode 10.

[0064] The drain electrode 12, substrate 1, and heteroepitaxial buffer layer 2 are arranged sequentially from bottom to top. The material of heteroepitaxial buffer layer 2 is β-Ga2O3. The material of heteroepitaxial buffer layer 2 is unintentionally doped β-Ga2O3. Source current blocking layers 4 are respectively provided on both sides of the heteroepitaxial buffer layer 2.

[0065] Source region current blocking layer 4 is along the depth direction (e.g.) Figure 1 It is an L-shaped structure extending in both the height and thickness directions and the horizontal direction. The portion of the source current blocking layer 4 extending along the depth direction is close to the outer edge of the heteroepitaxial buffer layer 2 and its top is flush with the top of the heteroepitaxial buffer layer 2. The two source current blocking layers 4 are arranged symmetrically.

[0066] An epitaxial channel layer 3 is provided within the heterogeneous epitaxial buffer layer 2 between the portions of the two source current blocking layers 4 extending along the depth direction. The top of the epitaxial channel layer 3 is flush with the top of the source current blocking layers 4; the material of the epitaxial channel layer 3 is doped β-Ga2O3. Trenches are formed on the epitaxial channel layer 3.

[0067] A first gate oxide layer 6 is provided on the epitaxial channel layer 3 and the inner wall of the trench. A second gate oxide layer 7 is provided on the surface of the first gate oxide layer 6, and a third gate oxide layer 8 is provided on the surface of the second gate oxide layer 7. The first gate oxide layer 6 is made of a low-k material and has a dielectric constant of less than 10; the second gate oxide layer 7 is made of a high-k material and has a dielectric constant of greater than 15 and less than 25; the third gate oxide layer 8 is made of an ultra-high-k material and has a dielectric constant of greater than 40.

[0068] A passivation layer 9 is provided on the heteroepitaxial buffer layer 2. The gate electrode 10 has a T-shaped structure, and is disposed on the surface of the passivation layer 9 and extends to the lateral surface of the third gate oxide layer 8. Source electrodes 11 are respectively provided on both sides of the gate electrode 10; the source electrodes 11 extend through the passivation layer 9 to the plane where the top of the epitaxial channel layer 3 is located. The two source electrodes 11 are located on both sides of the gate electrode 10, and the source electrodes 11 pass through the passivation layer 9, the third gate oxide layer 8, the second gate oxide layer 7, and the first gate oxide layer 6 to connect with the heavily doped ohmic contact region 5 of the source region. Each source electrode 11 is connected to a heavily doped ohmic contact region 5 at its lower end.

[0069] Further, the material of the epitaxial channel layer 3 is doped β-Ga2O3 with Si, Sn or Ge. The substrate 1 can be Si, SiC or diamond. The material of the passivation layer 9 is Al2O3 or SiO2.

[0070] Further, the material of the first gate oxide layer 6 is Al2O3 or SiO2. The material of the second gate oxide layer 7 is one of HfO2, Hf x Al 1-x O (x = 0.2 - 0.3), Hf x Si 1-x O (x = 0.3 - 0.4), Hf x Zr 1-x O (x = 0.5 - 0.7), La2O3, Ta2O3, ZrO2. Of course, the second gate oxide layer 7 can also use other high-k materials. The material of the third gate oxide layer 8 is one of BaTiO3, SrTiO3, LaMnO3, KTaO3, BiFeO3. Of course, the third gate oxide layer 8 can also use other ferroelectric materials with very high dielectric constant.

[0071] Further, the material of the source region current blocking layer 4 is doped β-Ga2O3 with Mg 2+ .

[0072] Further, the material of the gate electrode 10 is a double layer or more than two layers of metal layer structure formed by at least two different metals including Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb. Among them, the lowermost layer mainly uses Ti or Cr or Ni to improve the adhesion of the metal, for example, the upper layer / lower layer is Au / Ti.

[0073] Further, the source electrode 11 and the drain electrode 12 are a double layer metal layer structure formed by two different metals, wherein the metals are Au, Al, Ti. Of course, the source electrode 11 and the drain electrode 12 can also use other metals.

[0074] Further, the doping element of the source region heavily doped ohmic contact region 5 can be β-Ga2O3 material heavily doped with Si, Sn or Ge.

[0075] The thickness of the substrate 1 is 200-600 μm, the thickness from the bottom of the heteroepitaxial buffer layer 2 to the bottom of the source region current blocking layer 4 is 5-7 μm, the thickness of the source region current blocking layer 4 is 8-15 μm, that is, the source region current blocking layer 4 is located inside the heteroepitaxial buffer layer 2, and the thickness of the heteroepitaxial buffer layer 2 is the sum of the thickness of the source region current blocking layer 4 and the thickness of the heteroepitaxial buffer layer 2 below the source region current blocking layer 4, which is 15-20 μm. The partial thickness (height) of the source region current blocking layer 4 in the depth direction is 7-12 μm, the thickness of the part of the source region current blocking layer 4 extending in the horizontal direction is 1-3 μm, the thickness of the epitaxial channel layer 3 is 7-12 μm, the thickness of the source region heavily doped ohmic contact region 5 is 1-2 μm, the depth of the trench is 100-500 nm, the thickness of the first gate oxide layer 6 is 10-20 nm, the thickness of the second gate oxide layer 7 is 20-50 nm, and the thickness of the third gate oxide layer 8 is 60-100 nm. The thickness (height) of the source electrode 11 is 150 nm-350 nm, the vertical segment thickness (height) of the gate electrode 10 is 200-400 nm, the horizontal segment thickness of the gate electrode 10 is 200-300 nm, the thickness of the passivation layer 9 is 100-300 nm, and the thickness of the drain electrode 12 is 100-200 nm.

[0076] Embodiment two

[0077] The second aspect of the embodiment of the present application provides a preparation method of a heterojunction trench T-gate power MOSFET device, which is used for preparing the device of embodiment one, and includes the following steps.

[0078] Step one: treating the surface of a single crystal material to obtain a substrate 1. The substrate 1 can be Si, SiC or diamond.

[0079] Specifically, a SiC substrate 1 with a thickness of 200 μm-600 μm is prepared, and the surface of the prepared SiC single crystal material is treated by using an ICP etching method or an RIE etching method or a CMP polishing method or a wet etching method to control the thickness of the substrate 1 to be preferably about 500 nm. Common etching gases include Cl2, BCl3, Ar, Cl2 / BCl3, Cl2 / Ar / BCl3 and other different mixed gas atmospheres, and etching solutions include 10%-50% HF, 40-70% HNO3, 80-85% H3PO4 and KOH, etc. The etching time is selected according to the etching speed of different gases and solutions, and the thickness of the substrate 1 can be tested by an optical ellipsometry method. At the same time, the back surface is also polished to remove the damaged part of the surface due to wafer slicing, so as to form a good ohmic contact in the subsequent process.

[0080] Preferably, the substrate 1 is selected from SiC. Since SiC is a newly emerging wide-bandgap semiconductor material, it has a high bandgap of 3.3 eV, a high thermal conductivity of 490 W / m·K and a high electron mobility of 1000 cm2 The SiC can improve the low thermal conductivity and low electron mobility of the gallium oxide power MOSFET. The substrate 1 can also be replaced by a material with high thermal conductivity, such as diamond, aluminum oxide, or gallium nitride.

[0081] Then, the substrate 1 is pretreated and cleaned. Organic cleaning: ultrasonic cleaning with acetone, ethanol, and deionized water respectively for 8 minutes, and the ultrasonic power should be low to avoid too high to cause the substrate 1 to break along the crystal direction. After the organic cleaning, acid cleaning is performed, using 1:20 hydrofluoric acid solution for cleaning for 5 minutes to remove the natural oxide film, and then using H2SO4:H2O2=3:1 solution for immersion for 1 minute to oxidize the possible metal contamination on the surface and dissolve in the cleaning solution, and can oxidize the organic matter to generate CO2 and H2O, and finally using deionized water for immersion and heating to 90°C for cleaning for 5 minutes, and then cooling to room temperature.

[0082] Step two, growing β-Ga2O3 on the substrate 1 to form a heteroepitaxial buffer layer 2. Specifically:

[0083] A non-intentionally doped UID β-Ga2O3 with a thickness of about 10-15 μm is grown on the substrate 1 by using PLD, PECVD or O plasma assisted MBE process to form a heterojunction structure. The process uses O2 and Ar mixed gas atmosphere, the MBE process can select a growth temperature of 650-800 degrees Celsius, the PECVD process can select a growth temperature of 700-800 degrees Celsius and use metal gallium as gallium source, the PLD process can select a temperature of 500-800 degrees Celsius, and the MBE process growth rate is controlled at 0.1-0.6 μm / h, and the PECVD process growth rate is controlled at 2 μm / h.

[0084] Step three, as shown in Figure 2a , using the first photoetching plate 13 to perform ion implantation in the heteroepitaxial buffer layer 2 corresponding to the first preset area 14 on the first photoetching plate 13, and performing thermal annealing in a nitrogen atmosphere to form a part of the source region current blocking layer 4 extending in the horizontal direction. The first preset area 14 is located at a position corresponding to the two side portions of the heteroepitaxial buffer layer 2. Specifically:

[0085] Using the first photoetching plate 13 to perform high-energy ion implantation in the two side portions of the heteroepitaxial buffer layer 2, the implantation ions are Mg 2+ , the implantation energy is 560 kev, and the implantation dose is 8×10 12 cm -2 , the implantation depth (thickness) is 1-3 μm at a position with a height of 5-7 μm in the heteroepitaxial buffer layer 2, to form a current blocking layer with a concentration of 2×10 17 cm -3 , and at the same time, the Mg 2+The Ga2O3 region implanted is subjected to thermal annealing to compensate for implantation damage, so that the region forms the part of the source region current blocking layer 4 extending in the horizontal direction.

[0086] Step four, as shown in Figure 2b , using the second photoetching plate 15, the top of the second preset region 16 on the second photoetching plate 15 to the part of the source region current blocking layer 4 extending in the horizontal direction is subjected to ion implantation, and annealing is performed in a nitrogen atmosphere to form the part of the source region current blocking layer 4 extending in the depth direction; the part of the source region current blocking layer 4 extending in the horizontal direction and the part of the source region current blocking layer 4 extending in the depth direction constitute the source region current blocking layer 4.

[0087] The second preset region 16 is located at a position corresponding to the two sides of the heteroepitaxial buffer layer 2 close to the outer edge.

[0088] The top of the heteroepitaxial buffer layer 2 on the two sides of the heteroepitaxial buffer layer 2 close to the outer edge is subjected to high-energy ion implantation using the second photoetching plate 15, and the implantation ion is Mg 2+ , the implantation energy is 560 kev, the implantation dose is 8×10 12 cm -2 , the implantation depth (thickness) is 7-12 μm, and a current blocking layer of 2×10 17 cm -3 is formed, and the Mg 2+ implanted Ga2O3 region is subjected to thermal annealing to compensate for implantation damage, so that the region forms the part of the source region current blocking layer 4 extending in the depth direction.

[0089] Step five, as shown in Figure 2c , using the third photoetching plate 17, the heteroepitaxial buffer layer 2 corresponding to the third preset region 18 on the third photoetching plate 17 is subjected to ion implantation to form the epitaxial channel layer 3; the third preset region 18 is located at a position corresponding to the heteroepitaxial buffer layer 2 between the two parts of the source region current blocking layer 4 extending in the depth direction. Specifically:

[0090] The heteroepitaxial buffer layer 2 between the two parts of the source region current blocking layer 4 extending in the depth direction is subjected to ion implantation using the third photoetching plate 17, and the implantation ion can be Si, Sn or Ge, etc., the implantation angle is 7 degrees, the implantation depth (thickness) is 7-12 μm, and the doping concentration is 10 17 -10 18 cm -3 order of magnitude, and a doped epitaxial channel layer 3 is obtained.

[0091] Step six, as shown in Figure 2dAs shown, ion implantation is performed on the product surface prepared in step five, corresponding to the fourth preset region 20 on the fourth photomask 19, to form a heavily doped ohmic contact region 5 in the source region; the fourth preset region 20 is located at positions corresponding to both sides of the epitaxial channel layer 3. Specifically:

[0092] High-energy ion implantation was performed on both sides of the epitaxial channel layer 3 using the fourth photomask 19. The implantation angle was 0-90 degrees, the implantation depth (thickness) was 1-2 μm, the implantation energy was 20-300 keV, and the implantation dose was 1×10⁻⁶. 14 -1×10 15 cm -3 Then, rapid thermal annealing was performed at 470°C in an N2 atmosphere for 1 minute to achieve a doping concentration greater than 10%. 19 cm -3 The source region is heavily doped with ohmic contact region 5.

[0093] Step 7, as follows Figure 2e As shown, a trench is etched in the epitaxial channel layer 3 corresponding to the fifth preset region 22 on the fifth mask 21; the fifth preset region 22 is located on the epitaxial channel layer 3. Specifically:

[0094] Using the fifth mask 21, trenches with a thickness of 100-500 nm are etched into the epitaxial channel layer 3 by ICP etching or RIE etching. The ICP etching or RIE etching can be performed using a gas atmosphere of Cl2, BCl3, Ar, or a mixture thereof with a mass percentage purity of 99.999%. The ICP power is 300-900 W, the RF power is 20-100 W, and the etching temperature can be 25-80℃. Under these operating conditions, β-Ga2O3 can be etched stably and uniformly.

[0095] Step 8: Clean the product prepared in Step 7. Specifically:

[0096] In step seven, the surface of the product prepared is subjected to plasma ion bombardment for 5-20 minutes under the action of O plasma using a plasma descaling machine to clean surface impurities. The plasma bombardment power range can be 200-400W. Then, organic cleaning is performed: ultrasonic cleaning is performed for 8 minutes each with acetone, ethanol, and deionized water. The ultrasonic power should be low to avoid causing the substrate 1 to crack along the crystal direction due to excessive power. After organic cleaning, acid cleaning is performed: cleaning with a 1:20 hydrofluoric acid solution for 5 minutes to remove the natural oxide film, followed by immersion in a 3:1 H2SO4:H2O2 solution for 1 minute to allow any metal contaminants on the surface to oxidize and dissolve in the cleaning solution, and to oxidize organic matter to generate CO2 and H2O. Finally, immersion in deionized water and cleaning at 90°C for 5 minutes, followed by cooling to room temperature.

[0097] Step nine, a first gate oxide layer 6 is grown on the epitaxial channel layer 3 and the inner wall of the trench by a plasma enhanced ALD atomic layer deposition process; the dielectric constant of the first gate oxide layer 6 is less than 10.

[0098] Specifically,

[0099] A first gate oxide layer 6 with a thickness of 10-20 nm is grown on the epitaxial channel layer 3 and the inner wall of the trench by a plasma enhanced ALD atomic layer deposition process; the material of the first gate oxide layer 6 is SiO2 or Al2O3. Among them, Al2O3 takes trimethylaluminum and O2 as the reaction precursor, N2 or Ar as the inert carrier gas, and the ALD growth temperature is 250-350 degrees Celsius. SiO2 takes tri-dimethylsilane and O3 as the reaction precursor, N2 or Ar as the inert carrier gas, and the ALD growth temperature is 175-250 degrees Celsius.

[0100] Step ten, a second gate oxide layer 7 is grown on the surface of the first gate oxide layer 6 by a plasma enhanced ALD atomic layer deposition process; the dielectric constant of the second gate oxide layer 7 is greater than 15 and less than 25.

[0101] Specifically,

[0102] A second gate oxide layer 7 with a thickness of 20-50 nm is grown on the surface of the first gate oxide layer 6 by a plasma enhanced ALD atomic layer deposition process. The material of the second gate oxide layer 7 is one of HfO2, Hf x Al 1-x O(x=0.2-0.3), Hf x Si 1-x O(x=0.3-0.4), Hf x Zr 1-x O(x=0.5-0.7), La2O3, Ta2O3, ZrO2, of course, the second gate oxide layer 7 can also use other high-k materials. The process growth temperature is 200-250 degrees Celsius, and the selection of high-k materials can improve the gate control ability of the device and reduce the gate leakage current.

[0103] Step eleven, a third gate oxide layer 8 is sputtered and grown on the surface of the second gate oxide layer 7 by a radio frequency magnetron process; the dielectric constant of the third gate oxide layer 8 is greater than 40. Specifically,

[0104] A 60-100 nm thick third gate oxide layer 8 is sputtered onto the surface of the second gate oxide layer 7 using radio frequency magnetron sputtering. The material of the third gate oxide layer 8 is one of BaTiO3, SrTiO3, LaMnO3, KTaO3, or BiFeO3. Alternatively, other ferroelectric materials with very high dielectric constants (dielectric constants much greater than 40) can also be used. The magnetron sputtering growth temperature is 650-750 degrees Celsius, and the radio frequency power is 50-100 W. The sputtering target is BaTiO3 with a mass percentage purity >99.9%, and Ar with a mass percentage purity of 99.999% is used as the sputtering gas introduced into the sputtering cavity. The vacuum level is 1×10⁻⁶. -4 -2×10 -3 Pa, argon flow rate 20-30 cm⁻¹ 3 Fabricated under conditions of 100W / second, target-to-substrate distance of 20cm, and operating RF power of 50W-100W.

[0105] Step 12, as follows Figure 2f As shown, the first gate oxide layer 6, the second gate oxide layer 7, and the third gate oxide layer 8 corresponding to the sixth preset region 24 on the sixth photomask 23 are etched using the sixth photomask 23; the sixth preset region 24 is located at the position corresponding to the edge of the product prepared in step eleven, extending from the surface of the heavily doped ohmic contact region 5 in the source region. Specifically, ICP etching or RIE etching process is used.

[0106] Step Thirteen, as Figure 2g As shown, a source electrode 11 is formed by growing a source metal in a seventh predetermined region 26 on a seventh photomask 25; the seventh predetermined region 26 is located at the position corresponding to the surface of the heavily doped ohmic contact region 5 in the source region. Specifically:

[0107] Using the seventh photolithography plate 25, a source metal with a thickness of 150nm-350nm is grown on the surface of the heavily doped ohmic contact region 5 in the source region by magnetron sputtering. The source electrode 11 is a bilayer metal structure formed by two different metals, wherein the metals are two of Au, Al, and Ti, or a 5-20nm transparent oxide film (TCO), such as ITO, FTO, AZO, etc., can be inserted between the semiconductor layer and the metal layer to reduce contact resistance and increase operating current. The source electrode 11 can be replaced by metals such as Ni, Ag, and Pt. Among them, Au, Ag, and Pt have stable chemical properties; Al, Ti, and Ni are low cost.

[0108] Step Fourteen, as follows Figure 2h As shown, a vertical segment of the T-shaped gate electrode 10 is grown in an eighth predetermined region 28 on the eighth photomask 27; the eighth predetermined region 28 is located at a position corresponding to the lateral surfaces of the third gate oxide layer 8. Specifically:

[0109] The vertical section of the Ti / Au double-layer metal gate electrode 10 is grown between the lateral surfaces of the third gate oxide layer 8 using the eighth photoetching plate 27 by magnetron sputtering, and the electrode thickness is 200-400 nm. The metal of the gate electrode 10 can be selected from Au, Al, Ti, Ni, Pt, Cr and double-layer structures composed of different elements, wherein the first layer is 2-4 nm of Ti or Cr or Ni to improve the metal adhesion, and the second layer is selected from Au, Pt, Ni and other elements with high metal work function to improve the threshold voltage of the device.

[0110] Step fifteen, as shown in the figure, the passivation layer 9 is grown on the ninth preset area 30 on the ninth photoetching plate 29 using the ninth photoetching plate 29; the ninth preset area 30 is located at the corresponding position outside the source electrode 11 and the gate electrode 10. Specifically: Figure 2i The surface Si3N4 or SiO2 passivation layer 9 is grown at the corresponding position outside the source electrode 11 and the gate electrode 10 using the magnetron sputtering process by using the ninth photoetching plate 29, and the electrical isolation is formed below the passivation layer 9 to prevent pollution, and the thickness of the passivation layer 9 is 100-300 nm.

[0111] Step sixteen, as shown in the figure, the horizontal section of the T-shaped gate electrode 10 is grown on the tenth preset area 32 on the tenth photoetching plate 31 using the tenth photoetching plate 31; the tenth preset area 32 is located at the corresponding position between the two source electrodes 11. Specifically:

[0112] Figure 2j The horizontal section of the T-shaped gate electrode 10 with a thickness of 200-300 nm is grown between the two source electrodes 11 using the tenth photoetching plate 31 by magnetron sputtering, and the growth method is the same as that of the vertical section of the Ti / Au double-layer metal gate electrode 10.

[0113] The horizontal section of the T-shaped gate electrode 10 with a thickness of 200-300 nm is grown between the two source electrodes 11 using the tenth photoetching plate 31 by magnetron sputtering, and the growth method is the same as that of the vertical section of the Ti / Au double-layer metal gate electrode 10.

[0114] The vertical section of the Ti / Au double-layer metal gate electrode 10 is grown between the lateral surfaces of the third gate oxide layer 8 using the eighth photoetching plate 27 by magnetron sputtering, and the electrode thickness is 200-400 nm. The metal of the gate electrode 10 can be selected from Au, Al, Ti, Ni, Pt, Cr and double-layer structures composed of different elements, wherein the first layer is 2-4 nm of Ti or Cr or Ni to improve the metal adhesion, and the second layer is selected from Au, Pt, Ni and other elements with high metal work function to improve the threshold voltage of the device.

[0115] Step seventeen, as shown in the figure, the drain metal is grown on the back of the substrate 1 to form the drain electrode 12. The drain metal is grown on the back by magnetron sputtering process, and the electrode thickness is 100-200 nm. The magnetron sputtering process conditions are the same as those of the source electrode 11 growth, and the device of Example 1 is prepared. Figure 1 Wherein, after the use of each photoetching plate and mask plate is completed, the next process is continued.

[0116]

[0117] ​​In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0118] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0119] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0120] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0121] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.

[0122] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A heterojunction trench T-gate power MOSFET device, characterized by, The application relates to a heteroepitaxial field effect transistor, which comprises a substrate (1), a heteroepitaxial buffer layer (2), an epitaxial channel layer (3), a source region heavily doped ohmic contact region (5), a drain electrode (12) and a gate electrode (10). The drain electrode (12), the substrate (1) and the heteroepitaxial buffer layer (2) are sequentially arranged from bottom to top. The material of the heteroepitaxial buffer layer (2) is beta-Ga2O3, and the material of the substrate (1) is Si, SiC or diamond. Source region current blocking layers (4) are arranged in the two side portions of the heteroepitaxial buffer layer (2) respectively. The part of the source region current blocking layer (4) extending in the depth direction is close to the outer edge of the heteroepitaxial buffer layer (2), and the top of the source region current blocking layer (4) is flush with the top of the heteroepitaxial buffer layer (2). The source region current blocking layer (4) is an L-shaped structure extending in the depth direction and the horizontal direction, and the material of the source region current blocking layer (4) is β-Ga2O3 doped with Mg 2+ . The epitaxial channel layer (3) is arranged in the heteroepitaxial buffer layer (2) between the parts of the two source region current blocking layers (4) extending in the depth direction; the top of the epitaxial channel layer (3) is flush with the top of the source region current blocking layer (4); and the material of the epitaxial channel layer (3) is doped beta-Ga2O3. A groove is arranged on the epitaxial channel layer (3). A first gate oxide layer (6) is arranged on the epitaxial channel layer (3) and the inner wall of the groove. A second gate oxide layer (7) is arranged on the surface of the first gate oxide layer (6), and a third gate oxide layer (8) is arranged on the surface of the second gate oxide layer (7). The dielectric constant of the first gate oxide layer (6) is less than 10; the dielectric constant of the second gate oxide layer (7) is greater than 15 and less than 25; and the dielectric constant of the third gate oxide layer (8) is greater than 40. A passivation layer (9) is arranged on the heteroepitaxial buffer layer (2). The gate electrode (10) is in a T-shaped structure, is arranged on the surface of the passivation layer (9) and extends to the lateral surface of the third gate oxide layer (8). Source electrodes (11) are arranged on the two sides of the gate electrode (10) respectively; the source electrodes (11) extend to the plane where the top of the epitaxial channel layer (3) is located through the passivation layer (9). The source region heavily doped ohmic contact region (5) is connected to the lower end of the source electrode (11), and the source region heavily doped ohmic contact region (5) is connected to the source region current blocking layer (4) and the epitaxial channel layer (3) respectively on the two sides. The material of the epitaxial channel layer (3) is doped beta-Ga2O3 with Si, Sn or Ge.

2. The heterojunction trench T-shaped gate power MOSFET device according to claim 1, wherein, The material of the first gate oxide layer (6) is Al2O3 or SiO2.

3. The heterojunction trench T-shaped gate power MOSFET device according to claim 1, wherein, The material of the third gate oxide layer (8) is BaTiO3, SrTiO3, LaMnO3, KTaO3 or BiFeO3. The material of the second gate oxide layer (7) is HfO2, Hf x Al 1-x O, Hf x Si 1-x O, Hf x Zr 1-x O, La2O3, Ta2O3 or ZrO2; The material of the gate electrode (10) is a multilayer metal layer structure formed by at least two different metals selected from Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu and Pb.

4. The heterojunction trench T-shaped gate power MOSFET device according to claim 1, wherein, The source electrode (11) and the drain electrode (12) are a double-layer metal layer structure formed by two different metals, and the metals are Au, Al and Ti.

5. The heterojunction trench T-shaped gate power MOSFET device according to claim 1, wherein, ​ 6. The heterojunction trench T-shaped gate power MOSFET device according to claim 1, wherein, The doping element of the source region heavily doped ohmic contact region (5) can be Si, Sn or Ge heavily doped β-Ga2O3 material.

7. A method for fabricating a heterojunction trench T-gate power MOSFET device, characterized in that, The method comprises the following steps: Step one, treating the surface of a single crystal material to obtain a substrate (1); the material of the substrate (1) is Si, SiC or diamond; Step two, growing β-Ga2O3 on the substrate (1) to form a heteroepitaxial buffer layer (2); Step three, using the first photoetching plate (13) to perform high-energy ion implantation in the heteroepitaxial buffer layer (2) corresponding to the first preset area (14) on the first photoetching plate (13), and the implantation ion is Mg 2+ Meanwhile, heat annealing is performed under a nitrogen atmosphere to form a part of the source region current blocking layer (4) extending in the horizontal direction; wherein the first preset area (14) is located at a position corresponding to the two side portions of the heteroepitaxial buffer layer (2). Step four, using the second photoetching plate (15) to perform high-energy ion implantation on the part of the source region current blocking layer (4) extending along the horizontal direction between the top of the heteroepitaxial buffer layer (2) and the second preset area (16) on the second photoetching plate (15) corresponding to the source region current blocking layer (4), and the implantation ion is Mg 2+ At the same time, annealing is performed under a nitrogen atmosphere to form the part of the source region current blocking layer (4) extending along the depth direction; the part of the source region current blocking layer (4) extending along the horizontal direction and the part of the source region current blocking layer (4) extending along the depth direction constitute the source region current blocking layer (4). The second preset area (16) is located at a position corresponding to the outer edge of the heteroepitaxial buffer layer (2) on both sides; Step five, using a third photoetching plate (17) to perform ion implantation on the heteroepitaxial buffer layer (2) corresponding to the third preset area (18) on the third photoetching plate (17) to form an epitaxial channel layer (3); the third preset area (18) is located at a position corresponding to the heteroepitaxial buffer layer (2) between the two source region current blocking layers (4) extending in the depth direction; Step six, using a fourth photoetching plate (19) to perform ion implantation on the surface of the product prepared in step five corresponding to the fourth preset area (20) on the fourth photoetching plate (19) to form a source region heavily doped ohmic contact region (5); the fourth preset area (20) is located at a position corresponding to the two sides of the epitaxial channel layer (3) respectively; Step seven, using a fifth mask plate (21) to etch a groove on the epitaxial channel layer (3) corresponding to the fifth preset area (22) on the fifth mask plate (21); the fifth preset area (22) is located on the epitaxial channel layer (3); Step eight, cleaning the product prepared in step seven; Step nine, growing a first gate oxide layer (6) on the epitaxial channel layer (3) and the inner wall of the groove by using a plasma enhanced ALD atomic layer deposition process; the dielectric constant of the first gate oxide layer (6) is less than 10; Step ten, growing a second gate oxide layer (7) on the surface of the first gate oxide layer (6) by using a plasma enhanced ALD atomic layer deposition process; the dielectric constant of the second gate oxide layer (7) is greater than 15 and less than 25; Step eleven, sputtering and growing a third gate oxide layer (8) on the surface of the second gate oxide layer (7) by using a radio frequency magnetron process; the dielectric constant of the third gate oxide layer (8) is greater than 40; Step twelve, etching the first gate oxide layer (6), the second gate oxide layer (7) and the third gate oxide layer (8) corresponding to the sixth preset area (24) on the sixth photoetching plate (23) by using the sixth photoetching plate (23); the sixth preset area (24) is located at a position corresponding to the edge of the product prepared in step eleven extending from the surface of the source region heavily doped ohmic contact region (5); Step thirteen, growing a source electrode (11) by using a seventh photoetching plate (25) on the seventh preset area (26) on the seventh photoetching plate (25); the seventh preset area (26) is located at a position corresponding to the surface of the source region heavily doped ohmic contact region (5); Step four, using the fourth photoetching plate (24) to grow the vertical segment of the T-shaped gate electrode (10) on the fourth pre-set area (25) on the fourth photoetching plate (24); the fourth pre-set area (25) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step five, using the fifth photoetching plate (26) to grow the vertical segment of the T-shaped gate electrode (10) on the fifth pre-set area (27) on the fifth photoetching plate (26); the fifth pre-set area (27) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step six, using the sixth photoetching plate (28) to grow the vertical segment of the T-shaped gate electrode (10) on the sixth pre-set area (29) on the sixth photoetching plate (28); the sixth pre-set area (29) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step seven, using the seventh photoetching plate (30) to grow the vertical segment of the T-shaped gate electrode (10) on the seventh pre-set area (31) on the seventh photoetching plate (30); the seventh pre-set area (31) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step eight, using the eighth photoetching plate (32) to grow the vertical segment of the T-shaped gate electrode (10) on the eighth pre-set area (33) on the eighth photoetching plate (32); the eighth pre-set area (33) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step nine, using the ninth photoetching plate (34) to grow the vertical segment of the T-shaped gate electrode (10) on the ninth pre-set area (35) on the ninth photoetching plate (34); the ninth pre-set area (35) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step ten, using the tenth photoetching plate (36) to grow the vertical segment of the T-shaped gate electrode (10) on the tenth pre-set area (37) on the tenth photoetching plate (36); the tenth pre-set area (37) is located at the corresponding position between the lateral surfaces of the third gate oxide layer (8); Step eleven, using the eleventh photoetching plate (38) to grow the vertical segment of the T-shaped gate electrode (10) on the eleventh pre-set area (39) on the eleventh photoetching plate (38); the eleventh pre-set area (39

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