A high-voltage level conversion circuit for battery management

Abstract

This invention discloses a high-voltage level conversion circuit for battery management. The circuit structure is a three-stage operational amplifier circuit. The first N-type MOSFET MN1 and the second N-type MOSFET MN2 are the input pair of the first stage of the operational amplifier. The first P-type MOSFET MP1 and the second P-type MOSFET MP2 are the load transistors of the first stage of the operational amplifier. The third P-type MOSFET MP3, the first P-type LDMOS transistor DP1, the second N-type LDMOS transistor DN2, the third resistor R3, the fourth resistor R4, and the fifth N-type MOSFET MN5 constitute the second stage of the operational amplifier circuit, where the third P-type MOSFET MP3 is the input transistor of the second stage. The sixth N-type MOSFET MN6, the third N-type LDMOS transistor DN3, the eighth resistor R8, and the seventh resistor R7 constitute the third stage of the operational amplifier circuit, where the sixth N-type MOSFET MN6 is the input transistor of the third stage. This circuit enables voltage information acquisition and unidirectional voltage conversion for a single lithium battery.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuits, specifically to a high-voltage level conversion circuit applied to battery management. Background Technology

[0002] Energy conservation and environmental protection have become new goals for the automotive industry. The new generation of electric vehicles, as a new type of transportation with diversified energy configurations, has attracted widespread attention and experienced significant development due to its advantages such as zero emissions and low noise. However, the problems restricting the development of electric vehicles remain the energy storage power battery and application technology. How to extend battery life, improve battery energy efficiency and operational reliability are problems that electric vehicle energy management systems must solve. Battery management chips are an important component of lithium-ion battery management systems. These chips need to collect voltage information from each cell in a series-connected battery string and can be directly used for analog-to-digital conversion. Involving both high-voltage and low-voltage modules is one of the challenges in circuit design. However, existing technologies lack semiconductor integrated circuits that address this aspect, making it difficult to collect battery voltage information. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention provides a high-voltage level conversion circuit for battery management, which realizes voltage information acquisition and unidirectional voltage conversion of a single lithium battery.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A high-voltage level conversion circuit for battery management includes a zero-th resistor R0, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first P-type MOSFET MP1, a second P-type MOSFET MP2, a third P-type MOSFET MP3, a first N-type MOSFET MN1, a second N-type MOSFET MN2, a third P-type MOSFET MP3, a fourth N-type MOSFET MN4, a fifth N-type MOSFET MN5, a sixth N-type MOSFET MN6, a seventh N-type MOSFET MN7, a first N-type LDMOS transistor DN1, a second N-type LDMOS transistor DN2, a third N-type LDMOS transistor DN3, a first P-type LDMOS transistor DP1, and a diode DZ0.

[0006] The voltage V between one end of the zero-resistance R0 and the battery terminal in1 Connection; the other end of the zero-resistance R0 is connected to the gate of the first N-type MOS transistor MN1;

[0007] The voltage V between one end of the first resistor R1, one end of the seventh resistor R7, and the battery terminal in2connect;

[0008] The other end of the first resistor R1, the source of the first P-type MOSFET MP1, the source of the second P-type MOSFET MP2, and the source of the third P-type MOSFET MP3 are connected to the negative terminal of the diode DZ0.

[0009] The gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the first P-type MOS transistor MP1, and one end of the second resistor R2 are connected to the drain of the first N-type MOS transistor MN1.

[0010] The drain of the second P-type MOSFET MP2, the other end of the second resistor R2, the gate of the third P-type MOSFET MP3, and the drain of the third P-type MOSFET MP3 are connected; the gate of the second N-type MOSFET MN2 is connected to one end of the sixth resistor R6; the source of the first N-type MOSFET MN1 and the source of the second N-type MOSFET MN2 are connected to one end of the third resistor R3; the other end of the third resistor R3 and one end of the fourth resistor R4 are connected to the gate of the first P-type LDMOS transistor DP1; the other end of the fourth resistor R4 is connected to the gate of the first N-type LDMOS transistor DP1. The drain of DN1 is connected; the gates of the first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, the third N-type LDMOS transistor DN3, and one end of the ninth resistor R9 are connected to the control signal CTRL; the source of the first N-type LDMOS transistor DN1 is connected to the drain of the fourth N-type MOS transistor MN4; the drain of the third N-type MOS transistor MN3, the gate of the third N-type MOS transistor MN3, the gate of the fourth N-type MOS transistor MN4, and the gate of the fifth N-type MOS transistor MN5 are connected to the bias current I. bias Connections: The source of the third N-type MOSFET MN3, the source of the fourth N-type MOSFET MN4, and the source of the fifth N-type MOSFET MN5 are grounded;

[0011] The drain of the third P-type MOS transistor MP3 and the positive terminal of the diode DZ0 are connected to the source of the first P-type LDMOS transistor DP1; the drain of the first P-type LDMOS transistor DP1 is connected to one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to the drain of the second N-type LDMOS transistor DN2; the source of the second N-type LDMOS transistor DN2 and the gate of the sixth N-type MOS transistor MN6 are connected to the source of the fifth N-type MOS transistor MN5.

[0012] The other end of the seventh resistor R7 and the other end of the sixth resistor R6 are connected to the drain of the third N-type LDMOS transistor DN3; the source of the third N-type LDMOS transistor DN3 is connected to the drain of the sixth N-type MOS transistor MN6; the source of the sixth N-type MOS transistor MN6 and the source of the seventh N-type MOS transistor MN7 are connected to one end of the eighth resistor R8; the other end of the eighth resistor R8 is grounded; the other end of the ninth resistor R9 is connected to the gate of the seventh N-type MOS transistor MN7; the drain of the seventh N-type MOS transistor MN7 is connected to the output voltage V. out connect.

[0013] Preferably, the first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, and the third N-type LDMOS transistor DN3 are all switching transistors.

[0014] Furthermore, when the control signal CTRL is high, the high-voltage level conversion circuit operates.

[0015] Preferably, the diode DZ0 is a Zener diode, which clamps the drain and source potentials of the third P-type MOSFET MP3.

[0016] Preferably, the third N-type MOS transistor MN3, the fourth N-type MOS transistor MN4, and the fifth N-type MOS transistor MN5 constitute a current mirror circuit.

[0017] Preferably, the voltage V at the battery terminal in1 The signal is the positive input terminal of the op-amp, node A is the feedback node of the op-amp, and the voltage V at node A is... A Equal to the voltage V at the battery terminals in1 .

[0018] Preferably, the voltage V of node B B =(V in2 -V in1 )*R8 / R7,

[0019] In the formula: V in2 and V in1 This refers to the voltage at the terminals of the two adjacent battery cells connected to the circuit.

[0020] Preferably, the output voltage V of the high-voltage level conversion circuit out With the voltage V at node B B equal.

[0021] Preferably, the current in the ninth resistor R9 is (V in2 -V in1 ) / R9;

[0022] In the formula: V in2 and V in1 This refers to the voltage at the terminals of the two adjacent battery cells connected to the circuit.

[0023] Compared with the prior art, the present invention has the following beneficial technical effects:

[0024] This invention provides a high-voltage level conversion circuit for battery management. The circuit structure is a three-stage operational amplifier (op-amp) circuit. The first N-type MOSFET MN1 and the second N-type MOSFET MN2 are the input pair of the first stage of the op-amp. The first P-type MOSFET MP1 and the second P-type MOSFET MP2 are the load transistors of the first stage of the op-amp. The third P-type MOSFET MP3, the first P-type LDMOS transistor DP1, the second N-type LDMOS transistor DN2, the third resistor R3, the fourth resistor R4, and the fifth N-type MOSFET MN5 constitute the second stage of the op-amp circuit, where the third P-type MOSFET MP3 is the input transistor of the second stage. The sixth N-type MOSFET MN6, the third N-type LDMOS transistor DN3, the eighth resistor R8, and the seventh resistor R7 constitute the third stage of the op-amp circuit, where the sixth N-type MOSFET MN6 is the input transistor of the third stage. This invention has a simple and effective circuit structure, simultaneously achieving battery information acquisition and level conversion, directly applicable to analog-to-digital conversion, facilitating the acquisition of voltage information for each battery cell. Here, the high level is converted to any low level voltage suitable for the ADC input range.

[0025] Furthermore, diode DZ0 is a Zener diode, which clamps the drain and source potentials of the third P-type MOSFET MP3 to prevent it from being damaged by high voltage.

[0026] Furthermore, the third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5 constitute a current mirror circuit, with the third N-type MOSFET MN3 connected to the bias current I. bias They provide bias current to the branches containing the fourth N-type MOSFET MN4 and the fifth N-type MOSFET MN5, respectively. Attached Figure Description

[0027] Figure 1 This is a high-voltage level conversion circuit diagram for battery management according to the present invention. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0029] Example

[0030] like Figure 1 As shown, a high-voltage level conversion circuit for battery management is used to acquire voltage information of a single lithium battery and perform unidirectional voltage conversion.

[0031] The level conversion circuit includes one P-type LDMOS transistor, three N-type LDMOS transistors, three P-type MOS transistors, seven N-type LDMOS transistors, ten resistors, and one Zener diode. Their connections are as follows: one end of the zero-th resistor R0 is connected to the battery terminal voltage V. in1 Connections; the other end of the zero-th resistor R0 is connected to the gate of the first N-type MOSFET MN1; one end of the first resistor R1 and one end of the seventh resistor R7 are connected to the voltage V at the battery terminal. in2 Connections are made as follows: the other end of the first resistor R1, the source of the first P-type MOSFET MP1, the source of the second P-type MOSFET MP2, the source of the third P-type MOSFET MP3, and the negative terminal of the zero Zener diode DZ0 are connected; the gate of the first P-type MOSFET MP1, the gate of the second P-type MOSFET MP2, the drain of the first P-type MOSFET MP1, and one end of the second resistor R2 are connected to the drain of the first N-type MOSFET MN1.

[0032] The drain of the second P-type MOSFET MP2, the other end of the second resistor R2, and the gate of the third P-type MOSFET MP3 are connected to the drain of the second N-type MOSFET MN2; the gate of the second N-type MOSFET MN2 is connected to one end of the sixth resistor R6; the source of the first N-type MOSFET MN1 and the source of the second N-type MOSFET MN2 are connected to one end of the third resistor R3; the other end of the third resistor R3 and one end of the fourth resistor R4 are connected to the gate of the first P-type LDMOS transistor DP1; the other end of the fourth resistor R4 is connected to the drain of the first N-type LDMOS transistor DN1.

[0033] The gates of the first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, the third N-type LDMOS transistor DN3, and one end of the ninth resistor R9 are connected to the control signal CTRL; the source of the first N-type LDMOS transistor DN1 is connected to the drain of the fourth N-type MOS transistor MN4; the drain of the third N-type MOS transistor MN3, the gate of the third N-type MOS transistor MN3, the gate of the fourth N-type MOS transistor MN4, and the gate of the fifth N-type MOS transistor MN5 are connected to the bias current I. bias Connections: The source of the third N-type MOSFET MN3, the source of the fourth N-type MOSFET MN4, and the source of the fifth N-type MOSFET MN5 are grounded.

[0034] The drain of the third P-type MOSFET MP3 and the positive terminal of the zeroth Zener diode DZ0 are connected to the source of the first P-type LDMOS transistor DP1; the drain of the first P-type LDMOS transistor DP1 is connected to one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to the drain of the second N-type LDMOS transistor DN2; the source of the second N-type LDMOS transistor DN2 and the gate of the sixth N-type MOSFET MN6 are connected to the source of the fifth N-type MOSFET MN5.

[0035] The other end of the seventh resistor R7 and the other end of the sixth resistor R6 are connected to the drain of the third N-type LDMOS transistor DN3; the source of the third N-type LDMOS transistor DN3 is connected to the drain of the sixth N-type MOS transistor MN6; the source of the sixth N-type MOS transistor MN6 and the source of the seventh N-type MOS transistor MN7 are connected to one end of the eighth resistor R8; the other end of the eighth resistor R8 is grounded; the other end of the ninth resistor R9 is connected to the gate of the seventh N-type MOS transistor MN7; the drain of the seventh N-type MOS transistor MN7 is connected to the output voltage V. out connect.

[0036] This embodiment presents a high-voltage level conversion circuit for battery management. The main circuit structure is a three-stage operational amplifier circuit, with the third N-type MOSFET MN3 connected to a bias current I. bias The third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5 form a current mirror circuit, which provides bias current to the branches where the fourth N-type MOSFET MN4 and the fifth N-type MOSFET MN5 are located, respectively.

[0037] The first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, and the third N-type LDMOS transistor DN3 are switching transistors. Their gates are connected to the control signal CTRL. The transistors are turned on and the circuit can work normally only when CTRL is high. Diode DZ0 is a Zener diode that clamps the drain and source potentials of the third P-type MOS transistor MP3 to prevent it from being damaged by high voltage.

[0038] The first N-type MOSFET MN1 and the second N-type MOSFET MN2 are the input pair of the first stage of the operational amplifier. The first P-type MOSFET MP1 and the second P-type MOSFET MP2 are the load transistors of the first stage of the operational amplifier. The third P-type MOSFET MP3, the first P-type LDMOS transistor DP1, the second N-type LDMOS transistor DN2, the third resistor R3, the fourth resistor R4, and the fifth N-type MOSFET MN5 constitute the second stage circuit of the operational amplifier, where the third P-type MOSFET MP3 is the input transistor of the second stage of the operational amplifier. The sixth N-type MOSFET MN6, the third N-type LDMOS transistor DN3, the eighth resistor R8, and the seventh resistor R7 constitute the third stage circuit of the operational amplifier, where the sixth N-type MOSFET MN6 is the input transistor of the third stage of the operational amplifier.

[0039] like Figure 1 As shown, the positive input terminal of the op-amp is connected to signals V. in1 If node A is the feedback node of the operational amplifier, then the voltage V at point A is... A =V in1 The current flowing through the ninth resistor R9 is (V) in2 -V in1 ) / R9, the voltage V at node B B =(Vin2 -V in1 R8 / R7, final output voltage V out =V B＝ (V in2 -V in1 )*R8 / R7. Corresponding to the series-connected battery string, V in2 and V in1 V represents the voltage at the terminals of two adjacent battery cells connected in series in a multi-cell series system. in2 and V in1 It is a high level. To facilitate the acquisition of voltage information for each battery cell, the high level is converted to an arbitrary low level voltage suitable for the ADC input range.

Claims

1. A high-voltage level conversion circuit for battery management, characterized in that, This includes the zero-th resistor R0, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the first P-type MOSFET MP1, the second P-type MOSFET MP2, the third P-type MOSFET MP3, the first N-type MOSFET MN1, the second N-type MOSFET MN2, the third P-type MOSFET MP3, the fourth N-type MOSFET MN4, the fifth N-type MOSFET MN5, the sixth N-type MOSFET MN6, the seventh N-type MOSFET MN7, the first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, the third N-type LDMOS transistor DN3, the first P-type LDMOS transistor DP1, and the diode DZ0; The voltage between one end of the zero-resistance R0 and the battery terminal V in1 Connection; the other end of the zero-resistance R0 is connected to the gate of the first N-type MOS transistor MN1; The voltage between one end of the first resistor R1, one end of the seventh resistor R7, and the battery terminal V in2 connect; The other end of the first resistor R1, the source of the first P-type MOSFET MP1, the source of the second P-type MOSFET MP2, and the source of the third P-type MOSFET MP3 are connected to the negative terminal of the diode DZ0. The gate of the first P-type MOS transistor MP1, the gate of the second P-type MOS transistor MP2, the drain of the first P-type MOS transistor MP1, and one end of the second resistor R2 are connected to the drain of the first N-type MOS transistor MN1. The drain of the second P-type MOSFET MP2, the other end of the second resistor R2, and the gate of the third P-type MOSFET MP3 are connected to the drain of the third P-type MOSFET MP3; the gate of the second N-type MOSFET MN2 is connected to one end of the sixth resistor R6; the source of the first N-type MOSFET MN1 and the source of the second N-type MOSFET MN2 are connected to one end of the third resistor R3; the other end of the third resistor R3 and one end of the fourth resistor R4 are connected to the gate of the first P-type LDMOS transistor DP1; the other end of the fourth resistor R4 is connected to the gate of the first N-type LDMOS transistor DP1. The drain of LDMOS transistor DN1 is connected; the gates of the first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, the third N-type LDMOS transistor DN3, and one end of the ninth resistor R9 are connected to the control signal CTRL; the source of the first N-type LDMOS transistor DN1 is connected to the drain of the fourth N-type MOS transistor MN4; the drain of the third N-type MOS transistor MN3, the gate of the third N-type MOS transistor MN3, the gate of the fourth N-type MOS transistor MN4, and the gate of the fifth N-type MOS transistor MN5 are connected to the bias current. I bias Connections: The source of the third N-type MOSFET MN3, the source of the fourth N-type MOSFET MN4, and the source of the fifth N-type MOSFET MN5 are grounded; The drain of the third P-type MOS transistor MP3 and the positive terminal of the diode DZ0 are connected to the source of the first P-type LDMOS transistor DP1; the drain of the first P-type LDMOS transistor DP1 is connected to one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to the drain of the second N-type LDMOS transistor DN2; the source of the second N-type LDMOS transistor DN2 and the gate of the sixth N-type MOS transistor MN6 are connected to the source of the fifth N-type MOS transistor MN5. The other end of the seventh resistor R7 and the other end of the sixth resistor R6 are connected to the drain of the third N-type LDMOS transistor DN3; the source of the third N-type LDMOS transistor DN3 is connected to the drain of the sixth N-type MOS transistor MN6; the source of the sixth N-type MOS transistor MN6 and the source of the seventh N-type MOS transistor MN7 are connected to one end of the eighth resistor R8; the other end of the eighth resistor R8 is grounded; the other end of the ninth resistor R9 is connected to the gate of the seventh N-type MOS transistor MN7; the drain of the seventh N-type MOS transistor MN7 is connected to the output voltage. V out connect.

2. The high-voltage level conversion circuit for battery management according to claim 1, characterized in that, The first N-type LDMOS transistor DN1, the second N-type LDMOS transistor DN2, and the third N-type LDMOS transistor DN3 are all switching transistors.

3. The high-voltage level conversion circuit for battery management according to claim 2, characterized in that, When the control signal CTRL is high, the high voltage level conversion circuit operates.

4. The high-voltage level conversion circuit for battery management according to claim 1, characterized in that, The diode DZ0 is a Zener diode, which clamps the drain and source potentials of the third P-type MOSFET MP3.

5. A high-voltage level conversion circuit for battery management according to claim 1, characterized in that, The third N-type MOSFET MN3, the fourth N-type MOSFET MN4, and the fifth N-type MOSFET MN5 constitute a current mirror circuit.

6. A high-voltage level conversion circuit for battery management according to claim 1, characterized in that, The voltage at the battery terminal V in1 The signal is the positive input terminal of the op-amp, node A is the feedback node of the op-amp, and the voltage at node A is... V A equal to the voltage at the battery terminals V in1 Node A is the connection point between the other end of the seventh resistor R7, the other end of the sixth resistor R6, and the drain of the third N-type LDMOS transistor DN3.

7. A high-voltage level conversion circuit for battery management according to claim 1, characterized in that, Voltage at node B V B =( V in2 - V in1 )*R8 / R7, In the formula: V in2 and V in1 The voltage at the terminals of the two adjacent battery cells is given. Node B is the connection point between the source of the sixth N-type MOSFET MN6, the source of the seventh N-type MOSFET MN7, and the eighth resistor R8.

8. A high-voltage level conversion circuit for battery management according to claim 1, characterized in that, Output voltage of high voltage level conversion circuit V out Voltage at node B V B Equal, where node B is the connection point between the source of the sixth N-type MOS transistor MN6, the source of the seventh N-type MOS transistor MN7, and the eighth resistor R8.

9. A high-voltage level conversion circuit for battery management according to claim 1, characterized in that, The current in the ninth resistor R9 is ( V in2 - V in1 ) / R9; In the formula: V in2 and V in1 This refers to the voltage at the terminals of the two adjacent battery cells connected to the circuit.

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