Pattern-based cache block compression

Abstract

Systems, methods, and apparatuses for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to a compressor. A byte value is identified in the uncompressed cache block. A cache block pattern is searched in a cache block pattern set based on the byte value. A compressed cache block is output based on the byte value and the cache block pattern. The compressed cache block is input to a decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary. A cache block pattern subset is determined from a training cache block trace based on a compression size set and a target number of patterns per size.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 939,990, filed November 25, 2019, entitled “Pattern-Based Cached Block Compression,” and U.S. Non-Provisional Application No. 17 / 029,158, filed September 23, 2020, entitled “Pattern-Based Cached Block Compression,” the contents of which are incorporated herein by reference.

[0003] Government licensing rights

[0004] This invention was carried out with government support under the PathForward project (Master Contract No. DE-AC52-07NA27344, Subcontract No. B620717) awarded by the U.S. Department of Energy (DOE) to the Lawrence Livermore National Security Agency. The government enjoys certain rights in this invention. Background Technology

[0005] A cache memory, or cache, is a hardware memory that is typically implemented on the same die as the processor that accesses the cache and is configured to reduce the time and / or energy required to access information that the processor frequently uses, compared to retrieving information from slower and / or more distant storage locations (such as main memory, backup storage, lower-level cache memories, etc.).

[0006] Information is typically stored in caches in fixed-size units, often referred to as cache blocks or cache lines. By compressing information within fixed-size cache blocks into smaller representations (e.g., compressing a 64-byte block into 32 bytes), cache capacity, link bandwidth, and / or memory can be increased. Compressing cache blocks in this way is commonly referred to as cache block compression.

[0007] The techniques used to compress cache blocks are also generally applicable to other types of data and / or storage devices. In this context, such techniques are often referred to as block compression. Attached Figure Description

[0008] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0009] Figure 1This is a block diagram of an exemplary apparatus in which one or more features of this disclosure may be implemented;

[0010] Figure 2 yes Figure 1 A block diagram of the device, showing further details;

[0011] Figure 3 This is a flowchart illustrating an exemplary process for compressing uncompressed cache blocks;

[0012] Figure 4 This is a schematic diagram illustrating an exemplary compression circuit;

[0013] Figure 5 This is a flowchart illustrating an exemplary process for decompressing compressed cache blocks;

[0014] Figure 6 This is a schematic diagram illustrating an exemplary decompression circuit;

[0015] Figure 7 This is a block diagram illustrating an exemplary set of cache block patterns;

[0016] Figure 8 This is a block diagram illustrating exemplary cache block values ​​represented by a specific cache block pattern;

[0017] Figure 9 This is a flowchart illustrating an exemplary process for generating a compressor and / or decompressor;

[0018] Figure 10 This is a flowchart illustrating an exemplary process for determining a pattern trajectory from a training trajectory;

[0019] Figure 11 It is a dot plot illustrating exemplary relationships between cache block patterns in an exemplary set of cache block patterns;

[0020] Figure 12 This is a flowchart illustrating an exemplary process for reducing the set of cache block patterns; and

[0021] Figure 13 This is a bar chart illustrating exemplary performance of various compression algorithms. Detailed Implementation

[0022] Some implementations provide a compressor and / or a method implemented within the compressor for performing pattern-based cache block compression. An uncompressed cache block is input to the compressor. Byte values ​​are identified within the uncompressed cache block. A cache block pattern is searched within a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values ​​and the cache block pattern.

[0023] In some implementations, byte values ​​are converted to symbols, and uncompressed cache blocks are represented by symbols, each symbol representing a specific cache block. In some implementations, cache block patterns are searched within a set of cache block patterns based on byte values ​​by searching the set of symbols. In some implementations, compressed cache blocks include byte values ​​and an index to the set of cache block patterns. In some implementations, compressed cache blocks include a byte dictionary and metadata. In some implementations, the metadata includes an index to the set of cache block patterns. In some implementations, the byte dictionary includes each of the byte values, and for each byte value, the byte dictionary includes only one copy.

[0024] Some implementations provide a method for performing pattern-based cache block decompression, implemented in a decompressor and / or decompressor. Compressed cache blocks are input to the decompressor. Cache block patterns are identified based on the cache block's metadata. The cache block patterns are applied to the cache block's byte dictionary. Uncompressed cache blocks are output based on the cache block patterns and the byte dictionary.

[0025] In some implementations, a compressed block includes byte values ​​and an index to a set of cache block patterns. In some implementations, a byte dictionary includes byte values ​​of an uncompressed cache block. In some implementations, the byte dictionary includes each of the byte values, and for each byte value, the byte dictionary includes only one copy. In some implementations, metadata includes an index to a set of cache block patterns. In some implementations, identifying cache block patterns based on cache block metadata includes searching for cache block patterns in the set of cache block patterns based on the metadata. In some implementations, a cache block pattern includes at least one symbol corresponding to at least one byte of the byte dictionary. In some implementations, a compressed cache block includes byte values. In some implementations, the byte dictionary of a cache block includes specific byte values ​​of an uncompressed cache block.

[0026] Some implementations provide methods, systems, and apparatus for generating hardware configured for pattern-based cache block compression. A cache trace is input, and a set of cache block patterns is determined based on the cache trace. A subset of cache block patterns is determined from the set of cache block patterns based on a set of compression sizes and a target number pattern for each size. A hardware description is output based on the determined subset of cache block patterns.

[0027] In some implementations, the cache block pattern set is sorted based on the frequency of occurrence in the cache trace to generate a sorted cache block pattern set. In some implementations, the sorted cache block patterns are reduced by removing patterns from the cache trace that occur at frequencies below a threshold frequency to generate a threshold cache block pattern set. In some implementations, cache block patterns that do not have maximum inclusion are removed from the threshold cache block patterns to generate a locally maximum cache block pattern set. In some implementations, the relatively maximum patterns in the locally maximum cache block pattern set are combined to generate an absolutely maximum cache block pattern set. In some implementations, a subset of the absolutely maximum cache block pattern set is iteratively sorted based on which pattern in the absolutely maximum cache block pattern set describes more cache blocks to determine the subset of cache block patterns.

[0028] Figure 1 This is a block diagram of an exemplary device 100 in which one or more features of this disclosure may be implemented. Device 100 may include, for example, a computer, gaming device, handheld device, set-top box, television, mobile phone, or tablet computer. Device 100 includes a processor 102, memory 104, storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include... Figure 1 Additional components not shown.

[0029] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache. In some embodiments, processor 102 includes a GPU implemented as an accelerator and a CPU configured to manage the GPU's input / output tasks.

[0030] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid-state drives, optical disks, or flash drives. Input device 108 includes, but is not limited to, keyboards, keypads, touchscreens, touchpads, detectors, microphones, accelerometers, gyroscopes, biometric scanners, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes, but is not limited to, displays, speakers, printers, haptic feedback devices, one or more lights, antennas, or network connections (e.g., wireless LAN cards for transmitting and / or receiving wireless IEEE 802 signals).

[0031] Input driver 112 communicates with processor 102 and input device 108, and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, and allows processor 102 to send output to output device 110. Note that input driver 112 and output driver 114 are optional components, and device 100 will operate in the same manner in the absence of input driver 112 and output driver 114. Output driver 116 includes an accelerated processing unit (“APD”) 116 coupled to display device 118. APD receives computation commands and graphics rendering commands from processor 102, processes those commands, and provides pixel output to display device 118 for display. As described in further detail below, APD 116 includes one or more parallel processing units that perform computations according to the Single Instruction Multiple Data (“SIMD”) paradigm. Therefore, although various functions are described herein as being performed by or in conjunction with the APD 116, in various alternatives, the functions described as being performed by the APD 116 may also be performed by other computing devices with similar capabilities, which are not driven by a host processor (e.g., processor 102) and provide graphics output to the display device 118. For example, it is conceivable that any processing system performing processing tasks according to the SIMD paradigm can perform the functions described herein. Alternatively, it is conceivable that a computing system not performing processing tasks according to the SIMD paradigm can perform the functions described herein.

[0032] Figure 2This is a block diagram of device 100, illustrating additional details related to the execution of processing tasks on APD 116. Processor 102 maintains one or more control logic modules in system memory 104 for execution by processor 102. The control logic modules include operating system 120, kernel-mode driver 122, and application program 126. These control logic modules control various features of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with the hardware and provides an interface to the hardware for other software executing on processor 102. Kernel-mode driver 122 controls the operation of APD 116 by providing, for example, an application programming interface (“API”) to software executing on processor 102 to access various functions of APD 116 (e.g., application program 126). Kernel-mode driver 122 also includes a just-in-time (JIT) compiler that compiles programs for execution by processing units of APD 116, such as SIMD unit 138, which is discussed in further detail below.

[0033] APD 116 executes commands and procedures related to selected functions, such as graphics and non-graphics operations suitable for parallel processing. APD 116 can be used to perform graphics pipeline operations based on commands received from processor 102, such as pixel manipulation, geometric calculations, and rendering images to display device 118. APD 116 can also perform computational processing operations not directly related to graphics operations based on commands received from processor 102, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks.

[0034] APD 116 includes a computation unit 132 comprising one or more SIMD units 138 that perform operations in parallel as requested by processor 102 according to a SIMD paradigm. A SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter, and thus execute the same program, but can execute that program with different data. In one example, each SIMD unit 138 includes sixteen channels, where each channel executes the same instruction simultaneously with other channels in the SIMD unit 138, but can execute that instruction with different data. If not all channels need to execute a given instruction, prediction can be used to close channels. Prediction can also be used to execute programs with divergent control flow. More specifically, for programs with conditional branches or other instructions, where control flow is based on computation performed by a single channel, prediction of channels corresponding to currently unexecuted control flow paths and serial execution of different control flow paths allow for arbitrary control flow.

[0035] The basic unit of execution in computing unit 132 is a work item. Each work item represents a single instance of a program that will be executed in parallel on a specific channel. Work items can be executed simultaneously as “wavefronts” on a single SIMD processing unit 138. One or more wavefronts are included in a “workgroup,” which comprises a set of work items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. Alternatively, wavefronts are executed sequentially on a single SIMD unit 138, or partially or completely in parallel on different SIMD units 138. A wavefront can be considered as the largest set of work items that can be executed simultaneously on a single SIMD unit 138. Therefore, if a command received from processor 102 indicates that a particular program will be parallelized to the extent that the program cannot be executed simultaneously on a single SIMD unit 138, the program is decomposed into wavefronts that are parallelized on two or more SIMD units 138 or serialized on the same SIMD unit 138 (or parallelized and serialized as needed). Scheduler 136 performs various wavefront-related operations on different computing units 132 and SIMD units 138.

[0036] The parallelism provided by computing unit 132 is suitable for graphics-related operations, such as pixel value calculation, vertex transformation, and other graphics operations. Therefore, in some instances, graphics pipeline 134, which receives graphics processing commands from processor 102, provides computational tasks to computing unit 132 for parallel execution.

[0037] The computing unit 132 is also used to perform computational tasks that are unrelated to graphics or not part of the “normal” operation of the graphics pipeline 134 (e.g., performing custom operations to supplement processing performed as part of the operation of the graphics pipeline 134). An application program 126 or other software executing on the processor 102 transfers programs defining such computational tasks to the APD 116 for execution.

[0038] Cache block compression (or more generally, data block compression) is fundamental to cache, memory, and link compression schemes. By compressing information in fixed-size cache blocks into a smaller representation (e.g., compressing a 64-byte block into 32 bytes), cache block compression effectively increases link bandwidth and cache and memory capacity, depending on the implementation. In some implementations, cache block compression can significantly improve system performance and energy efficiency. Cache block compression techniques are often applicable to compressing other non-cacheable data blocks. Therefore, cache block compression applied to non-cacheable use cases is referred to as data block compression. This article discusses techniques and examples related to cache blocks and cache block compression; however, it should be noted that these techniques and examples are generally also applicable to data block compression.

[0039] Cache block compression techniques involving byte selection are referred to herein as "Byte Selected Compression" (BSC). Exemplary BSC techniques are discussed in U.S. Patent Application US2020 / 0133866A1 by Das et al., the contents of which are incorporated herein by reference in their entirety as if fully described herein. During compression, byte selection refers to selecting which bytes to store in a cache block and where to store those selected bytes. In this context, compression can be described as byte deduplication. During decompression, byte selection refers to moving stored bytes from the compressed cache block back to their original order within the uncompressed (i.e., decompressed) cache block.

[0040] The examples in this article illustrate techniques for compressing and decompressing cache blocks based on a set of patterns, as well as techniques for generating such a set of patterns. Hardware for performing compression and decompression according to these techniques can be derived based on the set of patterns.

[0041] While cache block compression algorithms have been proposed, existing designs are typically based on the application of specific selections of common patterns observed by designers in the data. Therefore, some implementations provide a search strategy to identify cache block patterns whose resulting compression algorithms exhibit performance closer to the ideal than current compression algorithms (e.g., performance closer to algorithms that find and compress each pattern that can be described within bounds of the compressed output size), while also incurring lower hardware overhead than current compression methods.

[0042] Mainly about Figure 3 , Figure 4 , Figure 5 and Figure 6 This paper discusses pattern-based techniques for compressing and decompressing cache blocks, primarily focusing on... Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 The discussion covers the techniques used to generate pattern sets and the corresponding hardware used to perform compression and decompression. The relative performance of BSC compression is primarily related to... Figure 13 Let's have a discussion.

[0043] Figure 3 This is a flowchart illustrating an exemplary process 300 for using BSC to compress uncompressed cache blocks based on a pattern.

[0044] In step 310, the uncompressed cache block is fed into the compressor. The compressor is implemented using any suitable compression circuitry and in any suitable manner, such as entirely in hardware or as a combination of hardware and software or firmware. In some implementations, the uncompressed cache block is fed into the compressor's input buffer. An exemplary uncompressed 12-byte cache block comprises 12 bytes of information, represented in hexadecimal format in Table 1.

[0045] Table 1

[0046] FF FF FF 14 FF FF FF 18 FF FF FF 1C

[0047] In step 320, appropriate comparator logic of the compression circuitry is used, for example, to identify a specific byte value within the uncompressed cache block. For instance, in some implementations, the comparator is used to detect duplicate bytes within the uncompressed cache block. Table 2 illustrates exemplary byte values ​​within uncompressed cache blocks from Table 1.

[0048] Table 2

[0049] FF 14 18 1C

[0050] In this context, the term "specific byte value" refers to a byte value that appears at least once in an uncompressed cache block. For example, the specific byte value "FF" appears nine times in the exemplary 12-byte cache block shown in Table 1, while the specific byte value "1C" appears once. The byte value "00" does not appear in the exemplary uncompressed 12-byte cache block shown in Table 1, therefore it is not a specific byte value of the uncompressed cache block and is not included in Table 2. Because the uncompressed cache block of Table 1 can be represented based on the specific byte values ​​of Table 2, these specific byte values ​​are referred to in this context as a "byte dictionary".

[0051] In step 330, a pattern for a specific byte value within an uncompressed cache block is searched in the cache block pattern set. The cache block pattern set can be stored in any suitable manner, such as as a table, matrix, or vector within storage memory (such as a register file). In some implementations, patterns are "searched" or indexed, for example, based on the output of a comparator. For example, to search for a pattern, symbols can be used instead of full bytes to represent and reference a specific byte value. Exemplary symbols for each specific byte value in the byte dictionary are shown in decimal form in Table 3. Because there are four specific byte values ​​in this exemplary byte dictionary, each symbol can be represented using a minimum of two bits. Note that these specific symbols are exemplary, and any suitable symbols are available in other implementations. The process of using symbols to represent specific byte values ​​in the byte dictionary is further discussed herein.

[0052] Table 3

[0053] 0 1 2 3

[0054] Based on the symbols in Table 3, the byte patterns in the exemplary cache blocks shown in Table 1 can be represented as shown in Table 4.

[0055] Table 4

[0056] 0 0 0 1 0 0 0 2 0 0 0 3

[0057] In some implementations, generating cache block patterns based on symbols in this manner is an intermediate step in finding cache block patterns. Note that the patterns for specific byte values ​​present in the exemplary uncompressed cache blocks shown in Table 1 can be represented in other ways. The determination of such pattern representations and the determination of the set of cache block patterns are discussed further herein.

[0058] Under condition 340, where the cache block pattern shown in Table 4 is not found in the cache block pattern set, process 300 ends, and the exemplary uncompressed cache block shown in Table 1 is not compressed, or is compressed using other techniques. Under condition 340, where the pattern shown in Table 4 is found in the cache block pattern set, in step 350, a compressed cache block is output based on the index of the cache block pattern in the cache block pattern set and a byte dictionary. In some implementations, the compressed cache block includes a byte dictionary (e.g., as shown in Table 2) and metadata, the metadata including the index of the cache block pattern in the set. For example, the compressed cache block may be stored in a cache or transmitted over a link. Table 5 illustrates an exemplary compressed cache block.

[0059] Table 5

[0060] Metadata FF 14 18 1C

[0061] In some implementations, the metadata also includes bits indicating whether cache lines are compressed.

[0062] Figure 4 This is a schematic diagram illustrating an exemplary compression circuit 400 for compressing uncompressed cache blocks using BSC-based pattern compression. For example, the exemplary compression circuit 400 can be used to implement... Figure 3 The process shown and described. Note that the exemplary compression circuit 400 is merely illustrative, and any suitable hardware and / or software configuration can be used to generate compressed cache blocks based on the BSC pattern in other implementations.

[0063] Compression circuit 400 includes: logic 450, which includes comparator circuit 410 and stored cache block mode 460; multiplexer circuit 420; memory unit 430, which holds uncompressed cache blocks; and memory unit 440, which stores compressed cache blocks including byte dictionary and metadata.

[0064] During operation, uncompressed cache blocks are stored in memory cells 430 of the compression circuit 400. This corresponds to, as per [reference to...] Figure 3 Step 310 is shown and described. Memory unit 430 includes a cache block storage device within a cache, or any other suitable buffer or other storage circuitry. In this example, the uncompressed cache block corresponds to the exemplary 12-byte cache block shown and described with respect to Table 1.

[0065] Comparator circuit 410 compares bytes of an uncompressed cache block to identify patterns in specific byte values ​​within the cache block. This corresponds to, for example, regarding... Figure 3 Step 320 is shown and described. In some embodiments, comparator circuitry 410 is part of or communicates with logic circuitry 450. In this example, a specific byte value within an exemplary cache block corresponds to an exemplary byte shown and described with respect to Table 2. Patterns are symbolically recognizable, for example, as shown and described with respect to Table 4.

[0066] Search for a pattern of a specific byte value within an uncompressed cache block in the cache block pattern set 460. This corresponds to, for example, regarding... Figure 3 Step 330, as shown and described, involves comparing cache block patterns with cache block pattern set 460 using any suitable logic, such as within logic circuit 450 and / or comparator circuit 410. In some embodiments, cache pattern set 460 is represented by symbols, and converting cache block patterns to symbols is an intermediate step, for example, as per [reference to...]. Figure 3 Regarding the discussion in step 330.

[0067] If the cache block pattern does not match the corresponding pattern in the cache block pattern set 460, the uncompressed cache block is not compressed, or other compression techniques are used. If the cache block pattern matches the corresponding pattern in the cache block pattern set 460, the logic circuit 450 configures the multiplexer circuit 420 (e.g., by setting a select line) to store a specific byte value in memory cell 440 as a byte dictionary of the compressed cache block corresponding to the uncompressed cache block, and encodes and stores the index of the cache block pattern within the cache block pattern set 460 in memory cell 440 as metadata of the compressed cache block. This corresponds to, as per the information regarding... Figure 3Conditions 340 and step 350 are shown and described. In this example, the compressed cache block includes a byte dictionary and metadata, wherein the metadata includes an index to the cache block pattern set 460. In some implementations, the metadata includes other information, as discussed further herein.

[0068] Figure 5 This is a flowchart illustrating an exemplary process 500 for using BSC to decompress compressed cache blocks based on a pattern.

[0069] In step 510, the compressed cache block is fed into a suitable decompressor. Any suitable decompression circuitry is used and the decompressor is implemented in any suitable manner, such as entirely in hardware or as a combination of hardware and software or firmware. In some embodiments, the compressed cache block is fed into a buffer of the decompressor. Table 5 above illustrates exemplary compressed cache blocks. In some embodiments, the compressed cache block is based on, respectively, regarding... Figure 3 and / or Figure 4 The processes and / or circuits shown and described are used to generate this.

[0070] Under condition 520, where the metadata of the compressed cache block does not include an index to the cache block pattern set, the cache block is not decompressed using process 500, and the process ends. If the metadata does include an index to the cache block pattern set, then in step 530, the cache block pattern is looked up in the set based on the index. In this example, the cache block patterns correspond to Table 4. In this example, it is assumed that if an index exists in the metadata, the cache block pattern is included in the cache block pattern set.

[0071] In step 540, the byte dictionary from the compressed block (corresponding to Table 2 in this example) is applied to the cache block pattern (e.g., based on the symbol mapping in Table 3) to generate an uncompressed cache block (shown in Table 1 in this example), and in step 550, the uncompressed cache block is output. The uncompressed cache block can be stored in a CPU register or any other suitable storage location.

[0072] Figure 6 This is a schematic diagram illustrating an exemplary decompression circuit 600 for decompressing compressed cache blocks using BSC-based pattern decompression. For example, the exemplary decompression circuit 600 can be used to implement... Figure 5 The process is shown and described. Note that the exemplary decompression circuit 600 is merely illustrative, and any suitable hardware and / or software configuration can be used to generate decompression cache blocks based on the BSC pattern in other implementations.

[0073] The decompression circuit 600 includes a memory unit 610 configured to input specific byte values ​​from a byte dictionary of a compressed cache block. This corresponds to, as per [reference to...] Figure 5 Step 510 is shown and described. Memory unit 610 includes a cache block storage device within a cache, or any other suitable buffer or other storage circuitry. In this example, the compressed cache block corresponds to the exemplary compressed cache block illustrated in Table 5 above.

[0074] The decompression circuit 600 also includes logic circuitry 620, which is configured to input metadata from compressed cache blocks in memory unit 610 and identify cache block patterns within a stored set of cache block patterns based on indexes included in the metadata. This corresponds to, as per [reference to...] Figure 5 Conditions 520 and steps 530 are shown and described. If the metadata does not include an index to the cache block pattern set, the compressed cache blocks are not decompressed using the decompression circuit 600.

[0075] Otherwise, if the metadata does include an index to a set of cache block patterns, then logic circuit 620 identifies the cache block pattern within that set. Logic circuit 620 sets the select line of multiplexer 630 based on the identified cache block pattern, such that multiplexer 630 maps the byte dictionary of compressed cache blocks to memory cells 640 corresponding to uncompressed cache blocks. This corresponds to... Figure 5 Steps 540 and 550 are shown and described. Uncompressed cache blocks can be stored in CPU registers or any other suitable storage location.

[0076] In some implementations, such as regarding Figure 5 As shown and described, the BSC compressor (including a set of cache block patterns) is implemented using comparators (e.g., for detecting duplicate bytes), multiplexers (e.g., for routing bytes to and from the byte dictionary), and logic (e.g., for encoding and decoding metadata). In some implementations, such as regarding Figure 6 As shown and described, the BSC decompressor (including a set of cache block patterns) is implemented using a multiplexer, wherein a byte dictionary of the compressed cache block is input to the input of the multiplexer, and wherein the multiplexer selector value is derived from the metadata of the compressed cache block. In some implementations, the implementation of the compressor and / or decompressor is primarily limited by the advantages of the comparator and multiplexer in limiting the complexity of the algorithm and limiting the area and / or latency of the corresponding hardware.

[0077] In some implementations, the area complexity of BSC compression and decompression hardware is determined by the number of inputs to the byte multiplexer and the complexity of the logic used to generate and process metadata. In some implementations, latency is determined by the maximum number of inputs to any multiplexer and the depth of the metadata logic. In some implementations, the size and content of the cache block pattern set affect the performance of BSC compression and / or decompression in terms of both speed and die area.

[0078] Therefore, some implementations provide techniques for generating pattern sets and corresponding hardware for performing compression and decompression. (See also: Regarding...) Figure 3 , Figure 4 , Figure 5 and Figure 6 As illustrated by the exemplary processes and circuits described, a cache block pattern can be represented as a string of symbols, one symbol for each byte in the cache block, where each symbol represents a pattern of byte values ​​within the cache block. If bytes with the same value in a cache block are represented by the same symbol in the cache block pattern, then the cache block can be described by a specific cache block pattern. For example, the exemplary cache blocks listed in Table 1 can be described by the cache block patterns listed in Table 4 because each byte with the same value in Table 1 is represented by the same symbol in Table 4.

[0079] A cache block pattern serves as a series of indices for the byte dictionary. If a byte dictionary can be created from uncompressed cache blocks, and the indices of a particular cache block pattern can be used to decompress the byte dictionary into uncompressed cache blocks, then the uncompressed cache blocks can be described by that particular cache block pattern.

[0080] Such as about Figure 3 , Figure 4 , Figure 5 and Figure 6 As described, cache block patterns are used to deduplicat bytes in an uncompressed cache block to produce a compressed cache block that includes a byte dictionary and metadata. The metadata includes an index to a set of cache block patterns from which the uncompressed cache block can be reconstructed.

[0081] Figure 7 This is a block diagram illustrating a set of exemplary cache block patterns for an exemplary 4-byte cache block. For example... Figure 7 As shown, a 4-byte cache block that repeats a specific byte value in each of its four bytes can be represented using a symbol (0 in this exemplary cache block pattern set). Note that the set shown is not exhaustive for such cache blocks. For example, in other examples, any available symbol can be used to represent a specific byte value.

[0082] Similarly, Figure 7 As shown, a 4-byte cache block containing two specific byte values ​​can be represented using two symbols, the order of which depends on their position in the cache block. Figure 7 The document illustrates several cache block patterns that include cache blocks with two specific cache byte values. It should be noted that the set shown is not exhaustive for such cache blocks. A cache block pattern with two symbols can also represent a cache block containing one specific byte value, as shown regarding... Figure 8 Further discussion is needed.

[0083] like Figure 7 As further shown, a 4-byte cache block containing three specific byte values ​​can be represented using three symbols, the order of which depends on their position in the cache block. Figure 7 The document illustrates several cache block patterns that include cache blocks with three specific cache byte values. It should be noted that the set shown is not exhaustive for such cache blocks. A cache block pattern with three symbols can also represent cache blocks containing one or two specific byte values, as shown in the document. Figure 8 Further discussion is needed.

[0084] like Figure 7 As further shown, a 4-byte cache block comprising four specific byte values ​​can be represented using four symbols. Because each byte in the cache block in this example includes a distinct specific byte value, the order of the symbols is irrelevant. Therefore, Figure 7 The example cache block pattern shown is an exemplary cache block pattern comprising four specific cache byte values. It should be noted that the exemplary cache block pattern shown is not exhaustive for such cache blocks. However, other cache block patterns that can be used to represent such cache blocks would be equivalent and therefore redundant. This is for illustrative purposes only. Figure 7 The system provides alternative orderings for representing symbols in a cache block where each byte includes a distinct specific byte value. A cache block pattern with four symbols can also represent cache blocks containing one, two, or three specific byte values, as shown in the example below. Figure 8 Further discussion is needed.

[0085] Figure 7 The exemplary cache block patterns included in the set of exemplary cache block patterns shown are not exhaustive. For example, in the case of a 4-byte cache block comprising four specific byte values, the symbols 0, 1, 2, and 3 can be used to represent bytes in any order, or different symbols can be used. Figure 7 The same applies to the cases of specific byte values ​​one, two, and three as described in the text.

[0086] Figure 8This is a block diagram illustrating an exemplary cache block pattern of an exemplary 4-byte cache block and an exemplary cache block value that can be described using these exemplary cache block patterns. Figure 8 The examples illustrate some patterns that can be used to describe many cache blocks.

[0087] like Figure 8 As shown, if the symbol "0" maps to the value "FF" and the symbol "1" maps to the value "01", then the cache block pattern 0 1 0 1 describes a cache block with the byte value FF 01 FF 01. Similarly, if the symbol "0" maps to the value "00" and the symbol "1" maps to the value "01", then this cache block pattern can also be used to describe a cache block with the byte value 00 01 00 01. If the symbol "0" maps to the value "00" and the symbol "1" also maps to the value "00", then this cache block pattern also describes a cache block with the byte value 00 00 00 00. In each of these cases, the exemplary cache block is described by the cache block pattern 0 1 0 1 because each specific byte value with the same value in the exemplary cache block is represented by the same symbol in the cache block pattern.

[0088] like Figure 8 Similarly, as shown, if the symbol "0" maps to the value "00", the symbol "1" maps to the value "01", and the symbol "2" maps to the value "02", then the cache block pattern 0102 describes a cache block with the byte value 00010002. This example illustrates the cache block pattern 0102 representing a cache block with three specific byte values. Similarly, if the symbol "0" maps to the value "00", the symbol "1" maps to the value "01", and the symbol "2" also maps to the value "01", then the cache block pattern 0102 also describes a cache block with the byte value 00010001. This example illustrates the cache block pattern 0102 representing a cache block with two specific byte values. If the symbol "0" maps to the value "00", the symbol "1" maps to the value "00", and the symbol "2" also maps to the value "02", then the cache block pattern 0 1 0 2 also describes a cache block with the byte value 00 00 00 02. This example illustrates a second example of the cache block pattern 0 1 0 2, which represents a cache block with two specific byte values, where the specific cache blocks are in different arrangements.

[0089] If the symbol "0" maps to the value "00", the symbol "1" also maps to the value "00", and the symbol "2" also maps to the value "00", then the cache block pattern 0102 also describes a cache block with the byte value 00000000. This example illustrates the cache block pattern 0102 representing a cache block with a specific byte value. In each of these cases, the exemplary cache block is described by the cache block pattern 0102 because the symbols in the cache block pattern indicate the specific byte value at each location where they appear, and in some cases, different symbols can be used to represent the same specific byte value.

[0090] like Figure 8 As shown in the examples, some patterns can be used to describe many cache blocks. For example, any cache block with all matching bytes, including "all zero" cache blocks, can be described using any pattern.

[0091] Because each pattern can be used to describe the values ​​of multiple different cache blocks, a subset of all possible patterns can be used to describe all possible cache blocks. If patterns are removed from this subset, the number of cache blocks can be further reduced.

[0092] An ideal BSC compression and / or decompression algorithm would include every possible non-equivalent pattern in the set of cache block patterns (i.e., an exhaustive list of possible symbolic representations of bytes in an uncompressed cache block). However, the metadata used to index the set of cache block patterns that includes every possible pattern can be so large that compressed blocks are smaller than (or sufficiently smaller than) uncompressed cache blocks.

[0093] Therefore, some implementations include methods, apparatus, and systems for selecting a subset of all possible cache block patterns that still produce the desired level of performance (e.g., to limit the metadata and / or hardware complexity required for BSC compression and decompression).

[0094] In some implementations, a subset of all possible cache block patterns is developed such that it best fulfills the selected constraints to compress cache blocks to a desired target size set (i.e., a quantized compression ratio) to reach or fall below a desired threshold cost (e.g., in terms of latency and / or energy consumption).

[0095] It should be noted that the set of all cache block patterns differs from the set of all n-byte strings consisting of numbers from 0 to n-1. This is because many patterns are equivalent in terms of the set of cache blocks they can describe. Any patterns that differ only in the symbol names they use are equivalent.

[0096] For example, consider the following 4-byte patterns: 0101, 1010, and 1313. These patterns (and many others) all describe the same set of cache blocks where the first and third bytes match, and the second and fourth bytes match. Therefore, in some implementations, a subset of all unique sets of describable cache blocks is selected, one pattern per set, rather than a subset of all possible pattern length strings.

[0097] In some implementations, the number of patterns considered is constrained to keep the implemented hardware area and latency costs at or below a threshold (i.e., constraining area and / or latency), for example, when using a relatively large byte dictionary size. For example, in some implementations, limiting the number of patterns considered limits the number of comparators in the compressor and the complexity of the selector computation logic in both the compressor and decompressor.

[0098] Therefore, the constraints on pattern search are the set of compression sizes, d, and the number of target patterns, n, for each size. In some implementations, the only metadata required to decompress compressed cache blocks is the pattern index. In this case, metadata is required. The byte dictionary size is defined as p, where n is the number of target patterns. In some implementations, the metadata required for each target compression size is subtracted to produce a set of byte dictionary size constraints. In some implementations, the target size is independent of the interaction between patterns of different target sizes. In some implementations, for a byte dictionary size not greater than p, the pattern search constraint constrains the selection of the pattern set to the best n among all possible pattern sets.

[0099] Given the pattern-based compression and decompression techniques discussed above, in some implementations, it is desirable to select a set of patterns that satisfies certain objectives, which may conflict in some cases. This task is known as the pattern search problem. One exemplary objective is to develop a pattern set large enough to achieve the desired (i.e., appropriately high) quantization compression ratio. In other words, in some implementations, the pattern set is developed such that it describes the desired (e.g., appropriately large) portion of the block, for example, for the desired set of workloads (e.g., in a general workload set, for a training workload set, for most workloads, etc.). Another exemplary objective is to develop a pattern set small enough to achieve the desired (i.e., appropriately limited and / or appropriately low) metadata size.

[0100] In some implementations, compression represents the requirement for metadata. The number of bits is sufficient to fully describe the p-mode. Therefore, in some implementations, as metadata increasingly occupies space in the compressed representation, a larger number of modes will tend to reduce the number of bytes available in the byte dictionary. Furthermore, a larger number of modes will increase the area and latency overhead of the compression and decompression logic circuitry. On the other hand, in some implementations, fewer modes require fewer comparators, lower-priority encoders in the compressor, and fewer inputs to the multiplexers in both the compressor and decompressor.

[0101] Another exemplary objective is to select a mode based on the available compressed output size. As mentioned above, compressing to fewer bytes than the quantized output size offers no benefit unless it is compressed to a smaller quantized output size. Therefore, in some implementations, a set of compressed output sizes is input, and a set of modes is identified for each size.

[0102] In some implementations, the development of the cache block pattern set does not consider the interaction between patterns with different target sizes. In some implementations (e.g., for simplicity), the multi-target size problem is decomposed into a separate search problem for each quantized output size. In some implementations, encoding techniques are used to distinguish different sizes in the metadata, for example, by encoding each target output size with a unique symbol. Therefore, in some implementations, the core search problem is formulated as: selecting the best p patterns with a byte dictionary size no greater than n from all possible pattern sets.

[0103] Figure 9 This is a flowchart illustrating an exemplary process 900 for generating a BSC compressor and / or decompressor. Process 900 includes a process for selecting a subset of all possible cache block patterns. The process of selecting a suitable subset of all possible cache block patterns solves the pattern search problem discussed above. Process 900 also generates a hardware description for a suitable compressor and / or decompressor based on the subset. Typically, after determining an ordered set of cache block patterns, the ordered set of cache block patterns is reduced to generate a subset of these patterns, for example, using an associated counter. For example, in some implementations, the optimal p pattern (e.g., where p is a target number pattern derived from the target compressed cache block size, as described above) requires no more than n bytes for decompression.

[0104] More specifically, in step 910, a training procedure is executed using a cache or cache model (e.g., in hardware or in simulation), and a trajectory (e.g., log) of cache blocks appearing during the execution of the training procedure is captured. In some implementations, the training procedure represents a program to be run after training. In some implementations, the training procedure represents a program to be run after training if patterns appear in the training procedure and the target future program at the same or similar proportions (e.g., within a threshold level or percentage similarity). Cache block patterns appearing in the trajectory are identified based on the training trajectory and these patterns are sorted to generate a sorted list of all cache block patterns. In some implementations, the cache block patterns are sorted based on how many cache blocks appearing in the training trajectory are represented by each pattern.

[0105] In step 920, the sorted set of cache block patterns is reduced based on different characteristics (e.g., in the four stages discussed below) to generate a reduced set of cache block patterns. In step 930, a register transfer language (RTL) or other suitable representation of the compression and decompression hardware is generated based on the reduced set of cache block patterns.

[0106] Exemplary implementations of steps 910, 920, and 930 are discussed in more detail below. In step 910, pattern counts for generating a sorted set of cache block patterns are derived from the training trajectory. This process is called trajectory processing. In some implementations, patterns appearing in the trajectory are identified to derive the pattern counts. A straightforward approach to deriving the pattern counts is to determine, for each cache block pattern in a list of all possible cache block patterns for a given cache block size, how many of the cache blocks appearing in the trajectory (i.e., passed through the cache during training execution) can be described by that pattern. However, in some implementations, the number of all possible patterns is very large, and a cache block can be described by multiple patterns. Therefore, directly counting patterns in this way is not only computationally expensive but also loses some useful information about which patterns share which blocks in some implementations. For example, if two patterns can describe some (but not all) of the same cache blocks in the training trajectory, it is impossible to know how many cache blocks were counted by both patterns and how many were counted by only one pattern by counting both patterns. This can be disadvantageous in implementations that require deciding which of two modes represents more modes (e.g., eliminating one mode for efficiency).

[0107] Therefore, in some implementations, for each pattern appearing in the track, the number of cache blocks whose pattern is the simplest (i.e., includes the fewest number of symbols) pattern that can describe the cache block is determined. In some implementations, the simplest pattern for each cache block appearing in the track is determined, and the frequency of each of these patterns is counted. In some implementations, to determine the simplest pattern for a cache block, specific byte values ​​in the cache block are placed into an array (or otherwise indexed) in the order they appear in the cache block. Subsequently, each byte value in the original cache block is replaced with its index in the array.

[0108] As illustrative examples of various aspects of step 910, Figure 10 This is a flowchart illustrating an exemplary process 1000 for determining a pattern trajectory from a training trajectory. A pattern trajectory is a list of patterns describing cache blocks that appear in the training trajectory. This pattern trajectory can be used to derive the pattern count of the training trajectory.

[0109] In step 1010, an exemplary cache track comprising five uncompressed four-byte cache blocks is captured based on an exemplary training run. In step 1020, specific byte values ​​of each of the five uncompressed four-byte cache blocks are placed into an array (or equivalently indexed) in the order they appear in the uncompressed cache block. In step 1030, a record pattern for each of the five uncompressed four-byte cache blocks is created by replacing each specific byte value with its index in the array.

[0110] For example, the four-byte block FF FF 00 00 appears in the original trajectory captured in step 1010 and includes the specific byte values ​​FF and 00. In step 1020, these specific byte values ​​are placed into an array (or equivalently indexed) in the order they appear in the cache block, i.e., FF 00, where FF is at index 0 and 00 is at index 1. In step 1030, in the recorded pattern trajectory, each occurrence of the byte value FF in the original trajectory is replaced with index 0, and each occurrence of the byte value 00 in the original trajectory is replaced with index 1. Figure 10 As shown, an exemplary procedure 1000 is performed on each of the several four-byte blocks in the original trajectory to generate the corresponding recorded pattern trajectory.

[0111] After the pattern trajectory has been determined from the training trajectory, for example, the pattern count is determined using a procedure consistent with exemplary procedure 1000. For example, although each exemplary four-byte cache block in the original trajectory has a different value, one of the patterns in the recorded pattern trajectory (pattern 0 0 1 1 in this example) is the simplest byte pattern representation of three of those cache blocks. Therefore, this pattern has a count of 3, while the other two exemplary patterns in the recorded pattern trajectory both have a count of 1.

[0112] After determining the pattern count, return to Figure 9 In step 920, the cache block pattern set is reduced. In some embodiments, the cache block pattern set is reduced in a multi-stage process, where more patterns are successively removed in each stage. In exemplary process 900, step 920 is a four-stage process. In some embodiments, each stage has the same or greater algorithmic complexity than the previous stage. The first stage takes as input the patterns and counters (e.g., a sorted set of cache block patterns) generated in step 910. In step 930, the final (e.g., fourth) stage outputs a sorted set of patterns from which the maximum p can be used to generate RTL.

[0113] In Phase 1, infrequent patterns are removed. In some implementations, Phase 1 removes any patterns that most simply describe the pattern for a number of cache blocks less than a threshold. In some implementations, a threshold is set such that subsequent phases complete within an acceptable amount of time. Higher thresholds result in fewer patterns for later, more complex phases to process. In some implementations, a threshold is set to provide regularization to the process. For example, a higher threshold can improve compression results in subsequent phases or prevent or avoid input from this phase from negatively impacting subsequent phases. In some implementations, patterns are pruned at this phase solely based on the heuristic that less frequent patterns are unlikely to be useful (i.e., unlikely to describe cache blocks seen after training, e.g., in the target application). In some implementations, the output of Phase 1 has the same format as the input of Phase 1; for example, a list of cache block patterns that were not pruned in Phase 1, which includes a corresponding count of how many cache blocks in the trajectory have patterns that are the simplest descriptors of the pattern.

[0114] If the number of patterns input to stage 1 is n1, then stage 1 can be described as having O(n1) complexity, where the complexity represents the number of operations performed in that stage. Subsequent stages are described relative to that stage based on this functionality.

[0115] In phase 2, cache block patterns that do not have the maximum inclusion relative to the training trajectory (i.e., "non-maximum" cache block patterns) are removed from the pattern list output from phase 1.

[0116] A cache block pattern is considered maximally inclusive (i.e., "maximally") relative to the training trajectory if the cache blocks described by the cache block pattern in the recorded pattern trajectory are not a subset of cache blocks that can be described by any other cache block pattern in the recorded pattern trajectory. In other words, a cache block pattern is maximally inclusive if no other cache block pattern in the recorded pattern trajectory describes the same cache blocks as well as any other cache blocks. Conversely, a cache block pattern is not maximally inclusive relative to the training trajectory if the cache blocks that can be described by a cache block pattern are a subset of cache blocks that can be described by another cache block pattern in the recorded pattern trajectory. In other words, a cache block pattern is not maximally inclusive relative to the training trajectory if another cache block pattern in the recorded pattern trajectory describes all the same cache blocks as well as any other cache blocks in the trajectory.

[0117] Because if a pattern describes a set of cache blocks that is a subset of the cache blocks described by another pattern in the recorded pattern track, we can say that this pattern is smaller than the other pattern. Therefore, a partial ordering of cache block patterns in the recorded pattern track can be created based on the set of cache blocks they describe in the track. This partial ordering of cache block patterns can be represented using a lattice of all possible cache block patterns of cache block size. In this context, a partial ordering of cache block patterns in the recorded pattern track means a set of partial orderings; that is, for all patterns, the subset operation is reflexive, antisymmetric, and transitive. In partial ordering, for some pairs of cache block patterns, neither is a subset of the other, while in full ordering, for any pair of cache block patterns, one pattern will compress a subset of the blocks compressed by the other pattern.

[0118] Figure 11 This is a dot plot illustrating exemplary relationships between cache block patterns in an exemplary set of 4-byte cache block patterns.

[0119] exist Figure 11In the dot matrix, arrows connecting different patterns indicate that the source pattern (at the root of the arrow) is smaller than the target pattern (at the head of the arrow). The "bottom" of the dot matrix includes patterns that describe cache blocks containing only a specific byte value. In this example, the bottom of the dot matrix uses the symbol "0 0 0 0" to describe a cache block containing only a specific byte value. The "top" of the dot matrix includes patterns that describe the maximum number of specific byte values ​​for the size of a cache block (i.e., four specific byte values ​​for a four-byte cache block in this example). In this example, the top of the dot matrix uses the symbol "0 12 3" to describe a cache block containing four specific byte values. Patterns closer to the top of the dot matrix describe a greater number of cache blocks than patterns closer to the bottom; that is, cache blocks with larger maximum values. The cache block patterns at the arrowhead describe all cache blocks that the patterns at the arrowroot can describe, and also describe other cache blocks.

[0120] As mentioned above, in some implementations, the constraint n on the byte dictionary size is derived from the target compression size. Therefore, for quantized compression, compressing to a size smaller than the size used to derive n does not provide any benefit in some implementations.

[0121] Therefore, return Figure 9 In phase 2, those patterns from the cache block pattern set output from phase 1 that are as close as possible to the top of the lattice describing the set while still satisfying the byte dictionary size constraint n are retained and are considered to be the largest relative to the output of phase 1.

[0122] To illustrate this, let's assume... Figure 11 An exemplary dot matrix is ​​provided, which includes all cache block patterns of 1, 2, 3, and 4-byte dictionaries (i.e., all 4-byte long cache blocks). For example, assuming a constraint of n=3, the largest patterns across the entire dot matrix that satisfy this constraint are those patterns that require a 3-byte dictionary. Figure 11 The legend indicates exemplary recorded pattern trajectories (i.e., cache block patterns 0000, 0010, and 0011) within the dot matrix from the input of stage 1. Based on this input, none of the patterns requiring 3 bytes in the dot matrix appear in the input from stage 1. Therefore, in this example, the largest patterns from the input of stage 1 relative to the training trajectory are 0010 and 0011, because no patterns with larger maximum values ​​appear in the training trajectory. Pattern 0000 is not the largest because it is located at the root of the arrow pointing to one of these patterns (i.e., the pattern with the larger maximum value appears in the training trajectory).

[0123] Therefore, the output of Phase 2 includes the maximum patterns and excludes non-maximum patterns. In addition to eliminating non-maximum patterns from the search, a count of the number of cache blocks described by each maximum pattern is tracked. For each maximum pattern, the count includes the count of all patterns whose maximum value is less than or equal to itself. However, since the maximum value of a non-maximum pattern may be less than several maximum patterns, a set of non-maximum patterns and counts is maintained to avoid duplicate counting of patterns in subsequent phases. In some implementations, this ensures that the same set of cache blocks is described in subsequent phases. However, non-maximum patterns are excluded from the search itself. In other words, in some implementations, although none of the non-maximum patterns identified in Phase 2 are used in the final compression algorithm output, they may be used in subsequent phases to select among the maximum patterns that may be included in the final compression algorithm.

[0124] The set of patterns that is largest relative to the output of stage 1 (i.e., in the output of stage 2) can represent n or fewer specific byte values ​​of a cache block (i.e., can be used with a dictionary of n or fewer bytes). However, patterns that are largest relative to the entire lattice are needed to represent n specific byte values ​​of a cache block (i.e., can be used with a dictionary of n bytes). The pattern that is largest relative to the entire lattice is called the absolute maximum or generally maximum because it has the maximum inclusion independent of the training trajectory.

[0125] If the number of patterns input to stage 2 is n², then stage 2 can be described as having O(n²) time complexity. 2 Complexity.

[0126] In Phase 3, the relatively largest patterns (i.e., the patterns that are largest relative to the training set but not usually the largest relative to the lattice) are grouped together to reduce the number of patterns in the set.

[0127] As discussed regarding Phase 2, some patterns are largest relative to the set of patterns under consideration (e.g., patterns present in the training trajectory), but not necessarily the largest relative to the set of all possible patterns. In other words, they are relatively largest (e.g., largest relative to the training trajectory) but not absolutely largest (i.e., relative to the lattice). Patterns that are only relatively largest do not fully utilize the available byte dictionary space. Such underutilization provides no benefit because the additional reduction in compressed block size by more than n bytes is useless in the target hardware application. Therefore, in some implementations, patterns that are only relatively largest in the set are replaced by patterns with a larger maximum value in the lattice (i.e., relative to the lattice) that are larger than the replaced pattern while still satisfying the constraints (if such a pattern exists). Because larger cache block patterns describe all cache blocks described by fewer cache block patterns, it is guaranteed that larger patterns identified in Phase 3 that did not appear in the training trajectory describe at least the same cache blocks (i.e., the described cache blocks are not reduced after Phase 3).

[0128] Back Figure 11 In the trajectory, no pattern is absolutely maximum. The maximum values ​​of the two relatively maximum patterns 0010 and 0011 are both smaller than the maximum value of pattern 0012, satisfying the constraint n=3. Therefore, pattern 0012 can replace both 0010 and 0011 in the cache block pattern set, so that the same cache block can be described using (at least) fewer patterns.

[0129] Back Figure 9 In some implementations of Phase 3, an attempt is made to combine all the pattern pairs under consideration. For example, to combine a pair, the simplest pattern that can describe the union of the cache block sets described by the two patterns in the pair is determined. If the new pattern satisfies a given byte dictionary size constraint, the two patterns in the pair are replaced by the new pattern. Any other relatively maximum pattern whose maximum value is smaller than the new pattern is also removed. To calculate the counter value for the new pattern, a counter from the disjoint cache block sets in Phase 1 is used. In some implementations, Phase 3 continues to combine cache block pattern pairs in the set that are not absolutely the largest until no cache block pattern pairs can be combined.

[0130] If the number of patterns input to stage 3 is n3, then stage 3 can be described as having O(n3) time complexity. 3 Complexity.

[0131] In stage 4, a subset of cache block patterns representing the maximum number of cache blocks from the output of stage 3 is selected. In some implementations, this subset is selected by first iteratively sorting the remaining cache block patterns. During the iterative sorting, two sets of patterns are maintained. The first set is empty in the first iteration, and the second set contains all patterns remaining after stage 3. In each iteration, patterns from the second set that increase the number of cache blocks compressed in the first set (from the training trajectory) are moved from the second set to the first set. Then, the optimal p patterns are selected from the sorted list.

[0132] Figure 12 This is an explanation of how to reduce from Figure 9 A flowchart of an exemplary process 1200 for the output cache block pattern set in stage 3. In step 1210, the process begins with no pattern and the iteration count i = 0. Figure 12 In the flowchart, this exemplary iteration counter is used only for convenience and ease of illustration, and it should be noted that iterations can be tracked in any suitable manner. In step 1220, a pattern describing the maximum number of cache blocks is selected from the pattern list output in stage 3. In some implementations, this is determined based on a counter associated with the ordered set of cache block patterns discussed above with respect to step 1010 (i.e., the count of cache blocks represented by each pattern).

[0133] Under condition 1230, where no target number pattern has been added to the set, the iteration counter is incremented in step 1240 (or otherwise tracks iterations), and step 1220 is repeated. The target number pattern is based on p. After at least one pattern has been added to the set, a next pattern is selected in subsequent iterations of step 1220, the next pattern describing an additional number of cache blocks beyond the maximum number of cache blocks already described by the patterns in the set. In some implementations, iteratively constructing a sorted list of selected patterns in this manner guarantees the selection of the best pattern while taking into account the current sorted list in each iteration. In some implementations, this guarantee requires updating the benefit of adding each remaining pattern to the current pattern set in each iteration based on the describable line. A* search can be used to make this search practical. In some implementations, the "guarantee" of selecting the best pattern while taking into account the current sorted list is weaker than the guarantee of selecting the best set of patterns overall. In some implementations, the "best" pattern is the pattern that increases the number of cache blocks compressed by the current set from the training trajectory the most when added to the current set. A* search is an exemplary search algorithm known in the field of artificial intelligence.

[0134] Under condition 1230, where the target number of patterns has been added to the set, the list of cache block patterns is complete, and stage 4 outputs the pattern list to, for example, HDL or any other suitable format for later implementation in hardware and / or software.

[0135] In some implementations, the iterative sorting in stage 4 produces a single list of sorting patterns that can be reused for different p values. Once a sufficiently large sorting list has been generated, the largest p can be selected for any p value less than or equal to the list size.

[0136] The output from stage 4 is a set of p patterns that comply with the byte dictionary size constraint n, and a sorted list of the p best cache block patterns input from stage 3.

[0137] Back Figure 9 After the set of cache block patterns has been reduced and sorted in step 920, circuitry and / or software can be generated to implement the BSC compressor and / or decompressor based on these patterns. In step 930, RTL or other suitable hardware description code or other descriptions for implementing the compression and decompression processes are generated based on the patterns output from stage 4. Figure 3 , Figure 4 , Figure 5 and Figure 6 Examples of compression process, compression circuit, decompression process, and decompression circuit are provided, which can be generated in step 930 based on the output of stage 4.

[0138] For example, in some implementations, regarding Figure 3 Step 330 Figure 4 Logic circuit 450 Figure 5 Step 530 and Figure 6 The set of cache block patterns shown and described in logic circuit 620 is generated based on the output of stage 4.

[0139] In some implementations, the RTL or other representation is "hard-coded" to the cache block pattern from stage 4; that is, the value of the cache block pattern in the hardware is explicitly defined. In some implementations, this hard-coding has the following advantages over non-hard-coding methods: it facilitates the logical synthesis of the input RTL or other representation, thereby significantly improving the performance and area characteristics of the resulting hardware.

[0140] Figure 13This is a bar chart comparing the exemplary performance of existing algorithms (Variable-Based Compression (BDI), Bit-Plane Compression (BPC), Cache Packer (CPack), Common Pattern Compression (FPC), and Zero Content Enhancement (ZCA)) with the exemplary performance of byte-selective compression using one byte of metadata (UB-M1). It shows that the performance of existing algorithms is only half the ideal performance of the exemplary byte-selective algorithms. As can be seen from the chart, for example, for the compression ratio of ideal byte-selective performance, UB-M1 is at least twice that of existing 1-bit quantization algorithms.

[0141] Table 6 shows exemplary performance and overhead characteristics of various compression algorithms:

[0142] Table 6

[0143]

[0144]

[0145] In some implementations, data compression in BSC is greater than other algorithms, but single-loop compression and decompression introduce corresponding latency. In some implementations, greater data reduction can be achieved by trading die area and compression latency (e.g., one latency loop).

[0146] The teachings disclosed herein may be useful in any hardware where data storage capacity and / or data transfer bandwidth are issues. This includes all CPUs, GPUs, and SoCs. The teachings disclosed herein automate the design of cache block compression algorithms to provide the algorithm with the maximum number of compressed blocks. It should be understood that many variations are possible based on the disclosures herein. While features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0147] The various functional units shown in the figures and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, computing unit 132, and SIMD unit 138) may be implemented as a general-purpose computer, processor, or processor core, or implemented as a program, software, or firmware, stored on a non-transitory computer-readable medium or another medium, executable by a general-purpose computer, processor, or processor core. The methods provided can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of such processing can be a mask, which is then used in the semiconductor manufacturing process to manufacture a processor that implements the features of this disclosure.

[0148] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROMs and DVDs).

[0149] ***

Claims

1. A method implemented in a compressor for performing pattern-based cache block compression, the method comprising: inputting an uncompressed cache block; identifying byte values in the uncompressed cache block; converting the byte values into symbols, each symbol representing a particular cache block; searching for a cache block pattern in a set of cache block patterns based on the byte values by searching the set of cache block patterns based on the symbols; and outputting a compressed cache block based on the byte values and the cache block pattern.

2. The method of claim 1, further comprising representing the uncompressed cache block in terms of the symbols.

3. The method of claim 1, wherein the compressed cache block comprises the byte values and an index of the set of cache block patterns.

4. The method of claim 1, wherein the compressed cache block comprises a byte dictionary defined by the byte values identified in the uncompressed cache block and metadata, the metadata comprising an index of the set of cache block patterns.

5. The method of claim 4, wherein the metadata comprises an index of the set of cache block patterns.

6. The method of claim 4, wherein the byte dictionary comprises each of the byte values, and for each of the byte values, the byte dictionary comprises only one copy.

7. A method implemented in a decompressor for performing pattern-based cache block decompression, the method comprising: inputting a compressed cache block; identifying a cache block pattern in a set of cache block patterns based on metadata of the compressed cache block, wherein the cache block pattern comprises symbols; converting the symbols of the cache block pattern into byte values based on a byte dictionary of the compressed cache block; and outputting an uncompressed cache block based on the byte values.

8. The method of claim 7, wherein the compressed cache block comprises an index of the set of cache block patterns.

9. The method of claim 7, wherein the byte dictionary comprises each of the byte values, and for each of the byte values, the byte dictionary comprises only one copy.

10. The method of claim 7, wherein the metadata comprises an index of the set of cache block patterns.

11. The method of claim 7, wherein identifying the cache block pattern in the set of cache block patterns based on the metadata of the compressed cache block comprises searching for the cache block pattern in the set of cache block patterns based on the metadata.

12. The method of claim 7, wherein the cache block pattern comprises at least one symbol corresponding to at least one byte of the byte dictionary.

13. The method of claim 7, wherein the compressed cache block comprises byte values.

14. The method of claim 7, wherein the byte dictionary of the cache block comprises particular byte values of the uncompressed cache block.

15. A method for generating hardware configured for pattern-based cache block compression, the method comprising: inputting, to a computing system, a cache trace captured from an execution of a training program; determining, by the computing system, a set of cache block patterns based on the cache trace; determining, by the computing system, a subset of cache block patterns from the set of cache block patterns, wherein the subset of cache block patterns is determined based on a set of compressed cache block sizes and a target number of patterns per cache block size, wherein a compressed size represents a desired compression ratio based on which constraints on a byte dictionary are derived; and outputting, by the computing system, a hardware description for generating hardware configured for pattern-based cache block compression, the hardware description based on the determined subset of cache block patterns.

16. The method of claim 15, wherein determining the subset of cache block patterns further comprises: ordering, by the computing system, the set of cache block patterns based on frequency of occurrence in the cache trace to generate an ordered set of cache block patterns.

17. The method of claim 16, wherein determining the subset of cache block patterns further comprises: reducing, by the computing system, the ordered set of cache block patterns to generate a threshold set of cache block patterns by removing patterns that occur with a frequency lower than a threshold frequency in the cache trace; and removing, by the computing system, from the threshold set of cache block patterns, cache block patterns that do not have maximum inclusivity to generate a locally maximum set of cache block patterns.

18. The method of claim 17, wherein determining the subset of cache block patterns further comprises: combining, by the computing system, patterns of the locally maximum set of cache block patterns that are most frequent relative to patterns present in the cache trace to generate an absolutely maximum set of cache block patterns; and iteratively ordering, by the computing system, a subset of the absolutely maximum set of cache block patterns based on which pattern describes more cache blocks in the absolutely maximum set of cache block patterns to determine the subset of cache block patterns.

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