Neuromorphic device with crossbar array structure

Abstract

Neuromorphic methods, systems, and devices (10, 11, 12) are provided. Embodiments can include a neuromorphic device (10, 11, 12) that can include a crossbar structure (110) and analog circuitry. The crossbar structure (110) can include N input lines (111, 112) and M output lines (120) interconnected at junctions via N x M electronic devices (131, 132, 32a, 132b, 132c), in preferred embodiments each including a memristive device. The input lines can include N1 first input lines (111) and N2 second input lines (112). The first input lines (111) can be connected to the M output lines (120) via N1 x M first devices (131, 132) of the electronic devices (131, 132). Similarly, the second input lines (112) can be connected to the M output lines (120) via N2 x M second devices (132) of the electronic devices (131, 132). The analog circuitry (140, 150, 160, 170) can be configured to program the electronic devices (131, 132) such that the first devices (131) store synaptic weights and the second devices (132) store neuron states.

Description

BACKGROUND

[0001] The present invention relates generally to the field of neuromorphic devices with a crossbar array structure. In particular, the present invention relates to a neuromorphic device whose crossbar array structure comprises additional input lines to store neuron states of a neural network, whereby neuron functionality is at least partially implemented by analog circuitry of the device.

[0002] Machine learning often relies on artificial neural networks (ANN), which are computational models inspired by biological neural networks in the human or animal brain. Such systems learn tasks progressively and autonomously by example; they have been successfully applied, for example, to speech recognition, text processing, and computer vision.

[0003] ANNs comprise a set of connected units or nodes, which are compared to biological neurons in the animal brain and are therefore called artificial neurons. Similar to synapses, signals are transmitted along connections between artificial neurons, also called edges. That is, an artificial neuron receiving a signal processes it and subsequently signals connected neurons. Typically, the signal transmitted along such a connection is an analog real number, and the output of an artificial neuron is computed as a non-linear function of the sum of its inputs.

[0004] Connection weights, also called synaptic weights, are associated with connections and nodes; such weights are adjusted as learning proceeds. Each neuron can have several inputs, and a connection weight is assigned to each input (the weight of that particular connection). Such connection weights are learned and thereby updated during a training phase. The learning process is iterative: data cases are presented to the network, typically one at a time, and at each time step the weights associated with input values are adjusted.

[0005] Many types of neural networks are known, starting with feedforward neural networks, such as multilayer perceptrons, deep neural networks, and convolutional neural networks. In addition, new types of neural networks have emerged, such as spiking neural networks. Spiking neural networks (SNNs) fundamentally differ from usual neural networks in that SNNs operate with spikes, which are discrete binary events that can happen asynchronously at any point in time, rather than analog values that are computed at regular time steps. That is, SNNs incorporate the concept of time in addition to neuron and synapse states. That is, neurons fire only when the membrane potential reaches a certain value, rather than firing at every propagation cycle as in, for example, multilayer perceptron networks. In the context of SNNs, firing means that a neuron generates a signal that reaches other neurons, which in turn increase or decrease their potential according to the signals they receive from other neurons.

[0006] Neural networks are typically implemented in software. However, neural networks can also be implemented in hardware, e.g. as resistive processing units (relying on crossbar array structures) or optical neuron morphic systems. That is, a hardware-implemented ANN is a physical machine that is significantly different from a classical computer (general- or special-purpose computer) in that it is primarily and specifically designed to implement an ANN (for training and / or inference purposes). A hardware-implemented ANN can at most be emulated with a classical computer (albeit not with the same efficiency), while it cannot perform multiple data processing tasks like a classical computer.

[0007] The following papers form part of the background art:

[0008] Nandakumar, S. R., et al. "A phase-change memory model for neuromorphic computing." J. Appl. Phys., vol. 124, no. 15, 21 Oct. 2018, p. 152135;

[0009] Tuma, T., et al. "Stochastic phase-change neurons." Nat. Nanotechnol, vol. 11, 16 May. 2016, pp. 693-699.

[0010] Pantazi, A. et al. "All-memristive neuromorphic computing with level-tuned neurons." Nanotechnology 27 35 (2016): 355205. SUMMARY

[0011] According to a first aspect, the invention is embodied as a neuromorphic device substantially comprising a crossbar structure and an analog circuit. The crossbar structure comprises N input lines and M output lines interconnected at junctions via N x M electronic devices, which in a preferred embodiment each comprise a memristive device. The input lines comprise N1 first input lines and N2 second input lines. The first input lines are connected to the M output lines by N1 x M first devices of said electronic devices. Similarly, the second input lines are connected to the M output lines via N2 x M second devices of said electronic devices. The following relations hold: N1 > 1, N2 > 1, N1 + N2 = N, and M > 1. The analog circuit is configured to program the electronic devices such that the first devices store synaptic weights and such that the second devices store neuron states. Further, the analog circuit is configured to read out M output signals obtained from the M output lines by a multiply-accumulate operation. In operation, the read out is based on N1 input signals coupled to the first input lines, N2 control signals coupled to the second input lines, and values stored on each of the first and second devices.

[0012] According to the present solution, both synaptic weights and neuron states (e.g. membrane potentials) can be represented by electronic devices (e.g. memristive devices) at the junctions. However, this approach is compatible with different electronic devices (e.g. flash memory cells, memristive devices, static random access memory devices, etc.). The present solution makes it possible to compute neuron states in constant time without the need for additional circuitry, in particular without the need for any conversion in the digital domain. Since the analog circuit allows to compute neuron states in the analog domain, the proposed solution is in principle more time-efficient than the solutions implemented by previous neuromorphic devices based on crossbar structures.

[0013] In embodiments, the analog circuit is further configured to update neuron states stored on at least some of the N2 x M second devices, whereby in operation said at least some of the N2 x M second devices can be reprogrammed according to the M output signals previously read out by the analog circuit.

[0014] In further embodiments, the analog circuit is further configured to couple said N1 input signals and said N2 control signals to the N1 first input lines and the N2 second input lines, respectively.

[0015] In a preferred embodiment, the second input lines comprise given control lines connected to the output lines via M given electronic devices. Such electronic devices can be programmed by the analog circuit to store M initial membrane potential values. Moreover, the analog circuit can be further configured to couple a given control signal into the given control lines so that the M output signals read out represent M final membrane potential values obtained as a leaky integrator of the synaptic input obtained in operation by coupling the N1 input signals into the N1 first input lines, based on the M initial membrane potential values.

[0016] In this respect, in operation, the given control signal (as coupled into the given control lines) preferably represents a decay parameter a. Moreover, the analog circuit can be further configured to adjust the N1 input signals so that they represent synaptic input values scaled complementarily by 1-a.

[0017] Preferably, the analog circuit can be further configured to update the membrane potential values stored on the M given electronic devices in operation by reprogramming such devices according to the M output signals representing the M final membrane potential values previously read out by the analog circuit.

[0018] In an embodiment, the analog circuit can be further configured to perform, for each of the M output lines, a comparison between each of the M output signals read out and a threshold value 0.

[0019] Preferably, the analog circuit can be further configured to generate a signal for each of the M output lines based on the result of the comparison and to reset the values stored on any of the M given electronic devices.

[0020] In a preferred embodiment, the second electronic devices comprise M further electronic devices and the second input lines comprise further control lines connected to the output lines via the M further electronic devices. The M further electronic devices can be programmed by the analog circuit to store M threshold values so that, in operation, the M output signals read out represent M differences between the M final membrane potential values and the M threshold values of a further control signal coupled into the further control lines.

[0021] Preferably, the analog circuit can be configured to select the further control signal to be coupled into the further control lines for the further control signal to represent an input value of 0 or an input value of -1. For the input value of 0, the M output signals read out represent the M final membrane potential values. For the input value of -1, the M output signals read out represent the M differences between the M final membrane potential values and the M threshold values.

[0022] In a preferred embodiment, the second input line includes three control lines, including the given control line. The three control lines include two additional control lines in addition to the given control line. The two additional control lines are connected to the output line via 2×M additional electronic devices in the electronic device. The analog circuit is further configured to program the 2×M additional electronic devices to store operands for the adaptive firing threshold.

[0023] Preferably, the analog circuit is further configured to couple two additional control signals into the two additional control lines and is further configured to select each of the two additional control signals so that the output signal read out by the circuit represents M differences between M final membrane potential values ​​and M adaptive excitation thresholds.

[0024] More preferably, the analog circuit is further configured to reprogram M of the 2×M additional electronic devices connected to one of the two additional control lines so as to update the operands stored thereon in operation according to the output value previously read by the analog circuit (e.g., during a previous iteration).

[0025] In an embodiment, the analog circuit is further configured to reprogram the N1×M first devices to change the synaptic weights stored thereon according to an automatic learning process.

[0026] Preferably, the analog circuit comprises a programming circuit and a readout circuit, the readout circuit being connected to the programming circuit, wherein the readout circuit is configured to read out the M output signals, and the programming circuit is configured to program the electronic device according to the output signal previously read out by the readout circuit.

[0027] More preferably, the programming circuit comprises an input circuit configured to, on the one hand, couple a signal into the input line and, on the other hand, select the signal to be coupled into the input line so as to program the electronic device in operation based on the signal coupled into the input line.

[0028] According to another aspect, the present invention is embodied as a neuromorphic system. The system includes L neuromorphic devices, each of which is a neuromorphic device according to the embodiments described above. The system also includes a communication bus, wherein the system is configured to forward an output signal read out of a given neuromorphic device in the L neuromorphic devices to a next neuromorphic device in the L neuromorphic devices via the communication bus.

[0029] According to a last aspect, the invention is embodied as a method of operating a neuromorphic device. The method relies on a neuromorphic device having an analog circuit and a crossbar structure. The crossbar structure comprises N input lines and M output lines interconnected at junctions via N x M electronic devices. The input lines comprise N1 first input lines and N2 second input lines connected to the M output lines via N1 x M first devices of the electronic devices and N2 x M second devices of the electronic devices, respectively, with N1 > 1, N2 > 1, N1 + N2 = N, and M > 1. The method comprises programming the electronic devices via the analog circuit such that the first devices store synaptic weights and such that the second devices store neuron states. Further, the method comprises reading out M output signals obtained from the M output lines according to a multiply-accumulate operation again via the analog circuit. The latter is based on N1 input signals coupled to the N1 first input lines, N2 control signals coupled to the N2 second input lines, and values stored on each of the first and second devices.

[0030] In a preferred embodiment, the method further comprises updating neuron states stored on at least some of the N2 x M second devices by reprogramming the at least some of the N2 x M second devices according to the M output signals previously read out with the analog circuit.

[0031] Devices, systems and methods embodying the invention will now be described by way of non-limiting examples and with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain all the principles and advantages according to the present disclosure, wherein:

[0033] Figure 1 is a diagram schematically illustrating high-level components of a prior art neuromorphic system. The system comprises a memristive crossbar array and implements an artificial neural network. The neuron functionality is implemented by a digital processing engine: the input to the neuron is the result of a multiply-accumulate operation which is converted to the digital domain to implement the neuron functionality.

[0034] Figure 2is a diagram schematically illustrating high-level components of a neuromorphic system according to an embodiment. The system comprises a neuromorphic device with a crossbar array of memristors implementing a spiking neural network. The neuron function is now implemented by an analog circuit that reads out all useful signals and computes the neuron output before converting these outputs into the digital domain.

[0035] Figures 3A to 3B schematically represents a crossbar array of memristors of a neuromorphic device according to an embodiment, wherein the device is intended to implement a layer of a spiking neural network. Figure 3A is schematically depicted the operations performed by the analog circuit, whereby the neuron state is updated in the crossbar array of memristors and the membrane potential is compared to a threshold to generate the neuron output. Figure 3B is explicitly shown the components of the analog circuit for performing the comparison in the output of the crossbar array of memristors.

[0036] Figure 4 is shown Figure 3B a variant of, wherein the components of the analog circuit for making the comparison are now integrated in the crossbar array of memristors, as in the embodiment.

[0037] Figure 5 is shown Figure 4 a variant of, wherein the analog circuit comprises an additional component integrated in the crossbar array of memristors for programming the electronic devices of the array to make the electronic devices store an operand of the adaptive firing threshold, as in the embodiment.

[0038] Figure 6 is a flowchart showing high-level steps of a method of operating a neuromorphic device such as Figures 2 to 5 depicted in, according to an embodiment.

[0039] The drawings show simplified representations of devices or parts thereof involved in the embodiments. The technical features depicted in the drawings are not necessarily drawn to scale. Like or functionally similar elements have been allocated the same reference numerals in the drawings, unless otherwise indicated. DETAILED DESCRIPTION

[0040] Neuromorphic devices based on crossbar array structures have been proposed. These devices are used to implement ANNs. However, external circuits (involving digital processing units) are needed to implement the neuron function. That is, most of the neuron function relies on digital processing units connected to analog circuits, see for example S. R. Nandakumar, et al., ISCAS 2018, cited in the background section. That is, only the synaptic weights are stored in the analog units, while the neuron activation is implemented in the digital processing units. In Figure 1This situation is synthetically captured: synapses are implemented in a crossbar array of memristive devices. Pulse width modulation (PWM) circuits can for example be used to generate the input x,(t) to a synapse. However, the neuron functionality is implemented by a digital processing engine and static random access memory (SRAM). This functionality is thus not directly mapped on the crossbar array. The input to a neuron is a multiply-accumulate operation performed in the analog space (i.e., ∑ i W ji x i (t)) of the results. This result is then converted to the digital domain using an analog-to-digital converter (ADC) circuit. In the digital domain the neuron activation function f(∑ i W ji x i (t)) is computed, resulting in an output y i (t) that is passed to a core-to-core communication bus that relays such signals to the neurons of the next layer.

[0041] Starting from these observations, the inventors have realized that neuron functionality can be at least partially integrated in a crossbar array structure. They have accordingly developed different neuromorphic devices and corresponding computing systems that can be used to implement both usual ANNs as well as SNNs. Such solutions are described in detail in the following description

[0042] With reference to Figures 3A to 3B and Figures 4 and 5 , aspects of the invention are first described that relate to a neuromorphic device 10 to 12. In essence, this device comprises a crossbar array structure and analog circuits, wherein the latter integrate a plurality of functionalities.

[0043] The crossbar array structure 110 comprises N input lines (horizontal lines) 111, 112 and M output lines (vertical lines) 120. The input lines and the output lines are interconnected at junctions via N x M electronic devices 131, 132, which are preferably memristive devices. Such devices are also referred to as “cells” in this document.

[0044] Interestingly, the input lines 111, 112 are decomposed into two subsets of input lines, which are referred to as first input lines and second input lines, respectively. As we will see, the first input lines and the second input lines have different functionalities. Similarly, the electronic devices 131, 132 delimit two subsets, which are referred to as first devices 131 and second devices 132, respectively.

[0045] Structurally, the input lines are decomposed into N1 first input lines 111 and N2 second input lines 112. The first input lines 111 are connected to the M output lines 120 via N1 x M first devices 131, while the second input lines 112 are connected to the M output lines 120 via N2 x M second devices 132. The above different numbers are constrained as follows: N1 > 1, N2 > 1, N1 + N2 = N, and M > 1, subject to the following additional comments.

[0046] The analog circuit 140-170 is notably configured to program S110 the electronic devices 131, 132 for their storage of values, or more precisely, to have properties (e.g. conductance, or amount of stored charge) that can be interpreted as such. Note that all references to "Sijk" refer to method steps that notably appear in the flowchart of Figure 6 As in prior art devices, the first devices 131 can accordingly be programmed to store synaptic weights. However, the second devices 132 are here programmed by the analog circuit to store neuron states of an artificial neural network (ANN) implemented by the array.

[0047] The analog circuit is also configured to read out S140 M output signals (e.g. currents) obtained from the M output lines 120. This readout is performed according to a multiply-accumulate operation that takes into account signals (e.g. currents or voltage biases) coupled into each input line, including the second input lines, that are used to apply the control signals. That is, in operation, the readout is based on N1 input signals coupled S121 to the first input lines 111, while N2 control signals are coupled S122 to the second input lines. According to the multiply-accumulate operation performed, the values stored S110 on each of the first devices 131 and the second devices 132 influence the readout.

[0048] Furthermore, the same analog circuit 140-170 is preferably used to couple input signals into the input lines. That is, a third function of the circuit can be to couple S120 said N1 input signals and said N2 control signals into N1 first input lines 111 and N2 second input lines 112, respectively. Thus, the analog circuit can have three different functions: (i) program S110 the electronic devices 131, 132; (ii) read out S140 output signals obtained from the M output lines 120; and (iii) couple input signals into the input lines in order to read out said output signals. In variants, separate input circuits can be used for any of the functions. In both cases, the input can for example be implemented via a PWM circuit.

[0049] According to the above relations, i.e. N1≥1, N2≥1, N1+N2=N, and M≥1, there is at least one output line and at least two input lines. The at least two input lines comprise at least one input line, i.e. the first input line, for coupling at least one input signal (corresponding to a synaptic input). The at least two input lines further comprise at least one control line, i.e. the second input line, this time for applying a control signal. The applied control signal is typically constant during at least one operation cycle (e.g. to allow a membrane potential to be stored on the second subset of electronic devices), but can vary from one operation cycle to another, as discussed later. Such control signals can further be optional signals, e.g. to include a threshold (possibly a varying threshold) in a crossbar array, as in embodiments discussed later.

[0050] However, in practice, there will likely be several input lines 111 (e.g. 8, 32,..., 250,..., 1000, etc., where the number can be even or odd). In possible embodiments, the number of input lines 111 will be on the order of a few hundreds. Similarly, there will typically be several output lines 120, typically between 8 and 2000. The number of control lines 112 depends on the level of complexity sought; one, two, three or more control lines can be involved, as discussed later with reference to Figures 3A to 3B and Figures 4 and 5 as shown.

[0051] In practice, the first input line and the second input line will preferably form well-separated subsets. I.e. the present devices 10-12 preferably comprise non-overlapping subsets of input lines, such that the array presents a first subset of consecutive input lines for coupling input values, while a different second subset of consecutive input lines is used for applying control signals, which is necessary to take into account the neuron state of the device.

[0052] The multiply-accumulate operation performed by the analog circuit results in the signals coupled into the input lines being multiplied by the values stored on the electronic devices at the synapses, respectively, as is common in memristive crossbar arrays. However, in the present case, the analog multiply-accumulate operation takes into account the control signal. Thus, the signals coupled into the first input line 111 and the second input line 112 are multiplied by the values stored on the first electronic device and the second electronic device, respectively.

[0053] Interestingly, the present devices 10-12 can be used to implement a regular ANN or even a spiking neural network (SNN), it being noted that SNNs are considered to be a subclass of the general ANN in the present document. Thus, unless otherwise indicated, ANN is meant to cover SNNs here.

[0054] However, strictly speaking, in Figures 3A to 3B and Figures 4 and 5The architecture of the devices shown in corresponds to a single layer of nodes, rather than a multi-layer network. Thus, the neuromorphic devices 10 to 12 as described above typically correspond to a single layer of a neural network (NN). Such neuromorphic devices 10 to 12 can be considered as analog core processing devices. In principle, their architecture could be expanded (or stacked) to implement several connected layers (thus forming a multi-layer network), or could be connected, for example, via a core-to-core communication bus (possibly including digital processing units). That is, such as Figures 3A to 3B and Figures 4 and 5 Several devices 10 to 12 shown in FIG can be coupled to form a neuromorphic system 1, as will be seen later with respect to another aspect of the invention. Figure 2 described.

[0055] Note that the weights stored on the first device 131 are typically constant for inference purposes, whereas they will need to be reprogrammed for learning purposes. For learning, the analog circuits 140 to 170 can be used to reprogram the N1×M first devices 131 to change the synaptic weights stored thereon, and this can be done according to any suitable automated learning process. However, more generally, the present devices 10 to 12 can be used for both learning and inference purposes.

[0056] As previously mentioned, analog circuits 140 to 170 may include, for example, input circuits, readout circuits, and programming circuits. Interestingly, the input circuits and programming circuits may be formed as the same circuit, as the applied signals may be selected in such a way as to couple the signals into the input lines or program the cells, as in the preferred embodiment. Note that this analog circuit may also be considered an analog processing unit, as it includes programming functionality. Nevertheless, this analog circuit may still be coupled to a digital processing unit, and the digital processing unit may perform portions of the calculations necessary for subsequent programming, as in the embodiments discussed later.

[0057] According to the present solution, both synaptic weights and neuron states (e.g., membrane potentials) can be represented by electronic devices at the junction (e.g., memristive devices). However, this approach is compatible with different electronic devices (e.g., flash memory cells, memristive devices, SRAM devices, etc.). The present solution makes it possible to calculate neuron states in constant time without the need for additional circuitry, in particular without any conversion in the digital domain. Since the analog circuits used allow the calculation of neuron states in the analog domain, the proposed solution can, in principle, be more time-efficient than previous neuromorphic devices.

[0058] For example, neuron outputs can be generated directly from multiply-accumulate operations performed with a crossbar array, for example using comparator circuits. There is no need to convert the signal in the digital domain (so no ADC is needed in the crossbar structure in this case) and store it in memory (i.e., no SRAM is needed for this purpose).

[0059] As in the preferred embodiment involving SNN implementations, again in the analog domain, simple activation functions can be implemented, e.g., based on comparison with one or more threshold values. The output spikes can be computed analogously, and then, using the usual core-to-core infrastructure, transmitted to another like device 10-12 as binary signals. Incidentally, the present approach is compatible with the standard address event representation (AER) protocol for core-to-core communication.

[0060] All of this will now be described in detail with reference to specific embodiments of the invention. First, each of the electronic devices of the neuromorphic devices 10-12 can comprise a memristive device, as previously alluded to. Any type of memristive device can be envisaged, such as a phase change memory cell, a resistive random access memory (RRAM), an SRAM, or an electrochemical random access memory (ECRAM). In a variant, reliance can be placed on a flash memory cell.

[0061] In a typical embodiment, the analog circuitry 140-170 of the neuromorphic devices 10-12 is further configured to update S116, S118 the neuron states stored on at least a subset of the N2xM second devices 132. More precisely, in operation, such neuron states are updated by reprogramming S116, S118 the second devices of the subset in accordance with the M output signals previously read out by the analog circuitry. Note that the update operation will typically be iterative, i.e., the neuron states can be updated at each operation cycle.

[0062] The neuron states will include values computed as the result of a multiply-accumulate operation, which can be used for usual ANN applications. However, in a variant, for SNN applications, the neuron states can include membrane potential values, as now described with reference to Figures 3A to 3B and Figures 4 and 5 That is, in an embodiment, the second input lines include a given control line 112, which is connected to the M output lines 120 via M given electronic devices 132. The given electronic devices 132 can be programmed by the analog circuitry 140-170 so that they store M initial membrane potential values, as now described with reference to Figures 3A to 3B and Figures 4 and 5As assumed in . Therefore, in this case, the neuron state captured by the device 132 includes the minimum value, the membrane potential value. In addition, the analog circuits 140 to 170 can also be configured to couple S122 a given control signal to the given control line 112 so that the M output signals read out S140 represent M final membrane potential values. Note that, in contrast to the "initial" value captured by the device 132, the latter can be regarded as the "final" membrane potential value. More precisely, the final membrane potential value is obtained based on the M initial membrane potential values ​​as a leaky integrator of the synaptic input, which in operation is itself obtained by coupling S121 the N1 input signals to the N1 first input lines 111.

[0063] In this regard, and as Figures 3A to 3B and Figures 4 and 5 As further seen in FIG, in operation, the control signal coupled to the control line 112 preferably represents the attenuation parameter α. Simultaneously, the analog circuits 140 to 170 may also be configured to adjust S120 the N1 input signals so that they represent complementary scaled (i.e., 1-α) synaptic input values. Thus, the evolution of the membrane potential may be written as:

[0064] V j (t+δt)=αV j (t)+∑ i W ji [(1-α)x i (td ji )]

[0065] where d ji is the synaptic delay, which is typically fixed (but in principle this parameter could be trained). In a variant, the scaled weights may be stored on the electronic device.

[0066] Note that more than one such line 112 can be used to store the membrane potential. That is, the membrane potential V of a given neuron may be stored in several devices 132 in the same column. For example, n lines 112 (n>1) can be used together with n×M electronic devices 132 to store a fraction of the membrane potential. For a given neuron, this fraction can simply be equal to V / n. If desired, adopting a configuration with multiple control lines 112 enhances the accuracy of the membrane potential representation. However, in the following, for simplicity, it is assumed that only one control line 112 is used to store the membrane potential.

[0067] Then, preferably, the analog circuit 140 to 170 is also configured to update S116 the membrane potential values stored on the M given electronic devices 132. This is implemented in operation by reprogramming S116 the M given electronic devices 132 according to the M output signals representative of the M final membrane potential values previously read out S140 by the analog circuit. Again, the membrane potential values can be iteratively updated (by which the values are changed at each cycle). That is, the corresponding elements can be programmed to store different values, updated at each cycle according to the output signals read during the preceding cycle. In Figures 3A to 3B and Figures 4 and 5 This operation is symbolically described in Figures 3A to 3B which shows the circuit components 140 adapted to perform the readout S140, based on which new membrane potential values are updated S116 in the devices 132 (see the corresponding back loop routing arrows in

[0068] However, the iterative update as described above should not be confused with the scheme of iterative programming, in which, for example, a plurality of pulses is used to program a single PCM cell in an iterative manner. In the present case, the iterative steps of programming the cell are not necessary. It is also possible to program the cell with a pulse only, which can represent a coarser update step. Moreover, here, the updated membrane potential can be computed in constant time (meaning that all output results are obtained at each operation cycle). However, the update will have a linear complexity.

[0069] Interestingly, the comparison of the membrane potential values with the threshold values can also be performed analogously in order to speed up the computation. That is, in an embodiment, the analog circuit 140 to 170 is also configured to perform S160, S165, for each of the M output lines 120, a comparison between each of the M output signals read out and a threshold value θ. Note that this threshold value can be a single constant threshold value. In a variant, the device can be designed to allow comparison with several (different) threshold values, which are different from one output line 120 to another. In a further variant, the threshold value can be changed throughout the operation cycle.

[0070] The comparison can be performed analogously, for example, with the help of a comparator, as assumed in Figure 3B This example shows the layout of the circuit components 160, which makes it possible to compare the membrane potential values with a threshold value θ (which can be different across the output lines 120) analogously. Moreover, the circuit components 160 compare the result of the difference V - θ with zero and the output is fed to further circuit components 170.

[0071] The circuit components 170 also form part of the analog circuit 140-170. Assuming the above conditions are met, these components 170 make it possible to generate a signal S170 for each of the M output lines 120. The generated signal can be seen as a spike. Also, the corresponding signal can be represented by an analog signal or a binary signal. Such a signal is generated based on the result of a comparison between the membrane potential value and the corresponding threshold value. Note, however, that in practice it can also be necessary to compare the signal corresponding to the difference V-0 with a signal corresponding to zero in order to determine whether the measured potential has indeed exceeded its respective threshold value. That is, in the example of Figures 3A to 3B and Figures 4 and 5 an additional comparison with zero can be performed, e.g. using an analog comparator, in order to decide whether to generate the final spike output z j . In other words, if the membrane potential crosses the threshold value, a spike signal z j is obtained, which spike signal z j may then be propagated to one or more subsequent neurons.

[0072] Furthermore, the circuit components 160 are operatively connected to the programming circuit in order for the programming circuit to reset S114 the value stored on any of the M given electronic devices 132. That is, if a neuron emits a spike, the corresponding membrane potential needs to be reset.

[0073] In a variant of Figure 3B the functionality related to the comparison (with the threshold value and then with the zero value) can be integrated in the crossbar array structure, as now discussed with reference to Figure 4 . Such an approach makes it possible to exploit the crossbar array structure, resulting in a more integrated solution (only one additional control line is needed to achieve this, but possibly additional control lines).

[0074] So far, the neuron state captured by the electronic devices 132 shown in Figure 3B only includes the membrane potential. As will now be seen, the threshold value can also be captured by additional electronic devices 132a, as in the embodiment of Figure 4 . In this example, the second electronic devices 132, 132a of the neuromorphic device 11 include M additional electronic devices 132a. Furthermore, the second input lines 112, 112a include an additional control line 112a, which is connected to the output lines 120 via the M additional electronic devices 132a. The devices 132a can be programmed by the analog circuit 140-170 to store the M threshold values. In this way, as discussed below, if a suitably selected control signal is coupled S122 into the control line 112a, the M output signals S142 as finally read out can represent the M difference values of the M final membrane potential values and the M threshold values as stored on the devices 132a (again by means of a multiplication-accumulation operation).

[0075] Note that, at least in simple implementations, the threshold value captured by the electronic device 132a typically does not depend on the output signal. However, since the device 132a can be programmed by the analog circuit, in more complex variants, the value captured by the device 132a can well depend on the output signal. Also, more than one control line 112a can be relied on, if needed.

[0076] In more detail, the analog circuit 140 to 170 can be configured to select a control signal to be coupled to the control line 112a, which control signal represents either the input value of 0 or the input value of -1, as assumed in the example of Figure 4 When the coupled signal corresponds to the input value of 0, the M output signals of the final read-out S140 represent the unique membrane potential value. However, when the coupled signal corresponds to the input value of -1, the M output signals now represent the difference V - Θ, i.e. the difference of the M final membrane potential value and the M threshold value. Thus, a properly selected signal allows to read either the membrane potential value (as required by the update device 132) or the difference between such membrane potential value and the threshold value (as required for determining whether to “fire” or not). Thus, two read-outs are required in this case.

[0077] As now referring to Figure 5 discussed, for example, in order to account for the adaptive firing threshold, it can be possible to include an additional control line. That is, in embodiments, the input (control) lines of the neuromorphic device 12 now include three types of control lines 112, 112b, 112c. That is, they particularly include the control lines 112 for storing the membrane potential value, as previously described with respect to Figures 3A to 3B and 4. In addition, now two additional control lines 112b, 112c are included, which are connected to the output lines 120 via 2 x M additional electronic devices 132b, 132c. In that case, the analog circuit 140 to 170 can be further designed to program the 2 x M devices 132b, 132c for their storing the adaptive firing threshold’s operand. This makes it possible to implement an advanced spiking neuron model with a varying firing threshold (as opposed to a fixed threshold), as exemplified below.

[0078] Note that, instead of three control lines 112, 112b, 112c, three groups of control lines can be involved, since each of the neuromorphic state features (membrane potential and adaptive threshold operand) can be captured by more than one line in the crossbar array.

[0079] Similarly to the optional signal in the control line 112a coupled to Figure 4 the device, Figure 5The analog circuits 140 to 170 can now be used to couple two additional control signals into the control lines 112 b, 112 c and select each of the two additional control signals S121 b, S121 c to obtain a difference signal. That is, for appropriately selected control signals, the output signal ultimately read out by the circuit can represent M differences between the M final membrane potential values ​​and the M adaptive firing thresholds.

[0080] Additionally, some of the operands may need to be updated (e.g., at each operation cycle iteration), which may be accomplished by reprogramming the device 132c based on previously obtained (e.g., during a previous iteration) output values, such as Figure 5 As shown. That is, analog circuits 140 to 170 can be used to reprogram S118 M of the 2×M additional devices, namely, the devices connected to control line 112 c. This is done so that the operands stored therein are updated (e.g., iteratively) based on previously obtained output values. Note that in that case, only electronic device 132 c needs to be programmed, while electronic devices 132 b remain fixed (at least during a single operation), wherein they behave like electronic device 132 a.

[0081] Note that the implementation of adaptive threshold is similar to Figure 4 The implementation of the threshold is very similar. The threshold value is recorded as B j (t). This quantity can be written as:

[0082] B j (t) = b j 0 +βb j (t), where

[0083] b j (t+δt)=ρ j b j (t)+(1-ρ j )z j (t).

[0084] In the above equation, b j 0 and b j (t) are operands captured by devices 132b and 132c of the j-th output line, respectively, where b j 0 is fixed, with b j (t) On the contrary, b j (t) needs to be updated in each cycle. B j The evolution of (t) is thus determined by two parameters β and ρ j Determine, where the first parameter is constant and the second parameter may be different for each column. Therefore, in order to calculate B according to the above equationj (t), it is sufficient to select the signals coupled to the control lines 112b, 112c such that the signals coupled to the lines 112b and 112c represent {0, 0}, {-1, -β} or {0, β}, as Figure 5 Several readouts are performed while the control signals are appropriately selected, allowing to successively read out and compute all components, i.e., V j (t), B j (t), z j (t), and then b j (t). In this case, the computation of all neuron states (membrane potential and adaptive threshold) involved can still be performed in constant time.

[0085] As mentioned above, the analog circuits 140 to 170 have different functions, which can be provided by different circuit components. In particular, the circuit can comprise a programming circuit and a readout circuit 140, the latter being connected to the former. The readout circuit is configured to read out the M output signals, while the programming circuit is configured to program Figures 3A to 3B and Figures 4 and 5 the electronic devices 132, 132a to 132c (e.g., iteratively), wherein some of these devices can be reprogrammed based on the output signals as previously read out by the readout circuit, as discussed above.

[0086] Such circuit components are known per se in crossbar array structures. A first difference with respect to prior art circuits is that, in the current case, the analog circuits 140 to 170 extend to additional input lines for storing neuron states, i.e., the control lines 112, 112a to 112c. The multiply-accumulate operations remain unchanged, except that they now include the additional row lines, all other things being equal. Thereby, the readout circuit component is still essentially similar to the readout circuit used in the previous crossbar array structure. However, another difference is that here several readout operations (e.g., 1, 2 or 3 in the example of Figures 3A to 3B and Figures 4 and 5 are required in order to obtain all quantities of interest. The computational cost of the additional operations required to obtain such quantities is still advantageous, since such operations are performed analogically, i.e., without any conversion to the digital domain. That is, once the operations have been performed analogically, they do not need to be converted and then not performed digitally, thereby benefiting in terms of computational speed.

[0087] Note that the programming circuitry can for example only correspond to the input circuitry, which is designed to couple signals into the input lines and to select the signals to be coupled into such input lines. However, some programming logic can be outsourced to digital circuitry connected to the analog circuitry in order to properly program the electronic device. This logic can thus rely on complex algorithms, which is something that is more difficult to implement based on pure analog circuitry. Nonetheless, an analog front-end is needed to select the signals and to couple such signals in the control lines, so that in that case the "actual" programming is still performed by the analog circuitry.

[0088] However, in a variant, the analog circuitry 140 to 170 can comprise three functionally distinct circuits (although they are partly connected), namely an input circuitry, a programming circuitry and a readout circuitry, in order to respectively select and couple the appropriate input signals, program the electronic device and readout the output signals, without involving any digital processing at all. At least two of the above three functions are preferably performed by analogy, while the third function (programming) can be partly offloaded to a digital processing unit. However, in other variants, all readouts can be converted into the digital domain and further processed digitally. In particular, the comparison with the threshold can be made using digital logic, as previously explained.

[0089] Reference is made to Figure 2 Another aspect of the application is now described, which relates to a system of neurons 1. The system 1 comprises L neuromorphic devices 10 (such as previously seen in Figures 3A to 3B and Figures 4 and 5 described) and a communication bus. In general, the system 1 is configured to forward S180 the output signal read out at a given neuromorphic device 10 to the next neuromorphic device of the L neuromorphic devices via the communication bus, thus being in the cycle shown in Figure 2 The communication bus will typically comprise an analog-to-digital (ADC) converter and a digital-to-analog (DAC) converter in order to transfer digitized versions of the signals from one neuromorphic device to another. This way, a neural network of several layers can be formed, with the benefits of a single analog layer as previously described.

[0090] Also as previously explained, the device 10 allows the programming S110 to S120, the electronic device, the multiply-accumulate operation S140, the update S116, the comparison S160, and the spike computation S180 to all be performed in the analog domain, subject to the earlier comments regarding the programming, which can be partly offloaded to a digital processing unit. The output signal is forwarded S180 to a core-to-core communication bus, which can optionally comprise some digital processing logic for updating the weights and the states, as previously described. A new input signal is thus obtained and received S190 at the neuron of the (another) device 10 embodying another layer, and so on.

[0091] Reference is next made to Figure 6 The final aspect of the application, in the flowchart of Figure 1 1, relates to a method of operating a neuromorphic device 10 to 12 (or system 1 ) as described above. Essential aspects of the method have been described already with reference to the device and system. The method is therefore only briefly described hereafter.

[0092] In essence, the method relies on an S100 such as the neuromorphic device 10 to 12 described herein, i.e. having an analog circuit 140 to 170 and a crossbar array structure 1 10. The analog circuit 140 to 170 is used to program S1 10 the electronic devices 131, 132, so that the first devices 131 store synaptic weights, and the second devices 132 store neuron states of an ANN layer implemented by the devices. Further, the analog circuit 140 to 170 reads out S140 M output signals obtained from the M output lines 120. As described above, this is done in accordance with a multiply-accumulate operation based on N1 input signals coupled into the first input line 1 1 1, N2 control signals coupled into the second input line 1 12, and values stored on each of the first devices 131 and the second devices 132. This can result in updating (e.g. iteratively) S1 16 neuron states stored on at least a subset of the N2 x M second devices 132 by reprogramming said subset of the N2 x M second devices 132 in accordance with the M output signals previously read out with the analog circuit 140 to 170 (e.g. during a previous iteration).

[0093] For example, Figure 6 The flowchart of Figure 1 1 illustrates the following operations performed at the level of a neuromorphic device 10 embodying a single layer of an ANN, which can be considered as an analog core computing device. First, the memristive devices 131, 132 of the neuromorphic device are programmed S1 1 1, S1 12 via input or programming circuit components of the analog circuit. The memristive devices comprise devices for storing neuron states. Signals, including control signals, are subsequently coupled S120 into input lines of the neuromorphic device. This includes coupling S121 input signals (e.g. determined based on spike signals from a lower layer, as received in step S190) into the input lines, and selecting and coupling S122 control signals into control lines. A multiply-accumulate operation is then performed at step S140 to obtain membrane potential values, which can be compared S160 analogously to a threshold value. Next, if the threshold value is exceeded S171, a spike signal is generated S172 at step S172, which is then forwarded S180 to a core-to-core communication infrastructure, which can relay (and possibly further process) such signals to a lower core 10, etc.

[0094] The proposed approach significantly allows for implementing a spiking neural network with multiple neurons and with layers of memristive crossbar structures. The approach provides acceleration over conventional computing paradigms and also enables advanced neural models. In particularly advantageous embodiments, the synaptic weights and neuron states are represented by phase change memory devices 132, 132a-c, thus allowing for potential acceleration compared to conventional devices. For example, a mixed-precision training scheme for ANNs can be employed, which is compatible with the analog cores described herein.

[0095] While the application has been described with reference to a limited number of embodiments, variations and alternatives, it will be appreciated that many modifications can be made within the scope of the application without departing from the spirit thereof. In particular, features recited in the description of a given embodiment, variant or in the drawings can be combined or replaced with features recited in another embodiment, variant or drawing without departing from the scope of the application. Thus, various combinations of features described with respect to any of the above-described embodiments or variants are envisaged, which combinations remain within the scope of the appended claims. Furthermore, many modifications can be made to adapt a particular situation or material to the teachings of the application without departing from the scope thereof. Therefore, the application is not intended to be limited to the particular embodiments disclosed but it is intended to cover all embodiments falling within the scope of the appended claims. Furthermore, many other variations than those mentioned above will be apparent to those skilled in the art in the light of the overall disclosure, and therefore, the application is not intended to be limited to the disclosed variations but is intended to cover all variations falling within the scope of the appended claims.

Claims

1. A neuromorphic device comprising: a crossbar array structure comprising N input lines and M output lines interconnected at junctions via N x M electronic devices, wherein the input lines comprise N1 first input lines and N2 second input lines connected to the M output lines via N1 x M first devices of the electronic devices and N2 x M second devices of the electronic devices, respectively, wherein N1 > 1, N2 > 1, N1 + N2 = N, and M > 1, wherein the N1 x M first devices are operable for storing synaptic weight values and the N2 x M second devices are operable for storing neuron state values, and wherein the N2 second input lines comprise a given control line connected to the output lines via M given electronic devices, wherein the M given electronic devices are programmable by the analog circuit to store M initial membrane potential values; and an analog circuit configured to: store the synaptic weight values on the first devices and the neuron state values on the second devices; implement neuron states as synapses in the same memristive crossbar array; in operation, read out M output signals obtained from the M output lines, respectively, as a result of a multiply-accumulate operation based on N1 input signals coupled to the N1 first input lines, N2 control signals coupled to the N2 second input lines, and values stored on each of the first and second devices; the read out M output signals representing M final membrane potential values obtained based on the M initial membrane potential values as a leaky integrator of synaptic inputs obtained in operation by coupling the N1 input signals to the N1 first input lines; and in operation, update the membrane potential values stored on the M given electronic devices by reprogramming such devices according to M output signals representing M final membrane potential values previously read out by the analog circuit.

2. The neuromorphic device of claim 1, wherein the analog circuit is further configured to update neuron states stored on at least some of the N2 x M second devices by reprogramming the at least some of the N2 x M second devices according to M output signals previously read out in operation by the analog circuit.

3. The neuromorphic device of claim 1, wherein: the analog circuit is further configured to couple the N1 input signals and the N2 control signals into the N1 first input lines and the N2 second input lines, respectively.

4. The neuromorphic device of claim 1, wherein the analog circuit is further configured to perform, for each of the M output lines, a comparison between each of the read out M output signals and a threshold value θ.

5. The neuromorphic device of claim 4, wherein ​ The analog circuit is further configured to generate a signal for each of the M output lines based on a result of the comparison, and is further configured to reset a value stored on any of the M given electronic devices.

6. The neuromorphic device of claim 4, wherein: The second electronic device comprises M additional electronic devices, and the second input line comprises additional control lines connected to the output lines via the M additional electronic devices, wherein the M additional electronic devices are programmable by the analog circuit to store M threshold values, so that the M output signals read out by the circuit represent M differences between the M final membrane potential values and the M threshold values coupled in operation to an appropriate selection of the additional control signals in the additional control lines.

7. The neuromorphic device of claim 6, wherein The analog circuit is configured to select the additional control signals to be coupled to the additional control lines for the additional control signals to represent either: an input value of 0, whereby the M output signals read out by the circuit represent the M final membrane potential values; or an input value of -1; whereby the M output signals read out by the circuit represent differences between the M final membrane potential values and the M threshold values.

8. The neuromorphic device of claim 1, wherein The given control signal coupled in operation to the given control line represents a decay parameter a, and The analog circuit is further configured to adjust the N1 input signals so that they represent synaptic input values scaled complementarily by 1 - a.

9. The neuromorphic device of claim 1, wherein: The second input line comprises three control lines, including the given control line, whereby the three control lines comprise two additional control lines in addition to the given control line, The two additional control lines are connected to the output lines via 2 x M additional electronic devices of the electronic device, and The analog circuit is further configured to program the 2 x M additional electronic devices so that they store operands of adaptive firing thresholds.

10. The neuromorphic device of claim 9, wherein: The analog circuit is further configured to couple two additional control signals to the two additional control lines and is further configured to select each of the two additional control signals so that the output signals read out by the circuit represent M differences between M final membrane potential values and M adaptive firing thresholds.

11. The neuromorphic device of claim 10, wherein The analog circuit is further configured to reprogram, in operation, M of the 2 x M additional electronic devices connected to one of the two additional control lines so that operands stored thereon are updated according to output values previously read out by the analog circuit.

12. The neuromorphic device of claim 1, wherein The analog circuit is further configured to reprogram the N1 x M first devices so that synaptic weights stored thereon are changed according to an automatic learning process.

13. The neuromorphic device of claim 1, wherein The analog circuit comprises a programming circuit and a readout circuit, the readout circuit being connected to the programming circuit, wherein the readout circuit is configured to read out the M output signals and the programming circuit is configured to program the electronic devices in dependence on output signals previously read out by the readout circuit.

14. The neuromorphic device of claim 13, wherein The programming circuit comprises an input circuit configured to, on the one hand, couple signals into the input lines and, on the other hand, select signals to be coupled into the input lines so as to program the electronic devices in operation based on the signals coupled into the input lines.

15. The neuromorphic device of claim 1, wherein Each of the electronic devices comprises a memristive device.

16. A neuromorphic system comprising: L neuromorphic devices each being a neuromorphic device according to claim 1, and a communication bus, wherein the system is configured to forward output signals read out at a given one of the L neuromorphic devices to a next one of the L neuromorphic devices via the communication bus.

17. A method of operating a neuromorphic device, the method comprising: providing a neuromorphic device having an analog circuit and a crossbar structure, the crossbar structure comprising N input lines and M output lines interconnected at synapses via N x M electronic devices, wherein the input lines comprise N1 first input lines and N2 second input lines, the N1 first input lines and the N2 second input lines being connected to the M output lines via N1 x M first devices of the electronic devices and N2 x M second devices of the electronic devices, respectively, wherein N1 > 1, N2 > 1, N1 + N2 = N, and M > 1, wherein the N1 x M first devices are operable for storing synaptic weight values and the N2 x M second devices are operable for storing neuron state values, and wherein the N2 second input lines comprise a given control line connected to the output lines via M given electronic devices, wherein the M given electronic devices are programmable by the analog circuit to store M initial membrane potential values; and storing the synaptic weight values on the first devices and the neuron state values on the second devices via the analog circuit; implementing neuron states as synapses in the same memristive crossbar; reading out M output signals obtained from the M output lines, respectively, as a multiplication-accumulation operation based on N1 input signals coupled into the N1 first input lines, N2 control signals coupled into the N2 second input lines, and values stored on each of the first devices and the second devices; the M output signals read out representing M final membrane potential values obtained based on the M initial membrane potential values as leaky integrators of synaptic inputs obtained in operation by coupling the N1 input signals into the N1 first input lines; and ​ ​ In operation, the membrane potential values stored on the M given electronic devices are updated by reprogramming such devices according to M output signals representative of M final membrane potential values previously read out by the analog circuit.

18. The method of claim 17, wherein the method further comprises: updating the neuron states stored on at least some of the N2 x M second devices by reprogramming the at least some of the N2 x M second devices according to M output signals previously read out by the analog circuit.

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