Neuromorphic computing chip based on single-transistor synaptic array

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor) transistors, and discloses a neural morphology computing chip based on a single transistor synapse array, which sequentially comprises a carbon nano transistor, a vertical interconnection layer and a floating gate transistor from top to bottom, a dielectric layer is filled between the carbon nano transistor and the vertical interconnection layer, and a dielectric layer is filled between the vertical interconnection layer and the floating gate transistor. The interior of the carbon nano transistor sequentially comprises a gate electrode layer, a gate dielectric layer and a carbon nano tube layer from top to bottom. According to the neuromorphic computing chip based on the single-transistor synaptic array, the carbon nano-transistors and the floating gate transistors are integrated in a three-dimensional stacked structure, so that integration of sensing, storage and computing functions is realized, and photoelectric response characteristics of the carbon nano-tubes are used as input trigger signals; and the nonvolatile modulation of the synaptic weight is realized through a floating gate layer charge storage mechanism, so that the integration density and the energy efficiency ratio of the synaptic unit are remarkably improved, and a feasible technical path is provided for realizing large-scale neural network hardware.

Description

Technical Field

[0001] This invention relates to the field of MOS transistor technology, and more particularly to a neuromorphic computing chip based on a single-transistor synaptic array. Background Technology

[0002] Current neuromorphic hardware is mainly based on two-terminal memristors (such as 1T1R structures) or traditional CMOS synaptic circuits. The former is difficult to implement signal routing and weight storage functions simultaneously due to the limitations of the device structure, and there is an inherent contradiction between read / write speed and durability. The latter has a large chip area and high static power consumption due to the complex unit structure, which seriously restricts the integration of large-scale parallel neural networks. Although three-dimensional integration technology provides a new path for high-density synaptic arrays, existing solutions are still limited by the single function of the device and insufficient system flexibility, making it difficult to meet the hardware requirements of emerging computing paradigms such as spiking neural networks for dynamic connectivity and efficient simulation.

[0003] Existing patents disclose broadband photoelectric synaptic transistors based on single-photosensitive layer materials, their fabrication methods, and applications (Publication No. CN118019358A). The organic polymer photosensitive material used in this patent has shortcomings in terms of long-term device stability and durability. Its planar device structure limits the integration density of the synaptic array, and its function mainly relies on a single light input mode, lacking flexible electrical control capabilities. This leads to performance and integration bottlenecks when realizing high-density, multimodal neuromorphic computing applications. Summary of the Invention

[0004] This invention provides a neuromorphic computing chip based on a single-transistor synaptic array to solve existing technical problems, thereby addressing the limitations of existing solutions in terms of single device function and insufficient system flexibility.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a neuromorphic computing chip based on a single-transistor synaptic array, comprising, from top to bottom, carbon nanotube transistors, a vertical interconnect layer, and a floating gate transistor, wherein a dielectric layer is filled between the carbon nanotube transistors and the vertical interconnect layer, and between the vertical interconnect layer and the floating gate transistor. The interior of the carbon nanotube transistor comprises, from top to bottom, a gate electrode layer, a gate dielectric layer, and a carbon nanotube layer. A drain electrode is provided in the drain region below the carbon nanotube layer, and a source electrode is provided in the source region below the carbon nanotube layer. The vertical interconnect layer includes source channel layer 2, drain metal layer 1, source metal layer 1, gate metal layer 1, gate channel layer 1, source channel layer 1, and drain channel layer 1. The floating gate transistor comprises, from bottom to top, a substrate layer, a P-well layer, a tunnel oxide layer, a floating gate layer, an oxide layer, and a control gate; wherein the top left and right sides of the P-well layer are respectively formed by ion implantation to form a doped drain region and a doped source region. The doped source region is ohmically connected to the drain electrode via source channel layer one, source metal layer one, and source channel layer two in sequence. The control gate is ohmically connected to the gate metal layer through the gate channel layer; the doped drain region is ohmically connected to the drain metal layer through the drain channel layer.

[0006] Furthermore, the gate electrode layer is made of Al material; the gate dielectric layer is made of HfO material; and the doped source region and doped drain region are both N-type semiconductors.

[0007] Furthermore, the source electrode is used to connect to an external source voltage, the gate metal layer is used to connect to an external gate control voltage, the drain metal layer is used to connect to an external sampling terminal, and the substrate layer is used to connect to an external substrate voltage.

[0008] Furthermore, a doped P-well is formed inside the P-well layer and below the doped source region and doped drain region by ion implantation, and the bottom end of the doped P-well is in direct contact with the substrate layer.

[0009] Furthermore, the interior of the P-well layer, directly below the doped source and doped drain regions, is covered with P-wells through ion implantation.

[0010] Furthermore, the top of the covered P-well is in direct contact with the doped source region or the doped drain region, while the bottom of the covered P-well is not in contact with the doped P-well.

[0011] Furthermore, within the P-well layer and below the doped source and doped drain regions, several independent P-wells are formed by ion implantation, with the bottom of each independent P-well in direct contact with the substrate layer.

[0012] Furthermore, the interior of the independent P-well is formed with several independent doped N-particles through ion implantation, and the bottom of the doped N-particles is in direct contact with the substrate layer.

[0013] The neuromorphic computing chip based on a single-transistor synaptic array provided by this invention achieves the following advantages compared to existing technologies: 1. The present invention is a neuromorphic computing chip based on a single transistor synaptic array. By integrating carbon nanotube transistors and floating gate transistors in a three-dimensional stacked structure, it realizes the integration of sensing, storage and computing functions. It utilizes the photoelectric response characteristics of carbon nanotubes as input trigger signals and realizes non-volatile modulation of synaptic weights through the charge storage mechanism of the floating gate layer, thereby significantly improving the integration density and energy efficiency of synaptic units, and providing a feasible technical path for the hardware implementation of large-scale neural networks.

[0014] 2. This invention uses high-k dielectric material HfO2 as the gate dielectric layer and combines it with the excellent electrical characteristics of carbon nanotube channels. While ensuring device reliability, it achieves precise control and rapid update of multi-level weights, effectively improving the processing accuracy and response speed of neuromorphic computing. It is suitable for high-frequency, low-power edge intelligent computing scenarios.

[0015] 3. By introducing a composite well region structure consisting of a doped P-well and a covered P-well, this invention optimizes the potential distribution and carrier transport path of the floating gate transistor, significantly suppresses short-channel effects and leakage current, and enhances the stability and durability of the synaptic unit under continuous operation, enabling it to meet the needs of dynamic connection reconstruction in spiking neural networks.

[0016] 4. This invention employs a localized doping technique using independent P-wells and doped N-particles to achieve high electrical isolation between synaptic units and precise control of threshold voltage. This not only reduces crosstalk and static power consumption between units but also improves the scalability and anti-interference capability of the overall array, providing a process foundation for high-density, high-reliability neuromorphic chip integration.

[0017] 5. The present invention fully considers compatibility with existing CMOS processes in terms of structural design and process implementation. Through three-dimensional heterogeneous integration and low-temperature process steps, it achieves high integration and performance optimization of synaptic functions without significantly increasing manufacturing costs, and has good industrialization prospects and application expansion potential. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the floating gate transistor in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the floating gate transistor in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the floating gate transistor in Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of the floating gate transistor in Embodiment 5 of the present invention.

[0019] In the figure: 1. Carbon nanotube transistor; 2. Vertical interconnect layer; 3. Dielectric layer; 4. Floating gate transistor; 101. Gate electrode layer; 102. Gate dielectric layer; 103. Carbon nanotube layer; 104. Drain electrode; 105. Source electrode; 201. Source channel layer 2; 202. Drain metal layer 1; 203. Source metal layer 1; 204. Gate metal layer 1; 205. Gate channel layer 1; 206. Source channel layer 1; 207. Drain channel layer 1; 401. Substrate layer; 402. P-well layer; 403. Doped source region; 404. Doped drain region; 405. Control gate; 406. Oxide layer; 407. Floating gate layer; 408. Tunnel oxide layer; 409. Doped P-well; 410. Covered P-well; 411. Independent P-well; 412. Doped N particles. Detailed Implementation

[0020] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example 1

[0021] like Figure 1 As shown, according to one aspect of the present invention, a neuromorphic computing chip based on a single-transistor synaptic array is provided, comprising, from top to bottom, a carbon nanotube transistor 1, a vertical interconnect layer 2, and a floating gate transistor 4, wherein a dielectric layer 3 is filled between the carbon nanotube transistor 1 and the vertical interconnect layer 2, and between the vertical interconnect layer 2 and the floating gate transistor 4, characterized in that: the interior of the carbon nanotube transistor 1 comprises, from top to bottom, a gate electrode layer 101, a gate dielectric layer 102, and a carbon nanotube layer 103, a drain electrode 104 is provided in the drain region below the carbon nanotube layer 103, and a source electrode 105 is provided in the source region below the carbon nanotube layer 103; The vertical interconnect layer 2 includes a source channel layer 201, a drain metal layer 202, a source metal layer 203, a gate metal layer 204, a gate channel layer 205, a source channel layer 206, and a drain channel layer 207. The floating gate transistor 4 includes, from bottom to top, a substrate layer 401, a P-well layer 402, a tunnel oxide layer 408, a floating gate layer 407, an oxide layer 406, and a control gate 405; wherein, the top left and right sides of the P-well layer 402 are respectively formed by ion implantation to form a doped drain region 404 and a doped source region 403. Among them, the doped source region 403 is ohmically connected to the drain electrode 104 through the first source channel layer 206, the first source metal layer 203 and the second source channel layer 201 in sequence. The control gate 405 is ohmically connected to the gate metal layer 204 through the gate channel layer 205; the doped drain region 404 is ohmically connected to the drain metal layer 202 through the drain channel layer 207.

[0022] The gate electrode layer 101 is made of Al; the gate dielectric layer 102 is made of HfO2; the doped source region 403 and the doped drain region 404 are both N-type semiconductors. The source electrode 105 is used to connect to the external source voltage, the gate metal layer 204 is used to connect to the external gate control voltage, the drain metal layer 202 is used to connect to the external sampling terminal, and the substrate layer 401 is used to connect to the external substrate voltage.

[0023] The working principle of this device is as follows: like Figure 1 As shown, after the source voltage is applied to the source electrode 105, if the carbon nanotube transistor 1 is exposed to light, then the source electrode 105 and the drain electrode 104 will be in a conducting state (the light at this time is equivalent to the gate voltage in the MOS transistor, so the drain electrode and the source electrode will be conducting). After conduction, the charge will sequentially pass through the second source channel layer 201, the first source metal layer 203, and the first source channel layer 206 into the doped source region 403.

[0024] If no voltage is applied to the control gate 405, the charge in the doped source region 403 will not enter the doped drain region 404, and the drain metal layer 202 will output a low level (denoted as 0). If a high voltage (e.g., 20V) is applied to the control gate 405, a path is formed between the doped source region 403 and the doped drain region 404 (at which point the drain metal layer 202 outputs a high level, denoted as 1). Simultaneously, free electrons will also penetrate and be stored inside the floating gate layer 407 under the influence of a strong gate electric field (this will result in an increased threshold voltage of the control gate 405). If a normal voltage (e.g., 3V) is applied to the control gate 405 at this time, the drain metal layer 202 will output a low level (denoted as 0). Furthermore, when a normal voltage (e.g., 3V) is applied in the absence of light, the drain metal layer 202 will still output a low level (denoted as 0).

[0025] If it is necessary to clear the charge stored in the floating gate layer 407 so that the drain metal layer 202 will also output a high level when the floating gate transistor 4 is connected to a normal voltage, then it is only necessary to connect a high voltage (20V) to the drain metal layer 401, so that the charge stored in the floating gate layer 407 will be cleared.

[0026] This embodiment integrates carbon nanotube transistor 1 and floating gate transistor 4 in three dimensions through vertical interconnect layer 2. It utilizes the photosensitive properties of carbon nanotube layer 103 as input trigger and combines the charge storage of floating gate layer 407 to achieve weight memory. The principle is that when carbon nanotube transistor is turned on by light, charge is injected into floating gate layer through vertical interconnect path, thereby modulating the threshold voltage of floating gate transistor and realizing non-volatile programming of synaptic weights. The advantage is that it integrates sensing, storage and computing functions into a single device, which significantly improves synaptic density and energy efficiency and supports parallel processing of neuromorphic computing. Example 2

[0027] like Figure 1 , 2 As shown, according to one aspect of the present invention, a neuromorphic computing chip based on a single-transistor synaptic array is provided, comprising, from top to bottom, a carbon nanotube transistor 1, a vertical interconnect layer 2, and a floating gate transistor 4. A doped P-well 409 is formed by ion implantation inside the P-well layer 402 of the floating gate transistor 4 and below the doped source region 403 and the doped drain region 404. The bottom end of the doped P-well 409 is in direct contact with the substrate layer 401.

[0028] This embodiment introduces a doped P-well 409 into the P-well layer 402 of the floating gate transistor 4. The principle is to form a P-type region that is in direct contact with the substrate layer 401 through ion implantation, which optimizes the potential distribution of the well region and the carrier migration path, and enhances the device isolation. The advantage is that it effectively suppresses leakage current and crosstalk, improves the stability and reliability of the synaptic unit, and is suitable for high-precision weight updates. Example 3

[0029] like Figure 1 , 3 As shown, according to one aspect of the present invention, a neuromorphic computing chip based on a single-transistor synaptic array is provided, comprising, from top to bottom, a carbon nanotube transistor 1, a vertical interconnect layer 2, and a floating gate transistor 4. A doped P-well 409 is formed by ion implantation inside the P-well layer 402 of the floating gate transistor 4 and below the doped source region 403 and the doped drain region 404. The bottom end of the doped P-well 409 is in direct contact with the substrate layer 401.

[0030] Inside the P-well layer 402 and directly below the doped source region 403 and the doped drain region 404, a covering P-well 410 is formed by ion implantation. The top of the covering P-well 410 is in direct contact with the doped source region 403 or the doped drain region 404, while the bottom of the covering P-well 410 is not in contact with the doped P-well 409.

[0031] This embodiment adds a covered P-well 410 to the embodiment 2. The principle is to form a local P-well directly below the doped source region 403 and the doped drain region 404 by ion implantation. It is isolated from the doped P-well 409 but directly contacts the source and drain regions, realizing precise control of the channel region. The advantage is that it further reduces the short-channel effect and leakage current, improves the linearity and durability of weight modulation, and supports more efficient dynamic reconstruction of spiking neural networks. Example 4

[0032] like Figure 1 , 4As shown, according to one aspect of the present invention, a neuromorphic computing chip based on a single-transistor synaptic array is provided, comprising, from top to bottom, a carbon nanotube transistor 1, a vertical interconnect layer 2, and a floating gate transistor 4. The floating gate transistor 4 contains a plurality of independent P-wells 411 formed by ion implantation inside the P-well layer 402 and below the doped source region 403 and the doped drain region 404. The bottom ends of the independent P-wells 411 are in direct contact with the substrate layer 401.

[0033] This embodiment uses multiple independent P-wells 411 instead of a single doped P-well. The principle is to form an independent P-well array through ion implantation. Each P-well is in direct contact with the substrate layer 401, achieving electrical isolation between synaptic units. The advantages are enhanced array anti-interference capability and scalability, allowing for higher density synaptic integration, while reducing power consumption and heat accumulation. Example 5

[0034] like Figure 1 , 5 As shown, according to one aspect of the present invention, a neuromorphic computing chip based on a single-transistor synaptic array is provided, comprising, from top to bottom, a carbon nanotube transistor 1, a vertical interconnect layer 2, and a floating gate transistor 4. Within the floating gate transistor 4, a plurality of independent P-wells 411 are formed by ion implantation inside the P-well layer 402 and below the doped source region 403 and the doped drain region 404. The bottom ends of the independent P-wells 411 are in direct contact with the substrate layer 401. Within the independent P-wells 411, a plurality of independent doped N-particles 412 are formed by ion implantation, and the bottom ends of the doped N-particles 412 are in direct contact with the substrate layer 401.

[0035] This embodiment introduces doped N particles 412 inside the independent P-well 411. The principle is to form a dispersed N-type region through ion implantation, modulate the carrier concentration and electric field distribution in the well region, and optimize the threshold voltage control of the floating gate transistor. The advantages are that it improves the device's switching ratio and weight update speed, while improving the linearity and retention characteristics of synaptic weights, making it suitable for low-power applications such as edge computing.

[0036] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A neuromorphic computing chip based on a single-transistor synaptic array, comprising, from top to bottom, carbon nanotube transistors (1), a vertical interconnect layer (2), and a floating-gate transistor (4), wherein a dielectric layer (3) is filled between the carbon nanotube transistors (1) and the vertical interconnect layer (2), and between the vertical interconnect layer (2) and the floating-gate transistor (4), characterized in that: The interior of the carbon nanotube transistor (1) includes, from top to bottom, a gate electrode layer (101), a gate dielectric layer (102), and a carbon nanotube layer (103). A drain electrode (104) is provided in the drain region below the carbon nanotube layer (103), and a source electrode (105) is provided in the source region below the carbon nanotube layer (103). The vertical interconnect layer (2) includes source channel layer 2 (201), drain metal layer 1 (202), source metal layer 1 (203), gate metal layer 1 (204), gate channel layer 1 (205), source channel layer 1 (206) and drain channel layer 1 (207). The floating gate transistor (4) includes, from bottom to top, a substrate layer (401), a P-well layer (402), a tunnel oxide layer (408), a floating gate layer (407), an oxide layer (406), and a control gate (405); wherein the top left and right sides of the P-well layer (402) are respectively formed by ion implantation to form a doped drain region (404) and a doped source region (403). The doped source region (403) is ohmically connected to the drain electrode (104) through source channel layer one (206), source metal layer one (203) and source channel layer two (201); The control gate (405) is ohmically connected to the gate metal layer (204) through the gate channel layer (205); the doped drain region (404) is ohmically connected to the drain metal layer (202) through the drain channel layer (207).

2. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 1, characterized in that: The gate electrode layer (101) is made of Al material; the gate dielectric layer (102) is made of HfO2 material; the doped source region (403) and the doped drain region (404) are both N-type semiconductors.

3. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 1, characterized in that: The source electrode (105) is used to connect to an external source voltage, the first gate metal layer (204) is used to connect to an external gate control voltage, the first drain metal layer (202) is used to connect to an external sampling terminal, and the substrate layer (401) is used to connect to an external substrate voltage.

4. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 1, characterized in that: A doped P-well (409) is formed inside the P-well layer (402) and below the doped source region (403) and the doped drain region (404) by ion implantation. The bottom end of the doped P-well (409) is in direct contact with the substrate layer (401).

5. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 4, characterized in that: The P-well layer (402) is internally located and directly below the doped source region (403) and the doped drain region (404), and is covered by P-wells (410) formed by ion implantation.

6. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 5, characterized in that: The top of the covered P-well (410) is in direct contact with the doped source region (403) or the doped drain region (404), while the bottom of the covered P-well (410) is not in contact with the doped P-well (409).

7. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 1, characterized in that: Inside the P-well layer (402) and below the doped source region (403) and doped drain region (404), a number of independent P-wells (411) are formed by ion implantation. The bottom of the independent P-wells (411) is in direct contact with the substrate layer (401).

8. The neuromorphic computing chip based on a single-transistor synaptic array according to claim 7, characterized in that: The interior of the independent P-well (411) is formed with several independent doped N particles (412) through ion implantation, and the bottom of the doped N particles (412) is in direct contact with the substrate layer (401).

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