Sense amplifier circuit, memory, and method of operating the same

Abstract

A sense amplifier circuit, a memory, and related operation methods are provided. The sense amplifier circuit includes an amplifier circuit for amplifying a voltage signal and a compensation circuit coupled to the amplifier circuit. The amplifier circuit includes a first inverter amplifier and a second inverter amplifier that are cross-coupled to each other, the first inverter amplifier being connected to a first bit line and the second inverter amplifier being connected to a second bit line. The compensation circuit includes a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit, and is configured to generate a compensation voltage between the first bit line and the second bit line by operating the switch circuits to perform charge injection, so as to compensate for an input-related offset voltage of the amplifier circuit. The operation method takes into account the influence of charge propagation on the voltage on the bit line, and thus more accurately compensates for the input-related offset voltage.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor technology, and more particularly, to a sense amplifier circuit and an operation method thereof. Background Art

[0002] A sense amplifier circuit is a circuit in a semiconductor memory chip that amplifies a stored signal in a memory cell. When reading data from a memory cell, the sense amplifier circuit receives an input representing a data bit stored in the memory cell and amplifies the input to a voltage level sufficient to be recognized by an external device so that the data bit of the memory cell can be correctly read.

[0003] Modern memories are becoming increasingly miniaturized in terms of size and power consumption, and the amount of charge in a single memory cell can only generate a small-amplitude signal for representing the data in the memory cell. Therefore, a sense amplifier circuit capable of appropriately amplifying a small input signal is crucial in modern memories.

[0004] However, due to inevitable differences in circuit characteristics, there is an offset voltage in the sense amplifier circuit that may reduce the sensitivity of the sense amplifier circuit. Due to the offset voltage, the voltage difference between two bit lines of the sense amplifier circuit must be greater than a minimum voltage, called the minimum voltage margin, for the sense amplifier circuit to operate properly. In other words, a sense amplifier circuit with an offset voltage may require a larger input signal than the input signal required to generate a recognizable voltage level. In addition, the voltage pulling capabilities between the pull-up circuit and the pull-down circuit of the sense amplifier circuit may be different, which may also affect the performance of the sense amplifier circuit. Therefore, a sense amplifier circuit capable of compensating for the above-mentioned defects including the offset voltage is needed.

[0005] It should be noted that the above information disclosed in this background art section is only for facilitating the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those skilled in the art. Summary of the Invention

[0006] In view of the limitations of the above-mentioned prior art, the present disclosure provides a sense amplifier circuit, a memory, and related operation methods to solve the above limitations.

[0007] One aspect of the present invention relates to a sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit coupled to the amplification circuit.

[0008] The amplifier circuit may include a first inverting amplifier and a second inverting amplifier. The first inverting amplifier may be connected to a first bit line, and the second inverting amplifier may be connected to a second bit line. The amplifier circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line. The compensation circuit may be coupled to the amplifier circuit and configured to compensate for an input-related offset voltage of the amplifier circuit by injecting charge into at least one of the first bit line and the second bit line.

[0009] In some embodiments, in the above circuit, injecting charge into at least one of the first bit line and the second bit line may include: injecting a first charge generated by the first inverting amplifier into the second bit line; and / or injecting a second charge generated by the second inverting amplifier into the first bit line. After the distribution of the first charge and / or the second charge on the bit line is stable, the first charge and / or the second charge may generate a compensation voltage between the first bit line and the second bit line, and the compensation voltage may be substantially equal to the input-referred offset voltage of the amplifier circuit.

[0010] In some embodiments, in the above circuit, the compensation circuit may include one or more capacitive elements, and the one or more capacitive elements may include Ni capacitors or bit line parasitic capacitors.

[0011] In some embodiments, in the above circuit, the input terminal of the first inverting amplifier may be connected to the output terminal of the second inverting amplifier at a first node, and the input terminal of the second inverting amplifier may be connected to the output terminal of the first inverting amplifier at a second node. Both the first inverting amplifier and the second inverting amplifier may be connected to a voltage node and may also be connected to a ground node.

[0012] In some embodiments, in the above circuit, the compensation circuit may include a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. The first end of the first switch circuit may be connected to the first end of the second switch circuit at the first bit line, the first end of the third switch circuit may be connected to the first end of the fourth switch circuit at the second bit line, the second end of the first switch circuit may be connected to the second end of the fourth switch circuit at the first node, and the second end of the second switch circuit may be connected to the second end of the third switch circuit at the second node.

[0013] In some embodiments, in the above circuit, each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit may include an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate.

[0014] In some embodiments, the above circuit may further include a switch control circuit coupled to the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit. The switch control circuit may be configured to control the on-state of each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit.

[0015] In some embodiments, the above circuit may further include a transconductance compensation circuit coupled to the pull-up circuit and the pull-down circuit. The pull-up circuit may be coupled to a voltage node, and the pull-down circuit may be coupled to a ground node. The transconductance compensation circuit may include a temperature sensor for sensing temperature and may be configured to provide compensation currents to the pull-up circuit and the pull-down circuit respectively to compensate for the change in the transconductance of the sense amplifier circuit caused by temperature variations.

[0016] In some embodiments, in the above circuit, the first inverter amplifier may include a first transistor and a second transistor, and the second inverter amplifier may include a third transistor and a fourth transistor. The second terminal of the first transistor and the first terminal of the second transistor may be connected to a second node, and the gate terminals of the first transistor and the second transistor may be connected to a first node. The second terminal of the third transistor and the first terminal of the fourth transistor may be connected to the first node, and the gate terminals of the third transistor and the fourth transistor may be connected to the second node. The first terminal of the first transistor and the first terminal of the third transistor may be connected to a voltage node, and the second terminal of the second transistor and the second terminal of the fourth transistor may be connected to a ground node.

[0017] In some embodiments, in the above circuit, the compensation circuit may be configured to generate a compensation voltage between the first bit line and the second bit line by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to compensate for the input-related offset voltage of the amplifier circuit.

[0018] In some embodiments, generating a compensation voltage between the first bit line and the second bit line in the above circuit to compensate for the input-related offset voltage of the amplifier circuit may include: turning on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; disconnecting the second switch circuit and the fourth switch circuit during a compensation time to generate a compensation voltage between the first bit line and the second bit line; and disconnecting the first switch circuit and the third switch circuit.

[0019] Another aspect of the present invention relates to another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bit line and a second inverting amplifier connected to a second bit line. The amplification circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line. The compensation circuit may be coupled to the amplification circuit and configured to compensate for an input-related offset voltage of the amplification circuit. The compensation circuit may be configured to perform a charging operation to charge at least one of the first bit line and the second bit line. At the end of the charging operation, the voltage difference between the proximal ends of the first bit line and the second bit line may be greater than the input-related offset voltage of the amplification circuit.

[0020] In some embodiments, in the above circuit, at the end of the charging operation, the voltage difference between the proximal ends of the first bit line and the second bit line may be 10%-40% greater than the input-related offset voltage of the amplification circuit.

[0021] Another aspect of the present invention relates to another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bit line and a second inverting amplifier connected to a second bit line. The amplification circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line during a signal amplification phase. The compensation circuit may be coupled to the first bit line, the second bit line, and the amplification circuit, and may be configured to compensate for an input-related offset voltage of the amplification circuit during an offset compensation phase. During the signal amplification phase, at least one of the first bit line and the second bit line may be connected to one of the outputs of the first inverting amplifier and the second inverting amplifier through the compensation circuit, and during the offset compensation phase, at least one of the first bit line and the second bit line may be connected to the other of the outputs of the first inverting amplifier and the second inverting amplifier.

[0022] Another aspect of the present invention relates to another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bit line and a second inverting amplifier connected to a second bit line. The amplification circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line during a signal amplification phase. The compensation circuit may be coupled to the amplification circuit and may be configured to compensate for an input-related offset voltage of the amplification circuit during an offset compensation phase, and the gain of the sense amplifier circuit is greater than 1 during the offset compensation phase.

[0023] Another aspect of the present invention relates to another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bit line and a second inverting amplifier connected to a second bit line. The amplification circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line during a signal amplification phase. The compensation circuit may be coupled to the amplification circuit and may be configured to compensate for an input-referred offset voltage of the amplification circuit during an offset compensation phase. The first inverting amplifier and the second inverting amplifier may be cross-coupled during the offset compensation phase.

[0024] In some embodiments, in the above circuit, during the signal amplification phase, the output of the first inverting amplifier may be connected to the first bit line, and the output of the second inverting amplifier may be connected to the second bit line. During the offset compensation phase, the output of the first inverting amplifier may be connected to the second bit line, and the output of the second inverting amplifier may be connected to the first bit line.

[0025] Another aspect of the present invention relates to a memory. The memory may include a plurality of memory cells and a plurality of sense amplifier circuits. Each of the plurality of sense amplifier circuits may be the sense amplifier circuit of any of the above embodiments and may be connected to one of the plurality of memory cells.

[0026] In some embodiments, in each of the plurality of sense amplifier circuits in the above memory, charge injection into at least one of the first bit line and the second bit line may include: injecting a first charge generated by the first inverting amplifier into the second bit line, and / or injecting a second charge generated by the second inverting amplifier into the first bit line. After the distribution of the first charge and / or the second charge on the bit line is stable, the first charge and / or the second charge may generate a compensation voltage between the first bit line and the second bit line, and the compensation voltage is substantially equal to the input-referred offset voltage of the amplification circuit.

[0027] In some embodiments, in each of the plurality of sense amplifier circuits in the above memory, the compensation circuit may include a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. A first end of the first switch circuit may be connected to a first end of the second switch circuit at the first bit line, and a first end of the third switch circuit may be connected to a first end of the fourth switch circuit at the second bit line. A second end of the first switch circuit may be connected to a second end of the fourth switch circuit at the output of the second inverting amplifier, and a second end of the second switch circuit may be connected to a second end of the third switch circuit at the output of the first inverting amplifier.

[0028] In some embodiments, in the above-mentioned memory, each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit of each of the plurality of sense amplifier circuits may include an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a transmission gate.

[0029] In some embodiments, in the above-mentioned memory, in each of the plurality of sense amplifier circuits, a bias voltage is provided to at least one of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch to control the on-state of the corresponding switch circuit.

[0030] In some embodiments, in the above-mentioned memory, each memory cell may be connected to a corresponding sense amplifier circuit through an adjustable resistor. The memory may further include a virtual bit line coupled to at least one of the adjustable resistors and a resistance control circuit. The resistance control circuit may be configured to generate a resistance control signal, and the virtual bit line may be configured to transmit the resistance control signal to the at least one adjustable resistor to control the resistance of the at least one adjustable resistor.

[0031] In some embodiments, the above-mentioned memory may be connected to a reference resistor, and a resistance control signal may be generated based on the measured resistance of the reference resistor.

[0032] In some embodiments, in the above-mentioned memory, each memory cell may be connected to a corresponding sense amplifier circuit through an adjustable capacitor. The memory may further include a virtual bit line coupled to at least one of the adjustable capacitors and a capacitance control circuit. The capacitance control circuit may be configured to generate a capacitance control signal, and the virtual bit line may be configured to transmit the capacitance control signal to the at least one adjustable capacitor to control the capacitance of the at least one adjustable capacitor.

[0033] Another aspect of the present invention relates to an input-related offset voltage compensation method applicable to the sense amplifier circuit of any of the above embodiments. The method may include generating a compensation voltage between a first bit line and a second bit line by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to compensate for the input-related offset voltage of the amplifier circuit.

[0034] In some embodiments, in the above method, generating a compensation voltage between the first bit line and the second bit line to compensate for the input-related offset voltage of the amplifier circuit may include: turning on the first switch circuit, the second switch circuit, the third switch circuit, the switch circuit, and the fourth switch circuit; determining a compensation time; disconnecting the second switch circuit and the fourth switch circuit within the compensation time to generate a compensation voltage between the first bit line and the second bit line, and disconnecting the first switch circuit and the third switch circuit.

[0035] In some embodiments, in the above method, at the end of the compensation time, the voltage difference between the proximal ends of the first bit line and the second bit line may be greater than the input-referred offset voltage of the amplifier circuit.

[0036] In some embodiments, in the above method, at the end of the compensation time, the voltage difference between the proximal ends of the first bit line and the second bit line may be 10%-40% greater than the input-referred offset voltage of the amplifier circuit.

[0037] In some embodiments, in the above method, the gain of the sense amplifier circuit may be greater than 1 during compensation.

[0038] In some embodiments, in the above method, turning on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit may include: turning on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to converge the voltages of the first bit line, the second bit line, the output terminal of the first inverter amplifier, and the output terminal of the second inverter amplifier to a voltage level.

[0039] In some embodiments, the above method may further include: after generating a compensation voltage between the first bit line and the second bit line, providing an input signal between the first bit line and the second bit line, providing a pull-up voltage to the voltage node; providing a pull-down voltage to the ground node; and turning on the second switch circuit and the fourth switch circuit to amplify the input signal, while the first switch circuit and the third switch circuit remain off.

[0040] In some embodiments, the above method may further include: after turning on the second switch circuit and the fourth switch circuit to amplify the input signal, disconnecting the sense amplifier circuit from the first bit line and the second bit line by operating the second switch circuit and the fourth switch circuit; keeping the sense amplifier circuit disconnected from the first bit line and the second bit line for a predetermined period of time; reconnecting the sense amplifier circuit to the first bit line and the second bit line by operating the second switch circuit and the fourth switch circuit.

[0041] In some embodiments, in the above method, reconnecting the sense amplifier circuit to the first bit line and the second bit line may include reconnecting the sense amplifier circuit to the first bit line and the second bit line by setting each of the second switch circuit and the fourth switch circuit to a partially conductive state.

[0042] In some embodiments, the above method may further include performing a calibration process. The calibration process may include: selecting one or more candidate pull-up circuits from a plurality of candidate pull-up circuits to be coupled to the voltage node of the replica inverter amplifier, and selecting one or more candidate pull-down circuits from a plurality of candidate pull-down circuits to be coupled to the ground node of the replica inverter amplifier, to make the output voltage of the replica inverter amplifier close to the calibration voltage; adjusting the candidate pull-up voltage provided to the selected one or more candidate pull-up circuits, and adjusting the candidate pull-down voltage provided to the selected one or more candidate pull-down circuits to make the output voltage closer to the calibration voltage; storing the adjusted candidate pull-up voltage and the adjusted candidate pull-down voltage in a register.

[0043] In some embodiments, the replica inverter amplifier may be a replica circuit of the first inverter amplifier or the second inverter amplifier.

[0044] In some embodiments, performing the calibration process may include repeatedly performing the calibration process at a fixed time interval.

[0045] In some embodiments, the fixed time interval may be 100 ms.

[0046] In some embodiments, providing a pull-up voltage to the voltage node may include: coupling the selected one or more candidate pull-up circuits to the voltage node; providing the adjusted candidate pull-up voltage to the voltage node through the selected one or more candidate pull-up circuits. Providing a pull-down voltage to the ground node may include: coupling the selected one or more candidate pull-down circuits to the ground node; providing the adjusted candidate pull-down voltage to the ground node through the selected one or more candidate pull-down circuits.

[0047] Another aspect of the present invention is an input-dependent offset voltage compensation method applicable to an amplifier circuit. The method may include: connecting a first node of the amplifier circuit to a second node of the amplifier circuit through a control circuit coupled to the amplifier circuit, so that the voltages on the first node and the second node converge. Separating the first node from the second node through the control circuit; determining a compensation time; turning on the amplifier circuit within the compensation time to generate a first signal and a second signal, where the first signal is generated at the first node and the second signal is generated at the second node; and routing the first signal to the second node and routing the second signal to the first node through the control circuit to compensate for the input-dependent offset voltage of the amplifier circuit.

[0048] In some embodiments, determining the compensation time may include: determining the compensation time based on the transconductance of the amplifier circuit, the bit line resistance, and the bit line parasitic capacitance of the amplifier circuit.

[0049] In some embodiments, in the above method, determining the compensation time may include: establishing a look-up table for the compensation time, the look-up table including a plurality of compensation durations, each compensation duration corresponding to a specific condition; determining the current condition; and determining the compensation time by looking up the compensation duration corresponding to the current condition in the look-up table.

[0050] In some embodiments, turning on the amplifier circuit to generate the first signal and the second signal within the compensation time may include: turning on the amplifier circuit by providing a pull-up voltage and a pull-down voltage to the amplifier circuit. The above method may further include performing a calibration process to determine the pull-up voltage and the pull-down voltage.

[0051] In some embodiments, the above method may further include: receiving input signal pairs for amplification at a first node and a second node, respectively. The input signal pairs may be superimposed on the second signal at the first node and the first signal at the second node, respectively.

[0052] Another aspect of the present invention relates to a method of operating a sense amplifier circuit. The sense amplifier circuit may be connected to a first bit line through a first bit line switch circuit and connected to a second bit line through a second bit line switch circuit. The sense amplifier circuit may be configured to amplify a voltage signal applied between the first bit line and the second bit line. The method may include: when the sense amplifier circuit amplifies the voltage signal, disconnecting the sense amplifier circuit from the first bit line and the second bit line by operating the first bit line switch circuit and the second bit line switch circuit; keeping the sense amplifier circuit disconnected from the first bit line and the second bit line for a predetermined period of time; and reconnecting the sense amplifier circuit to the first bit line and the second bit line by operating the first bit line switch circuit and the second bit line switch circuit.

[0053] In some embodiments, in the above method, reconnecting the sense amplifier circuit to the first bit line and the second bit line may include: reconnecting the sense amplifier circuit to the first bit line and the second bit line by setting each of the first bit line switch circuit and the second bit line switch circuit to a partially conductive state.

[0054] Another aspect of the present invention is a memory operation method applicable to a memory. The method may include: performing the above input-related offset voltage compensation method on a plurality of amplifier circuits arranged on a first side of a word line of the memory; and performing the above input-related offset voltage compensation method on a plurality of amplifier circuits arranged on a second side of the word line of the memory relative to the first side.

[0055] Another aspect of the present invention is to provide an input - related offset voltage compensation method, which is applicable to an amplifier circuit having a first sub - circuit and a second sub - circuit and having an input - related offset voltage. The method may include: in response to a voltage signal, generating a first signal on a first I / O of the amplifier circuit by the first sub - circuit, and generating a second signal on a second I / O of the amplifier circuit by the second sub - circuit. The difference between the first signal and the second signal may reflect the input - related offset voltage in the circuit. The method may further include connecting the first signal to the second I / O and connecting the second signal to the first I / O through a compensation circuit coupled to the amplifier circuit to compensate for the input - related offset voltage.

[0056] In some embodiments, the compensation circuit may include: a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. A first end of the first switch circuit may be connected to a first end of the second switch circuit at the first I / O, and a first end of the third switch circuit may be connected to a first end of the fourth switch circuit at the second I / O. A second end of the first switch circuit may be connected to a second end of the fourth switch circuit at the output of the second sub - circuit, and a second end of the second switch circuit may be connected to a second end of the third switch circuit at the output of the first sub - circuit. Generating the first signal on the first I / O of the amplifier circuit by the first sub - circuit and generating the second signal on the second I / O of the amplifier circuit by the second sub - circuit may include: by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit, generating the first signal on the first I / O by the first sub - circuit and generating the second signal on the second I / O by the second sub - circuit.

[0057] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings included in the specification and constituting a part of the specification illustrate embodiments consistent with the present invention and, together with the specification, are used to explain the disclosed principles. Obviously, these drawings only show some embodiments of the present invention, and those of ordinary skill in the art can obtain the drawings of other embodiments without creative efforts.

[0059] FIG. 1A shows a conventional sense amplifier circuit.

[0060] Figure 1B and 1C respectively show circuit diagrams of a sense amplifier circuit including mismatches and an equivalent circuit including a sense amplifier circuit without mismatches, an input - related offset voltage source, and an input - reference offset current source.

[0061] Figure 2A 、 2BFigures 2C show different operation phases of a sense amplifier circuit according to an embodiment of the present invention.

[0062] Figure 3 A schematic diagram of a memory according to an embodiment of the present invention is shown.

[0063] Figure 4 A flowchart of a method for compensating an input-related offset voltage of a sense amplifier circuit according to an embodiment of the present invention is shown.

[0064] Figure 5A and 5B Schematic diagrams of voltage waveforms on a first bit line and a second bit line of a sense amplifier circuit according to one or more embodiments of the present invention are shown.

[0065] Figure 6A and 6B respectively show Figure 5A enlarged views of regions A and B of

[0066] Figure 6C and 6D Schematic diagrams of charge density distributions on a first bit line and a second bit line of a sense amplifier circuit according to one or more embodiments of the present invention are shown.

[0067] Figure 7A and 7B Schematic diagrams of voltage waveforms on a first bit line and a second bit line of a sense amplifier circuit according to one or more embodiments of the present invention are shown.

[0068] Figure 8 A schematic diagram of a calibration circuit according to an embodiment of the present invention is shown.

[0069] Figure 9 A flowchart of a calibration process according to an embodiment of the present invention is shown.

[0070] Figure 10A A schematic diagram of a circuit for determining a compensation time according to an embodiment of the present invention is shown.

[0071] Figure 10B A flowchart of a method for determining a compensation time according to an embodiment of the present invention is shown.

[0072] Figure 11 A schematic diagram of a sense amplifier circuit including a transconductance compensation circuit according to an embodiment of the present invention is shown.

[0073] Figure 12A and 12B Schematic diagrams of a storage device including a circuit for compensating bit line resistance according to one or more embodiments of the present invention are shown.

[0074] Figure 13FIG. 0 shows a schematic diagram of a memory device including a circuit for compensating a bit line parasitic capacitor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0075] Exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in various forms and should not be construed as limited to the features set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. In addition, the described features, structures, and characteristics may be combined in any suitable manner in one or more embodiments. In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, those skilled in the art will recognize that various embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0076] Furthermore, the drawings are only for illustrative purposes and are not necessarily drawn to scale. Throughout the drawings, like reference numerals denote like or similar elements, and thus any repeated description thereof will be omitted. The blocks shown in the figures are merely functional entities and do not necessarily correspond to physically separate entities. In other words, these functional entities may be implemented as software, or fully or partially in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0077] The flowcharts shown in the drawings are merely illustrative and do not necessarily include all of the steps shown. For example, some of these steps may be divided, while some may be at least partially combined. Therefore, their actual execution order may vary depending on the actual situation.

[0078] 1. Sense Amplifier Circuit

[0079] FIG. 1A shows a conventional sense amplifier circuit. As shown in FIG. 1A, the conventional sense amplifier circuit may include a first inverter and a second inverter. The first inverter may include a first transistor M1 and a second transistor M2 connected together, and the second inverter may include a third transistor M3 and a fourth transistor M4 connected together. The input (node i1) of the first inverter may be connected to the output (node o2) of the second inverter, and the input (node i2) of the second inverter may be connected to the output (node o1) of the first inverter. That is, the first inverter and the second inverter may be cross-coupled to each other. The sense amplifier circuit may further include a pull-up circuit for providing a pull-up voltage and a pull-down circuit for providing a pull-down voltage. When data is read from a memory cell, bit line S x and bit line Sy One can serve as the input of the sense amplifier circuit and contain the charge from the corresponding memory cell, while the other bit line serves as a reference for the sensing operation.

[0080] As shown in FIG. 1A, the sense amplifier circuit can have two bit lines, each bit line connected to one or more memory cells. An input signal to the sense amplifier circuit can be received through one of the two bit lines, while the other bit line serves as a reference. When data is not being read from the memory cells of the memory, the memory cells are electrically isolated from the sense amplifier circuit, so no input signal is provided to the sense amplifier circuit. When a memory cell is selected for data reading, the transistor connected between the memory cell and the sense amplifier circuit conducts, causing the storage capacitor associated with that memory cell to be connected to the bit line of the sense amplifier circuit. Then the charge stored in the capacitor can generate an input signal (i.e., a voltage difference) on the bit line. When amplifying the input signal, a high voltage can be applied to the voltage node and a low voltage can be applied to the ground node of the sense amplifier circuit, and the input signal on the bit line can be amplified. Then the amplified signal can be sent to an external device through the bit line to read the data of the memory cell.

[0081] However, the sense amplifier circuit may have an offset voltage that can affect the circuit sensitivity. The offset voltage can be caused by various factors, including but not limited to the deviation between the threshold voltages of the corresponding transistors in the cross-coupled inverters, the mismatch between the series resistances on the source / drain nodes of the transistors, the mismatch between the structural dimensions of the corresponding circuit elements, the carrier mobility mismatch, the substrate bias, the conductivity coefficient mismatch, and the node capacitance mismatch of the corresponding transistors. In one example, the offset voltage may be caused by the difference between the threshold voltages of the corresponding transistors in two inverter amplifiers in the sense amplifier circuit. For example, due to variations in the manufacturing process, the threshold voltage of a transistor in one inverter may be higher than the threshold voltage of the corresponding transistor in the coupled inverter in the sense amplifier circuit. Therefore, the input signal of the sense amplifier circuit must be greater than the minimum voltage margin determined by the offset voltage in order for the data in the associated memory cell to be correctly read. In other words, the offset voltage reduces the sensitivity of the sense amplifier circuit. In this application, for the sake of description, all the above-mentioned variations and mismatches are collectively referred to as "mismatch" in the sense amplifier circuit.

[0082] The effect of the offset voltage on the sense amplifier circuit will be further described with reference to Figure 1B and 1C The presence of mismatch in the sense amplifier circuit may generate a DC output voltage that cannot be distinguished from the DC component of the amplified signal. As shown in Figure 1B the sense amplifier containing mismatch can be equivalently represented by an ideal mismatch-free sense amplifier, which, as shown in Figure 1CAs shown, there is an input reference voltage source V os (i.e., providing an input-related offset voltage) and an input reference current source I os (providing an input reference offset current). In this application, the term "input-related offset voltage" is used to represent the offset voltage of a sense amplifier including mismatches.

[0083] In this application, methods and devices for compensating a sense amplifier circuit from the perspective of voltage compensation (i.e., compensating the input-related offset voltage) are disclosed. However, the present invention is not limited in this regard. Based on the same inventive concept disclosed in this application, methods and devices for compensating a sense amplifier circuit from the perspective of current compensation (i.e., compensating the input reference offset current) are envisioned, and these methods and devices are within the scope of protection of this application.

[0084] This application first presents a sense amplifier circuit for compensating its input-related offset voltage. Figure 2A A sense amplifier circuit according to an embodiment of the present invention is shown. The following will refer to Figure 2A Describe this sense amplifier circuit in detail.

[0085] As Figure 2A shown, the sense amplifier circuit may include an amplification circuit for amplifying a voltage signal. The amplification circuit may include a first inverting amplifier connected to a first bit line BLa and a second inverting amplifier connected to a second bit line BLb. The amplification circuit may be configured to amplify a signal (e.g., a voltage signal) applied between the first bit line BLa and the second bit line BLb.

[0086] More specifically, the amplification circuit may include a first inverting amplifier INV1 ( Figure 2A the dashed box INV1 in Figure 2A ) and a second inverting amplifier INV2 (

[0087] the dashed box INV2 in Figure 2AAs shown, the sense amplifier circuit may further include a compensation circuit, which is coupled to the amplifier circuit and configured to compensate for the input-related offset voltage of the amplifier circuit. The input-related offset voltage of the amplifier circuit may be caused by mismatches in the amplifier circuit. In some embodiments, the input-related offset voltage may reflect the difference in the threshold voltages of the corresponding transistors in the first inverter INV1 and the second inverter INV2. The compensation circuit may be configured to compensate for the input-related offset voltage of the amplifier circuit by injecting charge into the first bit line BLa and the second bit line BLb.

[0088] In some embodiments, injecting charge into the first bit line BLa and the second bit line BLb may include: injecting a first charge generated by the first inverter INV1 into the second bit line BLb; injecting a second charge generated by the second inverter INV2 into the first bit line BLa. After the distribution of the first charge and the second charge on the bit lines stabilizes, the first charge and the second charge may generate a compensation voltage between the first bit line BLa and the second bit line BLb. In this application, a charge being "stable" on a bit line means that the charge has propagated sufficiently on the bit line, and the details of this concept will be explained in more detail with reference to the accompanying drawings in the later part of this application. The compensation voltage may be substantially equal to the input-related offset voltage of the amplifier circuit. In this application, a first voltage being "substantially equal to" a second voltage means that the first voltage is within a certain range of the second voltage. This range may be, for example, ±10% or ±5% of the second voltage, and the present invention is not limited thereto. In one example, the compensation voltage generated by the first charge and the second charge may be within ±5% of the input-related offset voltage of the sense amplifier circuit.

[0089] The first charge and the second charge may have the same or different amounts of charge, and the same or different charge polarities. The present invention is not limited in these aspects.

[0090] In some embodiments, injecting charge into the first bit line BLa and the second bit line BLa may include: injecting only the first charge generated by the first inverter INV1 into the second bit line BLb, or injecting only the second charge generated by the second inverter INV2 into the first bit line BLa. In these cases, after the distribution of the first charge or the second charge on the bit line stabilizes, the first charge or the second charge may generate a compensation voltage between the first bit line BLa and the second bit line BLB, and the compensation voltage may be substantially equal to the input reference offset voltage of the amplifier circuit.

[0091] The compensation circuit may include one or more capacitive elements. The capacitive element may be an element capable of storing electric charge, and may include, but is not limited to, a capacitor, a diode, a field-effect transistor (FET), and a metal-oxide-semiconductor field-effect transistor (MOSFET) capable of storing electric charge. In one example, the one or more capacitive elements may include a Ni capacitor or a bit-line parasitic capacitor.

[0092] In some embodiments, as Figure 2A shown, the compensation circuit may include a first switch circuit S1, a second switch circuit S2, a third switch circuit S3, and a fourth switch circuit S4. The first end of the first switch circuit S1 may be connected to the first end of the second switch circuit at a first bit line BLa, and the first end of the third switch circuit S3 may be connected to the first end of the fourth switch circuit S4 at a second bit line BLb. The second end of the first switch circuit S1 may be connected to the second end of the fourth switch circuit S4 at a first node a, and the second end of the second switch circuit S2 may be connected to the second end of the third switch circuit S3 at a second node b.

[0093] In some embodiments, each of the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may be a switch and may be in one of an "ON" or "OFF" state. However, the present invention is not limited thereto. Other suitable circuits capable of providing an on / off switch function may be used as the switch circuit.

[0094] In some embodiments, each of the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may be implemented using one or more transistors. For example, each switch circuit may include an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate. In this case, in addition to the "ON" or "OFF" state, the switch circuit may also be in an intermediate conduction state according to the conduction state of the transistor. The conduction state of each of these switch circuits may be controlled by applying a voltage to the corresponding transistor, such as to the corresponding NMOS transistor, PMOS transistor, or transmission gate.

[0095] In addition, in some embodiments, the sense amplifier circuit may further include a switch control circuit (not shown in the figure) coupled to the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4. The switch control circuit may be configured to control the on-state of each of these switch circuits. In one example, the switch control circuit may control the on-state of each of these switch circuits by applying a voltage to the gate terminals of the corresponding transistors in each switch circuit.

[0096] Reference Figure 2A , in some embodiments, the first inverter amplifier INV1 may include a first transistor M1 and a second transistor M2. Each of the first transistor M1 and the second transistor M2 may have a first terminal, a second terminal, and a gate terminal. The second end of the first transistor M1 and the first end of the second transistor M2 may both be connected to the second node b. The gate terminal of the first transistor M1 and the gate terminal of the second transistor M2 may both be connected to the first node a.

[0097] The second inverter amplifier may include a third transistor M3 and a fourth transistor M4. Each of the third transistor M3 and the fourth transistor M4 may have a first terminal, a second terminal, and a gate terminal. The second end of the third transistor M3 and the first end of the fourth transistor M4 may both be connected to the first node a. The gate terminal of the third transistor M3 and the gate terminal of the fourth transistor M4 may both be connected to the second node b. The first end of the first transistor M1 and the first end of the third transistor may be connected to the voltage node sapwr, and the second end of the second transistor M2 and the second end of the fourth transistor M4 may be connected to the ground node sagnd.

[0098] In some embodiments, each of the first transistor M1 and the third transistor M3 may have a first conduction type, and each of the second transistor M2 and the fourth transistor M4 may have a second conduction type opposite to the first conduction type. For example, the first transistor M1 and the third transistor M3 may be P-type transistors, and the second transistor M2 and the fourth transistor M4 may be N-type transistors.

[0099] Reference Figure 2A , in some embodiments, the sense amplifier circuit may be provided with a plurality of pull-up circuits having different voltage pull-up capabilities, and a plurality of pull-down circuits having different voltage pull-down capabilities. One or more of the plurality of pull-up circuits may be selected to be coupled to the voltage node sapwr, and a pull-up voltage may be provided to the sense amplifier circuit through the selected one or more pull-up circuits. One or more of the plurality of pull-down circuits may be selected to be coupled to the ground node sagnd, and a pull-down voltage may be provided to the sense amplifier circuit through the selected one or more pull-down circuits.

[0100] In the above embodiments, each of the first inverter INV1 and the second inverter INV2 may include two transistors. However, the first inverter INV1 and the second inverter INV2 may also be implemented by other suitable circuits as long as these circuits can provide an inverting function. For example, each of the first inverter INV1 and the second inverter INV2 may include three or more transistors. The present invention does not limit the specific configurations of the first inverter INV1 and the second inverter INV2.

[0101] In a sense amplifier circuit according to some embodiments of the present invention, the first switch circuit S1 and the second switch circuit S2 may be connected to the first bit line BLa, and the third switch circuit S3 and the fourth switch circuit S4 may be connected to the second bit line BLb. By controlling each switch circuit to be in the "ON" or "OFF" state, the first bit line BLa and the second bit line BLb can be connected to different internal components (e.g., an inverter) of the sense amplifier circuit.

[0102] In some embodiments, charge injection into the first bit line BLa and the second bit line BLb may include: performing charge injection into the first bit line BLa and the second bit line BLb by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit. After the first charge and the second charge are stabilized on the bit lines, a compensation voltage may be generated between the first bit line BLa and the second bit line BLb to compensate for the input-related offset voltage in the amplifier circuit, thereby improving the performance of the related memory.

[0103] Based on the above sense amplifier circuit, the present invention further provides a memory. Figure 3 A schematic diagram of a memory according to an embodiment of the present invention is shown. As Figure 3 shown, the memory may include a plurality of memory cells ( Figure 3 not shown in the figure) and a plurality of sense amplifier circuits. Each sense amplifier circuit may be the sense amplifier circuit in any of the foregoing embodiments. The detailed composition of the sense amplifier circuit may refer to the relevant parts in the above embodiments. For the sake of brevity, it will not be described herein again. For each of the plurality of sense amplifier circuits, each of the first bit line and the second bit line may be connected to one of the plurality of memory cells. When data is read from the memory, the data stored in the memory cell may be amplified by the corresponding sense amplifier circuit connected thereto. The plurality of memory cells may be connected by word lines (WL).

[0104] In some embodiments, multiple sense amplifier circuits may be alternately arranged on a first side of a word line and a second side of the word line relative to the first side. Each sense amplifier circuit arranged on the first side of the word line may be connected to one of a plurality of memory cells through a first bit line, and each sense amplifier circuit arranged on the second side of the word line may be connected to one of a plurality of memory cells through a second bit line. 2. Method of operating a sense amplifier circuit

[0105] Based on the above-described sense amplifier circuit, the present invention also proposes a method of operating a sense amplifier circuit, which compensates for an input-related offset voltage of an amplifier circuit.

[0106] 2.1 Compensating for an input-related offset voltage in an amplifier circuit

[0107] Figure 2A 、 2B Figures 2A, 2B, and 2C show diagrams of different stages of a method of operating a sense amplifier circuit according to some embodiments of the present invention. Figure 4 Figure 4 shows a flowchart of a method of operating a sense amplifier circuit according to an embodiment of the present invention. The method will be described in detail below with reference to these drawings.

[0108] In one example, the method of operating a sense amplifier circuit may be performed on the sense amplifier circuit shown in Figure 2A That is, the sense amplifier circuit may include an amplifier circuit for amplifying a voltage signal and a compensation circuit for compensating for an input-related offset voltage of the amplifier circuit. The amplifier circuit may include a first inverter INV1 and a second inverter INV2. The compensation circuit may include a first switch circuit S1, a second switch circuit S2, a third switch circuit S3, and a fourth switch circuit S4. The sense amplifier circuit may have a first bit line BLa and a second bit line BLb.

[0109] The method of operating a sense amplifier circuit may include generating a compensation voltage between the first bit line BLa and the second bit line BLb by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to compensate for an input-related offset voltage of the amplifier circuit.

[0110] More specifically, referring to Figure 4 Figure 4, the method of operating a sense amplifier circuit may include the following steps S410 to S450.

[0111] In step S410, a sense amplifier circuit may be provided. The sense amplifier circuit may be the sense amplifier circuit in any of the above embodiments. The detailed configuration of the sense amplifier circuit may refer to the relevant parts in the above embodiments. For the sake of brevity, it will not be described herein again.

[0112] In step S420, asFigure 2A As shown, the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 can all be turned on. This step can be referred to as the equalization (EQ) step. In this step, since all four switch circuits are turned on, the first bit line BLa is simultaneously connected to the first node a and the second node b, and the second bit line BLb is simultaneously connected to the first node a and the second node b. The fourth switch circuit can remain turned on for a long enough time to ensure that the voltages on the first bit line BLa, the second bit line BLb, the first node a, and the second node b converge to a voltage level. In this step, the voltage node sapwr can be provided with an initial rising voltage, and the ground node sagnd can be provided with an initial falling voltage.

[0113] In step S430, as Figure 2B shown, the second switch circuit S2 and the fourth switch circuit S4 can be turned off, while the first switch circuit S1 and the third switch circuit S3 remain turned on. In this step, the voltage node sapwr can be provided with a pull-up voltage higher than the initial rising voltage, and the ground node sagnd can be provided with a pull-down voltage lower than the initial falling voltage. Therefore, the sense amplifier circuit can operate as an amplifier. Since in the previous step (i.e., step S420), the voltages on the first bit line BLa, the second bit line BLb, the first node a, and the second node b have converged to a voltage level, the first bit line BLa and the second bit line BLb have no external input. Therefore, the voltage difference between the first bit line BLa and the second bit line BLb can reflect the input-related offset voltage in the amplifier circuit (e.g., the difference between the threshold voltages of the corresponding transistors in the first inverter INV1 and the second inverter INV2). In this step, the first inverter INV1 and the second inverter INV2 can be cross-coupled to each other.

[0114] During the compensation time (Time of compensation, Toc), the first switch circuit S1 and the third switch circuit S3 can remain turned on. By selecting an appropriate Toc, the voltage difference between the first bit line BLa and the second bit line BLb at the end of Toc, called the compensation voltage, can reach a desired voltage level. In some embodiments, the desired voltage level can be a voltage level that reflects the input-related offset voltage of the amplifier circuit. In some embodiments, the input-related offset voltage of the amplifier circuit can be the difference between the threshold voltages of the corresponding transistors in the first inverter INV1 and the second inverter INV2, and the compensation voltage can reflect the difference between the threshold voltages. For example, the compensation voltage can be substantially equal to the input-related offset voltage. However, the desired voltage level can be any other value depending on specific needs, and the present invention is not limited in this regard.

[0115] The above step S430 can also be understood as a charging process, in which the compensation circuit performs a charging operation to inject charge into at least one of the first bit line BLa and the second bit line BLb. After the charging operation is completed, the charge injected into the first bit line BLa and / or the second bit line BLb can stabilize on the bit line, and during this period, the voltage difference between the proximal ends of the first bit line BLa and the second bit line BLb can decrease. Therefore, in order to fully compensate for the input-related offset voltage, the voltage difference between the proximal ends of the first bit line BLa and the second bit line BLb can be greater than the input-related offset voltage of the amplifier circuit at the end of the charging operation. For example, the voltage difference may be 10%-40% larger than the input-related offset voltage at the end of the charging operation. Therefore, after the charge injected into the first bit line BLa and the second bit line BLb stabilizes on the bit line, the resulting voltage difference at the proximal end of the bit line can be substantially equal to the input-related offset voltage.

[0116] Next, in step S440, the first switch circuit S1 and the third switch circuit S3 can be turned off, so that all four switch circuits are turned off. Therefore, the compensation voltage can be maintained on the first bit line BLa and the second bit line BLb. In this step, the voltage of the voltage node sapwr can return to the initial rising voltage, and the voltage of the ground node sagnd can return to the initial falling voltage.

[0117] Next, as Figure 2C shown, in step S450, the second switch circuit S2 and the fourth switch circuit S4 can be turned on, while the first switch circuit S1 and the third switch circuit S3 remain off. In this step, the voltage node sapwr can be provided with a pull-up voltage, the ground node sagnd can be provided with a pull-down voltage, and the sense amplifier circuit can amplify the input signal between the first bit line BLa and the second bit line BLb.

[0118] Figure 5A and 5B show waveform diagrams of the voltage of the first bit line BLa and the voltage of the second bit line BLb of the sense amplifier circuit according to one or more embodiments of the present invention. The operation method of the sense amplifier circuit will be further described below in conjunction with these drawings to fully understand the compensation ability of the sense amplifier circuit.

[0119] Referring to Figure 4 and Figure 5A , in step S420, corresponding to Figure 5A the time EQ in Figure 2A shown, the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 are all turned on (as

[0120] shown). The voltages of the first bit line BLa and the second bit line BLb can converge to a voltage.Figure 5A Time Com in 开始 , the second switch circuit S2 and the fourth switch circuit S4 are turned off, while the first switch circuit S1 and the third switch circuit S3 remain on (as Figure 2B shown). At this time, the voltage node sapwr can be supplied with a pull-up voltage, and the ground node sagnd can be supplied with a pull-down voltage. Therefore, the sense amplifier can operate as an amplifier and amplify the voltage difference (e.g., the difference between the threshold voltages of the corresponding transistors in an inverting amplifier). The voltage difference can be reflected as the voltage difference between the first bit line BLa and the second bit line BLb. The larger the input-referred offset voltage, the faster the voltages on the first bit line BLa and the second bit line BLb will diverge.

[0121] In step S430, during the Toc duration, the second switch circuit S2 and the fourth switch circuit S4 can remain off, and the first switch circuit S1 and the third switch circuit S3 can remain on. During this period, as Figure 5A shown, the voltages of the first bit line BLa and the second bit line BLb continue to diverge, thereby amplifying the voltage difference in the sense amplifier circuit.

[0122] Next, in step S440, corresponding to Figure 5A the time Com in 结束 , all four switch circuits are turned off, and the voltage difference (compensation voltage) between the first bit line BLa and the second bit line BLb can be maintained. In some embodiments, the input-referred offset voltage of the amplifier circuit can be the difference between the threshold voltages of the corresponding transistors in the first inverting amplifier and the second inverting amplifier. By selecting an appropriate Toc, the compensation voltage can reflect the difference between the threshold voltages. For example, the compensation voltage can have an amplitude substantially the same as the difference between the threshold voltages.

[0123] As Figure 5A shown, the compensation voltage can be maintained on the first bit line BLa and the second bit line BLb until the specific memory cell corresponding to the sense amplifier circuit for reading the data thereon is selected (corresponding to Figure 5A the time charge sharing in ). Accessing a memory cell can cause charge sharing between the capacitor of the memory cell and the bit line capacitor. Charge sharing can cause the voltage on the bit line corresponding to the memory cell to increase for a stored logic 1 or decrease for a stored logic 0. When reading a memory cell, the voltage difference between the two bit lines, i.e., the signal voltage V sig , may depend on the capacitance C mbit of the memory cell, the equivalent capacitance C BL of the bit line, and the voltage V cell stored on the memory cell before access, and can be expressed as:

[0124]

[0125] In this case, as Figure 5A shown, when the storage unit is accessed (i.e., during time charge sharing), the voltage difference between the first bit line BLa and the second bit line BLb may start to change, and may ultimately result in a voltage change of ΔV.

[0126] In step S450, the second switch circuit S2 and the fourth switch circuit S4 are turned on, while the first switch circuit S1 and the third switch circuit S3 remain off (as Figure 2C shown). In this step, starting from the firing time in Figure 5A , the voltage node sapwr can be supplied with a pull-up voltage, the ground node can be supplied with a pull-down voltage, and the sense amplifier circuit can amplify the voltage difference between the first bit line BLa and the second bit line BLb. The voltage difference supplied to the sense amplifier circuit is the signal voltage V sig superimposed on the compensation voltage. Since the compensation voltage can reflect the input-related offset voltage in the amplifier circuit (e.g., the compensation voltage can have substantially the same magnitude as the input-related offset voltage), the input-related offset voltage of the sense amplifier circuit can be compensated.

[0127] Figure 5B shows a waveform diagram of the voltage on the first bit line BLa and the voltage on the second bit line BLb of the sense amplifier circuit according to another embodiment of the present invention. Figure 5B Similar to Figure 5A , except that Figure 5B 's sense amplifier circuit has a mismatch different from Figure 5A . Therefore, during the compensation time (i.e., Toc), the voltage on the first bit line BLa and the voltage on the second bit line BLb may diverge differently from the corresponding voltages shown in Figure 5A . As shown in Figure 5A and 5B , in the method for operating the sense amplifier circuit of the present invention, the compensation voltage between the first bit line BLa and the second bit line BLb can reflect a specific input-related offset voltage in the sense amplifier circuit. Therefore, by selecting an appropriate Toc, the input-related offset voltage in the sense amplifier circuit can be automatically compensated.

[0128] As Figure 2A , 2BAs shown in FIGS. 2C, in the method for operating a sense amplifier circuit according to the present invention, during the signal amplification phase, at least one of the first bit line BLa and the second bit line BLa can be connected to one of the outputs of the first inverter INV1 and the second inverter INV2 through a compensation circuit. During the offset compensation phase, at least one of the first bit line BLa and the second bit line BLb can be connected to the other of the outputs of the first inverter INV1 and the second inverter INV2. That is, during the signal amplification phase and the offset compensation phase, at least one of the first bit line BLa and the second bit line BLb will be connected to the outputs of different inverters. Additionally, during the offset compensation phase, the sense amplifier circuit acts as an amplifier to amplify the voltage caused by the mismatch in the sense amplifier circuit, so the gain of the sense amplifier circuit is greater than 1 during the offset compensation phase. During the signal amplification phase, the output of the first inverter INV1 can be connected to the first bit line BLa, and the output of the second inverter INV2 can be connected to the second bit line BLb, while during the offset compensation phase, the output of the first inverter INV1 can be connected to the second bit line BLb, and the output of the second inverter INV2 can be connected to the first bit line BLa.

[0129] In the method for operating a sense amplifier circuit according to the present invention described above, first, all four switch circuits are turned on for a sufficient length of time to converge the voltages on the first bit line BLa, the second bit line BLb, the first node a, and the second node b to a voltage level. Then, the second switch circuit and the fourth switch circuit are turned off, while the first switch circuit and the third switch circuit remain on for a duration of Toc. In this step, the mismatch in the sense amplifier circuit (e.g., the difference in the threshold voltages of the corresponding transistors) may cause a voltage difference (i.e., the compensation voltage) between the first bit line BLa and the second bit line BLb. By selecting an appropriate Toc, the compensation voltage can reflect the input-related offset voltage of the amplifier circuit (e.g., the compensation voltage can have substantially the same magnitude as the difference in the threshold voltages). Then, the first switch circuit and the third switch circuit are turned off to hold the compensation voltages on the first bit line BLa and the second bit line BLb. When the second switch circuit and the fourth switch circuit are subsequently turned on to amplify the input signal, the input signal is superimposed on the compensation voltage, thereby compensating for the input-related offset voltage of the amplifier circuit. Therefore, the performance of the related memory can be improved.

[0130] The inherent electrical characteristics of the bit line, such as the bit line resistance R BL and the bit line parasitic capacitance C BL , may affect the voltage on the bit line. The method for operating a sense amplifier circuit according to the present invention takes these effects into account, thereby improving the accuracy of input-related offset voltage compensation. Figure 6A and 6B respectively show Figure 5AEnlarged views of regions A and B. Figure 6C and 6D FIGS. Figure 6C and 6D illustrate charge density distributions on a first bit line and a second bit line of a sense amplifier circuit according to one or more embodiments of the present invention. A method of operating the sense amplifier circuit will be further described below with reference to these drawings.

[0131] Reference Figure 6A , after Toc (i.e., Com 结束 ), due to the propagation of charge along the first bit line BLa, the voltage at the first bit line BLa (i.e., the voltage at the node where the first bit line BLa is connected to the sense amplifier circuit) may gradually decrease from the charge voltage to a stable voltage (i.e., from V1_charge to V1_stable). The amount of voltage drop (i.e., V1_charge - V1_stable) can be determined by the total charge injected into the first bit line BLa and the electrical characteristics of the first bit line BLa (e.g., the bit line parasitic capacitance C BL ). Accordingly, Figure 6C FIG. Figure 6C shows that immediately after Toc, the charge density distribution on the first bit line BLa is related to the distance to the sense amplifier circuit (represented by the horizontal axis of Figure 6C ). That is, the closer a portion of the first bit line BLa is to the sense amplifier circuit, the higher the charge density thereon. As the charge propagates along the first bit line BLa, the charge density distribution on the first bit line BLa will eventually stabilize to an approximately constant distribution (the "stable" line in Figure 6C ). Similar to the first bit line BLa, the voltage and charge density distributions on the second bit line BLb may undergo similar changes after Toc, as shown in Figure 6B and 6D .

[0132] In some embodiments, considering the charge propagation on the bit lines, the voltages on the first and second bit lines immediately after Toc may be greater (in terms of magnitude) than the voltage required to compensate for the input-related offset voltage.

[0133] In some embodiments, when the compensation circuit is configured to compensate for the input-related offset voltage by injecting charge into the first and second bit lines, the charges injected into the bit lines (i.e., the first charge and the second charge) can be determined based on the stable voltages on the first bit line BLa and the second bit line BLb (i.e., V1_stable and V2_stable, respectively) that can compensate for the input-related offset voltage. The first charge and the second charge can be determined based on the electrical characteristics of the first bit line BLa and the second bit line BLb. More specifically, they can be based on, including but not limited to, the bit line resistance R BL associated with the first bit line BLa and the second bit line BLb and the bit line parasitic capacitance C BLdetermined by factors. In some embodiments, a mathematical model can be established to describe the relationship between the injected charge for compensating the input-related offset voltage and the electrical characteristics of the first bit line BLa and the second bit line BLb. Then, the first charge and the second charge can be determined based on this mathematical model. The injected charge can be determined by other methods, and the present invention is not limited thereto. By considering the charge propagation on the bit line and the voltage deviation caused thereby, the method improves the accuracy of input-related offset voltage compensation.

[0134] It should be noted that Figure 6A 、 6B 、6C and 6D show schematic diagrams of the voltage and charge density distributions on the first bit line BLa and the second bit line BLa in a specific compensation scenario (i.e., Figure 5A the compensation scenario shown). Based on a similar principle, the voltage and charge density distributions on the bit line in other compensation scenarios (e.g., Figure 5B the compensation scenario shown) can be obtained. For the sake of brevity, the detailed description of these compensation scenarios is omitted here.

[0135] Based on the above operation method of the sense amplifier circuit, the present invention also provides a memory operation method. The memory in this operation method may include word lines, a plurality of memory cells connected to the word lines, and a plurality of sense amplifier circuits, each sense amplifier circuit being connected to one of the plurality of memory cells. Each sense amplifier circuit can be the sense amplifier circuit of any of the above embodiments. The detailed composition of the sense amplifier circuit can refer to the relevant parts in the above embodiments, and for the sake of brevity, it will not be described in detail here.

[0136] The plurality of sense amplifier circuits can be alternately arranged on the first side of the word line and the second side of the word line opposite to the first side. Each of the sense amplifier circuits arranged on the first side of the word line can connect the first bit line to the corresponding memory cell, and each of the sense amplifier circuits arranged on the second side of the word line can connect the second bit line to the corresponding memory cell.

[0137] The memory operation method may further include: performing the sense amplifier operation method on each sense amplifier circuit arranged on the first side of the word line; then, performing the sense amplifier operation method on each sense amplifier circuit arranged on the second side of the word line. The operation method of the sense amplifier can be the method described in the above embodiments, and for the sake of brevity, the detailed description of the operation method of the sense amplifier is omitted here.

[0138] In the above memory operation method, first, an operation method for compensating the input-related offset voltage of the sense amplifier circuit located on the first side of the word line is performed, and then an operation method for compensating the input-related offset voltage of the sense amplifier circuit located on the second side of the word line is performed. Therefore, the interference between the sense amplifier circuits located on different sides of the word line can be reduced, if not eliminated.

[0139] 2.2 Control Switching Circuit for Faster Read Speed

[0140] The above sense amplifier circuit operation method may further include a method of controlling the conduction state of the switching circuit of the sense amplifier circuit to increase the read speed of data in the memory cell. Figure 7A and 7B FIG. shows a schematic diagram of voltage waveforms on the first bit line and the second bit line of a sense amplifier circuit according to one or more embodiments of the present invention. These methods will be described in detail below with reference to these drawings.

[0141] In some embodiments, the method of controlling the conduction state of the switching circuit of the sense amplifier circuit may be performed after the above sense amplifier circuit operation method. More specifically, this method may be performed after step S450 of the above method (i.e., after the second switching circuit and the fourth switching circuit are turned on).

[0142] In some embodiments, one method may include: after step S450, disconnecting the sense amplifier circuit from the first bit line and the second bit line by operating the second switching circuit and the fourth switching circuit; keeping the sense amplifier circuit disconnected from the first bit line and the second bit line for a predetermined period of time; reconnecting the sense amplifier circuit to the first bit line and the second bit line by operating the second switching circuit and the fourth switching circuit. This method will be described in more detail below.

[0143] Reference Figure 7A , after the second switching circuit and the fourth switching circuit are turned on to amplify the input voltage signal (e.g., t s ), the first bit line BLa and the second bit line BLb may be disconnected from the sense amplifier circuit. This can be done by disconnecting the second switching circuit and the fourth switching circuit. When the bit line is disconnected from the sense amplifier circuit, the bit line resistance R BL and the bit line parasitic capacitance C BL associated with the bit line are disconnected from the sense amplifier circuit. Therefore, the voltage signal can be amplified faster than when the bit line is connected. The second switching circuit and the fourth switching circuit may be kept disconnected for a predetermined period of time (Δt in Figure 7A ). This predetermined period of time can be determined according to specific needs, and the present invention does not limit this. Then, the second switching circuit and the fourth switching circuit may be turned on to reconnect the bit line to the sense amplifier circuit.

[0144] As Figure 7A shown, during the period when the bit lines are disconnected (i.e., between t s and t e ), the voltage signal can be amplified faster than when the bit lines are connected. Therefore, the voltages on the first bit line and the second bit line can reach the corresponding target values faster than when the bit lines are not disconnected (e.g., t Figure 7A in r1 and t r0 ). Thus, by disconnecting the first bit line and the second bit line from the sense amplifier circuit for a predetermined period of time, the sense amplifier circuit can amplify the input voltage signal to the desired amplitude faster, thereby improving the read speed of the corresponding memory cell.

[0145] As Figure 7A shown, when the first bit line BLa and the second bit line BLb are reconnected to the sense amplifier circuit (i.e., at t e ), due to the bit line resistance R BL and the bit line parasitic capacitance C BL being reconnected to the sense amplifier circuit, the voltage may be temporarily pulled back, which is not desirable because it prolongs the read time. To address this shortcoming, when reconnecting the sense amplifier circuit to the first bit line BLa and the second bit line BLb, instead of fully turning on the second switch circuit and the fourth switch circuit (i.e., setting them to the 100% on state), the second switch circuit and the fourth switch circuit can be set to a partially on state to reduce the adverse effects of the bit line resistance and the bit line parasitic capacitance. Figure 7B shows the voltage waveform when the second switch circuit and the fourth switch circuit are set to a partially on state when reconnected to the sense amplifier circuit. As Figure 7B shown, when the first bit line BLa and the second bit line BLb are reconnected and each of the second switch circuit and the fourth switch circuit is in a partially on state (i.e., at t e ), the voltages of the first bit line BLa and the second bit line BLb are pulled back less compared to that in Figure 7A . Thus, a faster read speed can be achieved.

[0146] In some embodiments, the above method of controlling the on state of the switch circuits of the sense amplifier circuit can also be performed on the sense amplifier circuit without first performing the above sense amplifier circuit operation method. More specifically, the method can be performed on a sense amplifier circuit connected to the first bit line through a first bit line switch circuit and connected to the second bit line through a second bit line switch circuit. The sense amplifier circuit can be configured to amplify a voltage signal applied between the first bit line and the second bit line.

[0147] One method may include: when the sense amplifier circuit amplifies the voltage signal, disconnecting the sense amplifier circuit from the first bit line and the second bit line by operating the first bit line switch circuit and the second bit line switch circuit; keeping the sense amplifier circuit disconnected from the first bit line and the second bit line for a predetermined period of time; and reconnecting the sense amplifier circuit to the first bit line and the second bit line by operating the first bit line switch circuit and the second bit line switch circuit.

[0148] In some embodiments, in the above method, when reconnecting the sense amplifier circuit to the first bit line and the second bit line, each of the first bit line switch circuit and the second bit line switch circuit may be set to a partially conductive state.

[0149] 2.3 Calibration of changes in voltage pulling ability

[0150] The present invention also provides a calibration circuit for performing a calibration operation to determine the pull-up circuit, pull-down circuit, pull-up voltage (Vpup), and pull-down voltage (Vpdn) of the sense amplifier circuit. Figure 8 A calibration circuit of a sense amplifier circuit according to an embodiment of the present invention is shown.

[0151] As Figure 8 shown, the calibration circuit may include a replicated inverter amplifier. The replicated inverter amplifier may include a first replicated transistor M10 and a second replicated transistor M20. The replicated inverter amplifier may be a replication of the first inverter amplifier described above. That is, in the replicated inverter amplifier, the first replicated transistor M10 and the second replicated transistor M20 may be replicas of the first transistor M1 and the second transistor M2 in the sense amplifier circuit described above, respectively. In some embodiments, the replicated inverter amplifier may be a replication of the second inverter amplifier in the sense amplifier circuit. The replicated inverter amplifier may be other suitable circuits according to specific needs, and its electrical characteristics may be the same as or different from those of the first inverter amplifier or the second inverter amplifier. The present invention is not limited in this regard.

[0152] In some embodiments, in the replicated inverter amplifier, each of the first replicated transistor M10 and the second replicated transistor M20 may have a first terminal, a second terminal, and a gate terminal. The gate terminal of the first replicated transistor M10 may be connected to the gate terminal of the second replicated transistor M20 at the output node z. The second terminal of the first replicated transistor M10 may be connected to the first terminal of the second replicated transistor M20, the first terminal of the first replicated transistor M10 may be connected to the voltage node sapwr0, and the second terminal of the second replicated transistor M20 may be connected to the ground node sagnd0.

[0153] The voltage node sapwr0 may be provided with multiple pull-up circuits having different voltage pull-up capabilities, and the ground node may be provided with multiple pull-down circuits having different voltage pull-down capabilities. One or more of the multiple pull-up circuits may be selected and coupled to the voltage node sapwr0, and one or more of the multiple pull-down circuits may be selected and coupled to the ground node sagnd0. A pull-up voltage may be provided to the replica inverter amplifier through the selected one or more pull-up circuits, and a pull-down voltage may be provided to the replica inverter amplifier through the selected one or more pull-down circuits.

[0154] As Figure 8 shown, in some embodiments, the multiple pull-up circuits may be three pull-up circuits having different voltage pull-up capabilities, and the multiple pull-down circuits may be three pull-down circuits having different voltage pull-down capabilities.

[0155] The output voltage of the replica inverter amplifier at the output node z may be sent to a feedback circuit. A calibration voltage may be provided to the feedback circuit for comparison with the output voltage. The calibration voltage may be the desired voltage at node z. In one example, the calibration voltage may be half of the source voltage VH (i.e., 1 / 2VH). The output of the feedback circuit may be provided to a calibration control circuit. The calibration control circuit may adjust the pull-up voltage Vpup and the pull-down voltage Vpdn based on the comparison result of the calibration voltage and the output voltage to adjust the output voltage towards the calibration voltage.

[0156] Figure 9 A flowchart showing the calibration process according to an embodiment of the present invention is shown. The calibration process will be described below with reference to Figure 9 describe the calibration process.

[0157] As Figure 9 shown, the calibration process may include the following steps S910 to S930.

[0158] In step S910, according to the calibration voltage, one or more candidate pull-up circuits may be selected from the multiple candidate pull-up circuits, and one or more candidate pull-down circuits may be selected from the multiple candidate pull-down circuits. One or more candidate pull-up circuits and one or more candidate pull-down circuits may be selected to make the output voltage at the output node z close to the calibration voltage. More specifically, the candidate pull-up circuits and the candidate pull-down circuits may be selected based on the fact that the output voltage they generate at the output node z is closer to the calibration voltage than any other combination of the candidate pull-up circuits and the candidate pull-down circuits. In this step, a candidate pull-up voltage Vpup may be provided to the selected one or more candidate pull-up circuits, and a candidate pull-down voltage Vpdn may be provided to the selected one or more candidate pull-down circuits.

[0159] In step S920, the pull-up voltage Vpup and the pull-down voltage Vpdn can be adjusted to make the output voltage closer to the calibration voltage.

[0160] In step S930, the adjusted pull-up voltage Vpup and the adjusted pull-down voltage Vpdn can be stored in one or more registers.

[0161] The candidate pull-up voltage Vpup and the candidate pull-down voltage Vpdn stored in one or more registers can be used in the above method for compensating the input-related offset voltage of the sense amplifier circuit. That is, in the above method, providing a pull-up voltage to a voltage node may include: coupling one or more selected candidate pull-up circuits to the voltage node; and providing the adjusted candidate pull-up voltage to the voltage node through the one or more selected candidate pull-up circuits. Providing a pull-down voltage to a ground node may include: coupling one or more selected candidate pull-down circuits to the ground node; and providing the adjusted candidate pull-down voltage to the ground node through the one or more selected candidate pull-down circuits.

[0162] In addition, for a memory including multiple sense amplifier circuits (i.e., SA array), the candidate pull-up voltage and the candidate pull-down voltage stored in one or more registers can be used as the pull-up voltage and the pull-down voltage, respectively, for each of the multiple sense amplifier circuits.

[0163] In some embodiments, the calibration circuit may further include a timing unit for setting a fixed time interval, and the calibration circuit may also be used to repeatedly perform the calibration process at the fixed time interval. Therefore, the pull-up voltage Vpup and the pull-down voltage Vpdn can be periodically adjusted according to changing conditions (such as temperature) or operational requirements. In some embodiments, the fixed time interval may be 100 ms.

[0164] In the above calibration process, by selecting one or more suitable pull-up circuits from multiple candidate pull-up circuits, selecting one or more suitable pull-down circuits from multiple candidate pull-down circuits, and adjusting the pull-up voltage Vpup and the pull-down voltage Vpdn, the output voltage of the replicated inverter can be made as close as possible to the calibration voltage (e.g., 1 / 2 VH). Therefore, the difference in the voltage pulling capabilities between the pull-up circuit and the pull-down circuit can be compensated.

[0165] 3. Determination of Compensation Time (Toc)

[0166] The Toc of the above compensation process can be selected such that the voltage difference (i.e., the compensation voltage) between the first bit line BLa and the second bit line BLb at the end of step S430 can reflect the input-referred offset voltage of the sense amplifier circuit, so that the input-referred offset voltage can be appropriately compensated. For example, the voltage difference can have substantially the same magnitude as the input-referred offset voltage.

[0167] The Toc can be determined based on various factors, including but not limited to the transconductance G of the sense amplifier circuit as a whole m , the bit line resistance R BL and the bit line parasitic capacitance C BL . That is, the Toc can be determined by the following equation:

[0168] Toc = f(G m , R BL , C BL )

[0169] In some embodiments, when determining the Toc, the charge propagation on the bit line can be considered, and the Toc can be determined such that the charges injected into the first bit line BLa and the second bit line BLa can generate a compensation voltage between the bit lines after completely propagating on the bit line to compensate for the input-referred offset voltage.

[0170] The Toc of the sense amplifier circuit can be determined by different methods. In one embodiment, the Toc can be determined by first establishing a mathematical model to obtain an analytical solution of the Toc and then calculating the Toc based on the analytical solution. In another embodiment, the Toc can be obtained through a look-up table of the Toc. More specifically, the look-up table of the Toc under different conditions can be established first according to experimental data. The look-up table can include multiple compensation durations, and each compensation duration corresponds to a specific condition (i.e., when each factor such as the transconductance G m , the bit line resistance R BL and the bit line parasitic capacitance C BL is at a specific value). Then, the current condition can be determined. The current condition can include the current values of each of the above factors, which can include but not limited to the transconductance G m , the bit line resistance R BL and the bit line parasitic capacitor C BL . Then the Toc can be determined by looking up the compensation duration corresponding to the current condition in the look-up table.

[0171] Figure 10A shows a schematic diagram of a circuit for determining the compensation time according to an embodiment of the present invention. Refer to Figure 10A, the circuit for determining the compensation time can be a feedback circuit and can include a sense amplifier (SA) circuit, a determination circuit, one or more counters / registers, a delay generation circuit, and a switch control circuit. The output of the SA circuit can be provided to the determination circuit, and the determination circuit can determine whether the desired compensation time has been reached based on the output and a predetermined condition. The determination circuit can be connected to one or more counters / registers, and the counter / register can be further connected to the delay generation circuit. The one or more counters / registers and the delay generation circuit can generate a delay signal according to the output of the determination circuit, and the delay signal can be sent to the switch control circuit, and the switch control circuit can apply the Toc to the SA circuit based on the delay signal.

[0172] Figure 10B FIG. shows a flowchart of a method for determining a compensation time according to an embodiment of the present invention. Refer to Figure 10B , the method for determining the compensation time can include the following steps S1010 to S1070.

[0173] In step S1010, an equalization (EQ) process can be performed on the sense amplifier (SA) circuit. That is, the SA circuit can connect its two input bit lines to reset the SA circuit.

[0174] In step S1020, the two input bit lines of the SA circuit are separated, and one of the input bit lines can be selected to read the data thereon (e.g., 0 or 1).

[0175] In step S1030, an EQ process can be performed on the SA circuit to reset the SA circuit.

[0176] In step S1040, after the EQ process, a compensation time T i , i = 1, 2,...) can be selected from a compensation time sequence and applied to the SA circuit. i

[0177] In step S1050, after Toc, the data on the selected input bit line can be read.

[0178] In step S1060, the data read from the selected input bit line can be compared with the data read in step S1020 to determine whether a change has occurred (i.e., from 0 to 1, or from 1 to 0).

[0179] If the data has changed, the method is completed, and T i is the determined compensation time ( Figure 10B step S1070 in). If the data has not changed, return to step S1030, another compensation time can be selected, and steps S1030 to S1060 can be repeated until the data changes.

[0180] In some embodiments, the compensation time series (T i ,i = 1, 2,...) may include multiple monotonically increasing or decreasing values of the compensation time.

[0181] 4. Constant Toc Compensation Circuit

[0182] The transconductance G of the sense amplifier circuit m , the bit line resistance R BL and the bit line parasitic capacitance C BL may change with changing conditions (e.g., temperature), which may affect Toc and thus the accuracy of compensation.

[0183] The present invention further provides a circuit and related method for respectively compensating the transconductance G of the sense amplifier circuit m , the bit line resistance R BL and the bit line parasitic capacitor C BL to adapt to changing conditions, so that the Toc of the amplifier circuit may remain relatively constant.

[0184] Figure 11 A schematic diagram of a sense amplifier circuit including a transconductance compensation circuit according to some embodiments of the present invention is shown. As Figure 11 shown, in some embodiments, a sense amplifier circuit having a transconductance compensation circuit may include a transconductance compensation circuit coupled to the sense amplifier circuit (SA circuit). In some embodiments, the transconductance compensation circuit may be coupled to the pull-up circuit and the pull-down circuit of the sense amplifier circuit and is configured to provide a compensation current for the pull-up circuit and the pull-down circuit of the sense amplifier circuit. The transconductance compensation circuit may include a temperature sensor for sensing temperature and is configured to provide a compensation current to the pull-up circuit and the pull-down circuit of the sense amplifier circuit according to the sensed temperature.

[0185] In some embodiments, the transconductance compensation circuit may include two constant Gm circuits, each circuit being respectively coupled to the pull-up circuit and the pull-down circuit of the sense amplifier circuit. Other circuits that can adjust the transconductance of the sense amplifier circuit according to external conditions may also be used, and the present invention does not limit this.

[0186] Figure 12A and 12B A schematic diagram of a memory including a circuit for compensating the bit line resistance according to some embodiments of the present invention is shown. Figure 13 A schematic diagram of a memory including a circuit for compensating the bit line parasitic capacitance according to an embodiment of the present invention is shown. These memories will be described below with reference to these drawings.

[0187] In one example, the memory may include word lines, a plurality of memory cells connected to the word lines, and a plurality of sense amplifier circuits, each sense amplifier circuit being connected to one of the plurality of memory cells. The sense amplifier circuit here may be the sense amplifier circuit in any of the above embodiments. The detailed composition of the sense amplifier circuit may refer to the relevant parts in the above embodiments. For the sake of brevity, it will not be described in detail here.

[0188] In some embodiments, in the memory, each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit in each of the plurality of sense amplifier circuits includes an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate.

[0189] In some embodiments, the memory may include a virtual bit line configured to generate a bias voltage applied to at least one of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit in each of the plurality of sense amplifier circuits. The bias voltage may control the on-state of the corresponding switch circuit.

[0190] In some embodiments, as Figure 12A shown, in the memory, each memory cell may be connected to a corresponding sense amplifier circuit through an input transistor. The memory may further include a virtual bit line coupled to at least one of the input transistor and the control circuit. The control circuit may be configured to generate a control signal (e.g., bias voltage VBIAS1), and the control signal may be applied to at least one of the input transistors through the virtual bit line to adjust the resistance of the at least one input transistor. By adjusting the resistance of the at least one input transistor according to changing external conditions, the bit line resistance R connected to each switch circuit can be compensated. BL .

[0191] As Figure 12B shown, in another example, each memory cell may be connected to a corresponding sense amplifier circuit through an adjustable resistor. The memory may further include a virtual line coupled to at least one of the adjustable resistor and the resistance control circuit. The resistance control circuit may be configured to generate a resistance control signal. The virtual bit line may be configured to transmit the resistance control signal to at least one adjustable resistor to control the resistance of the at least one adjustable resistor. By adjusting the resistance of the at least one adjustable resistor according to changing conditions, the resistance connected to each bit line of the sense amplifier circuit can be adjusted to compensate for the changing bit line resistance R. BL .

[0192] In some embodiments, the memory may be connected to a reference resistor, which may be a standard resistor whose resistance under specific conditions has been accurately determined. The resistance of the adjustable resistor may be adjusted according to the measured resistance of the reference resistor under the current conditions to compensate for the varying bit line resistance R BL . In one example, the reference resistor may be connected in a voltage dividing circuit, and the resistance of the reference resistor under the current conditions may be determined by measuring the voltage across the reference resistor. Other suitable methods may also be used to measure the resistance of the reference resistor under the current conditions, and the present invention is not limited thereto.

[0193] As Figure 13 shown, in another example, each memory cell may be connected to a corresponding sense amplifier circuit through an adjustable capacitor. In some embodiments, the adjustable capacitor may be a PN junction capacitor, and its capacitance may be adjusted by the voltage applied to the PN junction gate node. In some embodiments, the adjustable capacitor may include a plurality of capacitors connected in series or in parallel with each other. The capacitance adjustment circuit may be coupled to the plurality of capacitors and may be configured to select one or more capacitors from the plurality of capacitors to be connected to the sense amplifier circuit, thereby adjusting the capacitance of the adjustable capacitor.

[0194] The memory may further include a virtual bit line coupled to at least one of the adjustable capacitor and the capacitance control circuit. The capacitance control circuit may be configured to generate a capacitance control signal. The virtual bit line may be configured to transmit the capacitance control signal to at least one adjustable capacitor to control the capacitance of at least one adjustable capacitor. In one example, the capacitance control signal may be provided to the corresponding capacitance adjustment circuit to adjust the capacitance of at least one adjustable capacitor. By adjusting the capacitance of at least one adjustable capacitor according to the changing external conditions, the capacitance connected to each bit line of the sense amplifier circuit may be adjusted to compensate for the bit line parasitic capacitance C BL .

[0195] In some embodiments, the memory may include a memory cell matrix that includes multiple rows and multiple columns of memory cells. Each column of memory cells may be connected to a bit line, and each row of memory cells may be connected to a word line. In this case, a virtual bit line may be provided for every predetermined number of bit lines. In one example, the predetermined number may be 100. The predetermined number may be determined according to specific needs, and the present invention is not limited thereto.

[0196] Based on the above-described sense amplifier circuit and its operation method, the present invention further provides an input-related offset voltage compensation method applicable to an amplifier circuit. The method may include: connecting a first node of the amplifier circuit to a second node of the amplifier circuit through a control circuit coupled to the amplifier circuit to converge the voltages on the first node and the second node. Separating the first node from the second node through the control circuit; determining a compensation time; turning on the amplifier circuit during the compensation time to generate a first signal and a second signal, where the first signal is generated at the first node and the second signal is generated at the second node; and routing the first signal to the second node and routing the second signal to the first node through the control circuit to compensate for the input-related offset voltage of the amplifier circuit.

[0197] In some embodiments, in the above method, the input-related offset voltage of the amplifier circuit may include the difference between the threshold voltages of the corresponding transistors in the amplifier circuit, and turning on the amplifier circuit during the compensation time to generate a first signal and a second signal may include: determining the compensation time; and turning on the amplifier circuit during the compensation time to generate a first signal and a second signal. The difference between the first signal and the second signal reflects the difference between the threshold voltages.

[0198] In some embodiments, in the above method, determining the compensation time may include: determining the compensation time based on the transconductance of the amplifier circuit, the bit line resistance, and the bit line parasitic capacitance of the amplifier circuit.

[0199] In some embodiments, in the above method, determining the compensation time may include: establishing a compensation time lookup table, which may include a plurality of compensation durations, each compensation duration corresponding to a specific condition. Determining the current condition; determining the compensation time by looking up the compensation time corresponding to the current condition in the lookup table.

[0200] In some embodiments, in the above method, turning on the amplifier circuit during the compensation time to generate a first signal and a second signal may include: turning on the amplifier circuit by providing a pull-up voltage and a pull-down voltage to the amplifier circuit. The above method may further include: performing a calibration process to determine the pull-up voltage and the pull-down voltage.

[0201] In some embodiments, the above method may further include: receiving input signal pairs for amplification at the first node and the second node, respectively. The input signal pairs may be superimposed on the second signal at the first node and the first signal at the second node, respectively.

[0202] The present invention also provides another input-related offset voltage compensation method, which is applicable to an amplifier circuit having a first sub-circuit and a second sub-circuit and having an input-related offset voltage. The method may include generating, in response to a voltage signal, a first signal by the first sub-circuit at a first I / O of the amplifier circuit, and generating a second signal by the second sub-circuit at a second I / O of the amplifier circuit, wherein the difference between the first signal and the second signal reflects the input-related offset voltage in the circuit; connecting the first signal to the second I / O and connecting the second signal to the first I / O through a compensation circuit coupled to the amplifier circuit to compensate for the input-related offset voltage.

[0203] In some embodiments, in the above circuit, the compensation circuit may include: a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. A first end of the first switch circuit may be connected to a first end of the second switch circuit at the first I / O. A first end of the third switch circuit may be connected to a first end of the fourth switch circuit at the second I / O. A second end of the first switch circuit may be connected to a second end of the fourth switch at an output end of the second sub-circuit, and a second end of the second switch circuit may be connected to a second end of the third switch circuit at an output end of the first sub-circuit.

[0204] In some embodiments, in the above method, the first sub-circuit generates a first signal at the first I / O of the amplifier circuit, and the second sub-circuit generates a second signal at the second I / O of the amplifier circuit, which may include: by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit, the first sub-circuit generates a first signal at the first I / O, and the second sub-circuit generates a second signal at the second I / O.

[0205] In the above method, through the compensation circuit, the first signal is connected to the second I / O, and the second signal is connected to the first I / O. When the circuit receives input signals from the first I / O and the second I / O, the input signals are superimposed on the first signal and the second signal, so that the input-related offset voltage of the circuit can be compensated.

[0206] The drawings only illustrate a series of processes included in the method according to some embodiments of the present invention, rather than being restrictive. It is easy to understand that the way of illustrating these processes does not represent any time sequence of them or limit them to a specific time sequence. In addition, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0207] Other embodiments of the present invention will be apparent to those skilled in the art by considering the specification and practicing the embodiments disclosed herein. Accordingly, the present invention is intended to cover all and any variations, uses, or adaptations of the present invention that substantially follow the principles of the present invention and include departures from the present invention within the scope of common general knowledge or practice in the art to which the present invention pertains. It is also intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the appended claims.

Claims

1. A sense amplifier circuit, comprising: An amplifier circuit configured to amplify a voltage signal applied between a first bit line and a second bit line, comprising: A first inverter amplifier and a second inverter amplifier, an input terminal of the first inverter amplifier is connected to an output terminal of the second inverter amplifier at a first node, an input terminal of the second inverter amplifier is connected to an output terminal of the first inverter amplifier at a second node, the first inverter amplifier includes a first transistor and a second transistor, the second inverter amplifier includes a third transistor and a fourth transistor, a gate of the first transistor, a gate of the second transistor, a second end of the third transistor, and a first end of the fourth transistor are directly connected together to form an input terminal of the first inverter amplifier and an output terminal of the second inverter amplifier at the first node, a gate of the third transistor, a gate of the fourth transistor, a second end of the first transistor, and a first end of the second transistor are directly connected together to form an input terminal of the second inverter amplifier and an output terminal of the first inverter amplifier at the second node; A compensation circuit coupled to the amplifier circuit and configured to: In an equalization stage, control the first bit line to be connected to the first node and the second node, and control the second bit line to be connected to the first node and the second node; In an offset compensation stage, maintain the connection between the first bit line and the first node, maintain the connection between the second bit line and the second node, disconnect the connection between the first bit line and the second node, and disconnect the connection between the second bit line and the first node until the amount of charge injected into the first bit line and the second bit line is equal to a pre-calculated amount of charge that can compensate for the input-related offset voltage of the amplifier circuit; Disconnect the connection between the first bit line and the first node, and disconnect the connection between the second bit line and the second node.

2. The sense amplifier circuit according to claim 1, wherein, The compensation circuit includes one or more capacitive elements.

3. The sense amplifier circuit according to claim 2, wherein, The one or more capacitive elements include Ni capacitors or bit line parasitic capacitors.

4. The sense amplifier circuit according to claim 1, wherein, A first end of the first transistor and a first end of the third transistor are connected to a voltage node, and a second end of the second transistor and a second end of the fourth transistor are connected to a ground node.

5. The sense amplifier circuit according to claim 4, wherein, The compensation circuit includes: A first switch circuit; A second switch circuit; A third switch circuit; and A fourth switch circuit, wherein, a first end of the first switch circuit is connected to a first end of the second switch circuit at the first bit line, a first end of the third switch circuit is connected to a first end of the fourth switch circuit at the second bit line, a second end of the first switch circuit is connected to a second end of the fourth switch circuit at the first node, and a second end of the second switch circuit is connected to a second end of the third switch circuit at the second node.

6. The sense amplifier circuit according to claim 5, wherein, Each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit includes an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate.

7. The sense amplifier circuit according to claim 6, further comprising a switch control circuit coupled to the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit, Among them, The switch control circuit is configured to control the on-state of each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit.

8. The sense amplifier circuit according to claim 6, further comprising: A transconductance compensation circuit coupled to the pull-up circuit and the pull-down circuit, the pull-up circuit being coupled to the voltage node, and the pull-down circuit being coupled to the ground node, Wherein, the transconductance compensation circuit includes a temperature sensor for sensing temperature and is configured to provide compensation currents to the pull-up circuit and the pull-down circuit respectively to compensate for the change in the transconductance of the sense amplifier circuit caused by temperature change.

9. The sense amplifier circuit according to claim 5, wherein, The compensation circuit is configured to generate a compensation voltage between the first bit line and the second bit line by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to compensate for the input-related offset voltage of the amplifier circuit.

10. The sense amplifier circuit according to claim 9, wherein, Generating the compensation voltage between the first bit line and the second bit line to compensate for the input-related offset voltage of the amplifier circuit includes: Turning on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; Turning off the second switch circuit and the fourth switch circuit during the compensation time to generate the compensation voltage between the first bit line and the second bit line; and Turning off the first switch circuit and the third switch circuit.

11. The sense amplifier circuit according to claim 1, The compensation circuit is configured to perform a charging operation during the offset compensation phase to charge at least one of the first bit line and the second bit line, Among them, At the end of the charging operation, the voltage difference between the proximal ends of the first bit line and the second bit line is greater than the input-related offset voltage of the amplifier circuit.

12. The sense amplifier circuit according to claim 11, wherein, At the end of the charging operation, the voltage difference between the proximal ends of the first bit line and the second bit line is 10% - 40% larger than the input-related offset voltage of the amplifier circuit.

13. The sense amplifier circuit according to claim 1, wherein, The gain of the sense amplifier circuit is greater than 1 during the offset compensation phase.

14. A memory, comprising: A plurality of memory cells; And A plurality of sense amplifier circuits, wherein each of the plurality of sense amplifier circuits is the sense amplifier circuit according to claim 1, Among them, for each of the multiple sense amplifier circuits, each of the first bit line and the second bit line is connected to one of the multiple memory cells.

15. The memory according to claim 14, wherein, In each of the multiple sense amplifier circuits, the compensation circuit includes: A first switch circuit; A second switch circuit; A third switch circuit; and A fourth switch circuit, wherein a first end of the first switch circuit is connected to a first end of the second switch circuit at the first bit line, a first end of the third switch circuit is connected to a first end of the fourth switch circuit at the second bit line, a second end of the first switch circuit is connected to a second end of the fourth switch circuit at an output end of the second inverter amplifier, and a second end of the second switch circuit is connected to a second end of the third switch circuit at an output end of the first inverter amplifier.

16. The memory according to claim 15, wherein, Each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit in each of the multiple sense amplifier circuits includes an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate.

17. The memory according to claim 16, wherein in each of the multiple sense amplifier circuits, a bias voltage is provided to at least one of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to control a conduction state of the corresponding switch circuit.

18. The memory according to claim 16, wherein, Each memory cell is connected to a corresponding sense amplifier circuit through an adjustable resistor, wherein the memory further includes: A virtual bit line coupled to at least one of the adjustable resistors and a resistance control circuit, wherein the resistance control circuit is configured to generate a resistance control signal, and the virtual bit line is configured to transmit the resistance control signal to the at least one adjustable resistor to control a resistance of the at least one adjustable resistor.

19. The memory according to claim 18, wherein, The memory is connected to a reference resistor and generates the resistance control signal based on a measured resistance of the reference resistor.

20. The memory according to claim 16, wherein, Each memory cell is connected to a corresponding sense amplifier circuit through an adjustable capacitor, wherein the memory further includes: A virtual bit line coupled to at least one of the adjustable capacitors and a capacitance control circuit, wherein the capacitance control circuit is configured to generate a capacitance control signal, and the virtual bit line is configured to transmit the capacitance control signal to the at least one adjustable capacitor to control a capacitance of the at least one adjustable capacitor.

21. An input-related offset voltage compensation method applicable to the sense amplifier circuit according to claim 1, the method including: Generating a compensation voltage between the first bit line and the second bit line by operating the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to compensate for an input-related offset voltage of the amplifier circuit; During the equalization phase, control the first bit line to be connected to the first node and the second node, and control the second bit line to be connected to the first node and the second node; During the offset compensation phase, maintain the connection between the first bit line and the first node, maintain the connection between the second bit line and the second node, disconnect the connection between the first bit line and the second node, and disconnect the connection between the second bit line and the first node until the amount of charge injected into the first bit line and the second bit line is equal to a pre-calculated amount of charge that can compensate for the input-referred offset voltage of the amplifier circuit; Disconnect the connection between the first bit line and the first node, and disconnect the connection between the second bit line and the second node.

22. The method according to claim 21, wherein, Generating the compensation voltage between the first bit line and the second bit line to compensate for the input-referred offset voltage of the amplifier circuit includes: Turn on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; Determine the compensation time; During the compensation time, disconnect the second switch circuit and the fourth switch circuit to generate the compensation voltage between the first bit line and the second bit line; and Disconnect the first switch circuit and the third switch circuit.

23. The method according to claim 22, wherein At the end of the compensation time, the voltage difference between the proximal ends of the first bit line and the second bit line is greater than the input-referred offset voltage of the amplifier circuit.

24. The method according to claim 23, wherein At the end of the compensation time, the voltage difference between the proximal ends of the first bit line and the second bit line is 10% - 40% greater than the input-referred offset voltage of the amplifier circuit.

25. The method according to claim 22, wherein, The gain of the sense amplifier circuit is greater than 1 during the compensation time.

26. The method according to claim 22, wherein, Turning on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit includes: Turn on the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit to converge the voltages of the first bit line, the second bit line, the output terminal of the first inverting amplifier, and the output terminal of the second inverting amplifier to a voltage level.

27. The method according to claim 21, further comprising: After generating the compensation voltage between the first bit line and the second bit line, Provide an input signal between the first bit line and the second bit line; Provide a pull-up voltage to the voltage node; Provide a pull-down voltage to the ground node; And Turn on the second switch circuit and the fourth switch circuit to amplify the input signal, while the first switch circuit and the third switch circuit remain off.

28. The method according to claim 27, further comprising: After turning on the second switch circuit and the fourth switch circuit to amplify the input signal, Disconnect the sense amplifier circuit from the first bit line and the second bit line by operating the second switch circuit and the fourth switch circuit; Keep the sense amplifier circuit disconnected from the first bit line and the second bit line for a predetermined period of time; And Reconnect the sense amplifier circuit to the first bit line and the second bit line by operating the second switch circuit and the fourth switch circuit.

29. The method according to claim 28, wherein, Reconnecting the sense amplifier circuit to the first bit line and the second bit line includes: The sense amplifier circuit is reconnected to the first bit line and the second bit line by setting each of the second switch circuit and the fourth switch circuit to a partially conductive state.

30. The method according to claim 27, further comprising: Performing a calibration process, comprising: Selecting one or more candidate pull-up circuits from a plurality of candidate pull-up circuits to be coupled to a voltage node of a replicated inverter amplifier, and selecting one or more candidate pull-down circuits from a plurality of candidate pull-down circuits to be coupled to a ground node of the replicated inverter amplifier, to make the output voltage of the replicated inverter amplifier close to a calibration voltage; Adjusting a candidate pull-up voltage provided to the selected one or more candidate pull-up circuits, and adjusting a candidate pull-down voltage provided to the selected one or more candidate pull-down circuits to make the output voltage closer to the calibration voltage; and Storing the adjusted candidate pull-up voltage and the adjusted candidate pull-down voltage in a register.

31. The method according to claim 30, wherein, The replicated inverter amplifier is a replicated circuit of the first inverter amplifier or the second inverter amplifier.

32. The method according to claim 30, wherein The performing the calibration process comprises: Repeatedly executing the calibration process at a fixed time interval.

33. The method according to claim 32, wherein, The fixed time interval is 100 ms.

34. The method according to claim 30, wherein, Providing a pull-up voltage to the voltage node comprises: Coupling the selected one or more candidate pull-up circuits to the voltage node; and Providing the adjusted candidate pull-up voltage to the voltage node through the selected one or more candidate pull-up circuits, And wherein providing a pull-down voltage to the ground node comprises: Coupling the selected one or more candidate pull-down circuits to the ground node; providing the adjusted candidate pull-down voltage to the ground node through the selected one or more candidate pull-down circuits.

35. The method according to claim 21, the method comprising: Connecting a first node of the amplifier circuit to a second node of the amplifier circuit through a control circuit coupled to the amplifier circuit, so that the voltage of the first node and the voltage of the second node converge; Separating the first node from the second node through the control circuit; Determining a compensation time; Turning on the amplifier circuit within the compensation time to generate a first signal and a second signal, wherein the first signal is generated at the first node and the second signal is generated at the second node; And Routing the first signal to the second node and routing the second signal to the first node through the control circuit to compensate for an input-related offset voltage of the amplifier circuit.

36. The method according to claim 35, wherein The determining the compensation time comprises: Determining the compensation time based on a transconductance of the amplifier circuit, a bit line resistance, and a bit line parasitic capacitance of the amplifier circuit.

37. The method according to claim 35, wherein The determining the compensation time comprises: Establishing a look-up table for the compensation time, wherein the look-up table includes a plurality of compensation durations, and each compensation duration corresponds to a specific condition; Determining a current condition; and Determining the compensation time by looking up a compensation duration corresponding to the current condition in the look-up table.

38. The method according to claim 35, wherein, Turning on the amplifier circuit during the compensation time to generate the first signal and the second signal includes: Turning on the amplifier circuit by providing a pull-up voltage and a pull-down voltage to the amplifier circuit, And, the method further includes: Performing a calibration process to determine the pull-up voltage and the pull-down voltage.

39. The method according to claim 35, further includes: Receiving an input signal pair for amplification at the first node and the second node respectively, wherein the input signal pair is superimposed on the second signal at the first node and the first signal at the second node respectively.

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