Cross-point array of ferroelectric field effect transistors and method for manufacturing the same

Abstract

The present invention discloses a semiconductor structure comprising a layer stack structure extending laterally along a first horizontal direction and spaced apart from each other along a second horizontal direction by line grooves. Each layer stack structure in the layer stack structure comprises at least one instance of a unit layer sequence, which comprises, from bottom to top or from top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. A line trench filling structure is located within a corresponding one of the line trenches. Each line trench filling structure in the line trench filling structure comprises a laterally alternating sequence of a memory pillar structure and a dielectric pillar structure. Each memory pillar structure in the memory pillar structure comprises a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strip.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, and more particularly to cross-point arrays of ferroelectric field effect transistors and methods of fabricating the same. Background Art

[0002] Ferroelectric materials are materials that exhibit spontaneous polarization in the absence of an applied electric field. The net polarization P of the charge within a ferroelectric material is nonzero in its minimum energy state. Consequently, the material undergoes spontaneous ferroelectric polarization, and surface charges of opposite polarity accumulate on two opposing surfaces. The polarization P of a ferroelectric material exhibits hysteresis as a function of applied voltage V. The product of a ferroelectric material's remnant polarization and its coercive field is a measure used to characterize its effectiveness.

[0003] A ferroelectric memory device is a memory device that contains a ferroelectric material for storing information. The ferroelectric material serves as the memory material of the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the ferroelectric material's dipole moment is programmed to adopt two different orientations (e.g., "up" or "down" polarization positions based on the positions of atoms in the crystal lattice (such as oxygen and / or metal atoms)), thereby storing information in the ferroelectric material. The different orientations of the ferroelectric material's dipole moment can be detected by the electric field generated by the ferroelectric material's dipole moment. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in a field-effect transistor ferroelectric memory device. Summary of the Invention

[0004] According to aspects of the present disclosure, a semiconductor structure is provided, which includes: a layer stack structure that extends laterally along a first horizontal direction and is separated from each other along a second horizontal direction by line grooves, wherein each layer stack structure in the layer stack structure includes at least one instance of a unit layer sequence, which unit layer sequence includes, from bottom to top or from top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip; and a line trench filling structure that is located in a corresponding one of the line trenches, wherein each line trench filling structure in the line trench filling structure includes a laterally alternating sequence of memory pillar structures and dielectric pillar structures, and wherein each memory pillar structure in the memory pillar structure includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strip.

[0005] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a layer stack structure extending laterally along a first horizontal direction and spaced apart from each other along a second horizontal direction by line grooves, wherein each layer stack structure in the layer stack structure comprises at least one instance of a unit layer sequence, the unit layer sequence comprising, from bottom to top or from top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip; forming an in-process line trench filling structure comprising at least one pair of semiconductor channel material strips, a pair of ferroelectric dielectric plates, and a sacrificial filling material track within each line trench; dividing each in-process line trench filling structure into a row of in-process memory pillar structures by etching a pillar cavity through each in-process line trench filling structure; forming a dielectric pillar structure in the pillar cavity; and replacing the remaining portion of the sacrificial filling material track with a gate electrode, whereby a memory pillar structure comprising a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels is formed in each volume of the in-process memory pillar structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the drawings of the present disclosure, drawings with the same reference numerals represent the same structure. Each figure with the letter suffix A is a top view, i.e., a plan view. For example, Figure 1A 、 Figure 2A 、 Figure 3A etc. are top views. Each figure with a letter suffix B is a vertical sectional view along the vertical plane B-B' in the figure with the same figure number and the letter suffix A. Each figure with a letter suffix C is a vertical sectional view along the vertical plane C-C' in the figure with the same figure number and the letter suffix A. Each figure with a letter suffix D is a vertical sectional view along the vertical plane D-D' in the figure with the same figure number and the letter suffix A. Each figure with a letter suffix E is a vertical sectional view along the vertical plane E-E' in the figure with the same figure number and the letter suffix A. For example, Figure 2B It is along Figure 2A A vertical cross-section of plane B-B', Figure 2C It is along Figure 2A A vertical cross-section of plane C-C', and Figure 2D It is along Figure 1A Vertical cross-section of plane D-D'. Figures 1A to 1C Some structures are shown in a top view and two vertical cross-sectional views, some other structures are shown in a top view and three vertical cross-sectional views, and still other structures are shown in a top view and four vertical cross-sectional views.

[0007] Figure 1A 、 Figure 1B and Figure 1CVarious views of an exemplary structure after forming multiple instances of a cell layer sequence according to an embodiment of the present disclosure, the cell layer sequence including, from bottom to top, a metal source layer, a doped semiconductor source layer, a channel-level insulating layer, a doped semiconductor drain layer, a metal drain layer, and an inter-transistor-level insulating layer.

[0008] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D are various views of an exemplary structure after forming line trenches according to an embodiment of the present disclosure.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are various views of an exemplary structure after forming laterally extending grooves according to embodiments of the present disclosure.

[0010] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D are various views of an exemplary structure after forming strips of semiconductor channel material according to an embodiment of the present disclosure.

[0011] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D are various views of an exemplary structure after forming a continuous gate dielectric layer according to an embodiment of the present disclosure.

[0012] Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D are various views of an exemplary structure after forming a first metal liner plate and a first ferroelectric dielectric plate according to an embodiment of the present disclosure.

[0013] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D are various views of an exemplary structure after forming a sacrificial fill structure according to an embodiment of the present disclosure.

[0014] Figure 8A 、 Figure 8B 、 Figure 8C and Figure 8D are various views of an exemplary structure after recessing the first metal liner plate and the first ferroelectric dielectric plate according to embodiments of the present disclosure.

[0015] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D are various views of an exemplary structure after forming vertical dielectric spacers according to an embodiment of the present disclosure.

[0016] Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D are various views of an exemplary structure after forming a second metal liner plate and a second ferroelectric dielectric plate according to an embodiment of the present disclosure.

[0017] Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D are various views of an exemplary structure after forming a sacrificial fill structure according to an embodiment of the present disclosure.

[0018] Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D Various views of an exemplary structure after forming a track of sacrificial fill material within each wire cavity according to an embodiment of the present disclosure.

[0019] Figure 13A 、 Figure 13B 、 Figure 13C and Figure 13D are various views of an exemplary structure after forming a post cavity array according to an embodiment of the present disclosure.

[0020] Figure 14A 、 Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E Various views of an exemplary structure after column cavity expansion according to embodiments of the present disclosure.

[0021] Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D and Figure 15E are various views of an exemplary structure after forming an array of dielectric post structures according to an embodiment of the present disclosure.

[0022] Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D and Figure 16E are various views of an exemplary structure after forming a gate cavity according to an embodiment of the present disclosure.

[0023] Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D and Figure 17E are various views of an exemplary structure after forming a gate electrode in a gate cavity according to an embodiment of the present disclosure.

[0024] Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D and Figure 18E are various views of an exemplary structure after forming a gate contact via structure and a global gate line according to an embodiment of the present disclosure.

[0025] Figure 19A 、 Figure 19B 、 Figure 19C 、 Figure 19D and Figure 19E Various views of alternative configurations of exemplary structures according to embodiments of the present disclosure. Figure 19F and Figure 19G is a side cross-sectional view of another alternative configuration of an exemplary structure according to another embodiment of the present disclosure.

[0026] Figure 20 yes 18A to 18E A circuit diagram of a portion of an exemplary structure. DETAILED DESCRIPTION

[0027] As discussed above, embodiments of the present disclosure relate to a cross-point array of ferroelectric field effect transistors and a method for manufacturing the same, various aspects of which are described below.

[0028] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0029] The same reference numerals represent the same or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0030] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of a first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0031] A monolithic three-dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a semiconductor wafer, without intervening substrates. The term "monolithic" refers to the fact that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed on separate substrates, such memories are not true monolithic three-dimensional memory arrays.

[0032] refer to Figure 1A 、 Figure 1B and Figure 1C, shows an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 8, which can be a semiconductor substrate such as a commercially available wafer. Optionally, semiconductor devices (not shown) such as complementary metal oxide semiconductor (CMOS) transistors can be formed on the top surface of substrate 8. The CMOS transistors can include control (i.e., driver) circuitry for controlling a memory array subsequently formed thereon.

[0033] A planar dielectric isolation layer 14 comprising a dielectric material such as silicon oxide may be formed over substrate 8. In the event that semiconductor devices are formed on the top surface of substrate 8, planar dielectric isolation layer 14 may be formed over such semiconductor devices (such as field effect transistors). In one embodiment, planar dielectric isolation layer 14 may be planarized to provide a level top surface. The thickness of planar dielectric isolation layer 14 may be in the range of 50 nm to 500 nm, although lesser and greater thicknesses may also be used.

[0034] At least one instance of a cell layer sequence may be formed above the planar dielectric isolation layer 14. Each instance of the cell layer sequence may include a metal source layer 42L, a doped semiconductor source layer 44L, a channel-level insulating layer 32L, a doped semiconductor drain layer 46L, a metal drain layer 48L, and an inter-transistor insulating layer 30L (also referred to as a second insulating layer) above the planar dielectric isolation layer 14. The metal source layer 42L may contact a surface of the doped semiconductor source layer 44L and may be vertically spaced apart from the channel-level insulating layer 32L within each cell layer sequence by the doped semiconductor source layer 44L. The metal drain layer 48L may contact the doped semiconductor drain layer 46L and may be vertically spaced apart from the channel-level insulating layer 32L by the doped semiconductor drain layer 46L.

[0035] As used herein, a "unit layer sequence" refers to a layer stack of multiple layers used as a repeating unit within a structure of multiple instances of a repeating layer stack. In the topmost instance of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L), a topmost insulating layer may be formed instead of the inter-transistor insulating layer 30L. In one embodiment, multiple (e.g., two) instances of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L) may be formed above the planar dielectric isolation layer 14, such as Figure 1B and Figure 1C Alternatively, a single instance of the sequence of unit layers (42L, 44L, 32L, 46L, 48L, 30L) may be formed over the planar dielectric isolation layer 14, as will be described below with respect to Figures 19A to 19EThe total number of repetitions of the cell layer sequence (42L, 44L, 32L, 46L, 48L, 30L) can be the same as the total number of levels of subsequently formed vertical field-effect transistors, which in turn can be the same as the total number of levels of subsequently formed memory elements. As used herein, "level" refers to the volume of a device located between a horizontal plane including the top surface of an element of the device and a horizontal plane including the bottom surface of the element of the device.

[0036] Therefore, channel-level insulating layer 32L is an insulating layer formed between a horizontal plane including the top surface of a semiconductor channel to be formed later and a horizontal plane including the bottom surface of the semiconductor channel to be formed later. If at least two of the cell layer sequences (42L, 44L, 32L, 46L, 48L, 30L) are formed, inter-transistor-level insulating layer 30L is an insulating layer formed between a horizontal plane including the top surface of an inter-transistor gap to be formed later and a horizontal plane including the bottom surface of the inter-transistor gap to be formed later. When multiple instances of the cell layer sequence (42L, 44L, 32L, 46L, 48L, 30L) are formed, the number of repetitions of the cell layer sequence in the multiple instances of the cell layer sequence can be in the range of 2 to 1,024, such as 8 to 128, but a smaller or larger number of repetitions can also be used.

[0037] although Figures 1B to 1C An embodiment is shown in which the unit layer sequence includes a layer stack in which a metal source layer 42L, a doped semiconductor source layer 44L, a channel-level insulating layer 32L, a doped semiconductor drain layer 46L, a metal drain layer 48L, and an inter-transistor-level insulating layer 30L are arranged from bottom to top, but embodiments in which the layer stack is arranged in a manner similar to that of FIG. Figures 1B to 1C Typically, because the source and drain regions can be symmetrical in a field effect transistor, the positions of the source elements (42L, 44L) can be swapped with the positions of the drain elements (46L, 48L).

[0038] The inter-transistor insulating layer 30L and the channel-level insulating layer 32L are collectively referred to herein as insulating layers. Each of the insulating layers (30L, 32L) comprises a corresponding insulating material, such as doped silicate glass, undoped silicate glass (e.g., silicon oxide), a metal oxide (e.g., aluminum oxide), or organosilicate glass. The thickness of each channel-level insulating layer 32L may be in the range of 20 nm to 80 nm, and the thickness of each inter-transistor insulating layer 30L may be in the range of 10 nm to 60 nm, although smaller and larger thicknesses may also be employed.

[0039] According to an embodiment of the present disclosure, channel-level insulating layer 32L includes a first insulating material, and inter-transistor insulating layer 30L includes a different second insulating material that can provide an etch rate lower than that of the first insulating material in an isotropic etching process. For example, channel-level insulating layer 32L can include borosilicate glass or porous or non-porous organosilicate glass, and inter-transistor insulating layer 30L can include undoped silicate glass (e.g., silicon oxide). In this case, the etch rate of the material of channel-level insulating layer 32L in 100:1 diluted hydrofluoric acid can be at least 10 times, such as 100 times or more, greater than the etch rate of the material of inter-transistor insulating layer 30L in 100:1 diluted hydrofluoric acid. In another embodiment, inter-transistor insulating layer 30L can include a semiconductor oxide material (e.g., undoped silicate glass formed by the decomposition of tetraethyl orthosilicate), and channel-level insulating layer 32L can include a metal oxide (e.g., aluminum oxide) that has a higher etch rate than silicon oxide in an aluminum oxide-selective etchant.

[0040] The doped semiconductor source layer 44L and the doped semiconductor drain layer 46L include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon that may be subsequently annealed to form doped polysilicon. The conductivity type of the doped semiconductor source layer 44L and the doped semiconductor drain layer 46L is referred to herein as a first conductivity type, which may be p-type or n-type.

[0041] As used herein, "semiconductor material" refers to a material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0 × 10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0 × 10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state). 5 S / m) of semiconductor material. The "doped semiconductor material" may be a heavily doped semiconductor material, or may include a material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5 A semiconductor material containing an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with an electrical conductivity in the range of 100 s / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be either semiconducting or conductive, and can be either an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be either semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element. All conductivity measurements are performed under standard conditions.

[0042] The atomic concentration of the first conductivity type dopant in the doped semiconductor source layer 44L and the doped semiconductor drain layer 46L may be within a range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 The thickness of each doped semiconductor source layer 44L may be in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, and the thickness of each and the thickness of each doped semiconductor drain layer 46L may be in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0043] Metal source layer 42L and metal drain layer 48L include a metallic material, such as an elemental metal, an intermetallic alloy, a conductive metal nitride material, a conductive metal carbide material, or a metal-semiconductor alloy (e.g., a silicide). For example, metal source layer 42L and metal drain layer 48L may include tungsten, tantalum, titanium, ruthenium, molybdenum, their intermetallic alloys, titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, tungsten carbide, tungsten silicide, titanium silicide, alloys of at least two of the foregoing materials, and / or layer stacks of at least two of the foregoing materials. In one embodiment, metal source layer 42L and metal drain layer 48L may include tungsten and / or may consist essentially of tungsten. The thickness of each metal source layer 42L may be in the range of 10 nm to 50 nm, such as 20 nm to 30 nm, and the thickness of each and each metal drain layer 48L may be in the range of 10 nm to 50 nm, such as 20 nm to 30 nm, although smaller and larger thicknesses may also be employed.

[0044] Various examples of the cell layer sequence (42L, 44L, 32L, 46L, 48L, 30L) may include a first alternating stack of doped semiconductor source layers 44L and doped semiconductor drain layers 46L interleaved with a second alternating stack of channel-level insulating layers 32L and inter-transistor-level insulating layers 30L. Insulating layers (32L, 30L) are formed between each vertically adjacent pair of doped semiconductor source layers 44L and doped semiconductor drain layers 46L. Channel-level insulating layer 32L is formed between each vertically adjacent pair of doped semiconductor source layers 44L and doped semiconductor drain layers 46L. In one embodiment, each of the metal source layers 42L is formed below a corresponding one of the doped semiconductor source layers 44L, and each of the metal drain layers 48L is formed above a corresponding one of the doped semiconductor drain layers 46L.

[0045] refer to Figures 2A to 2D A photoresist layer (not shown) can be applied over the topmost one of the sequence of unit layers (42L, 44L, 32L, 46L, 48L, 30L) and can be photolithographically patterned to form linear openings extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The width of each linear opening can be uniform. In one embodiment, the pattern of the linear openings can be periodic along the second horizontal direction. The width of each linear opening can be the same and can be in the range of 60 nm to 300 nm, although smaller and larger widths are also possible. The spacing between each adjacent pair of linear openings can be in the range of 60 nm to 300 nm, although smaller and larger spacings are also possible.

[0046] An anisotropic etching process may be performed to transfer a pattern to the photoresist layer through at least one instance of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L). Line trenches 49 may be formed through each instance of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L). Line trenches 49 extend laterally along a first horizontal direction hd1 and divide at least one instance of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L) into layer stacks 120. Layer stacks 120 extend laterally along the first horizontal direction and are separated from each other along a second horizontal direction hd2 by line trenches 49.

[0047] Each patterned portion of metal source layer 42L includes metal source strips 42. Each patterned portion of doped semiconductor source layer 44L includes doped semiconductor source strips 44. Each patterned portion of channel-level insulating layer 32L includes channel-level insulating strips 32. Each patterned portion of doped semiconductor drain layer 46L includes doped semiconductor drain strips 46. Each patterned portion of metal drain layer 48L includes metal drain strips 48. Each patterned portion of inter-transistor insulating layer 30L includes inter-transistor insulating strips 30.

[0048] Each layer stack structure in the layer stack structure 120 includes at least one instance of the unit layer sequence (42, 44, 32, 36, 38, 30). Each unit layer sequence (42, 44, 32, 36, 38, 30) includes, from bottom to top or from top to bottom, a metal source strip 42, a doped semiconductor source strip 44, a channel-level insulating strip 32, a doped semiconductor drain strip 46, a metal drain strip 48, and an inter-transistor-level insulating strip 30. Each metal source strip 42 contacts the doped semiconductor source strip 44. Each metal drain strip 48 contacts the doped semiconductor drain strip 46. In one embodiment, each layer stack structure in the layer stack structure 120 may include multiple instances of the unit layer sequence (42, 44, 32, 36, 38, 30) stacked vertically.

[0049] refer to Figures 3A to 3DA laterally extending recess (i.e., recess) 349 can be formed at each level of the channel-level insulating layer 32L by laterally recessing the channel-level insulating layer 32L relative to the inter-transistor insulating layer 30L, the doped semiconductor source layer 44L, the doped semiconductor drain layer 46L, the metal source layer 42L, and the metal drain layer 48L. Line trenches 49 laterally expand at each level of the channel-level insulating layer 32L by the volume of the laterally extending recess 349. As discussed above, in an isotropic etching process, the first insulating material of the channel-level insulating layer 32L provides a greater etch rate than the second insulating material of the inter-transistor insulating layer 30L. If the channel-level insulating layer 32L comprises doped silicate glass, the isotropic etching process can be a wet etching process using 100:1 diluted hydrofluoric acid, or if the channel-level insulating layer 32L comprises aluminum oxide, the isotropic etching process can be a wet etching process using an aluminum oxide selective etching medium.

[0050] A vertical stack of laterally extending grooves 349 may be formed around each of the line-trenches 49. The height of each laterally extending groove 349 may be the same as the height of the channel-level insulating layer 32L, which is formed at the same level as the corresponding laterally extending groove 349. The lateral recess distance of each of the laterally extending grooves 349 may be in a range of 3 nm to 60 nm, such as 6 nm to 30 nm, although smaller and larger lateral recess distances may also be employed. Each of the channel-level insulating strips 32 may contact a corresponding one of the doped semiconductor source strips 44 and a corresponding one of the doped semiconductor drain strips 46 and may have a width along the second horizontal direction hd2 that is less than the width of the corresponding one of the doped semiconductor source strips 44 along the second horizontal direction hd2 and less than the width of the corresponding one of the doped semiconductor drain strips 46 along the second horizontal direction hd2.

[0051] refer to Figures 4A to 4D , the semiconductor channel material layer can be deposited by a conformal deposition process such as a chemical vapor deposition process. The continuous semiconductor channel layer includes a semiconductor material doped with a second conductivity type, which is opposite to the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa. The semiconductor material in the continuous semiconductor channel layer may include silicon (e.g., polycrystalline silicon or amorphous silicon), a silicon-germanium alloy, or a compound semiconductor material. The atomic concentration of the second conductivity type dopant in the continuous semiconductor channel layer may be in the range of 1.0×10 14 / cm 3 to 3.0×10 17 / cm 3The thickness of the continuous semiconductor channel layer is greater than the lateral recess distance of the laterally extending recess 349. For example, the thickness of the continuous semiconductor channel layer can be in the range of 6 nm to 120 nm, such as 12 nm to 60 nm, but smaller and larger thicknesses can also be used.

[0052] Subsequently, the portion of the semiconductor channel material layer located outside the laterally extending recess 349 can be removed by performing an anisotropic etching process, such as a reactive ion etching process. Each remaining portion of the semiconductor channel material layer comprises a semiconductor channel material strip 60S. Generally, the semiconductor channel material strip 60S can be formed by filling the laterally extending recess 349 with a doped semiconductor material having the second conductivity type and by removing excess portions of the semiconductor material from the outer volume of the laterally extending recess 349. The remaining portion of the semiconductor material in the laterally extending recess comprises the semiconductor channel material strip 60S.

[0053] In the case where each layer stack structure 120 includes multiple instances of the unit layer sequence (42, 44, 32, 36, 38, 30), a vertical stack of semiconductor channel material strips 60S can be formed on each sidewall of the layer stack structure 120. Each vertical stack of semiconductor channel material strips 60S is formed as a group of semiconductor channel material strips 60S located in corresponding laterally extending grooves 349 and vertically spaced apart from each other, i.e., not in direct contact with each other. Each semiconductor channel material strip 60S can have a rectangular horizontal cross-sectional shape along a vertical plane perpendicular to the first horizontal direction hd1.

[0054] Each of the semiconductor channel material strips 60S contacts the sidewalls of a corresponding one of the channel-level insulating layers 32L. The insulating layers (32L, 30L) in multiple instances of the cell layer sequence include a channel-level insulating layer 32L that contacts the sidewalls of a corresponding one of the semiconductor channel material strips 60S, and an inter-transistor-level insulating layer 30L that does not contact any of the semiconductor channel material strips 60S. The sidewalls of the channel-level insulating layer 32L are laterally recessed outward relative to the sidewalls of the inter-transistor-level insulating layer 30L and relative to the sidewalls of the doped semiconductor source layer 44L and the doped semiconductor drain layer 46L surrounding each linear trench 49. Each of the channel-level insulating layers 32L may be in direct contact with the horizontal surface of a corresponding one of the doped semiconductor source layers 44L and the doped semiconductor drain layers 46L.

[0055] Before forming the memory film and local word lines (i.e., gate electrodes) such as vertical word lines, each of the semiconductor channel material strips 60S is formed on the horizontal surface of a corresponding vertically adjacent pair of doped semiconductor source layer 44L and doped semiconductor drain layer 46L. A vertical stack of vertical semiconductor channels 60 is formed in each of the line trenches 49. Each of the vertical semiconductor channels 60 is connected to a corresponding vertically adjacent pair of doped semiconductor source layer 44L and doped semiconductor drain layer 46L.

[0056] In one embodiment, the entire sidewall of each semiconductor channel material strip 60S contacts the vertical sidewall of the corresponding channel-level insulating layer 32L located between the corresponding vertically adjacent pair of doped semiconductor source layers 44L and doped semiconductor drain layers 46L. Each semiconductor channel material strip 60S can contact the horizontal surface of the corresponding vertically adjacent pair of doped semiconductor source layers 44L and doped semiconductor drain layers 46L. As described above, the doped semiconductor source layers 44L can be located such as Figures 1A to 1C The doped semiconductor source strips 44 may be located below or above the doped semiconductor drain layer 46L in each unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L) of the continuous material layer formed in the processing steps. Therefore, the doped semiconductor source strips 44 may be located below or above the doped semiconductor drain strips 46 in each unit layer sequence (42, 44, 32, 46, 48, 30).

[0057] The physically exposed sidewalls of the semiconductor channel material strips 60S may vertically coincide with sidewalls of other layers within the same layer stack structure 120. Therefore, each of the semiconductor channel material strips 60S may include a corresponding sidewall that vertically coincides with sidewalls of at least one doped semiconductor source strip 44 and at least one doped semiconductor drain strip 46 within the same layer stack structure 120.

[0058] refer to 5A to 5D , a continuous gate dielectric layer 50C can be deposited on the physically exposed surfaces of the layer stack structure 120 and the semiconductor channel material strips 60S. The continuous gate dielectric layer 50C may include any gate dielectric material known in the art. For example, the continuous gate dielectric layer 50C may include silicon oxide and / or a dielectric metal oxide material (such as aluminum oxide). The continuous gate dielectric layer 50C may be formed by a conformal deposition method such as a chemical vapor deposition (CVD) process and may have a thickness in the range of 1 nm to 12 nm, for example, 2 nm to 6 nm. Each vertically extending portion of the continuous gate dielectric layer 50C includes a pair of straight sidewalls that extend vertically through multiple levels of the layer stack structure 120 and are located in a corresponding planar vertical plane perpendicular to the second horizontal direction hd2.

[0059] refer to 6A to 6D A first continuous metal liner layer can be conformally deposited and anisotropically etched. For example, the first continuous metal liner layer can be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process. An anisotropic etching process, such as a reactive ion etching process, can be performed to remove horizontal portions of the first continuous metal liner layer. The remaining portion of the first continuous metal liner in each linear trench 49 includes a pair of first metal liner plates 152P. The first metal liner plates 152P include a metallic (i.e., conductive) material, such as a metal nitride material, an elemental metal, or an intermetallic alloy. For example, the first metal liner plates 152P can include materials such as TiN, TaN, WN, Ti, Ta, W, or alloys or stacks thereof. In one embodiment, the first metal liner plates 152P include TiN. The thickness of the first metal liner plates 152P can be in the range of 2 nm to 30 nm, such as 4 nm to 15 nm, although lesser and greater thicknesses may also be employed.

[0060] A first continuous ferroelectric dielectric layer comprising a ferroelectric dielectric material may be conformally deposited. For example, the first continuous ferroelectric dielectric layer may be deposited by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. An anisotropic etching process may be performed to remove horizontal portions of the first continuous ferroelectric dielectric layer. The remaining portion of the continuous ferroelectric dielectric layer in each linear trench 49 comprises a pair of first ferroelectric dielectric plates 154P. The first ferroelectric dielectric plates 154P comprise and / or consist essentially of at least one ferroelectric dielectric material, such as hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase), zirconium oxide, hafnium zirconium oxide, barium oxide, barium titanate (such as BaTiO3; BT), colemanite (such as Ca2B6O 11 5H2O), bismuth titanate (such as Bi4Ti3O 12 ), europium barium titanate, ferroelectric polymers, germanium telluride, anhydrous potassium magnesium sulfate (such as M2M ' 2(SO4)3, where M is a monovalent metal and M' is a divalent metal), lead scandium tantalum (such as Pb(Sc x Ta 1-x )O3), lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN), (LaAlO3)), polyvinylidene fluoride (CH2CF2) n , potassium niobate (such as KNbO3), sodium tartrate (such as KNaC4H4O6·4H2O), potassium titanyl phosphate (such as KO5PTi), sodium bismuth titanate (such as Na 0.5 Bi 0.5 TiO3 or Bi0.5 Na 0.5 TiO3), lithium tantalate (such as LiTaO3 (LT)), lead lanthanum titanate (such as (Pb,La)TiO3 (PLT)), lead lanthanum zirconium titanate (such as (Pb,La)(Zr,Ti)O3 (PLZT)), ammonium dihydrogen phosphate (such as NH4H2PO4 (ADP)), or potassium dihydrogen phosphate (such as KH2PO4 (KDP)). In one embodiment, the ferroelectric dielectric material may include hafnium oxide or may consist essentially of hafnium oxide. The thickness of the first ferroelectric dielectric plate 154P may be in the range of 2 nm to 30 nm, such as 4 nm to 15 nm, although smaller and larger thicknesses may also be used. A wire cavity 49' exists within each wire trench 49.

[0061] refer to 7A to 7D A sacrificial fill material, such as amorphous silicon, a polymer material, amorphous carbon, or organosilicate glass, may be deposited at the bottom of line cavity 49'. The sacrificial fill material may be vertically recessed to a level in the horizontal plane, including the top surface of a set of inter-transistor insulating strips 30. The remaining portion of the sacrificial fill material constitutes a sacrificial fill structure 151.

[0062] refer to Figures 8A to 8D A first isotropic etching process may be performed to etch the material of the first ferroelectric dielectric plates 154P to remove portions of the first ferroelectric dielectric plates 154P located above the top surfaces of the sacrificial fill structures 151. The remaining portions of each first ferroelectric dielectric plate 154P may have a top surface that is recessed below a horizontal plane including the top surface of the sacrificial fill structures 151.

[0063] A second isotropic etching process that etches the material of the first metal liner plate 152P may be performed to remove portions of the first metal liner plate 152P that are located above the top surfaces of the sacrificial fill structures 151. The remaining portions of each first metal liner plate 152P may have a top surface that is recessed below a horizontal plane including the top surfaces of the sacrificial fill structures 151. A recessed cavity is formed above each combination of the first metal liner plate 152P and the first ferroelectric dielectric plate 154P between an adjacent pair of sacrificial fill structures 151 and the layer stack structure 120.

[0064] refer to 9A to 9D A dielectric material may be deposited in the recessed cavity using a conformal deposition process. For example, a doped silicate glass material may be deposited to a thickness sufficient to fill the recessed cavity. An isotropic etching process may be performed to etch the portion of the dielectric material located outside the recessed cavity. The remaining portion of the deposited dielectric material comprises vertical dielectric spacers 160.

[0065] refer to 10A to 10DA second continuous metal liner layer can be conformally deposited and anisotropically etched. For example, the second continuous metal liner layer can be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process. An anisotropic etching process, such as a reactive ion etching process, can be performed to remove horizontal portions of the second continuous metal liner layer. The remaining portion of the second continuous metal liner in each linear trench 49 includes a pair of second metal liner plates 252P. The second metal liner plates 252P include a metallic (i.e., conductive) material, such as a metal nitride material, an elemental metal, or an intermetallic alloy. For example, the second metal liner plates 252P can include materials such as TiN, TaN, WN, Ti, Ta, W, or alloys or stacks thereof. In one embodiment, the second metal liner plates 252P include TiN. The lateral thickness of the second metal liner plates 252P can be in the range of 2 nm to 30 nm, such as 4 nm to 15 nm, although smaller and larger thicknesses may also be employed.

[0066] A second continuous ferroelectric dielectric layer comprising a ferroelectric dielectric material can be conformally deposited. For example, the second continuous ferroelectric dielectric layer can be deposited by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. An anisotropic etching process can be performed to remove horizontal portions of the second continuous ferroelectric dielectric layer. The remaining portion of the continuous ferroelectric dielectric layer in each linear trench 49 includes a pair of second ferroelectric dielectric plates 254P. The second ferroelectric dielectric plates 254P include at least one ferroelectric dielectric material and / or consist essentially of at least one ferroelectric dielectric material. The second ferroelectric dielectric plates 254P can include any ferroelectric dielectric material that can be used for the first ferroelectric dielectric plates 154P. In one embodiment, the ferroelectric dielectric material can include or consist essentially of hafnium oxide. The thickness of the second ferroelectric dielectric plates 254P can be in the range of 2 nm to 30 nm, such as 4 nm to 15 nm, although smaller and larger thicknesses can also be used. A linear cavity 49' is present in each linear trench 49.

[0067] refer to 11A to 11D The sacrificial fill structure 151 may be removed by performing an isotropic etching process selectively with respect to the first ferroelectric dielectric plate 154P, the second ferroelectric dielectric plate 254P, and the vertical dielectric spacers 160. For example, if the sacrificial fill structure 151 includes amorphous silicon, a wet etching process using thermal trimethyl-2-hydroxyethylammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH) may be performed.

[0068] refer to 12A to 12DA sacrificial fill material may be deposited in each unfilled volume of the line trenches 79. The sacrificial fill material includes a material that is selectively removable relative to the material of the ferroelectric dielectric plates (154P, 254P). For example, the sacrificial fill material may include a semiconductor material such as amorphous silicon or polycrystalline silicon, or a dielectric material that is selectively etchable relative to silicon oxide (e.g., organosilicate glass), a carbon-based material (e.g., amorphous carbon or diamond-like carbon), or a polymer material. The sacrificial fill material may be deposited using a conformal deposition process or a non-conformal deposition process. Excess portions of the sacrificial fill material may be removed from a horizontal plane above the top surface of the topmost layer of the layer stack 120, for example, using a chemical mechanical planarization (CMP) process. Each remaining portion of the sacrificial fill material within a corresponding one of the line trenches 49 comprises a sacrificial fill material track 57R. Each sacrificial fill material track 57R may extend laterally along a first horizontal direction hd1 and may have a vertical cross-sectional shape within a vertical plane that is perpendicular to the first horizontal cross-sectional shape hd1 that remains unchanged when translated along the first horizontal direction hd1. The portion of the continuous gate dielectric layer 50C located above the top surface of the topmost layer of the layer stack 120 can be removed during the planarization process. Each remaining portion of the continuous gate dielectric layer 50C comprises a gate dielectric layer 50L. Each gate dielectric layer 50L may include a pair of first vertically extending portions extending laterally along a first horizontal direction hd1 and a horizontally extending portion adjacent to the bottom edges of the pair of first vertically extending portions. In one embodiment, the gate dielectric layer 50L may include a pair of second vertically extending portions (not shown) extending laterally along a second horizontal direction hd2 and adjacent to the side edges of the pair of first vertically extending portions of the gate dielectric layer 50L.

[0069] The collection of all material portions filling the line trenches 49 comprises a process-line trench fill structure (60S, 50L, 152P, 252P, 154P, 254P, 57R). Each process-line trench fill structure (60S, 50L, 152P, 252P, 154P, 254P, 57R) includes at least one pair of semiconductor channel material strips 60S, a gate dielectric layer 50L, a pair of metal liner plates (152P, 252P), a pair of ferroelectric dielectric plates (154P, 254P), and a sacrificial fill material track 57R. The gate dielectric layer 50L is formed on the at least one pair of semiconductor channel material strips 60S. The pair of metal liner plates (152P, 252P) are formed on the sidewalls of the gate dielectric layer 50L. The pair of ferroelectric dielectric plates (154P, 254P) are formed above and directly on the sidewalls of the metal liner plates (152P, 252P). A laterally alternating sequence of process-line trench-fill structures (60S, 50L, 152P, 252P, 154P, 254P, 57R) and layer stack structures 120 can be formed. The process-line trench-fill structures (60S, 50L, 152P, 252P, 154P, 254P, 57R) and layer stack structures 120 can alternate along a second horizontal direction hd2.

[0070] refer to 13A to 13D A photoresist layer 67 may be formed over the process line trench fill structures (60S, 50L, 152P, 252P, 154P, 254P, 57R) and the layer stack structure 120 and may be photolithographically patterned with a line and space pattern. Linear openings extending laterally along the second horizontal direction hd2 may be formed within the patterned portion of the photoresist layer 67. Each linear opening may have a uniform width along the first horizontal direction hd1. This uniform width may remain constant when translated along the second horizontal direction hd2. The spacing between each adjacent pair of linear openings may be uniform. The line and space pattern in the photoresist layer 67 may be a periodic pattern that repeats periodically along the first horizontal direction hd1. The width of each linear opening may be the same and may be in the range of 60 nm to 300 nm, although smaller and larger widths may also be employed. The spacing between each adjacent pair of linear openings may be in the range of 60 nm to 300 nm, although smaller and larger spacings may also be employed.

[0071] An anisotropic etching process may be performed to etch the unmasked portions of the sacrificial fill material track 57R. The anisotropic etching process selectively etches the material of the sacrificial fill material track 57R with respect to the material of the topmost layer of the layer stack 120, i.e., the topmost one of the inter-transistor insulating strips 30 within the region not masked by the photoresist layer 67. In one embodiment, the anisotropic etching process may selectively etch the material of the sacrificial fill material track 57R with respect to the material of the metal liner plates (152P, 252P) and / or the ferroelectric dielectric plates (154P, 254P) within the region not masked by the photoresist layer 67. Alternatively, the anisotropic etching process may etch the material of the sacrificial fill material track 57R, the metal liner plates (152P, 252P), and / or the ferroelectric dielectric plates (154P, 254P) within the region not masked by the photoresist layer 67. The patterned portion of the sacrificial fill material track 57R includes sacrificial fill material pillars 57 having corresponding rectangular horizontal cross-sectional shapes. A pillar cavity 59 is formed in each volume from which a portion of the sacrificial fill material track 57R is removed during the anisotropic etching process. A sacrificial fill material pillar 57 can be located between each pair of pillar cavities 59 that are located within the same linear trench 49 and are laterally spaced apart along the first horizontal direction hd1. A two-dimensional array of pillar cavities 59 and a two-dimensional array of sacrificial fill material pillars 57 can be formed in the exemplary structure.

[0072] refer to 14A to 14E In the event that the anisotropic etching process for etching the unmasked portions of the sacrificial fill material tracks 57R does not remove the unmasked portions of the ferroelectric dielectric plates (154P, 254P), an isotropic etching process can be performed while the photoresist layer 67 is present to isotropically etch the portions of the ferroelectric dielectric plates (154P, 254P) located around each pillar cavity 59. Each ferroelectric dielectric plate (154P, 254P) is divided into a plurality of discrete portions, each of which is referred to herein as a ferroelectric dielectric layer 54. Each ferroelectric dielectric layer 54 can include a pair of laterally concave and vertical sidewalls exposed to a pair of pillar cavities 59. As used herein, a surface is laterally concave if it has a concave profile in a horizontal cross-sectional view. A surface is vertical if it has a straight profile in a vertical cross-sectional view.

[0073] In the event that the anisotropic etching process for etching the unmasked portions of the sacrificial fill material rails 57R does not remove the unmasked portions of the metal liner plates (152P, 252P), another isotropic etching process can be performed while the photoresist layer 67 is present to isotropically etch the portions of the metal liner plates (152P, 252P) located around each pillar cavity 59. Each metal liner plate (152P, 252P) is divided into a plurality of discrete portions, each of which is referred to herein as a metal liner 52. Each metal liner 52 can include a pair of lateral recesses and vertical sidewalls exposed to a pair of pillar cavities 59.

[0074] An isotropic etching process can be performed to remove the physically exposed portions of the gate dielectric layer 50L. For example, if the gate dielectric layer 50L comprises silicon oxide, a wet etching process using dilute hydrofluoric acid can be used to etch the portions of the gate dielectric layer 50L located around the pillar cavities 59. Each gate dielectric layer 50L is divided into a plurality of discrete portions. Each patterned portion of the gate dielectric layer 50L comprises a gate dielectric 50. Each gate dielectric 50 can include a pair of vertically extending gate dielectric portions and a horizontally extending gate dielectric portion adjacent to bottom edges of the pair of vertically extending gate dielectric portions and contacting a corresponding sacrificial fill material pillar 57, as shown. Figure 14E As shown in .

[0075] Subsequently, an isotropic etching process can be performed to etch the material of the semiconductor channel material strips 60S to etch the physically exposed portions of the semiconductor channel material strips 60S. In one embodiment, the isotropic etching process can be selective to the material of the doped semiconductor source strips 44 and the doped semiconductor drain strips 46. In this case, an etching chemistry can be used that etches lightly doped semiconductor materials that are selective to heavily doped semiconductor materials. In an illustrative example, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be used to remove portions of the semiconductor channel material strips 60S from around the pillar cavities 59, as shown in FIG. Figure 14B Each semiconductor channel material strip 60S can be divided into a plurality of vertical semiconductor channels 60 that are laterally spaced apart from each other along a first horizontal direction hd1. Each vertical semiconductor channel 60 can contact a corresponding one of the gate dielectrics 50.

[0076] In an alternative embodiment, the isotropic etching process may not be selective to the material of the doped semiconductor source strips 44 and the doped semiconductor drain strips 46. In this case, the isotropic etching process may not be selective to the material of the semiconductor channel material strips 60S and the doped semiconductor source strips 44 and the doped semiconductor drain strips 46. Although portions of the doped semiconductor source strips 44 and the doped semiconductor drain strips 46 are incidentally etched around each pillar cavity 59, each of the doped semiconductor source strips 44 and the doped semiconductor drain strips 46 can be maintained as a continuous structure by limiting the lateral etching distance for the doped semiconductor source strips 44 and the doped semiconductor drain strips 46 to less than half the width of each of the doped semiconductor source strips 44 and the doped semiconductor drain strips 46 along the second horizontal direction hd2 and to less than half the width of each sacrificial fill material pillar 57 along the first horizontal direction hd1. In this case, each vertical semiconductor channel 60 may directly contact the horizontal surface of a corresponding one of the doped semiconductor source strips 44 and the horizontal surface of a corresponding one of the doped semiconductor drain strips 46. Subsequently, the photoresist layer 67 may be removed, for example, by ashing.

[0077] Each successive combination of the sacrificial fill material pillar 57, the gate dielectric 50, the pair of metal liners 52, the pair of ferroelectric dielectric layers 54, and the at least one pair of vertical semiconductor channels 60 constitutes an in-process memory pillar structure (57, 50, 52, 54, 60). Generally, each in-process line trench fill structure (60S, 50L, 152P, 252P, 154P, 254P, 57R) can be patterned into a row of in-process memory pillar structures (57, 50, 52, 54, 60) by etching a pillar cavity 59 through each in-process line trench fill structure (60S, 50L, 152P, 252P, 154P, 254P, 57R). Each pair of ferroelectric dielectric layers 54 in the process memory pillar structures (57, 50, 52, 54, 60) includes patterned portions of a corresponding pair of ferroelectric dielectric plates (154P, 254P). At least one pair of vertical semiconductor channels 60 in the process memory pillar structures (57, 50, 52, 54, 60) includes patterned portions of a corresponding subset of semiconductor channel material strips 60S.

[0078] Each of the vertical semiconductor channels 60 can contact a corresponding one of the doped semiconductor source strips 44, a corresponding one of the doped semiconductor drain strips 46, and a corresponding one of the channel-level insulation strips 32. In one embodiment, each of the channel-level insulation strips 32 can contact two rows of vertical semiconductor channels 60 arranged along the first horizontal direction hd1. Adjacent pairs of vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 can be laterally separated by a corresponding one of the pillar cavities 59.

[0079] In one embodiment, each of the ferroelectric dielectric layers 54 may have a first straight sidewall extending vertically through the multiple levels of the layer stack structure 120 and contacting a corresponding one of the sacrificial fill material pillars 57, and a second straight sidewall parallel to the first straight sidewall and facing a corresponding one of the layer stack structures 120. In one embodiment, each of the memory pillar structures (57, 50, 52, 54, 60) includes a pair of metal liners 52 contacting a pair of ferroelectric dielectric layers 54. Each of the memory pillar structures (57, 50, 52, 54, 60) includes a pair of vertically extending gate dielectric portions contacting the pair of metal liners 52. Each of the vertically extending gate dielectric portions may contact a sidewall of a corresponding one of the layer stack structures 120, as shown in FIG. Figure 14E In one embodiment, each of the vertically extending gate dielectric portions can contact each metal source strip 42, each doped semiconductor source strip 44, each doped semiconductor drain strip 46, and each metal drain strip 48 within a corresponding one of the layer stack structures 120, and does not directly contact any channel-level insulating strip 32 within a corresponding one of the layer stack structures 120. In one embodiment, each of the ferroelectric dielectric layers 54 includes a pair of laterally recessed and vertical sidewalls physically exposed to a pair of pillar cavities 59, as shown. Figure 14A As shown in .

[0080] refer to Figures 15A to 15EA dielectric material, such as silicon oxide, can be deposited in the pillar cavities 59 by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating). Excess portions of the dielectric material can be removed from a horizontal plane including the topmost surface of the layer stack structure 120, for example, by a planarization process. The planarization process can include a chemical mechanical planarization (CMP) process. Each remaining portion of the dielectric material filling the pillar cavities 59 comprises a dielectric pillar structure 62. A two-dimensional array of dielectric pillar structures 62 can be formed in the two-dimensional array of pillar cavities 59. A row of dielectric pillar structures 62 is formed in each line trench 49. During the process, a laterally alternating sequence of memory pillar structures (57, 50, 52, 54, 60) and dielectric pillar structures 62 can be formed in each line trench 49.

[0081] The in-process memory pillar structures (57, 50, 52, 54, 60) and dielectric pillar structures 62 in each line trench 49 may alternate along the first horizontal direction hd1. Thus, two rows of vertical semiconductor channels 60 may be provided at each level of the channel-level insulation strips 32 within each line trench 49. Each dielectric pillar structure 62 may include at least one pair of lateral protrusions that contact a corresponding one of the channel-level insulation strips 32 in the recess from which the semiconductor channel material strip 60S has been removed, as shown. Figure 15B Adjacent pairs of vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 may be laterally spaced apart by a lateral protrusion of a corresponding one of the dielectric pillar structures 62 .

[0082] refer to 16A to 16E , the material of the sacrificial fill material pillars 57 can be removed selectively with respect to the material of the ferroelectric dielectric layer 54, the material of the dielectric pillar structures 62, and the material of the inter-transistor insulating strips 30. For example, an isotropic etching process that etches the material of the sacrificial fill material pillars 57 selectively with respect to the material of the ferroelectric dielectric layer 54, the material of the dielectric pillar structures 62, and the material of the inter-transistor insulating strips 30 can be performed to remove the sacrificial fill material pillars 57. In an illustrative example, if the sacrificial fill material pillars 57 include a semiconductor material (such as amorphous silicon), a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be used to remove the sacrificial fill material pillars 57. A gate cavity 69 can be formed in the volume from which the sacrificial fill material pillars 57 are removed.

[0083] refer to 17A to 17EAt least one conductive material may be deposited in gate cavity 69 by a conformal deposition process, such as a chemical vapor deposition process. The at least one conductive material may include a heavily doped semiconductor material (e.g., polysilicon), an elemental metal, an intermetallic alloy, a metal nitride, a metal carbide, a metal-semiconductor alloy (e.g., a metal silicide), alloys thereof, and / or layer stacks thereof. For example, the at least one conductive material may include a layer stack of a titanium nitride liner and a tungsten fill material. Alternatively, the liner may be omitted. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the topmost surface of layer stack structure 120. Each remaining portion of the at least one conductive material filling gate cavity 69 constitutes a gate electrode (i.e., a local word line) 70. Thus, each sacrificial fill material pillar 57 (which is a remaining portion of sacrificial fill material rail 57R) is replaced by a gate electrode 70.

[0084] Each successive combination of gate electrode 70, gate dielectric 50, a pair of metal liners 52, a pair of ferroelectric dielectric layers 54, and at least one pair of vertical semiconductor channels 60 constitutes a memory pillar structure (70, 50, 52, 54, 60). Thus, in each process, memory pillar structures (57, 50, 52, 54, 60) are replaced by memory pillar structures (70, 50, 52, 54, 60). In one embodiment, each memory pillar structure (70, 50, 52, 54, 60) may include multiple pairs of vertical semiconductor channels 60 located at multiple levels of channel-level insulating strips 32.

[0085] Each line trench 49 may be filled with a corresponding line trench filling structure. Each line trench filling structure may include a laterally alternating sequence of memory pillar structures (70, 50, 52, 54, 60) and dielectric pillar structures 62. Each of the memory pillar structures (70, 50, 52, 54, 60) includes a gate electrode 70, a pair of ferroelectric dielectric layers 54, and at least a pair of vertical semiconductor channels 60 located at each level of the channel-level insulating strips 32.

[0086] refer to 18A to 18EAt least one interconnect-level dielectric layer 80 may be deposited over the two-dimensional array of memory pillar structures (70, 50, 52, 54, 60). Various metal interconnect structures (78, 82) may be formed in the at least one interconnect-level dielectric layer 80. The various metal interconnect structures (78, 82) may include, for example, a gate electrode connection via structure 78 that contacts a corresponding one of the gate electrodes 70, and a global gate line (i.e., a global word line) 82 that contacts a corresponding one or a corresponding subset of the gate electrode connection via structures 78. In one embodiment, the metal source strips 42 and the metal drain strips 48 may extend laterally along a first horizontal direction hd1, and the global gate line 82 may extend laterally along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.

[0087] A three-dimensional array of ferroelectric memory elements can be formed. Each ferroelectric memory element includes a portion of the ferroelectric dielectric layer 54 adjacent to a corresponding vertical semiconductor channel 60. The current passing through a selected vertical semiconductor channel 60 depends on the polarization direction (i.e., the direction of the electric dipole moment) within the proximal portion of the adjacent ferroelectric dielectric layer 54. Therefore, a data bit can be programmed into each portion of the ferroelectric dielectric layer 54 adjacent to a corresponding one of the vertical semiconductor channels 60. The number of channel-level insulating strips 32 within each layer stack structure 120 determines the number of vertically stacked ferroelectric memory elements.

[0088] refer to Figures 19A to 19E , shows an alternative configuration of the exemplary structure, which can be achieved by adopting Figures 1A to 1C Only one repetition of the unit layer sequence (42L, 44L, 32L, 46L, 48L, 30L) of the processing step is obtained from 18A to 18E In this case, a two-dimensional array of ferroelectric memory elements can be provided.

[0089] In another alternative embodiment, the global gate lines (ie, global word lines) 82 may be formed in two different vertical levels, such as Figure 19F and Figure 19G As shown in . Figure 19F and Figure 19G Corresponding to Figure 19C and Figure 19D For example, a first group 82A of global gate lines 82 may be formed at a first vertical level, and a second group 82B of global gate lines 82 may be formed in a second vertical level located above the first vertical level. The global gate lines in the first group 82A may alternate with the global gate lines in the second group 82B. Figure 19G In the embodiment shown, the dielectric pillar structure 62 can be compared to Figure 19DThe global gate line configuration can reduce the cell size and / or cell separation distance and increase device density. In addition, the global gate line configuration can also be used for 18A to 18E In the exemplary structure of , the exemplary structure contains multiple repetitions of the unit layer sequence.

[0090] refer to Figure 20 , shows the 18A to 18E FIG2 is a circuit diagram of a portion of an exemplary structure of FIG2 , which includes a layer stack 120, two rows of vertically stacked vertical semiconductor channels 60 located on one side of the layer stack 120, and a row of gate electrodes 70. Each continuous combination of a metal source strip 42 and a doped semiconductor source strip 44 constitutes a source line, which may be a first source line SL1 or a second source line SL2. Each continuous combination of a metal drain strip 48 and a doped semiconductor drain strip 46 constitutes a bit line, which may be a first bit line BL1 or a second bit line B21. Each gate electrode 70 constitutes a local word line (e.g., a vertical local word line). Each global word line 82 may be a first word line WL1, a second word line WL2, and so on. Each intersection between a word line and a pair of source and bit lines includes a ferroelectric field-effect transistor (FeFET), whose on-state current depends on the polarization direction of a portion of the ferroelectric dielectric layer 54 included therein. A first ferroelectric field effect transistor T1, a second ferroelectric field effect transistor T2, a third ferroelectric field effect transistor T3, and a fourth ferroelectric field effect transistor T4 are shown. The portion of the doped semiconductor source strip 44 located in each transistor serves as the source region of the transistor, and the portion of the doped semiconductor drain strip 46 located in each transistor serves as the drain region of the transistor. The memory array can be used as a NOR memory array.

[0091] With reference to all of the figures and in accordance with various embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a three-dimensional array of ferroelectric memory cells or a two-dimensional array of ferroelectric memory cells. The semiconductor structure includes: a layer stack structure 120, which extends laterally along a first horizontal direction hd1 and is spaced apart from each other along a second horizontal direction hd2 by line trenches 49, wherein each layer stack structure in the layer stack structure 120 includes at least one instance of a unit layer sequence (42, 44, 32, 46, 48, 30), which unit layer sequence includes, from bottom to top or from top to bottom, a doped semiconductor source strip 44, a channel-level insulation strip 32, and a doped semiconductor drain strip 46; and a line trench filling structure (70, 50, 52, 54, 60, 62), which is located in a corresponding one of the line trenches 49, wherein each of the line trench filling structures (70, 50, 52, 54, 60, 62) includes a memory pillar structure (70, 50, 52, 54, 60) and a laterally alternating sequence of dielectric pillar structures 62, and wherein each of the memory pillar structures (70, 50, 52, 54, 60) includes a gate electrode 70, at least one pair of ferroelectric dielectric layers 54 and at least one pair of vertical semiconductor channels 60 located at each level of the channel-level insulating strips 32.

[0092] In one embodiment, each of the vertical semiconductor channels 60 contacts a corresponding one of the doped semiconductor source strips 44 , a corresponding one of the doped semiconductor drain strips 46 , and a corresponding one of the channel-level insulation strips 32 .

[0093] In one embodiment, each of the channel-level insulation strips 32 contacts two rows of vertical semiconductor channels 60 arranged along the first horizontal direction hd1; and adjacent pairs of vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 are laterally spaced apart by a lateral protrusion of a corresponding one of the dielectric pillar structures 62.

[0094] In one embodiment, vertical semiconductor channel 60 has a doping of a first conductivity type; and doped semiconductor source strips 44 and doped semiconductor drain strips 46 have a doping of a second conductivity type opposite to the first conductivity type.

[0095] In one embodiment, each ferroelectric dielectric layer 54 has a first straight sidewall and a second straight sidewall, wherein the first straight sidewall extends vertically through multiple levels of the layer stack structure 120 and contacts a corresponding one of the gate electrodes 70, and the second straight sidewall is parallel to the first straight sidewall and faces a corresponding one of the layer stack structures 120.

[0096] In one embodiment, each of the vertical semiconductor channels 60 includes a respective sidewall that vertically coincides with a sidewall of one of the doped semiconductor source strips 44 and with a sidewall of one of the doped semiconductor drain strips 46. In one embodiment, each of the channel-level insulating strips 32 contacts a respective one of the doped semiconductor source strips 44 and a respective one of the doped semiconductor drain strips 46 and has a width along the second horizontal direction hd2 that is less than a width of the respective one of the doped semiconductor source strips 44 along the second horizontal direction hd2.

[0097] In one embodiment, each of the memory pillar structures (70, 50, 52, 54, 60) further includes at least one pair of metal liners 52 contacting at least one pair of ferroelectric dielectric layers 54. In one embodiment, each of the memory pillar structures (70, 50, 52, 54, 60) includes a pair of vertically extending gate dielectric portions contacting at least one pair of metal liners 52; and each of the vertically extending gate dielectric portions contacts a sidewall of a corresponding one of the layer stack structures 120.

[0098] In one embodiment, the cell layer sequence (42, 44, 32, 46, 48, 30) further includes: a metal source strip 42 that contacts the doped semiconductor source strip 44; and a metal drain strip 48 that contacts the doped semiconductor drain strip 46. In one embodiment, each of the vertically extending gate dielectric portions contacts each metal source strip 42, each doped semiconductor source strip 44, each doped semiconductor drain strip 46, and each metal drain strip 48 within a corresponding one of the layer stack structures 120, and does not directly contact any channel-level insulation strip 32 within the corresponding one of the layer stack structures 120.

[0099] In one embodiment, each of the layer stack structures 120 includes multiple instances of the unit layer sequence ( 42 , 44 , 32 , 46 , 48 , 30 ); and multiple instances of the vertically stacked unit layer sequence ( 42 , 44 , 32 , 46 , 48 , 30 ).

[0100] In one embodiment, each of the ferroelectric dielectric layers 54 includes a pair of lateral recesses and vertical sidewalls contacting a pair of dielectric post structures 62 within the dielectric post structures 62 .

[0101] In one embodiment, one of the gate electrodes 70 and one of the dielectric pillar structures 62 (which can be any contact pair of the gate electrode 70 and the dielectric pillar structure 62) have a continuous vertical interface, which includes: a first vertical interface segment, which is perpendicular to the first horizontal direction hd2; and a pair of second vertical interface segments, which are perpendicular to the second horizontal direction hd2 and adjacent to the corresponding vertical edges of the first vertical interface segment.

[0102] Various embodiments of the present disclosure can be used to provide a three-dimensional cross-point array of compact ferroelectric field effect transistors or a two-dimensional cross-point array of compact ferroelectric field effect transistors. Each ferroelectric field effect transistor has a small cell size and can be used as a ferroelectric memory cell that can store a data bit in the form of the polarization direction of the corresponding portion of the ferroelectric dielectric layer 54.

[0103] Although specific preferred embodiments have been mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments are shown in the present disclosure that employ a particular structure and / or configuration, it will be understood that the present disclosure may be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: a layer stack structure extending laterally along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches, wherein each layer stack structure in the layer stack structure comprises at least one instance of a unit layer sequence, each instance of the unit layer sequence comprising, from bottom to top or from top to bottom, a metal source strip, a doped semiconductor source strip, a channel-level insulating strip, a doped semiconductor drain strip, a metal drain strip, and an inter-transistor-level insulating strip; and A line trench filling structure, wherein the line trench filling structure is located in a corresponding one of the line trenches, wherein each of the line trench filling structures includes a laterally alternating sequence of memory pillar structures and dielectric pillar structures, the memory pillar structures and the dielectric pillar structures alternating along the first horizontal direction, and wherein each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers and at least one pair of vertical semiconductor channels, wherein each pair of the at least one pair of vertical semiconductor channels is located at the level of the channel-level insulating strip of a corresponding one of the at least one instance of the cell layer sequence.

2. The semiconductor structure of claim 1 , wherein each of the vertical semiconductor channels contacts a corresponding one of the doped semiconductor source strips, a corresponding one of the doped semiconductor drain strips, and a corresponding one of the channel-level insulation strips.

3. The semiconductor structure according to claim 1, wherein: each of the channel-level insulation strips contacts two rows of vertical semiconductor channels arranged along the first horizontal direction, wherein each vertical semiconductor channel of a corresponding row of vertical semiconductor channels is located in a corresponding memory pillar structure of a laterally alternating sequence of memory pillar structures and dielectric pillar structures; and Adjacent pairs of vertical semiconductor channels within each row of vertical semiconductor channels are laterally spaced apart by a lateral protruding portion of a corresponding one of the dielectric pillar structures.

4. The semiconductor structure according to claim 1, wherein: The doped semiconductor source strips and the doped semiconductor drain strips have doping of a first conductivity type; and The vertical semiconductor channel has a doping of a second conductivity type opposite to the first conductivity type.

5. A semiconductor structure according to claim 1, wherein each of the ferroelectric dielectric layers has a first straight sidewall and a second straight sidewall, the first straight sidewall vertically extending through multiple levels of the layer stack structure and contacting a corresponding one of the gate electrodes, and the second straight sidewall is parallel to the first straight sidewall and facing a corresponding one of the layer stack structures.

6. The semiconductor structure of claim 1 , wherein each of the vertical semiconductor channels comprises a respective sidewall that vertically coincides with a sidewall of one of the doped semiconductor source strips and vertically coincides with a sidewall of one of the doped semiconductor drain strips.

7. The semiconductor structure of claim 6 , wherein each of the channel-level insulating strips contacts the doped semiconductor source strip and the doped semiconductor drain strip, and has a width along the second horizontal direction that is smaller than a width of the doped semiconductor source strip contacting the channel-level insulating strip along the second horizontal direction.

8. The semiconductor structure of claim 1, wherein each of the memory pillar structures further comprises at least one pair of metal liners in contact with the at least one pair of ferroelectric dielectric layers.

9. The semiconductor structure of claim 8, wherein: each of the memory pillar structures includes a pair of vertically extending gate dielectric portions in contact with the at least one pair of metal liners; and Each of the vertically extending gate dielectric portions contacts a sidewall of a corresponding one of the layer stacks.

10. The semiconductor structure of claim 9, wherein the metal source stripe contacts the doped semiconductor source stripe; and the metal drain stripe contacts the doped semiconductor drain stripe.

11. A semiconductor structure according to claim 10, wherein each of the vertically extending gate dielectric portions contacts each metal source strip, each doped semiconductor source strip, each doped semiconductor drain strip and each metal drain strip within a corresponding one of the layer stack structures, and does not directly contact any channel-level insulation strip within the corresponding one of the layer stack structures. 12 . The semiconductor structure according to claim 1 , wherein the at least one instance of the unit layer sequence of each of the layer stack structures comprises a plurality of instances of the unit layer sequence stacked vertically.

13. The semiconductor structure of claim 1, wherein each of the ferroelectric dielectric layers comprises a pair of lateral recesses and vertical sidewalls in contact with a pair of the dielectric pillar structures.

14. The semiconductor structure according to claim 1 , wherein a boundary between one of the gate electrodes and one of the dielectric pillar structures has a continuous vertical interface, and the continuous vertical interface comprises: a first vertical interface section, wherein the first vertical interface section is perpendicular to the first horizontal direction; and A pair of second vertical interface sections are perpendicular to the second horizontal direction and adjacent to corresponding vertical edges of the first vertical interface section.

15. A method of forming a semiconductor structure, comprising: forming layer stack structures extending laterally along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches, wherein each layer stack structure in the layer stack structures comprises at least one instance of a unit layer sequence, and each instance of the unit layer sequence comprises, from bottom to top or from top to bottom, a metal source strip, a doped semiconductor source strip, a channel-level insulating strip, a doped semiconductor drain strip, a metal drain strip, and an inter-transistor-level insulating strip; forming an in-process line trench fill structure comprising at least a pair of semiconductor channel material strips, a pair of ferroelectric dielectric plates, and a track of sacrificial fill material within each line trench; dividing each in-process in-line trench fill structure into a row of in-process memory pillar structures by etching a pillar cavity through each in-process in-line trench fill structure; forming a dielectric pillar structure in the pillar cavity; as well as The remaining portion of the sacrificial fill material track is replaced with a gate electrode, thereby comprising a memory pillar structure comprising a gate electrode, at least one pair of ferroelectric dielectric layers and at least one pair of vertical semiconductor channels in each volume of a memory pillar structure formed in the process, the memory pillar structures and the dielectric pillar structures alternating along the first horizontal direction, wherein each pair of the at least one pair of vertical semiconductor channels is located at the level of the channel-level insulating strip of a corresponding one of the at least one instance of the cell layer sequence.

16. The method of claim 15, wherein each of the in-process memory pillar structures comprises: at least one pair of ferroelectric dielectric layers, the at least one pair of ferroelectric dielectric layers comprising patterned portions of a respective pair of ferroelectric dielectric slabs; and At least one pair of vertical semiconductor channels includes patterned portions of respective subsets of the strips of semiconductor channel material.

17. The method according to claim 15, further comprising: forming laterally extending grooves by laterally recessing the channel-level insulating layer and selectively laterally recessing the doped semiconductor source strips and the doped semiconductor drain strips; filling the laterally extending recess with a semiconductor material; as well as Excess portions of the semiconductor material are removed from an outer volume of the laterally extending recess, wherein the remaining portion of the semiconductor material in the laterally extending recess comprises the strip of semiconductor channel material.

18. The method of claim 15, wherein the in-process line-of-trench filling structure within each line-of-trench further comprises: a gate dielectric layer formed on the at least one pair of semiconductor channel material strips; and At least one pair of metal liner plates is formed on the sidewalls of the gate dielectric liner, wherein the at least one pair of ferroelectric dielectric plates is formed over the sidewalls of the metal liner layer.

19. The method of claim 15, wherein the metal source stripe contacts the doped semiconductor source stripe; and the metal drain stripe contacts the doped semiconductor drain stripe.

20. The method of claim 15, wherein: the at least one instance of the cell layer sequence of each of the layer stack structures comprises a plurality of instances of the cell layer sequence, the plurality of instances being vertically spaced apart by at least one inter-transistor level insulating strip; and Each memory pillar structure includes a plurality of pairs of vertical semiconductor channels.

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