QLC programming method using fine data staging

Abstract

The present disclosure relates generally to improved foggy-fine programming. Data can be written to SLC memory. The data can then be decoded and then foggy and fine written to MLC. After decoding, the data can be stored in DRAM located at the front end or in SRAM located in the flash manager before being written to the MLC. After being stored in DRAM or SRAM, the data is then decoded and written to the MLC.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 899,374, filed June 11, 2020, the entire contents of which are incorporated herein by reference. Background Technology Technical Field

[0004] The implementation scheme disclosed herein generally relates to improvements in fuzzy-fine writing to QLC.

[0005] Description of related fields

[0006] Programming or writing data may require two write phases: fuzzing and fine-tuning. In fuzz-fine programming, the bits to be written cannot be written only once. Instead, the data needs to be written first through fuzzing, where voltage pulses are provided to push the current state to a higher-resolution state, but not a fully resolved state. Fine-tuning is performed at a point in time after fuzzing to write the data again in a fully resolved state.

[0007] In fuzzy-fine programming, for a dual-plane device, for a total of 128KB of transmission, there are four pages of transmission for fuzzy programming and four pages for fine programming. The fuzzy state is unreadable, and the data needs to be protected against potential power loss events (PLI). Furthermore, fuzzy-fine programming occurs in an interleaved word line sequence, meaning that the amount of data transmitted is five or eight times the 128KB programmable unit. To perform fuzzy-fine programming, multiple megabytes can be programmed multiple times. To perform multiple programming operations, a large amount of data needs to be reserved so that repeated programming can be performed with the exact same data.

[0008] Therefore, there is a need in this field for improved fuzzy-fine programming. Summary of the Invention

[0009] This disclosure generally relates to improved fuzzy-fine programming. Data can be written to an SLC memory. The data can then be decoded and then written to the MLC in both fuzzy and fine-grained modes. After decoding, the data can be stored in front-end DRAM or in SRAM located in a flash manager before being written to the MLC. After being stored in DRAM or SRAM, the data is subsequently decoded and written to the MLC.

[0010] In one embodiment, a data storage device includes: one or more memory devices, the one or more memory devices including SLC memory and MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; fuzzily write data to the MLC memory, wherein fuzzily writing data to the MLC memory includes: retrieving data from latches in the one or more memory devices; decoding the data retrieved from the latches; encoding the decoded data retrieved from the latches; and writing the encoded data to the MLC memory; and finely writing the data to the MLC memory.

[0011] In another embodiment, a data storage device includes: one or more memory devices, each including a plurality of dies, wherein each die includes SLC memory and MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; read data from the SLC memory; decode the read data; transfer the decoded data to DRAM; perform a first encoding on the transferred data; and write the first-encoded data to the MLC memory for the first time.

[0012] In another embodiment, a data storage device includes: one or more memory devices, each memory device having a plurality of dies, wherein each of the one or more memory devices includes an SLC memory and an MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; read data from the SLC memory; decode the read data; deliver the decoded data to a first SRAM located in a front-end module; deliver the decoded data to a second SRAM located in a flash manager; write the data delivered to the first SRAM into the MLC memory; and write the data delivered to the second SRAM into the MLC memory. Attached Figure Description

[0013] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0014] Figure 1 This is a schematic diagram of a system for storing data according to one implementation plan.

[0015] Figure 2A and Figure 2BIt is a schematic diagram of scheduling fuzzy-fine programming based on various implementation schemes.

[0016] Figure 3 It is a diagram showing interlaced fuzzy-fine programming.

[0017] Figure 4A and Figure 4B This is a schematic diagram of scheduling fuzzy-fine programming and garbage collection based on an implementation scheme.

[0018] Figure 5 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme.

[0019] Figure 6 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme.

[0020] Figure 7 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme.

[0021] Figure 8 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme.

[0022] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0023] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, achieving a particular advantage through a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0024] This disclosure generally relates to improved fuzzy-fine programming. Data can be written to an SLC memory. The data can then be decoded and then written to the MLC in both fuzzy and fine-grained modes. After decoding, the data can be stored in front-end DRAM or in SRAM located in a flash manager before being written to the MLC. After being stored in DRAM or SRAM, the data is subsequently decoded and written to the MLC.

[0025] Figure 1 This is a schematic diagram of a system 100 for storing data according to one embodiment. The system 100 for storing data according to one embodiment includes a host device 102 and a data storage device 104. The host device 102 includes dynamic random access memory (DRAM) 112. The host device 102 can include a wide range of devices, such as computer servers, network attached storage (NAS) units, desktop computers, laptops, tablet computers (i.e., "smart" tablets), set-top boxes, mobile phones (i.e., "smart" phones), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and automotive applications (i.e., mapping, autonomous driving). In some embodiments, the host device 102 includes any device having a processing unit or any form of hardware capable of processing data, including general-purpose processing units, special-purpose hardware (such as application-specific integrated circuits (ASICs)), configurable hardware (such as field-programmable gate arrays (ASICs)), or any other form of processing unit configured by software instructions, microcode, or firmware.

[0026] Data storage device 104 communicates with host device 102 via interface 106 included in data storage device 104. Data storage device 104 includes controller 108, buffer 114, and one or more memory devices 110. Data storage device 104 may be an internal storage drive, such as a laptop hard drive or a desktop hard drive. Data storage device 104 may be a removable mass storage device, such as, but not limited to, a handheld removable storage device, such as a memory card (e.g., a Secure Digital (SD) card, a micro-Secure Digital (micro-SD) card, or a Multimedia Card (MMC)) or a Universal Serial Bus (USB) device. Data storage device 104 may take the form of an embedded mass storage device such as an eSD / eMMC embedded flash drive embedded in host device 102. Data storage device 104 may also be any other type of internal storage device, removable storage device, embedded storage device, external storage device, or network storage device.

[0027] Memory device 110 may be, but is not limited to, internal or external storage units. Memory device 110 relies on a semiconductor memory chip in which data can be stored as random access memory (RAM), read-only memory (ROM), or other forms of RAM and ROM. RAM is used for temporary data storage, while ROM is used for permanent data storage.

[0028] Data storage device 104 includes a controller 108 that manages the operation of data storage device 104, such as writing to or reading from memory device 110. Controller 108 executes computer-readable program code (e.g., software or firmware) executable instructions (referred to herein as "instructions") for transferring data. Instructions can be executed by various components of controller 108, such as processors, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, embedded microcontrollers, and other components of controller 108.

[0029] The data storage device 104 includes a buffer 114, which is a physical memory storage area used to temporarily store data when data is moved from one place to another (i.e., from the host device 102 to the memory device 110).

[0030] Data can be transferred to or from the DRAM 112 of host device 102 to data storage device 104. A data transfer path may originate from the DRAM 112 of host device 102 and communicate with controller 108 via interface 106 of data storage device 104. The data is then passed through buffer 114 of data storage device 104 and stored in memory device 110. If data is written to SLC memory, the data is simply written. However, if data is written to MLC (such as QLC memory), a fuzzy-fine write process occurs. It should be noted that throughout the disclosure, write and program are used interchangeably. In one embodiment, data is first written to SLC memory and then moved to MLC memory. In another embodiment, all data is first written to the SLC cache and then moved to QLC for sequential or non-repeating writes. In this case, the movement of data to QLC is scheduled by data storage device 204 to create free space in the SLC for subsequent writes from host device 102. In another implementation, repeated writes involve the host rewriting the most recently written LBA, where most recently means the data is still in the SLC cache. In this case, there are three possibilities: move all data (including old obsolete LBAs) to the QLC and create obsolete "holes"; move only valid data, skipping obsolete data in the SLC; and if the amount of obsolete data is high, compact the SLC cache, perform garbage collection, and do not move any data to the QLC.

[0031] Figure 2A and Figure 2B This is a schematic diagram of fuzzy-fine programming of scheduling according to various implementation schemes. The front-end (FE) module 202 includes an XOR engine 204 and static random-access memory (SRAM) 206. Host data can initially be delivered to the FE module 202. The data passes through the XOR engine 204 and is written to the SRAM 206. The XOR engine 204 generates XOR parity information before writing to the SRAM 206. The XOR parity information is used to improve the reliability of the storage device used to store data, such as enabling data recovery from data write failures or data read failures to and from the NVM, or enabling data recovery in case of power loss. The storage device can be... Figure 1 The data storage device 104. Reliability can be provided by using XOR parity information generated or calculated based on data stored in the storage device. The XOR engine 204 can generate a parity stream to be written to the SRAM 206. The SRAM 206 can contain multiple dies in which data can be written.

[0032] The second flash memory manager (FM2) module 210 includes an encoder 212, an SRAM 216, and a decoder 214. The decoder 214 may include a low-end (LG) decoder and a high-end (HG) decoder. The LG decoder can implement low-power bit-flip algorithms, such as low-density parity-check (LDPC) algorithms. The LG decoder can be used to decode data and correct bit flips, where such data has a low bit error rate (BER). The HG decoder can implement full-power decoding and error correction algorithms, which can be activated if the LG decoder fails to decode and correct bit flips in the data. The HG decoder can be used to correct bit flips in cases where such data has a high BER. Alternatively, the FM2 can be replaced by a combined FE-FM monolithic chip.

[0033] For example, encoder 212 and decoder 214 (including LG decoder and HG decoder) may include processing circuitry or a processor (having a computer-readable medium storing computer-readable program code (e.g., firmware) executable by the processor), logic circuitry, application-specific integrated circuit (ASIC), programmable logic controller, embedded microcontroller, combinations thereof, and so on. In some examples, encoder 212 and decoder 214 are separate from the memory controller, and in other examples, encoder 212 and decoder 214 are embedded in or part of the memory controller. In some examples, the LG decoder is hardened circuitry, such as logic circuitry, ASIC, and so on. In some examples, the HG decoder may be a software decoder (e.g., implemented by a processor). Data may be written to SRAM 216 after being decoded at decoder 214. Data at SRAM 216 may be further delivered to encoder 212, as discussed below.

[0034] The memory device may be a NAND memory device. Memory device 220 may include SLC 222 and MLC 224. It should be understood that the embodiments discussed herein are applicable to any multi-level cell, such as MLC, TLC, or QLC. MLC is merely exemplary. SLC 222, MLC, TLC, QLC, and PLC are named according to the number of bits that the memory cell can accept. For example, an SLC may accept one bit per memory cell, and a QLC may accept four bits per memory cell. Each bit is registered as 1 or 0 on the memory device. Additionally, although SLC memory is illustrated as a memory device, it is also contemplated that SLC memory may be replaced by 2-bit cell or MLC memory devices.

[0035] Figure 2AThis is a schematic diagram of a fuzzy-fine write process according to one implementation. Host data is fed to FE module 202. The host data is sent via XOR engine 204, generating XOR parity information. The data is then written to SRAM 206 at FE module 202. At FM2 module 210, data is delivered from SRAM 206 along stream 1 to encoder 212. The data is then written along stream 2 to SLC 222 of memory device 220. To continue fuzzy-fine writing to MLC 224, data is read from SLC 222 and then decoded along stream 3 at decoder 214 of FM2 module 210. The decoded data is then written to SRAM 216 of FM2 module 210 in stream 4. The data is then sent along stream 5 via encoder 212 for encoding. After the data from SRAM 216 of FM2 module 210 is encoded at encoder 212 of FM2 module 210, fuzzy writing occurs along stream 6. The initial write operation is performed from the encoder 212 of the FM2 module 210 to the MLC 224 of the memory device 220. To proceed with the fine write operation, data is then read from the SLC 222 and delivered along stream 7 to the decoder 214. After decoding, the data is then written to the SRAM along stream 8 and then delivered along stream 9 to the encoder 212 for encoding. The now-encoded data is then finely written along stream 10 to the MLC 224.

[0036] according to Figure 2A The implementation scheme mentioned may not involve DRAM bus traffic. Furthermore, SLC and MLC programming can be decoupled. The fuzzy-fine write process can involve multiple streams with direct-write hot / cold sorting support. However, bus traffic can be higher.

[0037] Figure 2BThis is a schematic diagram of a fuzzy-fine write process according to another embodiment. Host data is delivered to FE module 202. The host data passes through XOR engine 204, generating XOR parity information. The data is then written to SRAM 206 at FE module 202. The data is then transferred from SRAM 206 at FE module 202 along stream 1 to encoder 212. Once the data is encoded, it is written to SLC 222 along stream 2. Simultaneously, while data is transferred to encoder 212 along stream 1, data is transferred to DRAM 230 along stream 3. The fuzzy-fine write process involves first sending the written data to DRAM 230, and then along stream 4 to encoder 212 for encoding. The encoded data is then fuzzily written to MLC along stream 5. Afterward, data is again sent from DRAM 230 to encoder 212 along stream 6 for encoding. After encoding, the data is finely written to MLC 224 along stream 7. The fuzzy write step transfers data from DRAM 230 to encoder 212 and writes the data to MLC 224. The fine write step occurs after the fuzzy write step. The fine write step transfers data from DRAM 230 to encoder 212 and writes the data to MLC 224. Due to buffer limitations, the SLC and MLC procedures can occur during sequential writes.

[0038] Figure 3 This is a diagram illustrating interlaced fuzzy-fine programming. It should be understood that this disclosure is not limited to... Figure 3 The example illustrates interleaved fuzzy-refined programming, but other sequences are also envisioned. More specifically, to perform fuzzy-refined programming, fuzzy programming along word lines of a specific string cannot occur back-to-back. For example... Figure 3 As shown, in order to correctly perform a fuzzy-fine write to word line 0 at string 0, several additional writes need to occur between the fuzzy write to word line 0, string 0 and the fine write to word line 0, string 0. The fuzzy-fine write process is performed as follows.

[0039] Initially, data is fuzzily written to word line 0 and string 0. Then, data is fuzzily written to word line 0 and string 1. Next, data is fuzzily written to word line 0 and string 2. Then, data is fuzzily written to word line 0 and string 3. Finally, data is fuzzily written to word line 1 and string 0. Now, finally, data can be precisely written to word line 0 and string 0. Figure 3The arrows in the diagram illustrate the write path during the fuzzy-fine write process. Essentially, to correctly fuzz-fine write data, the data is initially fuzz-written to a specific data location. Then, three additional fuzzy data writes occur to the same word line but at different strings. A fifth fuzzy write occurs along the adjacent word line of the same string at the specific data location. Only after the fifth fuzzy write to the adjacent word line and the same string can a fine write be performed to the original word line and the original string (i.e., the original data location). A total of four additional fuzzy writes occur before the fine write at the original string on the word line and after the initial fuzzy write on the word line at the original string.

[0040] Figure 4A This is a schematic diagram of fuzzy-fine programming of scheduling based on an implementation scheme. Figure 2A and Figure 2B The aspects can be similar to Figure 4A The schematic diagram of the scheduling fuzzy-fine programming is shown in the embodiment described above. Host data is written to the first SRAM 406 of FE module 402. While the host data is written to the first SRAM 406, first XOR parity data can be generated simultaneously at the first XOR engine 404 of FE module 402. The host data and the generated first XOR parity data are passed from the first SRAM 406 to the encoder 412 along stream 1 for encoding. The host data and the generated first XOR parity data are encoded and written along stream 2 to the SLC 422 of memory device 420. SLC 422 may be a dedicated area of ​​memory device 420 for protecting data in the event of power loss. Figure 2B Compared to the implementation described herein, programming for the SLC 422 and programming for the MLC 424 are decoupled, thereby allowing for increased scheduling flexibility and performance. Host data can be further categorized from the SLC 422 into multiple streams or erase blocks of the MLC 424.

[0041] At stream 3, host data is read from SLC 422 at decoder 414. After decoding the host data at decoder 414, the host data is written along stream 4 to the second SRAM 416 of FM2410, where second XOR parity data is further generated for the host data at the second XOR engine 432 of FM2410. The host data and the second XOR parity data are encoded along stream 5 by encoder 412 and fuzzily written along stream 6 to MLC 424. During fuzzy writing, the controller can selectively pick the data to be read to allow data to be classified into one or more relevant streams.

[0042] The host data and the generated second XOR parity data are further transferred along stream 7 from the second SRAM 416 to the DRAM 430. In one embodiment, streams 5 and 7 occur simultaneously. In another embodiment, stream 5 occurs before stream 7. The DRAM 430 may be a storage device such as... Figure 1 The storage device 104 includes additional volatile memory. Furthermore, the DRAM 430 can grade (e.g., a temporary buffer) host data and second XOR parity data until the associated word line of the host data can be finely written. The host data and second XOR parity data are further transferred from the DRAM 430 along stream 8 to encoder 412 for encoding. After encoding, the host data and second XOR parity data are finely written to MLC 424 along stream 9.

[0043] The total number of TM bus transfers, or transfers from FM2410 to memory device 420, is approximately four. The total number of DRAM 430 bus transfers is approximately two. The total number of transfers from DRAM 430 or FE module 402 to FM2410, or transfers from FM2410 to DRAM 430 or FE module 402, is approximately three, of which approximately three transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 430 or FE module 402 to FM2410, or transfers from FM2410 to DRAM 430 or FE module 402, may be more than approximately three.

[0044] Figure 4B This is a schematic diagram of waste collection according to an implementation plan. Figure 2A and Figure 2B The aspects can be similar to Figure 4B The schematic diagram of the waste collection implementation scheme is shown below. Because the host data is in Figure 4A The aforementioned scheduling fuzzy-fine programming has been committed to the NAND (e.g., MLC 424), so there is no need to write host data from the SLC 422. Garbage collection is a memory management process in which storage devices such as... Figure 1 The controller of storage device 104, such as Figure 1 The controller 108 attempts to release memory locations containing outdated data in order to restore memory space. When garbage collection occurs, the controller may attempt to copy all relevant data (e.g., non-outdated data) from a relevant location, such as a first erase block of a first stream, to another location, such as a second erase block of a first stream, in order to release resources associated with the original location, i.e., the first erase block.

[0045] Host data from the first MLC 424 region (e.g., the first erase block of the first stream) is copied along stream 1 from the MLC 424 to the decoder 414 of the FM2410. The host data is decoded and transmitted along stream 2 to the second SRAM 416. Simultaneously, second XOR parity data is generated at the second XOR engine 432. The host data and the second XOR parity data are transmitted along stream 3 to the encoder 412, where they are encoded. After encoding, the host data and the second XOR parity data are blurred and written to the MLC 424 along stream 4.

[0046] Host data and the generated second XOR parity data are transferred from the second SRAM 416 to the DRAM 430 along stream 5. In one embodiment, streams 3 and 5 occur simultaneously. In another embodiment, stream 3 occurs before stream 5. After successful writing to the DRAM 430, the host data and the second XOR parity data are further transferred from the DRAM 430 to the encoder 412 along stream 6 for encoding. The encoded host data and the second XOR parity data are then finely written to the MLC 424 along stream 7. Garbage collection of the original location of the data can occur after any of streams 1-7 has been successfully completed. After garbage collection, the area in the MLC 424 storing the host data and the second XOR parity data contains the relevant data and may require less memory space compared to the memory space requirements before garbage collection.

[0047] The total number of TM bus transfers, or transfers from FM2410 to memory device 420, is approximately three. The total number of DRAM 430 bus transfers is approximately two. The total number of transfers from DRAM 430 or FE module 402 to FM2410, or transfers from FM2410 to DRAM 430 or FE module 402, is approximately two, of which approximately two transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 430 or FE module 402 to FM2410, or transfers from FM2410 to DRAM 430 or FE module 402, may be more than approximately two. When compared with the embodiment described in FIG2, the total number of TM bus transfers, or transfers from FM2210 to memory device 220, or transfers from memory device 220 to FM2210, is approximately three. The total number of DRAM 230 bus transfers is approximately three. The total number of transfers from DRAM230 or FE module 202 to FM2 210 or from FM2 210 to DRAM230 or FE module 202 is approximately three, of which approximately three transfers are responsible for host data transfer. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM230 or FE module 202 to FM2 210 or from FM2 210 to DRAM230 or FE module 202 may be more than approximately three.

[0048] Figure 5 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme. Figure 2A and Figure 2B The aspects can be similar to Figure 5 The implementation scheme is illustrated in the diagram of fuzzy-fine programming for scheduling. Host data is received by FE module 502, wherein first XOR parity data is generated by first XOR engine 504. The host data and the generated first XOR parity data are written to the first SRAM 506 of FE module 502.

[0049] Host data and first XOR parity data are transferred along stream 1 from first SRAM 506 to encoder 512 for encoding. The encoded host data and encoded first XOR parity data are written along stream 2 to SLC 522, where SLC 522 may include buffers to queue received data before fuzzing-fine programming. Host data is transferred along stream 3 from SLC 522 to decoder 514, where decoder 514 decodes the received host data. Decoded host data is written along stream 4 to second SRAM 516 of FM2 510. In one embodiment, XOR parity data is generated at second SRAM 516 for the received decoded host data. Host data is copied along stream 5 to encoder 512 for encoding, where encoded host data is fuzzed and written along stream 6 to MLC 524.

[0050] Host data is transferred from the second SRAM 516 to the DRAM 530 along stream 7. In one embodiment, streams 5 and 7 occur simultaneously. In another embodiment, stream 5 occurs before stream 7. After successful writing to the DRAM 530, the host data and the second XOR parity data are further transferred from the DRAM 530 to the encoder 512 along stream 8 for encoding. The encoded host data and the second XOR parity data are then finely written to the MLC 524 along stream 9.

[0051] according to Figure 5 The implementation scheme mentioned above allows for the decoupling of SLC and MLC programming. The fuzzy-fine write process can include multi-streaming with write-through hot / cold sorting support and SLC burst support. Furthermore, open block reads of SLC are supported, addressing the DR and RD open block issues. Figure 2A and Figure 2B Compared to the previous implementation described herein, DRAM requirements can also be reduced.

[0052] The total number of TM bus transfers, or transfers from FM2 510 to memory device 520, is approximately four. The total number of DRAM 530 bus transfers is approximately two. The total number of transfers from DRAM 530 or FE module 502 to FM2 510, or from FM2 510 to DRAM 530 or FE module 502, is approximately three, of which approximately three transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 530 or FE module 502 to FM2 510, or from FM2 510 to DRAM 530 or FE module 502, may be more than approximately three. When compared with the embodiment described in FIG2, the total number of TM bus transfers, or transfers from FM2 210 to memory device 220, is approximately three. The total number of DRAM 230 bus transfers is approximately three. The total number of transfers from DRAM 230 or FE module 202 to FM2 210 or from FM2 210 to DRAM 230 or FE module 202 is approximately three, of which approximately three transfers are responsible for host data transfer. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 230 or FE module 202 to FM2 210 or from FM2 210 to DRAM 230 or FE module 202 may be more than approximately three.

[0053] Figure 6 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme. Figure 2A and Figure 2B The aspects can be similar to Figure 6 The implementation scheme is illustrated in the diagram of fuzzy-fine programming for scheduling. Host data is received by FE module 602, wherein first XOR parity data is generated by first XOR engine 604. The host data and the generated first XOR parity data are written to the first SRAM 606 of FE module 602.

[0054] Host data and first XOR parity data are transferred along stream 1 from first SRAM 606 to encoder 612 for encoding. The encoded host data and encoded first XOR parity data are written along stream 2 to SLC 622, where SLC 622 may include buffers to queue the received data before fuzzy-fine programming. Host data is fuzzily written from SLC 622 to MLC 624 along stream 3.

[0055] At the first SRAM 606, host data and the first XOR parity data are written to DRAM 630 along stream 4. Writing to DRAM 630 along stream 4 can occur simultaneously with stream 1 or stream 2. Host data is copied from DRAM 630 to encoder 612 along stream 5 for encoding. The encoded host data is finely written to MLC 624 along stream 6.

[0056] The total number of TM bus transfers, or transfers from FM2610 to memory device 620, is approximately two, resulting in less TM bus power consumption than other previously described embodiments. The total number of DRAM 630 bus transfers is approximately two. The total number of transfers from DRAM 630 or FE module 602 to FM2610, or from FM2610 to DRAM 630 or FE module 602, is approximately two, of which approximately two transfers are responsible for host data transfer. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 630 or FE module 602 to FM2610, or from FM2610 to DRAM 630 or FE module 602, may be more than approximately two. When compared with the embodiment described in FIG2, the total number of TM bus transfers, or transfers from FM2 210 to memory device 220, is approximately three. The total number of DRAM 230 bus transfers is approximately three. The total number of transfers from DRAM 230 or FE module 202 to FM2 210, or from FM2 210 to DRAM 230 or FE module 202, is approximately three, of which approximately three transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 230 or FE module 202 to FM2 210, or from FM2 210 to DRAM 230 or FE module 202, may be more than approximately three.

[0057] Figure 7 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme. Figure 2A and Figure 2B The aspects can be similar to Figure 7 The implementation scheme is illustrated in the diagram of fuzzy-fine programming for scheduling. Host data is received at FE module 702, where a first XOR engine 704 generates first XOR parity data for the host data, and both the host data and the first XOR parity data are written to a first SRAM 706. The host data and the first XOR parity data are copied from SRAM 706 to encoder 712 along stream 1. Encoder 712 encodes the received host data and the first XOR parity data and writes the encoded data to SLC 722 along stream 2.

[0058] Host data is transferred from SLC 722 to decoder 714 along stream 3, where decoder 714 decodes the host data. The decoded host data is written to DRAM 730 along stream 4. The host data is encoded at encoder 712 along stream 5 and then fuzzily written to MLC 724 along stream 6. After fuzzy writing to MLC 724, the host data is again encoded at encoder 712 along stream 7, where the encoded host data is finely written to MLC 724 along stream 8. The fuzzy-fine writing to MLC 724 does not include XOR parity data. XOR parity data can be stored in SLC 722.

[0059] The total number of TM bus transfers, or transfers from FM2 710 to memory device 720, is approximately four. The total number of DRAM 730 bus transfers is approximately three. The total number of transfers from DRAM 730 or FE module 702 to FM2 710, or from FM2 710 to DRAM 730 or FE module 702, is approximately four, of which approximately four transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 730 or FE module 702 to FM2 710, or from FM2 710 to DRAM 730 or FE module 702, may be more than approximately four. When compared with the embodiment described in FIG2, the total number of TM bus transfers, or transfers from FM2 210 to memory device 220, is approximately three. The total number of DRAM 230 bus transfers is approximately three. The total number of transfers from DRAM 230 or FE module 202 to FM2 210 or from FM2 210 to DRAM 230 or FE module 202 is approximately three, of which approximately three transfers are responsible for host data transfer. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 230 or FE module 202 to FM2 210 or from FM2 210 to DRAM 230 or FE module 202 may be more than approximately three.

[0060] Figure 8 This is a schematic diagram of scheduling fuzzy-fine programming based on another implementation scheme. Figure 2A and Figure 2B The aspects can be similar to Figure 8The implementation scheme is illustrated in the diagram of fuzzy-fine programming for scheduling. Host data is received by FE module 802 and written to SRAM 806. First XOR engine 804 generates first XOR parity data for the host data and writes the first XOR parity data to SRAM 806. The host data and the first XOR parity data are transmitted along stream 1 to encoder 812, where encoder 812 encodes the host data and the first XOR parity data.

[0061] Both host data and the first XOR parity data are written to SLC 822 along stream 2. Host data is copied from SLC 822 to decoder 814 along stream 3, where decoder 814 decodes the host data. The decoded host data is copied along stream 4 to the second SRAM 816 of FM2 810, and along stream 5 to the third SRAM 832 of FE module 802. Host data is copied along stream 6 from the third SRAM 832 to encoder 812, and along stream 7 from the second SRAM 816 to encoder 812.

[0062] Encoded host data is fuzzily written from encoder 812 to MLC 824 along stream 8. Decoded host data is copied from second SRAM 816 to DRAM 830 along stream 9, and from third SRAM 832 to DRAM 830 along stream 10. Host data is copied from DRAM 830 to encoder 812 along stream 11. Then, encoded host data is finely written from encoder 812 to MLC 824 along stream 12. The fuzzy-fine write to MLC 824 does not include XOR parity data. XOR parity data can be stored in SLC 822.

[0063] The total number of TM bus transfers, or transfers from FM2 810 to memory device 820, is approximately four. The total number of DRAM 830 bus transfers is approximately two. The total number of transfers from DRAM 830 or FE module 802 to FM2 810, or from FM2 810 to DRAM 830 or FE module 802, is approximately 3.5, of which approximately 3.5 transfers are responsible for 50 / 50 SRAM buffer partitioning. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 830 or FE module 802 to FM2 810, or from FM2 810 to DRAM 830 or FE module 802, may be more than approximately 3.5. When compared with the embodiment described in Figure 2, the total number of TM bus transfers, or transfers from FM2 210 to memory device 220, is approximately three. The total number of DRAM 230 bus transfers is approximately three. The total number of transfers from DRAM 230 or FE module 202 to FM2 210, or from FM2 210 to DRAM 230 or FE module 202, is approximately three, of which approximately three transfers are responsible for host data transfers. Depending on the number of transfers associated with XOR parity data overhead, the total number of transfers from DRAM 230 or FE module 202 to FM2 210, or from FM2 210 to DRAM 230 or FE module 202, may be more than approximately three.

[0064] In one embodiment, a data storage device includes: one or more memory devices, including SLC memory and MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; and fuzzily write data to the MLC memory, wherein fuzzily writing data to the MLC memory includes: retrieving data from a latch in the one or more memory devices; decoding the data retrieved from the latch; encoding the decoded data retrieved from the latch; and writing the encoded data to the MLC memory; and finely writing the data to the MLC memory. Fine writing includes: decoding the data retrieved from the latch; generating XOR data for the decoded data retrieved from the latch; transferring the decoded data retrieved from the latch and the generated XOR data to DRAM; encoding the transferred data; and writing the encoded data to the MLC memory. Decoding the data retrieved from the latch for fine writing is the same as decoding the data retrieved from the latch for fuzzy writing. The controller is configured to perform garbage collection, which includes: reading data from MLC memory; decoding the read data; generating XOR data from the read data; encoding the generated XOR data and the read data; and fuzzily writing the encoded data to MLC memory. Garbage collection further includes finely writing data to MLC memory, wherein finely writing includes: decoding the data read from MLC; generating XOR data from the read data; transferring the read data and the generated XOR data to DRAM; encoding the transferred data; and finely writing the encoded data to MLC memory. Decoding the data retrieved from the latch for fine writing is the same as decoding the data retrieved from the latch for fuzzy writing. Fuzzy writing further includes: generating XOR data from the decoded data retrieved from the latch; and transferring the generated XOR data to DRAM.

[0065] In another embodiment, a data storage device includes: one or more memory devices, each including a plurality of dies, wherein each die includes SLC memory and MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; read data from the SLC memory; decode the read data; transfer the decoded data to DRAM; perform a first encoding on the transferred data; and first write the first-encoded data to the MLC memory. The controller is further configured to perform a second encoding on the transferred data. The controller is further configured to write the second-encoded data to the MLC memory. The first writing of the first-encoded data to the MLC memory is a fuzzy write. The second writing of the second-encoded data to the MLC memory is a fine write. The controller is further configured to transfer the decoded data to SRAM before transferring the decoded data to DRAM. The controller is further configured to encode some data transferred to SRAM without transferring the data transferred to SRAM to DRAM.

[0066] In another embodiment, a data storage device includes: one or more memory devices, each memory device having a plurality of dies, wherein each of the one or more memory devices includes SLC memory and MLC memory; and a controller coupled to the one or more memory devices, the controller being configured to: write data to the SLC memory; read data from the SLC memory; decode the read data; deliver the decoded data to a first SRAM located in a front-end module; deliver the decoded data to a second SRAM located in a flash manager; write the data delivered to the first SRAM into the MLC memory; and write the data delivered to the second SRAM into the MLC memory. The controller is further configured to deliver the decoded data to DRAM. The controller is further configured to encode the decoded data delivered to the DRAM and write the encoded data to the MLC memory. The encoded data written to the MLC memory is finely written. The data written from the first SRAM to the MLC memory is fuzzy written. The data written from the second SRAM to the MLC memory is fuzzy written.

[0067] By reducing data transfer on the NAND bus and DRAM bus, host write performance is improved and power consumption is reduced. Transfers on the NAND bus are reduced by 20%, and transfers on the DRAM bus are reduced by one-third.

[0068] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: One or more memory devices, the one or more memory devices including SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data into the SLC memory; The data is written to the MLC memory in a blurred state, wherein writing the data to the MLC memory in a blurred state includes: Retrieve the data from the SLC memory; Decode the data retrieved from the SLC memory; Encode the decoded data retrieved from the SLC memory; and Write the encoded data into the MLC memory; and The data is written precisely into the MLC memory.

2. A data storage device, the data storage device comprising: One or more memory devices, the one or more memory devices including SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data into the SLC memory; The data is written to the MLC memory in a blurred state, wherein writing the data to the MLC memory in a blurred state includes: Retrieve the data from the latches of the one or more memory devices; Decode the data retrieved from the latch; Encode the decoded data retrieved from the latch; and Write the encoded data into the MLC memory; and The data is written finely into the MLC memory, wherein the fine writing includes: Decode the data retrieved from the latch; XOR data is generated for the decoded data retrieved from the latch; The decoded data retrieved from the latch and the generated XOR data are transferred to DRAM; Encode the transmitted data; and The encoded data is written into the MLC memory.

3. The data storage device of claim 2, wherein decoding the data retrieved from the latch for fine writing is the same as decoding the data retrieved from the latch for fuzzy writing.

4. A data storage device, the data storage device comprising: One or more memory devices, the one or more memory devices including SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data into the SLC memory; The data is written to the MLC memory in a blurred state, wherein writing the data to the MLC memory in a blurred state includes: Retrieve the data from the latches of the one or more memory devices; Decode the data retrieved from the latch; Encode the decoded data retrieved from the latch; and Write the encoded data into the MLC memory; The data is carefully written into the MLC memory; and Performing garbage collection, wherein the garbage collection includes: Read data from MLC memory; Decode the read data; Generate XOR data based on the read data; Encode the generated XOR data and the read data; and The encoded data is written in a fuzzy manner into the MLC memory.

5. The data storage device of claim 4, wherein the garbage collection further comprises finely writing data to the MLC memory, wherein the fine writing comprises: Decode the data read from the MLC; Generate XOR data from the read data; The read data and the generated XOR data are transferred to DRAM; Encode the transmitted data; as well as The encoded data is carefully written into the MLC memory.

6. The data storage device of claim 5, wherein decoding the data retrieved from the latch for fine writing is the same as decoding the data retrieved from the latch for fuzzy writing.

7. A data storage device, the data storage device comprising: One or more memory devices, the one or more memory devices including SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data into the SLC memory; The data is written to the MLC memory in a blurred state, wherein writing the data to the MLC memory in a blurred state includes: Retrieve the data from the latches of the one or more memory devices; Decode the data retrieved from the latch; XOR data is generated for the decoded data retrieved from the latch; The generated XOR data is transferred to DRAM; Encode the decoded data retrieved from the latch; and Write the encoded data into the MLC memory; and The data is written precisely into the MLC memory.

8. A data storage device, the data storage device comprising: One or more memory devices, each of the one or more memory devices including a plurality of dies, wherein each die includes SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data to the SLC memory; Read data from SLC memory; Decode the read data; Transfer the decoded data to DRAM; The transmitted data is encoded for the first time. as well as The data encoded for the first time is written to the MLC memory for the first time.

9. The data storage device of claim 8, wherein the controller is further configured to encode the transmitted data a second time.

10. The data storage device of claim 9, wherein the controller is further configured to write the second-encoded data into the MLC memory.

11. The data storage device of claim 10, wherein writing the first encoded data to the MLC memory for the first time is an fuzzy write.

12. The data storage device of claim 11, wherein writing the second encoded data to the MLC memory for the second time is a fine write.

13. A data storage device, the data storage device comprising: One or more memory devices, each of the one or more memory devices including a plurality of dies, wherein each die includes SLC memory and MLC memory; and A controller, coupled to the one or more memory devices, is configured to: Write the data to the SLC memory; Read data from SLC memory; Decode the read data; Transfer the decoded data to DRAM; The decoded data is transferred to SRAM before being transferred to DRAM; The transmitted data is encoded for the first time. as well as The data encoded for the first time is written to the MLC memory for the first time.

14. The data storage device of claim 13, wherein the controller is further configured to encode some data transferred to the SRAM without transferring the data to the SRAM to the DRAM.

15. A data storage device, the data storage device comprising: One or more memory devices, wherein each of the one or more memory devices includes SLC memory and MLC memory; A controller, coupled to the one or more memory devices, is configured to: Write the data into the SLC memory; Read the data from the SLC memory; Decode the read data; Decode the data and deliver it to the first SRAM located in the front-end module. The decoded data is delivered to a second SRAM located in the flash memory manager; The data delivered to the first SRAM is written into the MLC memory; as well as The data delivered to the second SRAM is written into the MLC memory.

16. The data storage device of claim 15, wherein the controller is further configured to deliver decoded data to DRAM.

17. The data storage device of claim 16, wherein the controller is further configured to encode the decoded data delivered to the DRAM and write the encoded data to the MLC memory.

18. The data storage device of claim 17, wherein the encoded data written to the MLC memory is finely written.

19. The data storage device of claim 15, wherein the data written from the first SRAM to the MLC memory is fuzzy written.

20. The data storage device of claim 15, wherein the data written from the second SRAM to the MLC memory is fuzzy written.

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