Semiconductor die including a diffusion barrier layer embedding a bonding pad and method of forming the same

Abstract

A semiconductor device can be formed over a semiconductor substrate, and an interconnect level dielectric material layer embedding a metal interconnect structure can be formed over the semiconductor device. In one embodiment, a pad connection via level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad level dielectric material layer can be formed. A bonding pad surrounded by a dielectric diffusion barrier portion can be formed in the pad level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad and via level dielectric material layer can be formed. An integrated pad and via cavity can be formed through the pad and via level dielectric material layer and can be filled with a bonding pad containing a dielectric diffusion barrier portion and an integrated pad and via structure.

Description

[0001] Related Applications

[0002] This application claims priority benefits of the following patent applications: U.S. Non - Provisional Patent Application No. 16 / 888,055, filed on May 29, 2020; and U.S. Non - Provisional Patent Application No. 16 / 888,188, filed on May 29, 2020, the entire contents of which are hereby incorporated by reference herein for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to a semiconductor die including bond pads embedded in a diffusion barrier layer and a method of forming the same. Background Art

[0004] Semiconductor memory devices may include a memory array and driver circuits located on the same substrate. However, the driver circuits occupy valuable space on the substrate, thereby reducing the available space for the memory array. Summary of the Invention

[0005] According to one aspect of the present disclosure, a structure is provided that includes a first semiconductor die. The first semiconductor die includes: a first semiconductor device located above a first substrate; a first interconnect - level dielectric material layer embedding a first metal interconnect structure that is electrically connected to and covers the first semiconductor device; a layer stack of a first pad - connection via - level dielectric material layer and a first proximal dielectric diffusion barrier layer that covers the first interconnect - level dielectric material layer and embeds a first pad - connection via structure; and a first pad - level dielectric material layer including a first pad cavity filled with a respective combination of a first bond pad and a corresponding first dielectric diffusion barrier portion, wherein each of the first bond pads in the first bond pads contacts a respective subgroup of the first pad - connection via structures.

[0006] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a layer stack of a first pad connection via level dielectric material layer and a first proximal dielectric diffusion barrier layer over the first semiconductor device, the layer stack embedding a first metal interconnect structure; forming a first pad connection via structure through the layer stack over a subgroup of the first metal interconnect structure; forming a first pad level dielectric material layer over the layer stack; forming a first pad cavity through the first pad level dielectric material layer; forming a first distal dielectric diffusion barrier layer in the first pad cavity and over the first pad level dielectric material layer; forming an opening through the first distal dielectric diffusion barrier layer at a bottom portion of the first pad cavity, wherein a top surface of the first pad connection via structure is physically exposed; and forming a first bonding pad directly on the top surface of the first pad connection via structure in a remaining volume of the first pad cavity.

[0007] According to one aspect of the present disclosure, a structure is provided that includes a first semiconductor die. The first semiconductor die includes: a first semiconductor device located over a first substrate; a first interconnect level dielectric material layer embedding a first metal interconnect structure, the first metal interconnect structure being electrically connected to and covering the first semiconductor device; a layer stack of a first proximal dielectric diffusion barrier layer and a first pad and via level dielectric material layer covering the first interconnect level dielectric material layer and embedding a first integrated pad and via structure; and a first dielectric diffusion barrier portion embedded in the first pad and via level dielectric material layer, wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion contacts and laterally surrounds a pad portion of a corresponding first integrated pad and via structure in the first integrated pad and via structure.

[0008] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a first interconnect level dielectric layer embedding a first metal interconnect structure over the first semiconductor device; forming a first proximal dielectric diffusion barrier layer and a first pad and via level dielectric material layer over the first semiconductor device; forming a first integrated pad and via cavity through the first pad and via level dielectric material layer; forming a first distal dielectric diffusion barrier layer in the first integrated pad and via cavity and over the first pad and via level dielectric material layer; removing a horizontal portion of the first distal dielectric diffusion barrier layer within a region of the first integrated pad and via cavity, wherein a top surface of a subgroup of the first metal interconnect structure is physically exposed; and forming a first integrated pad and via structure in a remaining volume of the first pad and via cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first interconnect level dielectric material layer and a first metal interconnect structure in accordance with a first embodiment of the present disclosure.

[0010] Figure 1B is Figure 1A a schematic top view of the first semiconductor die.

[0011] Figure 1C is a schematic vertical cross-sectional view of a first configuration of a first semiconductor die along a Figure 1B vertical plane C-C' of.

[0012] Figure 1D is along Figure 1C a schematic horizontal cross-sectional view of a first configuration of a first semiconductor die along a horizontal plane D-D'. The vertical plane C-C' is the Figure 1C plane of the vertical cross-sectional view of.

[0013] Figure 1E is along Figure 1C a schematic horizontal cross-sectional view of a first configuration of a first semiconductor die along a horizontal plane E-E'. The vertical plane C-C' is the Figure 1C plane of the vertical cross-sectional view of.

[0014] Figure 2A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming an interconnect capping dielectric diffusion barrier layer, a first pad connection via level dielectric material layer, a first proximal dielectric diffusion barrier layer, and a first pad connection via in accordance with a first embodiment of the present disclosure.

[0015] Figure 2B is Figure 2A a schematic top view of the first semiconductor die.

[0016] Figure 3A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first pad connection via structure in accordance with a first embodiment of the present disclosure.

[0017] Figure 3B is Figure 3A a schematic top view of the first semiconductor die.

[0018] Figure 4A is a schematic vertical cross-sectional view of a region of a first configuration of a first semiconductor die after forming a first pad level dielectric material layer and a first pad cavity in accordance with a first embodiment of the present disclosure.

[0019] Figure 4Bis Figure 4A A schematic top view of a first semiconductor die.

[0020] Figure 5 A schematic vertical cross - sectional view of a region of a first configuration of a first semiconductor die after forming a first distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

[0021] Figure 6 A schematic vertical cross - sectional view of a region of a first configuration of a first semiconductor die after patterning a first distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

[0022] Figure 7 A schematic vertical cross - sectional view of a region of a first configuration of a first semiconductor die after removing a patterned photoresist layer according to a first embodiment of the present disclosure.

[0023] Figure 8A A schematic vertical cross - sectional view of a region of a first configuration of a first semiconductor die after forming a first bonding pad according to a first embodiment of the present disclosure.

[0024] Figure 8B is Figure 8A A schematic top view of a first semiconductor die.

[0025] Figure 9 A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after forming a second pad via - hole structure according to a first embodiment of the present disclosure.

[0026] Figure 10 A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after forming a second pad - level dielectric material layer and a second pad cavity according to a first embodiment of the present disclosure.

[0027] Figure 11 A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after forming a second distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

[0028] Figure 12 A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after patterning a second distal dielectric diffusion barrier layer according to a first embodiment of the present disclosure.

[0029] Figure 13 A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after removing a patterned photoresist layer according to a first embodiment of the present disclosure.

[0030] Figure 14A schematic vertical cross - sectional view of a region of a first configuration of a second semiconductor die after forming a second bonding pad, according to a first embodiment of the present disclosure.

[0031] Figure 15 A schematic vertical cross - sectional view of a first exemplary bonding structure after bonding a first configuration of a first semiconductor die to a first configuration of a second semiconductor die, according to a first embodiment of the present disclosure.

[0032] Figure 16 A schematic vertical cross - sectional view of a first exemplary bonding structure after thinning a first semiconductor die from the back side, according to a first embodiment of the present disclosure.

[0033] Figure 17 A schematic vertical cross - sectional view of a first exemplary bonding structure after forming a back - side insulating layer, an external bonding pad, and a solder material portion, according to a first embodiment of the present disclosure.

[0034] Figure 18 A schematic vertical cross - sectional view of an alternative embodiment of a first semiconductor die, according to a first embodiment of the present disclosure.

[0035] Figure 19 A schematic vertical cross - sectional view of an alternative embodiment of a first exemplary bonding structure, according to a first embodiment of the present disclosure.

[0036] Figure 20A Is along the Figure 20E A vertical cross - sectional view of a second alternative embodiment of a first exemplary bonding assembly along a vertical plane A–A' according to a first embodiment of the present disclosure.

[0037] Figure 20B Is along Figure 20E A vertical cross - sectional view of a first exemplary bonding assembly along a vertical plane B - B'.

[0038] Figure 20C Is along Figure 20E A vertical cross - sectional view of a memory array region of a first exemplary bonding assembly along a vertical plane C - C'.

[0039] Figure 20D Is along Figure 20E A vertical cross - sectional view of a peripheral region of a first exemplary bonding assembly along a vertical plane D - D'.

[0040] Figure 20E Is Figures 20A to 20D A perspective plan view of the first exemplary bonding assembly shown.

[0041] Figure 20F Is along Figure 20EVertical cross-sectional view of a first exemplary bonding assembly of the vertical plane F-F'.

[0042] Figure 20G is along Figure 20E Vertical cross-sectional view of a first exemplary bonding assembly of the vertical plane G-G'.

[0043] Figure 21A Vertical cross-sectional view of a third alternative embodiment of a first exemplary bonding assembly according to an embodiment of the present disclosure.

[0044] Figure 21B Vertical cross-sectional view of a fourth alternative embodiment of a first exemplary bonding assembly according to an embodiment of the present disclosure.

[0045] Figure 22 Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after forming a first interconnect level dielectric material layer, a first metal interconnect structure, a first proximal dielectric diffusion barrier layer, a first pad, and a via level dielectric material layer and a first pad cavity according to a second embodiment of the present disclosure.

[0046] Figure 23A Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after forming a first integrated pad and a via cavity according to a second embodiment of the present disclosure.

[0047] Figure 23B is Figure 23A Schematic top view of a first semiconductor die.

[0048] Figure 24 Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after forming a first distal dielectric diffusion barrier layer according to a second embodiment of the present disclosure.

[0049] Figure 25 Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after patterning a first distal dielectric diffusion barrier layer according to a second embodiment of the present disclosure.

[0050] Figure 26 Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after depositing a first metal liner layer and a first metal pad fill material layer according to a second embodiment of the present disclosure.

[0051] Figure 27A Schematic vertical cross-sectional view of a region of a second configuration of a first semiconductor die after forming a first integrated pad and a via structure according to a second embodiment of the present disclosure.

[0052] Figure 27B is Figure 27ASchematic top view of the first semiconductor die.

[0053] Figure 28 Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after forming a second proximal dielectric diffusion barrier layer, a second pad, a via - level dielectric material layer, and a second pad cavity, according to a second embodiment of the present disclosure.

[0054] Figure 29A Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after forming a second integrated pad and a via cavity, according to a second embodiment of the present disclosure.

[0055] Figure 29B Is Figure 29A Schematic top view of the second semiconductor die.

[0056] Figure 30 Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after forming a second distal dielectric diffusion barrier layer, according to a second embodiment of the present disclosure.

[0057] Figure 31 Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after patterning the second distal dielectric diffusion barrier layer, according to a second embodiment of the present disclosure.

[0058] Figure 32 Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after depositing a second metal liner layer and a second metal pad fill material layer, according to a second embodiment of the present disclosure.

[0059] Figure 33A Is a schematic vertical cross - sectional view of a region of a second configuration of a second semiconductor die after forming a second integrated pad and a via structure, according to a second embodiment of the present disclosure.

[0060] Figure 33B Is Figure 33A Schematic top view of the second semiconductor die.

[0061] Figure 34 Is a schematic vertical cross - sectional view of a second exemplary bonding structure after bonding the second configuration of the first semiconductor die to the second configuration of the second semiconductor die, according to a second embodiment of the present disclosure.

[0062] Figure 35 Is a schematic vertical cross - sectional view of a second exemplary bonding structure after thinning the first semiconductor die from the back side, according to a second embodiment of the present disclosure.

[0063] Figure 36A schematic vertical cross - sectional view of a second exemplary bonding structure after forming a dorsal insulating layer, an external bonding pad, and a solder material portion according to a second embodiment of the present disclosure.

[0064] Figure 37 A schematic vertical cross - sectional view of an alternative embodiment of a first semiconductor die according to a second embodiment of the present disclosure.

[0065] Figure 38 A schematic vertical cross - sectional view of an alternative embodiment of a second exemplary bonding structure according to a second embodiment of the present disclosure. Detailed Description

[0066] In a semiconductor die configured for pad - to - pad bonding, metal bonding pads are provided as discrete structures without metal lines located between the bonding pads in order to reduce concave deformation or corrosion of the metal bonding pads during a chemical - mechanical planarization (i.e., chemical - mechanical polishing CMP) process. Thus, the bonding pads in the edge - seal region do not completely surround the interior portion of the die, and the edge - seal structure has a lateral opening at the level of the metal bonding pads. Moisture or ionic impurities can diffuse through the dielectric matrix embedding the metal bonding pads and can penetrate into underlying semiconductor device components such as field - effect transistors, memory cells, or metal interconnect structures and cause reliability degradation of various components in the semiconductor device. In other words, moisture or impurities can laterally diffuse through the gaps between pairs of adjacent metal bonding pads. Embodiments of the present disclosure relate to a semiconductor die including bonding pads surrounded by a diffusion barrier layer and a method of manufacturing the same, aspects of which are discussed in detail below. The diffusion barrier layer reduces or prevents moisture and / or impurities from diffusing into underlying semiconductor device components and improves the reliability of the semiconductor device.

[0067] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is shown, unless explicitly described or otherwise clearly indicated as not having a repetition of the element. Ordinal numbers such as "first", "second", and "third" are used merely to identify similar elements and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0068] Like reference numerals designate like or similar elements. Unless otherwise specified, elements having like reference numerals are assumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements do not contact each other directly, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is an electrical conduction path between the first element and the second element formed of at least one conductive material. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0069] As used herein, a "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Additionally, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above it, and / or below it.

[0070] As used herein, a first surface and a second surface are "vertically coincident" with each other if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane including the first surface and the second surface. A substantially vertical plane is a plane that extends linearly in a direction at an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight in the vertical or substantially vertical direction and may or may not include curvature in a direction perpendicular to the vertical or substantially vertical direction.

[0071] As used herein, a "memory level" or "memory array level" refers to a level of a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) corresponding to the topmost surface of an array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through the memory level.

[0072] As used herein, a "semiconductor material" refers to a material having a conductivity between 1.0×10 -5from S / m to 1.0×10 5 a material having a conductivity in the range of S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of electrical dopants, and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 5 S / m when appropriately doped with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / m) when formed as a crystalline material or when converted to a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A "doped semiconductor material" may be a heavily doped semiconductor material or may be a semiconductor material including electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration providing a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, a "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are made under standard conditions.

[0073] The various three-dimensional memory devices of the present disclosure include single-level three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein. The single-level three-dimensional NAND strings are located in a single-level three-dimensional NAND string array located above a substrate. At least one memory cell in a first device tier of the three-dimensional NAND string array is located above another memory cell in a second device tier of the three-dimensional NAND string array.

[0074] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips"), which are through-bonded, for example, by flip-chip bonding or another chip-to-chip bonding method. The package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of its planes. Each die includes one or more planes. The same concurrent operations can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0075] Reference Figures 1A to 1E , a first semiconductor die 900 in a first configuration is shown. Figure 1B and Figures 1D to 1E views corresponding to the entire region of the first semiconductor die 900 and an adjacent scribe region that is subsequently removed during the die sawing process. The first semiconductor die 900 includes a first substrate 908, a first semiconductor device 920 overlying the first substrate 908, a first interconnect-level dielectric material layer (290, 960) overlying the first semiconductor device, and a first metal interconnect structure 980 embedded in the first interconnect-level dielectric material layer (290, 960). In one embodiment, the first substrate 908 can be a first semiconductor substrate, such as a commercially available silicon wafer having a thickness in the range of 500 microns to 1 mm.

[0076] Discrete substrate recess cavities can be formed in the upper portion of the first substrate 908 by applying a photoresist layer over the top surface of the first substrate 908, lithographically patterning the photoresist layer to form an array of discrete openings, and transferring the pattern of the discrete opening array into the upper portion of the first substrate by performing an anisotropic etching process. Subsequently, the photoresist layer can be removed, for example, by ashing. The depth of each discrete substrate recess cavity can be in the range of 500 nm to 10,000 nm, but smaller and larger depths can also be used. A through-substrate liner 386 and a through-substrate via structure 388 can be formed in each discrete substrate recess cavity.

[0077] Generally speaking, the first semiconductor device 920 may include any semiconductor device known in the art. In one embodiment, the first semiconductor die 900 includes a memory die and may include a memory device such as a three-dimensional NAND memory device. In an illustrative example, the first semiconductor device 920 may include a vertical alternating stack of an insulating layer 32 and a conductive layer 46, and a two-dimensional array of memory openings extending vertically through the vertical alternating stack (32, 46). The conductive layer 46 may include word lines of the three-dimensional NAND memory device.

[0078] A memory opening fill structure 58 may be formed in each memory opening. The memory opening fill structure 58 may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a blocking dielectric, a tunneling dielectric, and a charge storage material located between the blocking dielectric and the tunneling dielectric. The charge storage material may include a charge trapping layer (such as a silicon nitride layer) or a plurality of discrete charge trapping regions (such as floating gates or discrete portions of the charge trapping layer). In this case, each memory opening fill structure 58 and an adjacent portion of the conductive layer 46 constitute a vertical NAND string. Alternatively, the memory opening fill structure 58 may include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase change memory element, etc. The memory device may include an optional horizontal semiconductor channel layer 10 connected to the bottom end of each vertical semiconductor channel, and an optional dielectric spacer layer 910 providing electrical isolation between the first substrate 908 and the horizontal semiconductor channel layer 10.

[0079] The conductive layer 46 may be patterned to provide a platform region, where each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Contact via structures (not shown) may be formed in the platform regions on the conductive layer 46 to provide electrical connections to the conductive layer 46. Dielectric material portions 65 may be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46).

[0080] Through-memory-level via cavities may be formed through the dielectric material portions 65, the optional dielectric spacer layer 910, and the horizontal semiconductor channel layer 10. Optional through-memory-level dielectric liners 486 and through-memory-level via structures 488 may be formed in each through-memory-level via cavity. Each through-memory-level dielectric liner 486 contains a dielectric material, such as silicon oxide. Each through-memory-level via structure 488 may be formed directly on a corresponding one of the through-substrate via structures in the through-substrate via structure 388.

[0081] The first interconnect level dielectric material layer (290, 960) may include a first proximal interconnect level dielectric material layer 290 embedding contact via structures and bit lines 982, and a first distal interconnect level dielectric material layer 960 embedding a subgroup of first metal interconnect structures 980 located above the first proximal interconnect level dielectric material layer 290. The bit lines 982 are a subgroup of the first metal interconnect structures 980 and may be in electrical contact with a drain region above a semiconductor channel located at the top of the memory opening fill structure 58. The contact via structures contact respective nodes of the first semiconductor device. Generally speaking, the first metal interconnect structures 980 may be electrically connected to the first semiconductor device 920. A proximal subgroup of the first metal interconnect structures 980 may be located within the first distal interconnect level dielectric material layer 960. Interconnect metal lines and interconnect metal via structures as a subgroup of the first metal interconnect structures 980 may be embedded in the first distal interconnect level dielectric material layer 960. In an illustrative example, the first metal interconnect structures 980 may include a first memory side metal level M1 and a second memory side metal level M2, the first memory side metal level including memory side first level metal lines, and the second memory side metal level including memory side second level metal lines.

[0082] Each of the first proximal interconnect level dielectric material layer 290 and the first distal interconnect level dielectric material layer 960 may contain a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, silicon nitride, dielectric metal oxide, or a combination thereof. The first distal interconnect level dielectric material layer 960 may include one or more dielectric diffusion barrier layers (not explicitly shown). In such a case, each dielectric diffusion barrier layer embedded in the first distal interconnect level dielectric material layer 960 may contain silicon carbonitride (i.e., carbon silicon nitride “SiCN”, which is also referred to as silicon carbide nitride), silicon nitride (Si3N4), silicon oxynitride, or any other dielectric material effective in blocking the diffusion of copper. In one embodiment, each dielectric diffusion barrier layer embedded in the first distal interconnect level dielectric material layer 960 may include a dielectric material having a dielectric constant less than 5 such as less than 4, such as SiCN having a dielectric constant of about 3.8, to reduce the RC delay of the first metal interconnect structures 980. Each dielectric diffusion barrier layer may have a thickness in the range of 10 nm to 300 nm.

[0083] Figures 1B to 1EAt least one edge seal structure (688, 984, 986) shown can be formed around the periphery of the first semiconductor die 900 through the dielectric material portion 65 and the first interconnect level dielectric material layer (290, 960). For example, at least one trench groove can be formed that extends vertically through the dielectric material portion 65 and optionally through the lower level of the first interconnect level dielectric material layer (290, 960), and then the at least one trench groove can be filled with at least one dielectric material to form at least one first metal wall structure 688. A plurality of nested metal wall structures 688 can be formed. Each first metal wall structure 688 extends continuously around the periphery of the first semiconductor die 900 and completely laterally encapsulates the first semiconductor device 920. The entire bottom surface of each metal wall structure 688 can contact the top surface of the first substrate 908.

[0084] Each edge seal structure in the at least one edge seal structure (688, 984, 986) can also optionally include at least one via level ring structure 984 that is formed over the corresponding metal wall structure in the at least one metal wall structure 688 and at the corresponding metal via level. Each via level ring structure 984 is a component of the first metal interconnect structure 980. Additionally, each edge seal structure in the edge seal structures (688, 984, 986) can include at least one wire level ring structure 986. Each wire level ring structure 986 is a component of the first metal interconnect structure 980. Each wire level ring structure 986 is formed over the corresponding metal wall structure in the at least one metal wall structure 688 and at the corresponding metal wire level. Generally, each edge seal structure (688, 984, 986) includes at least one set of continuous conductive material portions that extend vertically from the first substrate 908 to the top surface of the first interconnect level dielectric material layer (290, 960). Each edge seal structure (688, 984, 986) includes a set of continuous conductive material portions that laterally surround the first semiconductor device 920 without any opening therethrough.

[0085] In one embodiment, each edge seal structure in the at least one edge seal structure (688, 984, 986) can include a metal wall structure 688 and a corresponding subgroup of the first metal interconnect structure 980 that provides a corresponding continuous barrier layer that laterally surrounds the first semiconductor device 920 without any lateral opening. Each first edge seal structure in the at least one edge seal structure (688, 984, 986) extends vertically from the first substrate 908 to the topmost surface of the first distal interconnect level dielectric material layer 980.

[0086] Reference Figure 2A and Figure 2B, a layer stack including a first interconnect capping dielectric diffusion barrier layer 962, a first pad connection via level dielectric material layer 964, and a first proximal dielectric diffusion barrier layer 972 can be formed. The first interconnect capping dielectric diffusion barrier layer 962 can include a dielectric material that blocks copper diffusion. In one embodiment, the first interconnect capping dielectric diffusion barrier layer 962 can include silicon nitride, silicon carbonitride, silicon oxynitride, or a stack thereof. In one embodiment, the first interconnect capping dielectric diffusion barrier layer 962 can include a dielectric material having a dielectric constant less than 5, such as less than 4, such as silicon carbonitride having a dielectric constant of about 3.8. The thickness of the first interconnect capping dielectric diffusion barrier layer 962 can range from 5 nm to 50 nm, but smaller and larger thicknesses can also be used.

[0087] The first pad connection via level dielectric material layer 964 can include undoped silicate glass, doped silicate glass, or organosilicate glass, and / or consist essentially of the foregoing. The thickness of the first pad connection via level dielectric material layer 964 can range from 100 nm to 3,000 nm, but smaller and larger thicknesses can also be used. The first pad connection via level dielectric material layer 964 can have a planar top surface.

[0088] The first proximal dielectric diffusion barrier layer 972 can include a dielectric material (e.g., a moisture barrier layer) that blocks moisture diffusion. The first proximal dielectric diffusion barrier layer 972 includes a dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of the dielectric material. In one embodiment, the first proximal dielectric diffusion barrier layer 972 can include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9. The thickness of the first proximal dielectric diffusion barrier layer 972 can range from 5 nm to 100 nm, but smaller and larger thicknesses can also be used.

[0089] A photoresist layer (not shown) can be applied over the first proximal dielectric diffusion barrier layer 972 and can be lithographically patterned to form discrete openings in the area overlying the topmost metal interconnect structure of the first metal interconnect structure 980. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the first proximal dielectric diffusion barrier layer 972, the first pad connection via level dielectric material layer 964, and the first interconnect capping dielectric diffusion barrier layer 962. A first pad connection via cavity 967 is formed through the first proximal dielectric diffusion barrier layer 972. The top surface of the topmost metal interconnect structure 980 can be physically exposed at the bottom of each first pad connection via cavity 967.

[0090] In one embodiment, the first pad connection via cavities 967 can be arranged as a cluster of first pad connection via cavities 967, asFigure 2B As shown. Each cluster of the first pad connection via cavities 967 may be located within the area of a corresponding bonding pad among the bonding pads to be subsequently formed. For example, each bonding pad may have a rectangular shape or a rounded rectangular shape with sides parallel to the first horizontal direction hd1 and the second horizontal direction hd2. The dimension of each bonding pad along the first horizontal direction hd1 and the dimension of each bonding pad along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers. In this case, each cluster of the first pad connection via cavities 967 may be arranged in a rectangular array. Although the drawings show each cluster of the first pad connection via cavities 967 as a 4×4 rectangular array, each cluster of the first pad connection via cavities 967 may be formed as an M×N rectangular array, where M and N are independent integers. Alternatively, a single first pad connection via cavity 967 may be formed for each area of the bonding pads to be subsequently formed.

[0091] Each first pad connection via cavity 967 is formed within the area of a corresponding topmost metal interconnect structure in the topmost metal interconnect structure 980. Clusters of the first pad connection via cavities 967 may be formed along each edge seal structure (688, 984, 986). Clusters of the first pad connection via cavities 967 and the gap regions may alternate along the perimeter of the first semiconductor die 900 over the entire area of each edge seal structure (688, 984, 986). In the presence of multiple nested edge seal structures (688, 984, 986), multiple lateral alternating sequences of clusters of the first pad connection via cavities 967 and the gap regions are provided along the perimeter of the first semiconductor die 900.

[0092] Reference Figure 3A and Figure 3B , an optional pad connection via level metal barrier layer and a pad connection via level metal fill material may be sequentially deposited in the first pad connection via cavities 967. The pad connection via level metal barrier layer comprises a conductive metal barrier material such as TiN, TaN, and / or WN. The conductive metal barrier material may block moisture and copper diffusion. The thickness of the pad connection via level metal barrier layer may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses may also be used. The pad connection via level metal fill material may include any suitable metal or metal alloy such as tungsten.

[0093] Excess portions of the via-level metal fill material and via-level metal barrier layer of the pad connections overlying a horizontal plane covering the top surface of the first proximal dielectric diffusion barrier layer 972 can be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the via-level metal fill material and via-level metal barrier layer filling the first pad connection via cavity 967 constitute the first pad connection via structure 968. Each first pad connection via structure 968 can include an optional via-level metal barrier liner 968A and a via-level metal fill material portion 968B. The via-level metal barrier liner 968A is a patterned remaining portion of the via-level metal barrier layer, and the via-level metal fill material portion 968B is a patterned remaining plug portion (e.g., tungsten plug) of the via-level metal fill material. Alternatively, the via-level metal barrier liner 968A can be omitted. The top surface of the first pad connection via structure 968 can be in the same horizontal plane as the top surface of the first proximal dielectric diffusion barrier layer 972.

[0094] Reference Figure 4A and Figure 4B , a first pad-level dielectric material layer 974 can be formed over the first proximal dielectric diffusion barrier layer 972. The first pad-level dielectric material layer 974 can include undoped silicate glass, doped silicate glass, or organosilicate glass, and / or can consist essentially of the foregoing. The thickness of the first pad-level dielectric material layer 974 can be in the range of 300 nm to 3,000 nm, although smaller and larger thicknesses can also be used. The first pad-level dielectric material layer 974 can have a planar top surface.

[0095] A photoresist layer (not shown) can be applied over the first pad-level dielectric material layer 974 and can be lithographically patterned to form discrete openings in each area of a cluster of the first pad connection via structures 968. In other words, each discrete opening in the photoresist layer overlies a corresponding cluster in the first pad connection via structure 968. Each discrete opening in the photoresist layer has the shape of a bonding pad to be formed subsequently. For example, each discrete opening in the photoresist layer can have a rectangular shape or a rounded rectangular shape having sides parallel to a first horizontal direction hd1 and a second horizontal direction hd2. The dimension of each opening along the first horizontal direction hd1 and the dimension of each opening along the second horizontal direction hd2 are in the range of 2 microns to 60 microns.

[0096] An etch process, such as an anisotropic etch process, can be performed to transfer the pattern of the openings in the photoresist layer through the first pad-level dielectric material layer 974. The first pad cavity 979 is formed through the first pad-level dielectric material layer 974. The top surface of the array of the first pad connection via structures 968 can be physically exposed at the bottom of each first pad cavity 979. Alternatively, the top surface of a single pad connection via structure 968 can be physically exposed at the bottom of each first pad cavity 979. Each first pad cavity 979 can have a horizontal cross-sectional shape that is rectangular or rounded rectangular, such that the dimension of each first pad cavity 979 along the first horizontal direction hd1 is in the range of 2 microns to 60 microns, and the dimension of each first pad cavity 979 along the second horizontal direction hd2 is in the range of 2 microns to 60 microns. In one embodiment, each first pad cavity 979 can have a horizontal cross-sectional shape that is square or rounded square, such that the dimension of each first pad cavity 979 along the first horizontal direction hd1 and the dimension of each first pad cavity 979 along the second horizontal direction hd2 are the same. In this case, the dimension of each first pad cavity 979 along the first horizontal direction hd1 and along the second horizontal direction hd2 can be in the range of 2 microns to 60 microns, such as 4 microns to 30 microns. The sidewalls of the first pad cavity 979 can be vertical, or can have a taper angle greater than 0 degrees and less than 30 degrees with respect to the vertical direction (such as a taper angle in the range of 3 degrees to 10 degrees).

[0097] Reference Figure 5 , a first distal dielectric diffusion barrier layer 976 can be deposited in the first pad cavity 979 and over the first pad-level dielectric material layer 974. The first distal dielectric diffusion barrier layer 976 is deposited on the top surface of the first pad connection via structures 968. The first distal dielectric diffusion barrier layer 976 includes a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of the diffusion barrier dielectric material. In one embodiment, the first distal dielectric diffusion barrier layer 976 includes a moisture-proof dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The thickness of the first distal dielectric diffusion barrier layer 976 can be in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses can also be used.

[0098] Reference Figure 6, a photoresist layer 977 may be applied over the first distal dielectric diffusion barrier layer 976 and may be lithographically patterned to form discrete openings therethrough. Each region of the discrete openings in the photoresist layer 977 may be located inside the bottom perimeter of the corresponding first pad cavity 979, i.e., inside the closed bottom edges of a set of sidewalls of the corresponding first pad cavity 979 that adjoin the top surface of the first proximal dielectric diffusion barrier layer 972. In other words, the openings through the photoresist layer 977 may be formed by lithographically patterning the photoresist layer 977 within the area of the bottom surface of the first pad cavity 979.

[0099] The unmasked portion of the first distal dielectric diffusion barrier layer 976 may be anisotropically etched by performing an anisotropic etching process using the patterned photoresist layer 977 as an etch mask. Openings are formed through the first distal dielectric diffusion barrier layer 976 at the bottom portion of the first pad cavity 979. The remaining portion of the patterned first distal dielectric diffusion barrier layer 976 includes first dielectric diffusion barrier portions 976P that laterally surround the corresponding first pad cavities in the first pad cavity 979. The top surface of the first pad connection via structure 968 is physically exposed below the first pad cavity 979.

[0100] Each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portions 976P of the first distal dielectric diffusion barrier layer 976 that laterally surrounds the corresponding first pad cavity in the first pad cavity 979 contacts the top surface of the first proximal dielectric diffusion barrier layer 972. Specifically, each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portions 976P includes a sidewall segment that contacts the first pad level dielectric material layer 974 and extends vertically from the bottom surface and the top surface of the first pad level dielectric material layer 974. In one embodiment, the perimeter of each opening through the first distal dielectric diffusion barrier layer 976 may be laterally offset inwardly from the bottom perimeter of the corresponding opening through the first pad level dielectric material layer 974. In this case, each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portions 976P includes a horizontal segment that has a bottom surface that contacts the bottom surface of the first proximal dielectric diffusion barrier layer 972. The bottom surface may include an outer perimeter that adjoins the bottom edge of the sidewall segment of the corresponding first dielectric diffusion barrier portion 976P and an inner perimeter that is laterally offset inwardly by an offset distance osd that is greater than the thickness of the sidewall segment of the first dielectric diffusion barrier portion 976P.

[0101] Reference Figure 7 , the patterned photoresist layer 977 may be removed, for example, by ashing. Reference Figure 8A and Figure 8B, the first bonding pad liner layer and the first metal pad fill material may be sequentially deposited in the first pad cavity 979. The first bonding pad liner layer comprises a metal nitride material such as TiN, TaN, and / or WN. The conductive metal barrier material may block copper diffusion. The first bonding pad liner layer is formed on the top surface of the first pad connection via structure 968 and on the portion of the top surface of the proximal dielectric diffusion barrier layer 972 within the opening through the first distal dielectric diffusion barrier layer 976 (i.e., within the first pad cavity 979). The thickness of the first bonding pad liner layer may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses may also be used. The first metal pad fill material may comprise copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the first pad cavity 979.

[0102] The excess portions of the first metal pad fill material and the first bonding pad liner layer covering the horizontal plane including the top surface of the first distal dielectric diffusion barrier layer 976 may be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the first metal pad fill material and the first bonding pad liner layer filling the first pad cavity 979 constitute the first bonding pad 988. Each first bonding pad 988 may include a first bonding pad liner 988A and a first metal pad fill material portion 988B. The first bonding pad liner 988A is the patterned remaining portion of the first bonding pad liner layer, and the first metal pad fill material portion 988B is the patterned remaining portion of the first metal pad fill material. The top surface of the first bonding pad 988 may be in the same horizontal plane as the top surface of the first distal dielectric diffusion barrier layer 976.

[0103] Generally speaking, the first bonding pad 988 is formed directly on the top surface of the first pad connection via structure 966 in the remaining volume of the first pad cavity 979 after patterning the first distal dielectric diffusion barrier layer 976. Each first bonding pad in the first bonding pad 988 includes a first bonding pad liner 988A and a first metal pad fill material portion 988B (e.g., a copper portion) and / or consists of the above items, the first bonding pad liner comprising a metal nitride material, and the first metal pad fill material portion being embedded in the bonding pad liner 988A.

[0104] In one embodiment, the first dielectric diffusion barrier portions 976P are interconnected through the first horizontally extending diffusion barrier portions covering the first pad level dielectric material layer 974. The top surface of the first bonding pad 988 may be located in the horizontal plane including the top surface of the first horizontally extending diffusion barrier portion of the first distal dielectric diffusion barrier layer 976.

[0105] In one embodiment, each first bonding pad 988 may physically and electrically contact a corresponding subgroup of the underlying first pad connection via structures 968, which may be a corresponding plurality of first pad connection via structures 968. Each first bonding pad in the first bonding pads 988 may directly contact a portion of the top surface of the first proximal dielectric diffusion barrier layer 972 that is located between the corresponding plurality of first pad connection via structures 968. Generally speaking, the first pad level dielectric material layer 974 includes first pad cavities filled with a corresponding combination of the first bonding pads 988 and corresponding first dielectric diffusion barrier portions 976P.

[0106] A first subgroup of the first bonding pads 988 may be located within a region surrounded by at least one edge seal structure (688, 984, 986) and may be electrically connected to corresponding nodes of the first semiconductor device 920. A second subgroup of the first bonding pads 988 may be located on a corresponding one of the at least one edge seal structure (688, 984, 986) and may be electrically connected to the corresponding edge seal structure.

[0107] Reference Figure 9 , shows a region of a second semiconductor die 700 in a first configuration. The second semiconductor die 700 includes a second substrate 708, a second semiconductor device 720 overlying the second substrate 708, a second interconnect level dielectric material layer 760 overlying the second semiconductor device 720, and second metal interconnect structures 780 embedded in the second interconnect level dielectric material layer 760. In one embodiment, the second semiconductor device 720 may include at least one complementary metal oxide semiconductor (CMOS) circuit that includes field effect transistors. In one embodiment, the second substrate 708 may be a second semiconductor substrate, such as a commercially available silicon substrate having a thickness in the range of 500 microns to 1 mm.

[0108] Generally speaking, the second semiconductor device may include any semiconductor device that can operate in conjunction with the first semiconductor device in the first semiconductor die 900 to provide enhanced functionality. In one embodiment, the first semiconductor die 900 includes a memory die, and the second semiconductor die 700 includes a logic die that includes support circuits (i.e., peripheral circuits) for operating memory devices (such as a three-dimensional memory element array) within the memory die. In one embodiment, the first semiconductor die 900 may include a three-dimensional memory device that includes a three-dimensional memory element array, word lines (which may include a subgroup of the conductive layer 46), and bit lines 982, and the second semiconductor device 720 of the second semiconductor die 700 may include peripheral circuits for operating the three-dimensional memory element array. The peripheral circuits may include: one or more word line driver circuits that drive the word lines of the three-dimensional memory element array of the first semiconductor die 900; one or more bit line driver circuits that drive the bit lines 982 of the first semiconductor die 900; one or more word line decoder circuits that decode the addresses of the word lines; one or more bit line decoder circuits that decode the addresses of the bit lines 982; one or more sense amplifier circuits that sense the state of the memory elements within the memory opening fill structure 58 of the first semiconductor die 900; a source power circuit that supplies power to the horizontal semiconductor channel layer 10 in the first semiconductor die 900; data buffers and / or latches; and / or any other semiconductor circuits that may be used to operate the three-dimensional memory device of the first semiconductor die 900.

[0109] The second interconnect level dielectric material layer 760 may comprise a dielectric material such as undoped silicate glass (e.g., silicon oxide), doped silicate glass, organosilicate glass, silicon nitride, dielectric metal oxide, or a combination thereof. In an illustrative example, the second metal interconnect structure 780 may include a first logic side metal level D1 and a second logic side metal level D2, the first logic side metal level including logic side first level metal lines, and the second logic side metal level including logic side second level metal lines.

[0110] The second interconnect level dielectric material layer 760 may include one or more dielectric diffusion barrier layers (not explicitly shown). In such a case, each dielectric diffusion barrier layer embedded in the second interconnect level dielectric material layer 760 may comprise silicon carbonitride (SiCN), silicon nitride (Si3N4), silicon oxynitride, or any other dielectric material effective to block the diffusion of copper. In one embodiment, each dielectric diffusion barrier layer embedded in the second interconnect level dielectric material layer 760 may include a dielectric material having a dielectric constant less than 5, such as less than 4, (such as SiCN having a dielectric constant of about 3.8) to reduce the RC delay of the first metal interconnect structure 980. Each dielectric diffusion barrier layer may have a thickness in the range of 10 nm to 300 nm. At least one edge seal structure (not shown) may be formed around the perimeter of the second semiconductor die 700 through the second interconnect level dielectric material layer 760 in the same manner as the first semiconductor die 900. Each edge seal structure in the at least one edge seal structure in the second semiconductor die 700 may include a metal wall structure and optionally at least one via level loop structure and / or at least one wire level loop structure. Each edge seal structure in the second semiconductor die 700 includes a set of continuous conductive material portions that laterally surround the second semiconductor device 720 without any openings therethrough. Each edge seal structure in the at least one edge seal structure in the second semiconductor die 700 extends vertically from the second substrate 708 to the top surface of the second interconnect level dielectric material layer 780.

[0111] A layer stack including a second interconnect capping dielectric diffusion barrier layer 762, a second pad connection via level dielectric material layer 764, and a second proximal dielectric diffusion barrier layer 772 may be formed over the second interconnect level dielectric material layer 780. The second interconnect capping dielectric diffusion barrier layer 762 may comprise a dielectric material that blocks the diffusion of copper. In one embodiment, the second interconnect capping dielectric diffusion barrier layer 762 may comprise silicon nitride, silicon carbonitride, silicon oxynitride, or a stack thereof. In one embodiment, the second interconnect capping dielectric diffusion barrier layer 762 may include a dielectric material having a dielectric constant less than 5, such as less than 4, such as silicon carbonitride having a dielectric constant of about 3.8. The thickness of the second interconnect capping dielectric diffusion barrier layer 762 may be in the range of 5 nm to 50 nm, although smaller and larger thicknesses may also be used.

[0112] The second pad connection via level dielectric material layer 764 may include undoped silicate glass, doped silicate glass, or organic silicate glass, and / or consist essentially of the foregoing. The thickness of the second pad connection via level dielectric material layer 764 may be in the range of 100 nm to 3,000 nm, although smaller and larger thicknesses may also be used. The second pad connection via level dielectric material layer 764 may have a planar top surface.

[0113] The second proximal dielectric diffusion barrier layer 772 may include a dielectric material that blocks the diffusion of moisture. The second proximal dielectric diffusion barrier layer 772 comprises a dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of such dielectric material. In one embodiment, the second proximal dielectric diffusion barrier layer 772 may include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9. The thickness of the second proximal dielectric diffusion barrier layer 772 may be in the range of 5 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0114] A photoresist layer (not shown) may be applied over the second proximal dielectric diffusion barrier layer 772 and may be lithographically patterned to form discrete openings in the area overlying the topmost metal interconnect structure of the second metal interconnect structure 780. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the second proximal dielectric diffusion barrier layer 772, the second pad connection via level dielectric material layer 764, and the second interconnect capping dielectric diffusion barrier layer 762. The second pad connection via cavity is formed through the second proximal dielectric diffusion barrier layer 772. The top surface of the topmost metal interconnect structure 780 may be physically exposed at the bottom of each second pad connection via cavity.

[0115] In one embodiment, the second pad connection via cavities may be arranged as clusters of second pad connection via cavities. Each cluster of second pad connection via cavities may be located within the area of a corresponding bonding pad that will be formed subsequently. For example, each bonding pad may have a rectangular shape with orthogonal sides or a rounded rectangular shape. The dimension of each bonding pad in the direction along the sides of the rectangular or rounded rectangular shape may be in the range of 2 micrometers to 60 micrometers. In such a case, each cluster of second pad connection via cavities may be arranged as a rectangular array. Each cluster of second pad connection via cavities may be formed as an M'×N' rectangular array, where M' and N' are independent integers. Alternatively, a single second pad connection via cavity may be formed for each area of the bonding pads that will be formed subsequently.

[0116] Each second pad connection via cavity is formed within the area of a corresponding topmost metal interconnect structure in the topmost metal interconnect structure 780. Clusters of second pad connection via cavities may be formed along each edge seal structure. Clusters of second pad connection via cavities and gap regions may alternate along the perimeter of the second semiconductor die 700 over the entire area of each edge seal structure. In the case where there are multiple nested edge seal structures, multiple lateral alternating sequences of clusters of second pad connection via cavities and gap regions are provided along the perimeter of the second semiconductor die 700.

[0117] Optional pad connection via-level metal barrier layers and pad connection via-level metal fill materials may be sequentially deposited in the second pad connection via cavity. The pad connection via-level metal barrier layer comprises a conductive metal barrier material such as TiN, TaN, and / or WN. The conductive metal barrier material may block copper diffusion. The thickness of the pad connection via-level metal barrier layer may range from 4 nm to 80 nm, such as 8 nm to 40 nm, although smaller and larger thicknesses may also be used. The pad connection via-level metal fill material may include any suitable metal or metal alloy such as tungsten.

[0118] Excess portions of the pad connection via-level metal fill material and the pad connection via-level metal barrier layer overlying a horizontal plane including the top surface of the second proximal dielectric diffusion barrier layer 772 may be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the pad connection via-level metal fill material and the pad connection via-level metal barrier layer filling the second pad connection via cavity constitute the second pad connection via structure 768. Each second pad connection via structure 768 may include an optional pad connection via-level metal barrier liner 768A and a pad connection via-level metal fill material portion 768B. The pad connection via-level metal barrier liner 768A is a patterned remaining portion of the pad connection via-level metal barrier layer, and the pad connection via-level metal fill material portion 768B is a patterned remaining plug portion (e.g., tungsten plug) of the pad connection via-level metal fill material. Alternatively, the pad connection via-level metal barrier liner 768A may be omitted. The top surface of the second pad connection via structure 768 may be in the same horizontal plane as the top surface of the second proximal dielectric diffusion barrier layer 772.

[0119] Reference Figure 10 , a second pad-level dielectric material layer 774 may be formed over the second proximal dielectric diffusion barrier layer 772. The second pad-level dielectric material layer 774 may include undoped silicate glass, doped silicate glass, or organosilicate glass, and / or consist essentially of the foregoing. The thickness of the second pad-level dielectric material layer 774 may range from 300 nm to 3,000 nm, although smaller and larger thicknesses may also be used. The second pad-level dielectric material layer 774 may have a planar top surface.

[0120] A photoresist layer (not shown) may be applied over the second pad level dielectric material layer 774 and may be lithographically patterned to form discrete openings in each area of the clusters of the second pad connection via structures 768. In other words, each discrete opening in the photoresist layer overlies a corresponding cluster in the second pad connection via structures 768. Each discrete opening in the photoresist layer has the shape of a bonding pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape having sides parallel to the second horizontal direction hd1 and the second horizontal direction hd2. The dimension of each opening along the second horizontal direction hd1 and the dimension of each opening along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers.

[0121] An etching process such as an anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the second pad level dielectric material layer 774. Second pad cavities 779 are formed through the second pad level dielectric material layer 774. The top surfaces of the arrays of the second pad connection via structures 768 may be physically exposed at the bottoms of each of the second pad cavities 779. Alternatively, the top surface of a single pad connection via structure 768 may be physically exposed at the bottom of each of the second pad cavities 779. Each pad cavity 779 may have a rectangular or rounded rectangular horizontal cross-sectional shape such that the dimension of each pad cavity 779 in the horizontal direction along the sides of the rectangle or rounded rectangle is in the range of 2 micrometers to 60 micrometers. In one embodiment, each pad cavity 779 may have a square or rounded square horizontal cross-sectional shape.

[0122] Reference Figure 11 , a second distal dielectric diffusion barrier layer 776 may be deposited in the second pad cavities 779 and over the second pad level dielectric material layer 774. The second distal dielectric diffusion barrier layer 776 is deposited on the top surfaces of the second pad connection via structures 768. The second distal dielectric diffusion barrier layer 776 includes a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of the diffusion barrier dielectric material. In one embodiment, the second distal dielectric diffusion barrier layer 776 includes a moisture-proof dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The thickness of the second distal dielectric diffusion barrier layer 776 may be in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses may also be used.

[0123] Reference Figure 12, a photoresist layer 777 may be applied over the second distal dielectric diffusion barrier layer 776 and may be lithographically patterned to form discrete openings therethrough. Each region of the discrete openings in the photoresist layer 777 may be located inside the bottom perimeter of the corresponding second pad cavity 779, i.e., inside the closed bottom edges of a set of sidewalls of the corresponding second pad cavity 779 that adjoin the top surface of the second proximal dielectric diffusion barrier layer 772. In other words, the openings through the photoresist layer 777 may be formed within the region of the bottom surface of the second pad cavity 779 by lithographically patterning the photoresist layer 777.

[0124] The unmasked portion of the second distal dielectric diffusion barrier layer 776 may be anisotropically etched by performing an anisotropic etching process using the patterned photoresist layer 777 as an etch mask. Openings are formed through the second distal dielectric diffusion barrier layer 776 at the bottom portion of the second pad cavity 779. The remaining portion of the patterned second distal dielectric diffusion barrier layer 776 includes second dielectric diffusion barrier portions 776P that laterally surround the corresponding second pad cavities in the second pad cavity 779. The top surface of the second pad connection via structure 768 is physically exposed below the second pad cavity 779.

[0125] Each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portions 776P of the second distal dielectric diffusion barrier layer 776 that laterally surrounds the corresponding second pad cavity in the second pad cavity 779 contacts the top surface of the second proximal dielectric diffusion barrier layer 772. Specifically, each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portions 776P includes a sidewall segment that contacts the second pad level dielectric material layer 772 and extends vertically from the bottom surface and the top surface of the second pad level dielectric material layer 774. In one embodiment, the perimeter of each opening through the second distal dielectric diffusion barrier layer 776 may be laterally offset inwardly from the bottom perimeter of the corresponding opening through the second pad level dielectric material layer 774. In such a case, each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portions 776P includes a horizontal segment that has a bottom surface that contacts the second proximal dielectric diffusion barrier layer 772. The bottom surface may include an outer perimeter that adjoins the bottom edge of the sidewall segment of the corresponding second dielectric diffusion barrier portion 776P and an inner perimeter that is laterally offset inwardly by an offset distance osd that is greater than the thickness of the sidewall segment of the second dielectric diffusion barrier portion 776P.

[0126] Reference Figure 13 , the patterned photoresist layer 777 may be removed, for example, by ashing.

[0127] Reference Figure 14, the second bonding pad liner layer and the second metal pad filling material may be sequentially deposited in the second pad cavity 779. The second bonding pad liner layer includes a metal nitride material such as TiN, TaN, and / or WN. The conductive metal barrier material may block copper diffusion. The second bonding pad liner layer is formed on the top surface of the second pad connection via structure 768 and on the part of the top surface of the proximal dielectric diffusion barrier layer 772 within the opening through the second distal dielectric diffusion barrier layer 776 (i.e., within the second pad cavity 779). The thickness of the second bonding pad liner layer may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses may also be used. The second metal pad filling material may include copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the second pad cavity 779.

[0128] The excess portions of the second metal pad filling material and the second bonding pad liner layer covering the horizontal plane including the top surface of the second distal dielectric diffusion barrier layer 776 may be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the second metal pad filling material and the second bonding pad liner layer filling the second pad cavity 779 constitute the second bonding pad 788. Each second bonding pad 788 may include a second bonding pad liner 788A and a second metal pad filling material portion 788B. The second bonding pad liner 788A is the patterned remaining portion of the second bonding pad liner layer, and the second metal pad filling material portion 788B is the patterned remaining portion of the second metal pad filling material. The top surface of the second bonding pad 788 may be in the same horizontal plane as the top surface of the second pad level dielectric material layer 774.

[0129] Generally, the second bonding pad 788 is formed directly on the top surface of the second pad connection via structure 766 in the remaining volume of the second pad cavity 779 after patterning the second distal dielectric diffusion barrier layer 776. Each second bonding pad in the second bonding pad 788 includes and / or consists of a second bonding pad liner 788A and a second metal pad filling material portion 788B, the second bonding pad liner contains a metal nitride material, and the second metal pad filling material portion is embedded in the second bonding pad liner 788A.

[0130] In one embodiment, the second dielectric diffusion barrier portion 776P interconnects through the second horizontally extending diffusion barrier portions covering the second pad level dielectric material layer 774. The top surface of the second bonding pad 788 may be located in the horizontal plane including the top surface of the second horizontally extending diffusion barrier portion of the second distal dielectric diffusion barrier layer 776.

[0131] In one embodiment, each second bonding pad 788 may physically and electrically contact a corresponding subgroup of the underlying second pad connection via structures 768, which may be a corresponding plurality of second pad connection via structures 768. Each second bonding pad in the second bonding pads 788 may directly contact a portion of the top surface of the second proximal dielectric diffusion barrier layer 772 that is located between the corresponding plurality of second pad connection via structures 768. Generally speaking, the second pad level dielectric material layer 774 includes second pad cavities filled with a corresponding combination of the second bonding pads 788 and corresponding second dielectric diffusion barrier portions 776P.

[0132] A first subgroup of the second bonding pads 788 may be located within a region surrounded by at least one edge seal structure in the second semiconductor die 700 and may be electrically connected to corresponding nodes of the second semiconductor device 720. A second subgroup of the second bonding pads 788 may be located on a corresponding edge seal structure of the at least one edge seal structure and may be electrically connected to the corresponding edge seal structure. The pattern of the second bonding pads 788 may be arranged as a mirror image pattern of the pattern of the first bonding pads 988.

[0133] Reference Figure 15 , the second semiconductor die 700 and the first semiconductor die 700 may be aligned such that each second bonding pad 788 faces a corresponding first bonding pad among the first bonding pads 988. Each pair of facing first bonding pads 988 and second bonding pads 788 may be aligned to maximize the area overlap between the first bonding pad 988 and the second bonding pad 788. If the first bonding pad 988 and the second bonding pad 788 have different areas, each overlap area between a pair of facing first bonding pads 988 and second bonding pads 788 may be the same as the area of the smaller bonding pad between the pair of facing first bonding pads 988 and second bonding pads 788. If the first bonding pad 988 and the second bonding pad 788 have the same area, the overlap area between a pair of facing first bonding pads 988 and second bonding pads 788 may be in the range of 90% to 100% of the area of the first bonding pad 988 (which is the same as the area of the second bonding pad 788), such as 95% to 100%.

[0134] The first semiconductor die 900 and the second semiconductor die 700 can be in contact with each other such that each first bonding pad 988 contacts a corresponding second bonding pad among the second bonding pads 788, with a corresponding area overlap therebetween. The assembly of the first semiconductor die 900 and the second semiconductor die 700 is annealed at a high temperature in the range of 250 degrees Celsius to 400 degrees Celsius to cause copper diffusion at each interface between the corresponding first bonding pads 988 and the corresponding second bonding pads 788 that are paired and facing each other. The duration of the annealing process at high temperature can be in the range of 5 minutes to 2 hours, but shorter or longer annealing durations can also be used. Each pair of facing first bonding pads 988 and second bonding pads 788 are bonded to each other during the annealing process at high temperature. A first exemplary bonding structure including the first semiconductor die 900 and the second semiconductor die 700 can be formed.

[0135] A layer stack including a horizontal extension portion of the first distal dielectric diffusion barrier layer 976 and a horizontal extension portion of the second distal dielectric diffusion barrier layer 776 can be located between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774. The vertical separation distance between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774 can be the sum of the thickness of the first distal dielectric diffusion barrier layer 976 and the thickness of the second distal dielectric diffusion barrier layer 776.

[0136] Reference Figure 16 , the first substrate 908 can be thinned from the back side by grinding, polishing, anisotropic etching, or isotropic etching. The thinning process can continue until the horizontal portion of the through-substrate liner 386 is removed and the horizontal surface of the through-substrate via structure 388 is physically exposed. Generally speaking, by thinning the back side of the first substrate 908, which can be the substrate of the memory die, the end surface of the through-substrate via structure 388 can be physically exposed. The thickness of the first substrate 908 after thinning can be in the range of 1 micron to 30 microns, such as 2 microns to 15 microns, but smaller and larger thicknesses can also be used.

[0137] Reference Figure 17 , a backside insulating layer 930 can be formed on the back side of the first substrate 908. The backside insulating layer 930 contains an insulating material, such as silicon oxide. The thickness of the backside insulating layer 930 can be in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be used. A photoresist layer (not shown) can be applied above the backside insulating layer 930 and can be lithographically patterned to form an opening above the area of the through-substrate via structure 388. An etching process can be performed to form a via cavity through the backside insulating layer 930 under each opening in the photoresist layer. The top surface of the through-substrate via structure 388 can be physically exposed at the bottom of each via cavity through the backside insulating layer 930.

[0138] At least one metal material may be deposited into the openings through the backside insulating layer 930 and deposited above the planar surface of the backside insulating layer 930 to form a metal material layer. The at least one metal material may include copper, aluminum, ruthenium, cobalt, molybdenum, and / or any other metal material that can be deposited by physical vapor deposition, chemical vapor deposition, electroplating, vacuum evaporation, or other deposition methods. For example, a metal nitride liner material (such as TiN, TaN, or WN) may be directly deposited on the physically exposed surface of the through-substrate via structure 388, on the sidewalls of the openings through the backside insulating layer 930, and above the physically exposed planar surface of the backside insulating layer 930. The thickness of the metal nitride liner material may be in the range of 10 nm to 100 nm, although smaller and larger thicknesses may also be used. At least one metal fill material, such as copper or aluminum, may be deposited above the metal nitride liner material. In one embodiment, the at least one metal fill material may include a stack of highly conductive metal layers (such as a copper layer or an aluminum layer) and an under-bump metallurgy (UBM) layer stack for bonding a solder ball thereto. Exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stacks, Al / Ni / Cu stacks, Cu / Ni / Au stacks, Cu / Ni / Pd stacks, Ti / Ni / Au stacks, Ti / Cu / Ni / Au stacks, Ti-W / Cu stacks, Cr / Cu stacks, and Cr / Cu / Ni stacks. The thickness of the metal material layer above the planar horizontal surface of the backside insulating layer 930 may be in the range of 0.5 microns to 10 microns, such as 1 micron to 5 microns, although smaller and larger thicknesses may also be used.

[0139] The at least one metal fill material and the metal material layer may then be patterned to form discrete backside bonding pads 936 that contact a respective one of the through-substrate via structures in the through-substrate via structure 388. The backside bonding pads 936 may be used as external bonding pads that can be used to electrically connect the respective nodes within the first semiconductor die 900 and the second semiconductor die 700 to external nodes, such as bonding pads on a package substrate or C4 bonding pads of another semiconductor die. For example, a solder material portion 938 may be formed on the backside bonding pads 936, and a C4 bonding process or a wire bonding process may be performed to electrically connect the backside bonding pads 936 to external electrically active nodes.

[0140] Generally, the backside bonding pads 936 may be formed on the backside surface of the first semiconductor die 900 (which may be a memory die) that is on the opposite side of the bonding interface between the first semiconductor die 900 and the second semiconductor die 700. The through-substrate via structures 388 may vertically extend through the first semiconductor die 900 and may provide an electrical connection between the backside bonding pads 936 and a subgroup of the bonding pads (988, 788).

[0141] Reference Figure 18 illustrates an alternative embodiment of the first semiconductor die 900 according to the first embodiment of the present disclosure. The alternative embodiment of the first semiconductor die 900 can be obtained from the first semiconductor die 900 of Figure 8A and Figure 8B by removing the horizontally extending portion of the first distal dielectric diffusion barrier layer 976 that overlies the first pad-level dielectric material layer 974. For example, after removing the metallic material above the top surface of the first distal dielectric diffusion barrier layer 976, the horizontally extending portion of the first distal dielectric diffusion barrier layer 976 that overlies the first pad-level dielectric material layer 974 can be removed by an additional polishing step of a chemical mechanical planarization process. In this case, the top surface of the first pad-level dielectric material layer 974 can be physically exposed after the planarization process, and the top surface of the first bonding pad 988 can be formed in the same horizontal plane as the top surface of the first pad-level dielectric material layer 974. After removing the horizontally extending portion of the first distal dielectric diffusion barrier layer 976, the remaining portion of the first distal dielectric diffusion barrier layer 976 includes first dielectric diffusion barrier portions 976'. The first dielectric diffusion barrier portions 976' are not interconnected with each other and are formed as discrete structures that laterally surround the respective first bonding pads 988.

[0142] Reference Figure 19 , the second semiconductor die 700 can be provided in the same manner as described above and can be bonded to the alternative configuration of the first semiconductor die shown in Figure 18 to provide an alternative embodiment of the first bonding assembly. The processing steps of Figure 19 shown can be performed on the structure shown in Figure 16 and Figure 17 . In this case, the horizontally extending portion of the second distal dielectric diffusion barrier layer 776 can be located between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774. The vertical separation distance between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774 can be the same as the thickness of the second distal dielectric diffusion barrier layer 776. The first dielectric diffusion barrier portions 976' are discrete material portions that are laterally spaced apart from each other by the first pad-level dielectric material layer 974. The top surface of the first bonding pad 988 can be located in the horizontal plane including the top surface of the first pad-level dielectric material layer 974.

[0143] In another alternative embodiment of the first semiconductor die 900 according to the first embodiment of the present disclosure, a horizontally extending portion of the second distal dielectric diffusion barrier layer 776 covering the second pad-level dielectric material layer 774 may be removed. In this alternative embodiment, the vertical separation distance between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774 may be the same as the thickness of the first distal dielectric diffusion barrier layer 976 disposed between the first pad-level dielectric material layer 974 and the second pad-level dielectric material layer 774.

[0144] Reference Figures 20A to 20G , a second alternative embodiment of the first exemplary bonding assembly is shown. In this case, the horizontal semiconductor channel layer 10 and the optional dielectric spacer layer 910 may be omitted from the Figure 17 first semiconductor die 900 shown, and a three-dimensional memory element array may be formed directly on the first substrate 908. The first semiconductor die 900 may include a backside metal material plate 906, which may be used as a conduction path for a subgroup of the through-memory-level via structures 488. The backside metal material plate 906 may be embedded in a backside insulating layer 930, which may include a first backside insulator layer 930A, a second backside insulator layer 930B, and a third backside insulator layer 930C. For example, the first backside insulator layer 930A may comprise silicon oxide, the second backside insulator layer 930B may comprise silicon oxide, and the third backside insulator layer 930C may comprise polyimide. The backside metal material plate 906 may be formed between the first backside insulator layer 930A and the second backside insulator layer 930B.

[0145] The dielectric diffusion barrier layer 952 may be embedded within the first distal interconnect-level dielectric material layer 960. In one embodiment, the dielectric diffusion barrier layer 952 may include a copper-barrier dielectric material having a dielectric constant less than 5, such as less than 4, such as carbon silicon nitride having a dielectric constant of about 3.8. Additionally, an additional dielectric diffusion barrier layer 752 may be embedded within the second interconnect-level dielectric material layer 760. In one embodiment, the additional dielectric diffusion barrier layer 752 may include a copper-barrier dielectric material having a dielectric constant less than 5, such as less than 4, such as carbon silicon nitride having a dielectric constant of about 3.8.

[0146] The combination of the first proximal dielectric diffusion barrier layer 972, the first distal dielectric diffusion barrier layer 976, the second proximal dielectric diffusion barrier layer 772, and the second distal dielectric diffusion barrier layer 776 forms a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect level dielectric material layer 960 and the second metal interconnect structure 780 embedded in the second interconnect level dielectric material layer 760 from moisture and / or contaminant diffusion through the first pad level dielectric material layer 974 or the second pad level dielectric material layer 774. Additionally, the combination of the first proximal dielectric diffusion barrier layer 972, the first distal dielectric diffusion barrier layer 976, and the pad connection via level metal barrier liner 968A forms a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect level dielectric material layer 960 from moisture and / or contaminant diffusion through the first pad connection via level dielectric material layer 964. The combination of the second proximal dielectric diffusion barrier layer 772, the second distal dielectric diffusion barrier layer 776, and the pad connection via level metal barrier liner 768A forms a continuous diffusion barrier structure that protects the second metal interconnect structure 780 embedded in the second interconnect level dielectric material layer 760 from moisture and / or contaminant diffusion through the second pad connection via level dielectric material layer 764. Further, if the opposing copper bonding pads of the first semiconductor die and the second semiconductor die are misaligned with each other, at least one of the first distal dielectric diffusion barrier layer 976 and the second distal dielectric diffusion barrier layer 776 blocks the diffusion of copper out of the edges of the misaligned copper bonding pads and into the opposing first pad level dielectric material layer or second pad level dielectric material layer (974, 774). This reduces void formation in the bonding pads and possible delamination of the bonding assembly.

[0147] Reference Figure 21A and Figure 21B , shows an alternative embodiment of the first exemplary bonding assembly. In Figure 21A the embodiment shown, the edge seal structure of the first semiconductor die 900 including the first metal wall structure 688 is electrically grounded to the second substrate 708 of the second semiconductor die 700 through the edge seal structure of the second semiconductor die 700 including the second metal wall structure 388. In Figure 21B the embodiment shown, the edge seal structure of the first semiconductor die 900 including the first metal wall structure 688 and the edge seal structure of the second semiconductor die 700 including the second metal wall structure 388 are electrically grounded to an external electrical ground through a stacked backside metal material plate 906 including a metal plate liner 906A and a metal fill material portion 906B. The backside metal material plate 906 can be formed through an opening in the backside insulating layer 930.

[0148] Reference Figures 1A to 21B And according to various embodiments of the present disclosure, the structure includes a first semiconductor die 900. The first semiconductor die 900 includes: a first semiconductor device 920 located above a first substrate 908; a first interconnect level dielectric material layer (290, 960) embedding a first metal interconnect structure 980 that is electrically connected to the first semiconductor device 920 and covers the first semiconductor device 920 (i.e., the first metal interconnect structure 980 is located on the side of the first substrate 908 opposite to the first semiconductor device 920); a layer stack of a first pad connection via level dielectric material layer 964 and a first proximal dielectric diffusion barrier layer 972 that covers the first interconnect level dielectric material layer (290, 960) and embeds a first pad connection via structure 968; and a first pad level dielectric material layer 974 including a first pad cavity filled with a corresponding combination of a first bonding pad 988 and a corresponding first dielectric diffusion barrier portion (976P or 976'), wherein each first bonding pad in the first bonding pads 988 contacts a corresponding subgroup of the first pad connection via structures 968.

[0149] In one embodiment, each first dielectric diffusion barrier portion (976P or 976') contacts the top surface of the first proximal dielectric diffusion barrier layer 972. In one embodiment, each first dielectric diffusion barrier portion (976P or 976') includes a sidewall segment that contacts the first pad level dielectric material layer 974 and extends from the bottom surface of the first pad level dielectric material layer 974 to the top surface of the first pad level dielectric material layer 974. In one embodiment, each first dielectric diffusion barrier portion (976P or 976') further includes a horizontal segment having a bottom surface that contacts the first proximal dielectric diffusion barrier layer 972, wherein the bottom surface includes an outer perimeter adjacent to the bottom edge of the sidewall segment and an inner perimeter that is laterally offset inward from the outer perimeter by an offset distance osd that is greater than the thickness of the sidewall segment of the first dielectric diffusion barrier portion (976P or 976').

[0150] In one embodiment, the corresponding subgroup of the first pad connection via structures 968 includes a plurality of first pad connection via structures 968; and each first bonding pad in the first bonding pads 988 directly contacts a portion of the top surface of the first proximal dielectric diffusion barrier layer 972 that is located between the plurality of first pad connection via structures 968. In one embodiment, the top surface of the first pad connection via structure 968 is in the same horizontal plane as the top surface of the first proximal dielectric diffusion barrier layer 972.

[0151] In one embodiment, each first bonding pad in the first bonding pads 988 includes: a first bonding pad liner 988A that includes a metal nitride material; and copper that includes a first metal pad fill material portion 988B embedded in the bonding pad liner 988A. In one embodiment, the first dielectric diffusion barrier portions 976P are interconnected to each other through a first horizontally extending diffusion barrier portion (i.e., a horizontally extending portion of the first distal dielectric diffusion barrier layer 976) covering the first pad-level dielectric material layer 974; and the top surface of the first bonding pads 988 lies in a horizontal plane that includes the top surface of the first horizontally extending diffusion barrier portion. In another embodiment, the first dielectric diffusion barrier portions 976' are discrete material portions that are laterally spaced apart from each other by the first pad-level dielectric material layer 974; and the top surface of the first bonding pads 988 lies in a horizontal plane that includes the top surface of the first pad-level dielectric material layer 974.

[0152] In one embodiment, the first dielectric diffusion barrier portion (976P or 976') includes a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and the first proximal dielectric diffusion barrier layer 972 includes a dielectric material selected from silicon nitride, silicon oxynitride, or silicon carbonitride.

[0153] In one embodiment, the structure includes a second semiconductor die 700 that includes: a second semiconductor device 720 located above a second substrate 708; a second interconnect-level dielectric material layer 760 that embeds a second metal interconnect structure 780 that is electrically connected to the second semiconductor device 720 and covers the second semiconductor device 720; and second bonding pads 788 that are electrically connected to the second metal interconnect structure 780 and bonded to corresponding ones of the first bonding pads 988. In one embodiment, each second bonding pad in the second bonding pads 788 contacts a corresponding second dielectric diffusion barrier portion 776P and is laterally surrounded thereby; and the second bonding pads 788 and the second dielectric diffusion barrier portions 776P are embedded in a second pad-level dielectric material layer 774. In one embodiment, the second semiconductor die 700 includes a layer stack of a second pad connection via-level dielectric material layer 764 and a second proximal dielectric diffusion barrier layer 772 that is located between the second interconnect-level dielectric material layer 760 and the second pad-level dielectric material layer 774 and embeds a second pad connection via structure 768, wherein each second bonding pad in the second bonding pads 788 contacts a corresponding subgroup of the second pad connection via structure 768.

[0154] In one embodiment, the first semiconductor die 900 includes: an additional planar diffusion barrier layer 962 (such as a first interconnect capping dielectric diffusion barrier layer 962), which is located between the first interconnect level dielectric material layer (290, 960) and the first pad connection via level dielectric material layer 964; and at least one edge sealing structure (688, 984, 986), which includes a corresponding subset of the first metal interconnect structure 980, and the at least one edge sealing structure provides a corresponding continuous barrier layer that laterally surrounds the first semiconductor device 920 without any lateral openings and extends vertically from the first substrate 908 to the additional planar diffusion barrier layer.

[0155] In the first exemplary bonding structure according to the first embodiment of the present disclosure, the bonding pad can be formed by a single damascene process. Figures 22 to 38 In the second exemplary bonding structure of the second embodiment of the present disclosure, the bonding pad may be formed by a dual damascene process. Figure 22 , showing a region of a second configuration of the first semiconductor die 900. The first semiconductor die 900 may be formed by sequentially depositing a layer stack including a first proximal dielectric diffusion barrier layer 972 and a first pad and via level dielectric material layer 954 over the first distal interconnect level dielectric material layer 960. Figures 1A to 1E The illustrated first configuration of the first semiconductor die 900 leads to a second configuration of the first semiconductor die 900 .

[0156] The first proximal dielectric diffusion barrier 972 contacts the top surface of the subset of the first metal interconnect structure 980 and the topmost surface of the first interconnect level dielectric material layer 960. The first proximal dielectric diffusion barrier 972 may include a dielectric material that blocks moisture diffusion. The first proximal dielectric diffusion barrier 972 contains a dielectric material such as silicon nitride, silicon oxynitride, and / or silicon carbon nitride, and / or is substantially composed of the dielectric material. In one embodiment, the first proximal dielectric diffusion barrier 972 may include silicon nitride, silicon oxynitride, or a stack thereof. In one embodiment, the first proximal dielectric diffusion barrier 972 may include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon nitride oxide having a dielectric constant in the range of 5 to 7.9. The thickness of the first proximal dielectric diffusion barrier 972 may be in the range of 5 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0157] A first pad and via-level dielectric material layer 954 may be formed over the first proximal dielectric diffusion barrier layer 972. The first pad and via-level dielectric material layer 954 may include undoped silicate glass, doped silicate glass, or organosilicate glass, and / or may consist essentially of the foregoing. The thickness of the first pad and via-level dielectric material layer 954 may be in the range of 600 nm to 6,000 nm, although smaller and larger thicknesses may also be used. The first pad and via-level dielectric material layer 954 may have a planar top surface.

[0158] A photoresist layer (not shown) may be applied over the first pad and via-level dielectric material layer 954 and may be lithographically patterned to form discrete openings in an area overlying a first metal interconnect structure 980 embedded within the topmost layer of the first distal interconnect-level dielectric material layer 960. Each discrete opening in the photoresist layer has the shape of a bonding pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape. The dimension of each opening in a direction along the sides of the opening in the photoresist layer may be in the range of 2 micrometers to 60 micrometers.

[0159] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through an upper portion of the first pad and via-level dielectric material layer 954. A first pad cavity 979 is formed partially through the first pad and via-level dielectric material layer 954. The depth of the first pad cavity 979 may be in the range of 20% to 80% of the thickness of the first pad and via-level dielectric material layer 954, such as 40% to 60%. Each first pad cavity 979 may have a rectangular or rounded rectangular horizontal cross-sectional shape such that the lateral dimension of each first pad cavity 979 in a direction along each side of the rectangular or rounded rectangular shape is in the range of 2 micrometers to 60 micrometers. In one embodiment, each first pad cavity 979 may have a square or rounded square horizontal cross-sectional shape. The sidewalls of the first pad cavity 979 may be vertical or may have a taper angle greater than 0 degrees and less than 30 degrees relative to the vertical direction (such as a taper angle in the range of 3 degrees to 10 degrees).

[0160] Reference Figure 23A and Figure 23B, another photoresist layer (not shown) may be applied over the first pad and the via-level dielectric material layer 954 and may be lithographically patterned to form discrete openings within the regions of the first pad cavities 979. Specifically, at least one opening in the photoresist layer may be formed within each region of the first pad cavities 979. In one embodiment, a cluster of openings (such as an array of openings) in the photoresist layer may be formed within each pad cavity region. In another embodiment, one opening in the photoresist layer may be formed within each pad cavity region. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the lower portion of the first pad and the via-level dielectric material layer 954. The first pad connection via cavities 969 are formed through the lower portion of the first pad and the via-level dielectric material layer 954. The top surface of the top metal interconnect structure 980 is physically exposed at the bottom of each of the first pad connection via cavities 969. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0161] The first integrated line and via cavities 959 are formed through the first pad and the via-level dielectric material layer 954. Each of the first integrated line and via cavities 959 includes a respective first pad cavity within the first pad cavities 979 and at least one first pad connection via cavity 969. In one embodiment, the first integrated line and via cavities 959 may include the first pad cavities 979 and a plurality of first pad connection via cavities 969 (such as a cluster of pad connection via cavities). The top surfaces of a subgroup of the first metal interconnect structures 980 are physically exposed to the first pad and via cavities 959 when the first pad and via cavities 959 are formed.

[0162] In one embodiment, the first pad connection via cavities 969 may be arranged as a cluster of first pad connection via cavities. Each cluster of the first pad connection via cavities 969 may be located within the region of a respective first pad cavity within the first pad cavities 979. For example, each of the first pad cavities 979 may have a rectangular shape or a rounded rectangular shape having sides parallel to a first horizontal direction hd1 and a second horizontal direction hd2. The dimension of each of the first pad cavities 979 along the first horizontal direction hd1 and the dimension of each of the first pad cavities 979 along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers. In such a case, each cluster of the first pad connection via cavities 969 may be arranged as a rectangular array. Each cluster of the first pad connection via cavities 969 may be formed as an M×N rectangular array, where M and N are independent integers. Alternatively, a single first pad connection via cavity 969 may be formed for each region of the bonding pads to be formed subsequently.

[0163] Each first pad connection via cavity 969 is formed within a region of a corresponding topmost metal interconnect structure in the topmost metal interconnect structure 980. Clusters of first pad connection via cavities 969 may be formed along each edge seal structure (688, 984, 986). Clusters of first pad connection via cavities 969 and gap regions may alternate along the perimeter of the first semiconductor die 900 over the entire area of each edge seal structure (688, 984, 986). In the presence of multiple nested edge seal structures (688, 984, 986), multiple lateral alternating sequences of clusters of first pad connection via cavities 969 and gap regions are provided along the perimeter of the first semiconductor die 900.

[0164] Reference Figure 24 , a first distal dielectric diffusion barrier layer 956L may be deposited in the first integrated line and via cavity 959 and over the first pad and via level dielectric material layer 954. The first distal dielectric diffusion barrier layer 956L is deposited on the top surface of the underlying first metal interconnect structure 980 and on the physically exposed surface of the first pad and via level dielectric material layer 954. The first distal dielectric diffusion barrier layer 956L comprises a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of such a diffusion barrier dielectric material. In one embodiment, the first distal dielectric diffusion barrier layer 956L comprises a moisture barrier dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The first distal dielectric diffusion barrier layer 956L may be deposited by a conformal deposition process such as a chemical vapor deposition process. The thickness of the first distal dielectric diffusion barrier layer 956L may be in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, although smaller and larger thicknesses may also be used.

[0165] Reference Figure 25 , a photoresist layer 977 may be applied over the first distal dielectric diffusion barrier layer 956L and may be lithographically patterned to form discrete openings therethrough. The openings are formed through the photoresist layer 977 in a region of the bottom surface of the first integrated pad and via cavity 959. Each region of the discrete openings in the photoresist layer 977 may be located interior to the bottom perimeter of the pad cavity portion of a corresponding first integrated line and via cavity 959, i.e., interior to the closed bottom edge of a set of sidewalls of the pad cavity portion of a corresponding first integrated line and via cavity 959. Each opening through the photoresist layer 977 may include the entire area of a set of at least one first pad connection via cavity 969 located below the pad cavity portion 979 of a corresponding first integrated line and via cavity 959.

[0166] The unmasked portion of the first distal dielectric diffusion barrier layer 956L is anisotropically etched by performing an anisotropic etching process using the patterned photoresist layer 977 as an etch mask. The unmasked horizontal portion of the first distal dielectric diffusion barrier layer 956L can be anisotropically etched by the anisotropic etching process. The horizontal portion of the first distal dielectric diffusion barrier layer 956L within the regions of the first integrated pad and the via cavity 959 can be removed by the anisotropic etching process, and the top surfaces of the subgroup of the first metal interconnect structures 980 that are directly beneath the first proximal dielectric diffusion barrier layer 972 are physically exposed.

[0167] Openings are formed through the first distal dielectric diffusion barrier layer 956L along each perimeter of the openings through the patterned photoresist layer 977. The horizontal extending portions of the first distal dielectric diffusion barrier layer 956L that are located at the bottom regions of the pad cavity portions of the first integrated line and the via cavity 959 and above the first pad connection via cavity 969 are removed. Accordingly, the horizontal portion of the first distal dielectric diffusion barrier layer 956L that is located at the bottom portion of the first pad connection via cavity 969 is removed. The remaining portion of the patterned first distal dielectric diffusion barrier layer 956L includes a first dielectric diffusion barrier portion 956P that laterally surrounds the respective pad cavity portions 979 of the first integrated line and the via cavity 959. Portions of the top surfaces of the respective first metal interconnect structures 980 are physically exposed beneath each first integrated line and the via cavity 959.

[0168] The remaining portion of the first distal dielectric diffusion barrier layer 956L after the anisotropic etching process includes a first dielectric diffusion barrier portion 956P formed on the sidewalls of the pad cavity portions 979 of the first integrated pad and the via cavity 959, and a first tubular dielectric diffusion barrier liner 955 formed on the sidewalls of the first via cavity portion 969 of the first integrated pad and the via cavity 959 that is located beneath the pad cavity portions 979. The continuous remaining portion of the first distal dielectric diffusion barrier layer 956L after the anisotropic etching process that includes the first dielectric diffusion barrier portion 956P is referred to herein as the first distal dielectric diffusion barrier layer 956. The first distal dielectric diffusion barrier layer 956 includes a first horizontally extending diffusion barrier portion that overlies the first pad and via level dielectric material layer 954. The first dielectric diffusion barrier portions 956P are interconnected to each other by the first horizontally extending diffusion barrier portion of the first distal dielectric diffusion barrier layer 956.

[0169] Each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P is vertically spaced apart from the first proximal dielectric diffusion barrier layer 972. Each tubular dielectric diffusion barrier liner 955 in the tubular dielectric diffusion barrier liner 955 laterally surrounds the first integrated pad and the first via cavity portion 969 of the corresponding first integrated pad and via cavity in the via cavity 959. In one embodiment, the tubular dielectric diffusion barrier liner 955 does not contact the first dielectric diffusion barrier portion 956P and is laterally spaced apart therefrom. Each tubular dielectric diffusion barrier liner 955 may contact the cylindrical sidewall of the corresponding opening in the first proximal dielectric diffusion barrier layer 972.

[0170] Each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P of the first distal dielectric diffusion barrier layer 956 laterally surrounds the pad cavity portion 979 of the corresponding first integrated line and via cavity 959, and is vertically spaced apart from the first proximal dielectric diffusion barrier layer 972 by the lower portion of the first pad and via level dielectric material layer 954. In one embodiment, the perimeter of each opening through the first distal dielectric diffusion barrier layer 956 may be laterally offset outwardly from a corresponding set of at least one tubular dielectric diffusion barrier liner 955. In such a case, each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P includes a horizontal segment having a bottom surface that contacts the horizontal surface of the first pad and via level dielectric material layer 954. The patterned photoresist layer 977 may then be removed, for example, by ashing.

[0171] Reference Figure 26 , the first bonding pad liner layer 958L and the first metal pad fill material layer 958F may be sequentially deposited in the first integrated line and via cavity 959. The first bonding pad liner layer 958L includes a metal nitride material such as TiN, TaN, and / or WN. The conductive metal barrier material may block copper diffusion. The first bonding pad liner layer 958L is formed on the top surface of a subgroup of the first metal interconnect structure 980 located at the topmost level of the first distal interconnect level dielectric material layer 960, on the inner wall of the tubular dielectric diffusion barrier liner 955, on the physically exposed surface of the first distal dielectric diffusion barrier layer 956, and on the physically exposed horizontal surface of the first pad and via level dielectric material layer 954 located between the topmost surface and the bottom surface of the first pad and via level dielectric material layer 954. The thickness of the first bonding pad liner layer 958L may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses may also be used. The first metal pad fill material layer 958F may include copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the first integrated line and via cavity 959.

[0172] Reference Figure 27A and Figure 27B The excess portions of the first metal pad fill material layer 958F and the first bond pad liner layer 958L covering the horizontal plane over the top surface of the first distal dielectric diffusion barrier layer 956 can be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the first metal pad fill material layer 958F and the first bond pad liner layer 958L that fill the first integrated line and via cavity 959 constitute the first integrated pad and via structure 958 (e.g., dual damascene first bond pad). Each first integrated pad and via structure 958 can include a first bond pad liner 958A and a first metal pad fill material portion 958B. The first bond pad liner 958A is the patterned remaining portion of the first bond pad liner layer 958L, and the first metal pad fill material portion 958B is the patterned remaining portion of the first metal pad fill material layer 958F. The top surface of the first integrated pad and via structure 958 can be in the same horizontal plane as the top surface of the first distal dielectric diffusion barrier layer 956.

[0173] Generally speaking, the first integrated pad and via structure 958 is formed in the remaining volume of the first integrated line and via cavity 959. Each first integrated pad and via structure in the first integrated pad and via structure 958 includes a first bond pad liner 988A and a first metal pad fill material portion 988B and / or consists of the above items, the first bond pad liner includes a metal nitride material, and the first metal pad fill material portion is embedded in the bond pad liner 988A.

[0174] In one embodiment, the first dielectric diffusion barrier portion 956P is interconnected through the first horizontally extending diffusion barrier portions covering the first pad and via level dielectric material layer 954. The top surface of the first integrated pad and via structure 958 can be located in the horizontal plane of the top surface of the first horizontally extending diffusion barrier portion including the first distal dielectric diffusion barrier layer 956. Each first integrated pad and via structure in the first integrated pad and via structure 958 can directly contact at least one sidewall of the first proximal dielectric diffusion barrier layer 972. Generally speaking, the first pad and via level dielectric material layer 954 includes first integrated lines and via cavities filled with corresponding combinations of the first integrated pad and via structures 958 and corresponding first dielectric diffusion barrier portions 956P.

[0175] The first sub-group of the first integrated pad and via structure 958 may be located within the region of at least one edge seal structure (688, 984, 986) and may be electrically connected to the corresponding nodes of the first semiconductor device 920. The second sub-group of the first integrated pad and via structure 958 may be located on the corresponding edge seal structure of at least one edge seal structure (688, 984, 986) and may be electrically connected to the corresponding edge seal structure.

[0176] In one embodiment, the first bonding pad liner 958A within each first integrated pad and via structure of the first integrated pad and via structure 958 extends continuously from the top surface of the corresponding first metal interconnect structure in the first metal interconnect structure 980 to a horizontal plane including the topmost surface of the first dielectric diffusion barrier portion 956P and directly contacts the horizontal surface of the first pad and via level dielectric material layer 954 located within the opening passing through the corresponding first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P.

[0177] Each first integrated pad and via structure 958 has at least one bottom surface in contact with the first metal interconnect structure 980. In one embodiment, the via portion of the first integrated pad and via structure 958 contacts the horizontal surface of the first metal interconnect structure 980 located at the topmost level of the first distal interconnect level dielectric material layer 960. The first dielectric diffusion barrier portion 956P is embedded in the first pad and via level dielectric material layer 954. Each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion 956P contacts and laterally surrounds the pad portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure 958. Each tubular dielectric diffusion barrier liner 955 laterally surrounds the via portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure 958.

[0178] Reference Figure 28 , a region of the second semiconductor die 700 in a second configuration is shown. The second configuration of the second semiconductor die 700 may be derived from the first configuration of the second semiconductor die 700 shown by sequentially depositing a layer stack including a second proximal dielectric diffusion barrier layer 772 and a second pad and via level dielectric material layer 754 directly on the topmost surface of the second interconnect level dielectric material layer 760. In other words, the second interconnect capping dielectric diffusion barrier layer 762 and the second pad connection via level dielectric material layer 764 shown are not formed, and the second proximal dielectric diffusion barrier layer 772 may be directly formed on the top surface of the second interconnect level dielectric material layer 760. Figure 9 shown. Figure 9 shown.

[0179] The second proximal dielectric diffusion barrier layer 772 contacts the top surface of a subgroup of the second metal interconnect structures 780 and the topmost surface of the second dielectric material layer 760. The second proximal dielectric diffusion barrier layer 772 may include a dielectric material that blocks moisture diffusion. The second proximal dielectric diffusion barrier layer 772 comprises a dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of such dielectric material. In one embodiment, the second proximal dielectric diffusion barrier layer 772 may include a dielectric material having a dielectric constant greater than 5, such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9. The thickness of the second proximal dielectric diffusion barrier layer 772 may be in the range of 5 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0180] A second pad and via level dielectric material layer 754 may be formed over the second proximal dielectric diffusion barrier layer 772. The second pad and via level dielectric material layer 754 may include undoped silicate glass, doped silicate glass, or organosilicate glass, and / or consist essentially of the foregoing. The thickness of the second pad and via level dielectric material layer 754 may be in the range of 600 nm to 6,000 nm, although smaller and larger thicknesses may also be used. The second pad and via level dielectric material layer 754 may have a planar top surface.

[0181] A photoresist layer (not shown) may be applied over the second pad and via level dielectric material layer 754 and may be lithographically patterned to form discrete openings in the regions overlying the second metal interconnect structures 780 embedded within the topmost layer of the second interconnect level dielectric material layer 760. Each discrete opening in the photoresist layer has the shape of a bonding pad to be subsequently formed. For example, each discrete opening in the photoresist layer may have a rectangular shape or a rounded rectangular shape. The dimension of each opening in the direction along the sides of the opening in the photoresist layer may be in the range of 2 micrometers to 60 micrometers.

[0182] An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the upper portion of the second pad and via level dielectric material layer 754. The second pad cavity 779 is formed partially through the second pad and via level dielectric material layer 754. The depth of the second pad cavity 779 can be in the range of 20% to 80% of the thickness of the second pad and via level dielectric material layer 754, such as 40% to 60%. Each second pad cavity 779 can have a horizontal cross-sectional shape that is rectangular or rounded rectangular, such that the lateral dimension of each second pad cavity 779 in the direction of each side of the rectangular or rounded rectangular shape is in the range of 2 microns to 60 microns. In one embodiment, each second pad cavity 779 can have a horizontal cross-sectional shape that is square or rounded square. The sidewalls of the second pad cavity 779 can be vertical, or can have a taper angle greater than 0 degrees and less than 30 degrees relative to the vertical direction (such as a taper angle in the range of 3 degrees to 10 degrees).

[0183] Reference Figure 29A and Figure 29B , a photoresist layer (not shown) can be applied over the second pad and via level dielectric material layer 754 and can be lithographically patterned to form discrete openings within the area of the second pad cavity 779. Specifically, at least one opening in the photoresist layer can be formed within each area of the second pad cavity 779. In one embodiment, a cluster of openings (such as an array of openings) in the photoresist layer can be formed within each pad cavity area. In another embodiment, one opening in the photoresist layer can be formed within each pad cavity area. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the lower portion of the second pad and via level dielectric material layer 754. The second pad connection via cavity 769 is formed through the lower portion of the second pad and via level dielectric material layer 754. The top surface of the top metal interconnect structure 780 can be physically exposed at the bottom of each second pad connection via cavity 769. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0184] The second integrated line and via cavity 759 is formed through the second pad and via level dielectric material layer 754. Each second integrated line and via cavity 759 includes a respective second pad cavity in the second pad cavity 779 and at least one second pad connection via cavity 769. In one embodiment, the second integrated line and via cavity 759 can include the second pad cavity 779 and a plurality of second pad connection via cavities 769 (such as a cluster of pad connection via cavities). The top surfaces of a subgroup of the second metal interconnect structures 780 are physically exposed to the second pad and via cavity 759 when the second pad and via cavity 759 is formed.

[0185] In one embodiment, the second pad connection via cavities 769 may be arranged as a cluster of second pad connection via cavities. Each cluster of the second pad connection via cavities 769 may be located within the area of a corresponding second pad cavity 779 in the second pad cavity. For example, each second pad cavity 779 may have a rectangular shape or a rounded rectangular shape having sides parallel to the second horizontal direction hd1 and the second horizontal direction hd2. The dimension of each second pad cavity 779 along the second horizontal direction hd1 and the dimension of each second pad cavity 779 along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers. In this case, each cluster of the second pad connection via cavities 769 may be arranged as a rectangular array. Each cluster of the second pad connection via cavities 769 may be formed as an M×N rectangular array, where M and N are independent integers. Alternatively, a single second pad connection via cavity 769 may be formed for each area of the bonding pads to be formed subsequently.

[0186] Each second pad connection via cavity 769 is formed within the area of a corresponding topmost metal interconnect structure 780 in the topmost metal interconnect structure. Clusters of the second pad connection via cavities 769 may be formed along each edge seal structure (not shown) in the second semiconductor die 700. Clusters of the second pad connection via cavities 769 and the gap regions may alternate along the perimeter of the second semiconductor die 700 over the entire area of each edge seal structure. In the case where there are multiple nested edge seal structures in the second semiconductor die 700, multiple lateral alternating sequences of clusters of the second pad connection via cavities 769 and the gap regions are provided along the perimeter of the second semiconductor die 700.

[0187] Reference Figure 30 Referring, the second distal dielectric diffusion barrier layer 756L may be deposited in the second integrated line and via cavities 759 and over the second pad and via level dielectric material layer 754. The second distal dielectric diffusion barrier layer 756L is deposited on the top surface of the underlying second metal interconnect structure 780 and on the physically exposed surface of the second pad and via level dielectric material layer 754. The second distal dielectric diffusion barrier layer 756L includes a diffusion barrier dielectric material such as silicon nitride, silicon oxynitride, or a stack thereof, and / or consists essentially of the diffusion barrier dielectric material. In one embodiment, the second distal dielectric diffusion barrier layer 756L includes a moisture-proof dielectric material having a dielectric constant greater than 5 (such as silicon nitride having a dielectric constant of 7.9 or silicon oxynitride having a dielectric constant in the range of 5 to 7.9). The second distal dielectric diffusion barrier layer 756L may be deposited by a conformal deposition process such as a chemical vapor deposition process. The thickness of the second distal dielectric diffusion barrier layer 756L may be in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses may also be used.

[0188] Reference Figure 31, a photoresist layer 777 may be applied over the second distal dielectric diffusion barrier layer 756L and may be lithographically patterned to form discrete openings therethrough. The openings are formed through the photoresist layer 777 in the regions of the bottom surface of the second integrated pad and the via cavity 759 by lithographically patterning the photoresist layer 777. Each region of the discrete openings in the photoresist layer 777 may be located inside the bottom perimeter of the corresponding second integrated line and the pad cavity portion of the via cavity 759, i.e., inside the closed bottom edges of a set of sidewalls of the corresponding second integrated line and the pad cavity portion of the via cavity 759. Each opening through the photoresist layer 777 may include the entire region of a set of at least one second pad connection via cavity located below the corresponding second integrated line and the pad cavity portion of the via cavity 759.

[0189] The unmasked portion of the second distal dielectric diffusion barrier layer 756L is anisotropically etched by performing an anisotropic etching process using the patterned photoresist layer 777 as an etch mask. The unmasked horizontal portion of the second distal dielectric diffusion barrier layer 756L may be anisotropically etched by the anisotropic etching process. The horizontal portion of the second distal dielectric diffusion barrier layer 756L in the regions of the second integrated pad and the via cavity 759 may be removed by the anisotropic etching process, and the top surfaces of a subgroup of the second metal interconnect structures 780 that are directly below the second proximal dielectric diffusion barrier layer 772 are physically exposed.

[0190] Openings are formed through the second distal dielectric diffusion barrier layer 756L along each perimeter of the openings through the patterned photoresist layer 777. The horizontally extending portions of the second distal dielectric diffusion barrier layer 756L that are located at the bottom region of the pad cavity portion 779 of the second integrated line and the via cavity 759 and above the second pad connection via cavity 769 are removed. The horizontal portion of the second distal dielectric diffusion barrier layer 756L that is located at the bottom portion of the second pad connection via cavity 769 is also removed. The remaining portion of the patterned second distal dielectric diffusion barrier layer 756L includes second dielectric diffusion barrier portions 756P that laterally surround the corresponding pad cavity portions of the second integrated line and the via cavity 759. Portions of the top surfaces of the corresponding second metal interconnect structures 780 are physically exposed below each second integrated line and the via cavity 759.

[0191] The remaining portion of the second distal dielectric diffusion barrier layer 756L after the anisotropic etching process includes a second dielectric diffusion barrier portion 756P formed on the sidewalls of the second integrated pad and the pad cavity portion of the via cavity 759, and a second tubular dielectric diffusion barrier liner 755 formed on the sidewalls of the second integrated pad and the second via cavity portion 769 of the via cavity 759 that is located below the pad cavity portion 779. The continuous remaining portion of the second distal dielectric diffusion barrier layer 756L after the anisotropic etching process that includes the second dielectric diffusion barrier portion 756P is referred to herein as the second distal dielectric diffusion barrier layer 756. The second distal dielectric diffusion barrier layer 756 includes a second horizontally extending diffusion barrier portion that overlies the second pad and via level dielectric material layer 754. The second dielectric diffusion barrier portions 756P are interconnected to each other through the second horizontally extending diffusion barrier portion of the second distal dielectric diffusion barrier layer 756.

[0192] Each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portion 756P is vertically spaced apart from the second proximal dielectric diffusion barrier layer 772. Each tubular dielectric diffusion barrier liner 755 in the tubular dielectric diffusion barrier liner 755 laterally surrounds the first via cavity portion 769 of the corresponding second integrated pad and via cavity in the second integrated pad and via cavity 759. The tubular dielectric diffusion barrier liner 755 does not contact the second dielectric diffusion barrier portion 756P and is laterally spaced apart therefrom. Each tubular dielectric diffusion barrier liner 755 may contact the cylindrical sidewall of the corresponding opening in the second proximal dielectric diffusion barrier layer 772.

[0193] Each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portion 756P of the second distal dielectric diffusion barrier layer 756 laterally surrounds the pad cavity portion of the corresponding second integrated line and via cavity 759, and is vertically spaced apart from the second proximal dielectric diffusion barrier layer 772 by a lower portion of the second pad and via level dielectric material layer 754. In one embodiment, the perimeter of each opening through the second distal dielectric diffusion barrier layer 756 may be laterally offset outwardly from a corresponding set of at least one tubular dielectric diffusion barrier liner 755. In this case, each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portion 756P includes a horizontal segment that has a bottom surface that contacts the horizontal surface of the second pad and via level dielectric material layer 754. The patterned photoresist layer 777 may then be removed, for example, by ashing.

[0194] Reference Figure 32, the second bonding pad liner layer 758L and the second metal pad fill material layer 758F may be sequentially deposited in the second integrated line and via cavity 759. The second bonding pad liner layer 758L comprises a metal nitride material such as TiN, TaN, and / or WN. The conductive metal barrier material may block moisture and copper diffusion. The second bonding pad liner layer 758L is formed on the top surface of a subgroup of the second metal interconnect structures 780 located at the topmost level of the second distal interconnect level dielectric material layer 760, on the inner wall of the tubular dielectric diffusion barrier liner 755, on the physically exposed surface of the second distal dielectric diffusion barrier layer 756, and on the physically exposed horizontal surface of the second pad and via level dielectric material layer 754 between the topmost surface and the bottom surface of the second pad and via level dielectric material layer 754. The thickness of the second bonding pad liner layer 758L may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses may also be used. The second metal pad fill material layer 758F may include copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and an electroplating process to fill the remaining volume of the second integrated line and via cavity 759.

[0195] Reference Figure 33A and Figure 33B , the excess portions of the second metal pad fill material layer 758F and the second bonding pad liner layer 758L covering the horizontal plane including the top surface of the second distal dielectric diffusion barrier layer 756 may be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the second metal pad fill material layer 758F and the second bonding pad liner layer 758L filling the second integrated line and via cavity 759 constitute the second integrated pad and via structure 758 (e.g., dual damascene bonding pad). Each second integrated pad and via structure 758 may include a second bonding pad liner 758A and a second metal pad fill material portion 758B. The second bonding pad liner 758A is the patterned remaining portion of the second bonding pad liner layer 758L, and the second metal pad fill material portion 758B is the patterned remaining portion of the second metal pad fill material layer 758F. The top surface of the second integrated pad and via structure 758 may be in the same horizontal plane as the top surface of the second distal dielectric diffusion barrier layer 756.

[0196] Generally speaking, the second integrated pad and via structure 758 is formed in the remaining volume of the second integrated line and via cavity 759. Each second integrated pad and via structure in the second integrated pad and via structure 758 includes a second bonding pad liner 788A and a second metal pad fill material portion 788B and / or consists of the above items, the second bonding pad liner includes a metal nitride material, and the second metal pad fill material portion is embedded in the bonding pad liner 788A.

[0197] In one embodiment, the second dielectric diffusion barrier portion 756P interconnects through second horizontally extending diffusion barrier portions covering the second pad and the via-level dielectric material layer 754. The top surface of the second integrated pad and via structure 758 may be in a horizontal plane including the top surface of the second horizontally extending diffusion barrier portion including the second distal dielectric diffusion barrier layer 756. Each second integrated pad and via structure in the second integrated pad and via structure 758 may directly contact at least one sidewall of the second proximal dielectric diffusion barrier layer 772. Generally, the second pad and via-level dielectric material layer 754 includes second integrated lines and via cavities filled with corresponding combinations of second integrated pad and via structures 788 and corresponding second dielectric diffusion barrier portions 756P.

[0198] A first subgroup of the second integrated pad and via structures 758 may be located within a region of at least one edge seal structure (not shown) in the second semiconductor die 700 and may be electrically connected to corresponding nodes of the second semiconductor device 720. A second subgroup of the second integrated pad and via structures 758 may be located on the corresponding edge seal structure in at least one edge seal structure and may be electrically connected to the corresponding edge seal structure. The pattern of the second dual damascene bond pads 758 may be arranged as a mirror image pattern of the pattern of the first dual damascene bond pads 958.

[0199] In one embodiment, the second bond pad liner 758A within each second integrated pad and via structure in the second integrated pad and via structure 758 extends continuously from the top surface of the corresponding second metal interconnect structure in the second metal interconnect structure 780 to a horizontal plane including the topmost surface of the second dielectric diffusion barrier portion 756P and directly contacts the horizontal surface of the second pad and via-level dielectric material layer 754 located within the region of the opening through the corresponding second dielectric diffusion barrier portion in the second dielectric diffusion barrier portion 756P.

[0200] Each second integrated pad and via structure 758 has at least one bottom surface contacting the second metal interconnect structure 780. In one embodiment, the via portion of the second integrated pad and via structure 758 contacts the horizontal surface of the second metal interconnect structure 780 located at the topmost level of the second interconnect-level dielectric material layer 760. The second dielectric diffusion barrier portion 756P is embedded in the second pad and via-level dielectric material layer 754. Each second dielectric diffusion barrier portion in the second dielectric diffusion barrier portion 756P contacts and laterally surrounds the pad portion of the corresponding second integrated pad and via structure in the second integrated pad and via structure 758. Each tubular dielectric diffusion barrier liner 755 laterally surrounds the via portion of the corresponding second integrated pad and via structure in the second integrated pad and via structure 758.

[0201] Reference Figure 34 The second semiconductor die 700 and the first semiconductor die 700 can be aligned such that each second integrated pad and via structure 758 faces a corresponding first integrated pad and via structure among the first integrated pads and via structures 958. Each pair of facing first integrated pads and via structures 958 and second integrated pads and via structures 758 can be aligned to maximize the area overlap between the first integrated pads and via structures 958 and the second integrated pads and via structures 758. If the first integrated pads and via structures 958 and the second integrated pads and via structures 758 have different areas, each overlap area between a pair of facing first integrated pads and via structures 958 and second integrated pads and via structures 758 can be the same as the area of the smaller integrated pad and via structure between the pair of facing first integrated pads and via structures 958 and second integrated pads and via structures 758. If the first integrated pads and via structures 958 and the second integrated pads and via structures 758 have the same area, the overlap area between a pair of facing first integrated pads and via structures 958 and second integrated pads and via structures 758 can be in the range of 90% to 100% of the area of the first integrated pads and via structures 958 (which is the same as the area of the second integrated pads and via structures 758), such as 95% to 100%.

[0202] The first semiconductor die 900 and the second semiconductor die 700 can be in contact with each other such that each first integrated pad and via structure 958 contacts a corresponding second integrated pad and via structure among the second integrated pads and via structures 758, with a corresponding area overlap therebetween. The assembly of the first semiconductor die 900 and the second semiconductor die 700 is annealed at a high temperature in the range of 250 degrees Celsius to 400 degrees Celsius to cause copper diffusion at each interface between the corresponding first integrated pads and via structures 958 and the corresponding second integrated pads and via structures 758 in the paired facing relationship. The duration of the annealing process at the high temperature can be in the range of 5 minutes to 2 hours, but shorter or longer annealing durations can also be used. Each pair of facing first integrated pads and via structures 958 and second integrated pads and via structures 758 are joined to each other during the annealing process at the high temperature. A first exemplary bonding structure including the first semiconductor die 900 and the second semiconductor die 700 can be formed.

[0203] A layer stack including a horizontal extension of a first distal dielectric diffusion barrier layer 956 and a horizontal extension of a second distal dielectric diffusion barrier layer 756 may be located between a first pad and a via-level dielectric material layer 954 and a second pad and a via-level dielectric material layer 754. A vertical separation distance between the first pad and the via-level dielectric material layer 954 and the second pad and the via-level dielectric material layer 754 may be a sum of a thickness of the first distal dielectric diffusion barrier layer 956 and a thickness of the second distal dielectric diffusion barrier layer 756.

[0204] Reference Figure 35 , the first substrate 908 may be thinned from the back side by grinding, polishing, anisotropic etching, or isotropic etching. The thinning process may continue until a horizontal portion of the through-substrate liner 386 is removed and a horizontal surface of the through-substrate via structure 388 is physically exposed. Generally, by thinning, an end surface of the through-substrate via structure 388 may be physically exposed at a back side of the first substrate 908 of the substrate of the memory die. A thickness of the first substrate 908 after thinning may be in a range of 1 micrometer to 30 micrometers, such as 2 micrometers to 15 micrometers, but smaller and larger thicknesses may also be used.

[0205] Reference Figure 36 , a backside insulating layer 930 may be formed on the back side of the first substrate 908. The backside insulating layer 930 includes an insulating material, such as silicon oxide. A thickness of the backside insulating layer 930 may be in a range of 50 nm to 500 nm, but smaller and larger thicknesses may also be used. A photoresist layer (not shown) may be applied over the backside insulating layer 930 and may be lithographically patterned to form an opening over an area of the through-substrate via structure 388. An etching process may be performed to form a via cavity through the backside insulating layer 930 under each opening in the photoresist layer. A top surface of the through-substrate via structure 388 may be physically exposed at a bottom of each via cavity through the backside insulating layer 930.

[0206] At least one metal material may be deposited into the openings through the backside insulating layer 930 and deposited above the planar surface of the backside insulating layer 930 to form a metal material layer. The at least one metal material may include copper, aluminum, ruthenium, cobalt, molybdenum, and / or any other metal material that can be deposited by physical vapor deposition, chemical vapor deposition, electroplating, vacuum evaporation, or other deposition methods. For example, a metal nitride liner material (such as TiN, TaN, or WN) may be directly deposited on the physically exposed surface of the through-substrate via structure 388, on the sidewalls of the openings through the backside insulating layer 930, and above the physically exposed planar surface of the backside insulating layer 930. The thickness of the metal nitride liner material may be in the range of 10 nm to 100 nm, although smaller and larger thicknesses may also be used. At least one metal fill material, such as copper or aluminum, may be deposited above the metal nitride liner material. In one embodiment, the at least one metal fill material may include a stack of high-conductivity metal layers (such as a copper layer or an aluminum layer) and a under-bump metallurgy (UBM) layer stack for bonding a solder ball thereto. Exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stacks, Al / Ni / Cu stacks, Cu / Ni / Au stacks, Cu / Ni / Pd stacks, Ti / Ni / Au stacks, Ti / Cu / Ni / Au stacks, Ti-W / Cu stacks, Cr / Cu stacks, and Cr / Cu / Ni stacks. The thickness of the metal material layer above the planar horizontal surface of the backside insulating layer 930 may be in the range of 0.5 microns to 10 microns, such as 1 micron to 5 microns, although smaller and larger thicknesses may also be used.

[0207] The at least one metal fill material and the metal material layer may then be patterned to form discrete backside bonding pads 936 that contact a respective one of the through-substrate via structures 388 in the through-substrate via structure. The backside bonding pads 936 may be used as external integration pads and via structures that can be used to electrically connect the respective nodes within the first semiconductor die 900 and the second semiconductor die 700 to external nodes, such as the integration pads and via structures on a package substrate or the C4 integration pads and via structures of another semiconductor die. For example, a solder material portion 938 may be formed on the backside bonding pads 936, and a C4 bonding process or a wire bonding process may be performed to electrically connect the backside bonding pads 936 to external electrically active nodes.

[0208] Generally speaking, a dorsal bonding pad 936 may be formed on the dorsal surface of the first semiconductor die 900 (which may be a memory die), and this dorsal surface is on the opposite side of the bonding interface between the first semiconductor die 900 and the second semiconductor die 700. The through-substrate via structure 388 may extend vertically through the first semiconductor die 900 and may provide an electrical connection between the dorsal bonding pad 936 and a subgroup of the integrated pads and via structures (958, 758).

[0209] Reference Figure 37 , an alternative embodiment of the first semiconductor die 900 according to a second embodiment of the present disclosure is shown. The alternative embodiment of the first semiconductor die 900 can be obtained from Figure 27A and Figure 27B by removing the horizontally extending portion of the first distal dielectric diffusion barrier layer 956 that covers the first pad and via-level dielectric material layer 954. For example, after removing a portion of the metal material above the top surface of the first distal dielectric diffusion barrier layer 956, the horizontally extending portion of the first distal dielectric diffusion barrier layer 956 that covers the first pad and via-level dielectric material layer 954 can be removed by an additional polishing step of a chemical mechanical planarization process. In this case, the top surface of the first pad and via-level dielectric material layer 954 may be physically exposed after the planarization process, and the top surface of the first integrated pad and via structure 958 may be formed in the same horizontal plane as the top surface of the first pad and via-level dielectric material layer 954. After removing the horizontally extending portion of the first distal dielectric diffusion barrier layer 956, the remaining portion of the first distal dielectric diffusion barrier layer 956 includes first dielectric diffusion barrier portions 956'. The first dielectric diffusion barrier portions 956' are not interconnected with each other and are formed as discrete structures that laterally surround the respective first integrated pad and via structures 958.

[0210] Reference Figure 38 , the second semiconductor die 700 may be provided in the same manner as described above and may be bonded to the alternative configuration of the first semiconductor die Figure 37 shown to provide an alternative embodiment of the second bonding assembly. The structure Figure 38 shown may be subjected to Figure 35 and Figure 36Processing steps. In this case, the horizontal extension portion of the second distal dielectric diffusion barrier layer 756 can be located between the first pad and the via-level dielectric material layer 954 and the second pad and the via-level dielectric material layer 754. The vertical separation distance between the first pad and the via-level dielectric material layer 954 and the second pad and the via-level dielectric material layer 754 can be the same as the thickness of the second distal dielectric diffusion barrier layer 756. The first dielectric diffusion barrier portion 956' is a discrete material portion that is laterally spaced apart from the first pad and the via-level dielectric material layer 954 from each other. The top surface of the first integrated pad and via structure 958 can be located in a horizontal plane including the top surface of the first pad and the via-level dielectric material layer 954.

[0211] In another alternative embodiment of the first semiconductor die 900 according to the first embodiment of the present disclosure, the horizontal extension portion of the second distal dielectric diffusion barrier layer 756 covering the layer 754 can be removed. In this alternative embodiment, the vertical separation distance between the first pad and the via-level dielectric material layer 954 and the second pad and the via-level dielectric material layer 754 can be the same as the thickness of the first distal dielectric diffusion barrier layer 956 provided between the layer 754 and the layer 954.

[0212] In one embodiment, the combination of the first proximal dielectric diffusion barrier layer 972, the first distal dielectric diffusion barrier layer 956, the tubular dielectric diffusion barrier liner 955, the first bonding pad liner 958A, the second proximal dielectric diffusion barrier layer 772, the second distal dielectric diffusion barrier layer 756, the tubular dielectric diffusion barrier liner 755, and the second bonding pad liner 758A forms a continuous diffusion barrier structure that protects the first metal interconnect structure 980 embedded in the first distal interconnect-level dielectric material layer 960 and protects the second metal interconnect structure 780 embedded in the second interconnect-level dielectric material layer 760 from moisture and / or contaminant diffusion through the first pad and the via-level dielectric material layer 954 or the second pad and the via-level dielectric material layer 754.

[0213] Although the present disclosure is described as employing a first semiconductor die 900 in a first configuration being bonded to a second semiconductor die 700 in a first configuration (as Figures 1A to 21B shown) and the first semiconductor die 900 in a second configuration being bonded to the second semiconductor die 700 in a second configuration (as Figures 22 to 38the illustrated embodiments), but embodiments in which a first semiconductor die 900 in a first configuration is bonded to a second semiconductor die 700 in a second configuration and / or a first semiconductor die 900 in a second configuration is bonded to a second semiconductor die 700 in a first configuration are explicitly contemplated herein. Accordingly, the claims of the present application should be construed to cover all possibilities in which the first semiconductor die 900 and the second semiconductor die 700 have any of the above configurations.

[0214] Reference Figures 22 to 38 and the related drawings and in accordance with various embodiments of the present disclosure, a structure including a first semiconductor die 900 is provided. The first semiconductor die 900 includes: a first semiconductor device 920 located above a first substrate 908; a first interconnect level dielectric material layer (290, 960) embedding a first metal interconnect structure 980 that is electrically connected to and overlies the first semiconductor device 920; a layer stack of a first proximal dielectric diffusion barrier layer 972 and a first pad and via level dielectric material layer 954 that overlies the first interconnect level dielectric material layer (290, 960) and embeds a first integrated pad and via structure 958; and a first dielectric diffusion barrier portion (956P, 956') embedded in the first pad and via level dielectric material layer 954, wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion (956P, 956') contacts and laterally surrounds a pad portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure 958.

[0215] In one embodiment, each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion (956P, 956') is vertically spaced apart from the first proximal dielectric diffusion barrier layer 972. In one embodiment, a tubular dielectric diffusion barrier liner 955 may laterally surround a via portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure 958. In one embodiment, the tubular dielectric diffusion barrier liner 955 does not contact the first dielectric diffusion barrier portion (956P, 956') and is laterally spaced apart therefrom. In one embodiment, the tubular dielectric diffusion barrier liner 955 contacts a sidewall of a corresponding opening in the first proximal dielectric diffusion barrier layer 972.

[0216] In one embodiment, the first proximal dielectric diffusion barrier layer 972 contacts a top surface of a subgroup of the first metal interconnect structure 980 and a topmost surface of the first interconnect level dielectric material layer (290, 960); and a via portion of the first integrated pad and via structure 958 contacts a horizontal surface of the subgroup of the first metal interconnect structure 980.

[0217] In one embodiment, each of the first integrated pad and via structures 958 includes: a first bond pad liner 958A that includes a metal nitride material; and copper that includes a first metal pad fill material portion 958B with an embedded portion within the first bond pad liner 958A. In one embodiment, the first dielectric diffusion barrier portions 956P are interconnected with each other through a first horizontally extending diffusion barrier portion covering the first pad and via level dielectric material layer 954; and the top surface of the first integrated pad and via structures 958 lies in a horizontal plane that includes the top surface of the first horizontally extending diffusion barrier portion. Alternatively, the first dielectric diffusion barrier portions 956' are discrete material portions that are laterally spaced apart from each other by the first pad and via level dielectric material layer 954; and the top surface of the first integrated pad and via structures 958 lies in a horizontal plane that includes the top surface of the first pad and via level dielectric material layer 954.

[0218] In one embodiment, the first bond pad liner 958A within each of the first integrated pad and via structures 958 extends continuously from the top surface of the corresponding first metal interconnect structure in the first metal interconnect structure 980 to the horizontal plane that includes the topmost surface of the first dielectric diffusion barrier portions (956P, 956') without any openings therein, and directly contacts the horizontal surface of the first pad and via level dielectric material layer 954 that is within the region of the opening through the corresponding first dielectric diffusion barrier portion in the first dielectric diffusion barrier portions (956P, 956').

[0219] In one embodiment, the first dielectric diffusion barrier portions (956P, 956') include a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and the first proximal dielectric diffusion barrier layer 972 includes a dielectric material selected from silicon nitride, silicon oxynitride, and / or silicon carbonitride.

[0220] In one embodiment, the structure includes a second semiconductor die 700 that includes: a second semiconductor device 720 located above a second substrate 708; a second interconnect-level dielectric material layer 760 that embeds a second metal interconnect structure 780 that is electrically connected to the second semiconductor device 720 and is located below the second semiconductor device 720 (in the bonded state); and a second bonding pad (which may be provided as a second bonding pad 788 in a first configuration of the second semiconductor die 700 or as a pad portion of a second integrated pad and via structure 758 in a second configuration of the second semiconductor die 700), the second bonding pad being electrically connected to the second metal interconnect structure 780 and bonded to a corresponding first integrated pad and via structure in the first integrated pad and via structure 958.

[0221] In one embodiment, each second bonding pad in the second bonding pads contacts a corresponding second dielectric diffusion barrier portion (776P, 756P, 756') and is laterally surrounded thereby; the second dielectric diffusion barrier portions (776P, 756P, 756') and the second bonding pads (788, 758) are embedded in a pad-level dielectric material layer (which may be an upper portion of a second pad-level dielectric material layer 774 or a second pad and via-level dielectric material layer 754); and the first pad and via-level dielectric material layer 954 and the pad-level dielectric material layers (774, 754) do not contact each other and are vertically spaced apart from each other by at least one horizontally extending diffusion barrier portion that laterally connects a first dielectric diffusion barrier portion 956P or laterally connects a second dielectric diffusion barrier portion 756P. The at least one horizontally extending diffusion barrier portion may include a horizontally extending portion of a first distal dielectric diffusion barrier layer 956 and / or a horizontally extending portion of a second distal dielectric diffusion barrier layer 756. In one embodiment, the first semiconductor device 920 may include a three-dimensional memory device, and the second semiconductor device 720 may include a driver circuit device (e.g., a CMOS device) for the three-dimensional memory device 920.

[0222] In one embodiment, the first semiconductor die 900 includes at least one edge seal structure (688, 984, 986) that includes a corresponding subgroup of the first metal interconnect structure 980, the at least one edge seal structure providing a corresponding continuous barrier layer that laterally surrounds the first semiconductor device 920 without any lateral openings and extends vertically from the first substrate 908 to the first proximal dielectric diffusion barrier layer 972.

[0223] Generally speaking, various embodiments of the present disclosure provide a moisture diffusion barrier structure at the level of the bonding pads. The formation of a continuous metal structure at the metal-to-metal bonding interface is disadvantageous for forming a high-quality bonding surface because the continuous metal structure causes local variations in the metal-to-dielectric area ratio, changes the microscopic recess depth of the metal relative to the dielectric surface, and degrades the bonding strength due to local variations in the recess depth of the metal structure. The methods and structures of the embodiments of the present disclosure provide a continuous diffusion barrier structure that can block the diffusion of moisture and impurities into the interconnect-level dielectric material layers (290, 960, 760) even if moisture and / or impurities enter through the openings at the level of the metal pads and the via connection structures, and thereby improve the reliability of the bonding assemblies of individual semiconductor dies (900, 700) and / or multiple semiconductor dies (900, 700).

[0224] In addition, the embodiments of the present disclosure provide compatibility of the wafer-level bonding pad structure and block the penetration of moisture from outside the bonded die. The uppermost bonding pads of the semiconductor dies (900, 700) preferably have a square horizontal shape to provide high bonding strength. The square shape of the bonding pads allows moisture to penetrate the space between the bonding pads. However, the dielectric diffusion barrier layer prevents moisture from penetrating into the memory and CMOS devices. Thus, the embodiments provide a combination of high bonding strength and moisture blocking.

[0225] Moisture is blocked by the hermetic ring conductive layer surrounding the semiconductor dies (900, 700) below the bonding pads, and moisture is blocked by the dielectric diffusion barrier layer at the bonding pad level. In addition, in some embodiments, when the bonding pads are partially misaligned, the dielectric diffusion barrier layer can prevent or reduce the outward diffusion of copper from the bonding pads into the silicon oxide dielectric layer.

[0226] In some embodiments, the bottom and sides of the bonding pads (e.g., copper bonding pads) are surrounded by a diffusion barrier metal or metal nitride and a dielectric diffusion barrier layer to reduce or prevent the diffusion of moisture into the bonding pads, which can lead to copper ionization and outward diffusion. In addition, since the outward diffusion of copper from the bonding pads is avoided or reduced, delamination of the bonded semiconductor dies can be avoided or reduced. In addition, since the dielectric diffusion barrier layer is located outside the barrier metal at the bonding pad level, the dielectric diffusion barrier layer blocks the diffusion of moisture into the copper bonding pads. In some embodiments, malfunctions in circuit operation caused by high-frequency noise can also be reduced or avoided.

[0227] In some embodiments, the capacitance between adjacent metal or metal alloy layers in the interconnect layer is reduced by using a low dielectric constant dielectric layer such as SiCN or other dielectric materials described above.

[0228] Figures 1A to 21BThe device of the first embodiment shown avoids or reduces the degradation of the circuit operation speed because the wiring capacitance does not increase when a dielectric layer having a high dielectric constant of at least 5 is placed at the bottom of the bonding pad level without having to place the layer above the top layer of the underlying circuit. Figures 22 to 38 The device of the second embodiment shown is formed by a dual damascene process, which provides reduced process costs. In the second embodiment, a dielectric layer having a high dielectric constant can be placed above the top layer of the underlying circuit.

[0229] Although specific embodiments have been mentioned previously, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". In embodiments shown in the present disclosure using a specific structure and / or configuration, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A structure, the structure comprising a first semiconductor die, wherein the first semiconductor die comprises: A first semiconductor device located above a first substrate; A first interconnect level dielectric material layer embedding a first metal interconnect structure, the first metal interconnect structure being electrically connected to the first semiconductor device and covering the first semiconductor device; A layer stack of a first pad connection via level dielectric material layer and a first proximal dielectric diffusion barrier layer, the layer stack covering the first interconnect level dielectric material layer and embedding a first pad connection via structure; and A first pad level dielectric material layer, the first pad level dielectric material layer including a first pad cavity filled with a respective combination of a first bonding pad and a respective first dielectric diffusion barrier portion, wherein each first bonding pad of the first bonding pads contacts a respective subgroup of the first pad connection via structures; Wherein each first dielectric diffusion barrier portion of the first dielectric diffusion barrier portions contacts a top surface of the first proximal dielectric diffusion barrier layer; Wherein each first dielectric diffusion barrier portion of the first dielectric diffusion barrier portions includes a sidewall segment contacting the first pad level dielectric material layer and extending from a bottom surface of the first pad level dielectric material layer to a top surface of the first pad level dielectric material layer; Wherein each first dielectric diffusion barrier portion of the first dielectric diffusion barrier portions further includes a horizontal segment having a bottom surface contacting the first proximal dielectric diffusion barrier layer, wherein the bottom surface includes an outer perimeter adjacent to a bottom edge of the sidewall segment and an inner perimeter laterally offset inwardly from the outer perimeter by an offset distance greater than a thickness of the sidewall segment of the first dielectric diffusion barrier portion.

2. The structure according to claim 1, wherein: The respective subgroup of the first pad connection via structures includes a plurality of first pad connection via structures; and Each first bonding pad of the first bonding pads directly contacts a portion of the top surface of the first proximal dielectric diffusion barrier layer located between the plurality of first pad connection via structures.

3. The structure according to claim 1, wherein a top surface of the first pad connection via structure is in the same horizontal plane as a top surface of the first proximal dielectric diffusion barrier layer.

4. The structure according to claim 1, wherein each first bonding pad of the first bonding pads comprises: A first bonding pad liner containing a metal nitride material; And Copper containing a first metal pad filling material portion embedded in the bonding pad liner.

5. The structure according to claim 4, wherein: The first dielectric diffusion barrier portions are interconnected through a first horizontally extending diffusion barrier portion covering the first pad level dielectric material layer; and A top surface of the first bonding pad is in a horizontal plane including a top surface of the first horizontally extending diffusion barrier portion.

6. The structure according to claim 4, wherein: the first dielectric diffusion barrier portion is a discrete material portion laterally spaced apart from each other by the first pad-level dielectric material layer; and the top surface of the first bonding pad lies in a horizontal plane including the top surface of the first pad-level dielectric material layer.

7. The structure according to claim 1, wherein: the first dielectric diffusion barrier portion comprises a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and the first proximal dielectric diffusion barrier layer comprises a dielectric material selected from silicon nitride, silicon oxynitride, or silicon carbonitride.

8. The structure according to claim 1, further comprising a second semiconductor die, the second semiconductor die comprising: a second semiconductor device located above a second substrate; a second interconnect-level dielectric material layer embedding a second metal interconnect structure electrically connected to the second semiconductor device; and a second bonding pad electrically connected to the second metal interconnect structure and bonded to a corresponding first bonding pad among the first bonding pads.

9. The structure according to claim 8, wherein: the first semiconductor device comprises a three-dimensional memory device or a driver circuit device for the three-dimensional memory device; the second semiconductor device comprises the other of the three-dimensional memory device or the driver circuit device for the three-dimensional memory device; each second bonding pad among the second bonding pads contacts a corresponding second dielectric diffusion barrier portion and is laterally surrounded thereby; the second bonding pads and the second dielectric diffusion barrier portions are embedded in a second pad-level dielectric material layer; the second semiconductor die comprises a layer stack of a second pad connection via-level dielectric material layer and a second proximal dielectric diffusion barrier layer located between the second interconnect-level dielectric material layer and the second pad-level dielectric material layer and embedding a second pad connection via structure, and each second bonding pad among the second bonding pads contacts a corresponding subgroup of the second pad connection via structure.

10. The structure according to claim 1, wherein the first semiconductor die comprises: an additional planar diffusion barrier layer located between the first interconnect-level dielectric material layer and the first pad connection via-level dielectric material layer; and at least one edge seal structure comprising a corresponding subgroup of the first metal interconnect structure, the at least one edge seal structure providing a corresponding continuous barrier layer laterally surrounding the first semiconductor device without any lateral opening and extending vertically from the first substrate to the additional planar diffusion barrier layer.

11. The structure according to claim 10, wherein the at least one edge seal structure is electrically grounded.

12. A method of forming a semiconductor structure, the method comprising forming a first semiconductor die by: forming a first semiconductor device above a first substrate; A layer stack of a first pad connection via level dielectric material layer and a first proximal dielectric diffusion barrier layer is formed over the first semiconductor device, and the layer stack embeds a first metal interconnect structure; A first pad connection via structure is formed through the layer stack over a subgroup of the first metal interconnect structure; A first pad level dielectric material layer is formed over the layer stack; A first pad cavity is formed through the first pad level dielectric material layer; A first distal dielectric diffusion barrier layer is formed in the first pad cavity and over the first pad level dielectric material layer; An opening is formed through the first distal dielectric diffusion barrier layer at a bottom portion of the first pad cavity, wherein a top surface of the first pad connection via structure is physically exposed; And A first bonding pad is formed directly on the top surface of the first pad connection via structure in a remaining volume of the first pad cavity; And Wherein the method further comprises: Forming a photoresist layer over the first distal dielectric diffusion barrier layer; Forming an opening through the photoresist layer in an area of a bottom surface of the first pad cavity by lithographically patterning the photoresist layer; and Anisotropically etching an unmasked portion of the first distal dielectric diffusion barrier layer, wherein a remaining portion of the first distal dielectric diffusion barrier layer comprises a first dielectric diffusion barrier portion; and Wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion comprises a sidewall segment that contacts the first pad level dielectric material layer and extends from a bottom surface of the first pad level dielectric material layer to a top surface of the first pad level dielectric material layer; Wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion further comprises a horizontal segment having a bottom surface that contacts a bottom surface of the first proximal dielectric diffusion barrier layer, wherein the bottom surface comprises an outer perimeter that abuts a bottom edge of the sidewall segment and an inner perimeter that is laterally offset inwardly from the outer perimeter by an offset distance that is greater than a thickness of the sidewall segment of the first dielectric diffusion barrier portion.

13. The method according to claim 12, wherein The top surface of the first pad connection via structure is physically exposed in the first pad cavity when the first pad cavity is formed; and The first distal dielectric diffusion barrier layer is deposited on the first pad level dielectric material layer and on the top surface of the first pad connection via structure.

14. The method according to claim 12, further comprising: After forming the opening through the first distal dielectric diffusion barrier layer, depositing a first bonding pad liner layer comprising a metal nitride material on the first pad connection via structure and on the first distal dielectric diffusion barrier layer; Depositing a first metal pad fill material layer on the first bonding pad liner layer; and Remove portions of the first metal pad fill material layer and the first bond pad liner layer that overlie a horizontal plane that includes the top surface of the first distal dielectric diffusion barrier layer, wherein the remaining portions of the first metal pad fill material layer and the first bond pad liner layer constitute the first bond pad.

15. The method according to claim 12 further comprises: Form a first interconnect level dielectric material layer over the first semiconductor device, the first interconnect level dielectric material layer embedding a first metal interconnect structure, wherein the first metal interconnect structure is electrically connected to the first semiconductor device, and wherein a layer stack is formed over the first interconnect level dielectric material layer.

16. The method according to claim 12, further comprising: Providing a second semiconductor die, the second semiconductor die including a second semiconductor device on a second substrate and a second pad level dielectric material layer embedding a second bond pad electrically connected to the second semiconductor device; and Bonding the second bond pad to the first bond pad.

17. A structure, the structure including a first semiconductor die, wherein the first semiconductor die includes: A first semiconductor device located over a first substrate; A first interconnect level dielectric material layer embedding a first metal interconnect structure, the first metal interconnect structure being electrically connected to the first semiconductor device and overlying the first semiconductor device; A layer stack of a first proximal dielectric diffusion barrier layer and a first pad and via level dielectric material layer, the layer stack overlying the first interconnect level dielectric material layer and embedding a first integrated pad and via structure; and A first dielectric diffusion barrier portion embedded in the first pad and via level dielectric material layer, wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion contacts and laterally surrounds a pad portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure, wherein the first semiconductor die includes at least one edge seal structure, the at least one edge seal structure including a corresponding subgroup of the first metal interconnect structure, the at least one edge seal structure providing a corresponding continuous barrier layer that laterally surrounds the first semiconductor device without any lateral openings and extends vertically from the first substrate to the first proximal dielectric diffusion barrier layer.

18. The structure according to claim 17, wherein each first dielectric diffusion barrier portion in the first dielectric diffusion barrier portion is vertically spaced apart from the first proximal dielectric diffusion barrier layer.

19. The structure according to claim 17, further comprising a tubular dielectric diffusion barrier liner that laterally surrounds a via portion of the corresponding first integrated pad and via structure in the first integrated pad and via structure.

20. The structure according to claim 19, wherein the tubular dielectric diffusion barrier liner does not contact the first dielectric diffusion barrier portion and is laterally spaced apart therefrom.

21. The structure according to claim 20, wherein the tubular dielectric diffusion barrier liner contacts sidewalls of corresponding openings in the first proximal dielectric diffusion barrier layer.

22. The structure according to claim 20, wherein: the first proximal dielectric diffusion barrier layer contacts a top surface of a subgroup of the first metal interconnect structures and a topmost surface of the first interconnect level dielectric material layer; and the via portion of the first integrated pad and via structure contacts a horizontal surface of the subgroup of the first metal interconnect structures.

23. The structure according to claim 17, wherein each first integrated pad and via structure in the first integrated pad and via structure comprises: a first bonding pad liner comprising a metal nitride material; and copper, the copper containing a first metal pad fill material portion partially embedded in the first bonding pad liner.

24. The structure according to claim 23, wherein: the first dielectric diffusion barrier portions are interconnected with each other through a first horizontally extending diffusion barrier portion covering the first pad and via level dielectric material layer; and a top surface of the first integrated pad and via structure lies in a horizontal plane including a top surface of the first horizontally extending diffusion barrier portion.

25. The structure according to claim 23, wherein: the first dielectric diffusion barrier portions are discrete material portions laterally spaced apart from each other by the first pad and via level dielectric material layer; and a top surface of the first integrated pad and via structure lies in a horizontal plane including a top surface of the first pad and via level dielectric material layer.

26. The structure according to claim 17, wherein the first bonding pad liner in each first integrated pad and via structure within the first integrated pad and via structure continuously extends from a top surface of a corresponding first metal interconnect structure in the first metal interconnect structures to a horizontal plane including a topmost surface of the first dielectric diffusion barrier portion, and directly contacts a horizontal surface of the first pad and via level dielectric material layer within a region of an opening passing through the corresponding first dielectric diffusion barrier portion in the first dielectric diffusion barrier portions.

27. The structure according to claim 17, wherein: the first dielectric diffusion barrier portion comprises a dielectric material selected from silicon nitride, silicon oxynitride, or a stack thereof; and the first proximal dielectric diffusion barrier layer comprises a dielectric material selected from silicon nitride, silicon oxynitride, or silicon carbonitride.

28. The structure according to claim 17, further comprising a second semiconductor die, the second semiconductor die comprising: a second semiconductor device located above a second substrate; a second interconnect level dielectric material layer embedding second metal interconnect structures, the second metal interconnect structures being electrically connected to the second semiconductor device; and a second bonding pad electrically connected to the second metal interconnect structures and bonded to a corresponding first integrated pad and via structure in the first integrated pad and via structures.

29. The structure according to claim 28, wherein: the first semiconductor device includes a three-dimensional memory device or a driver circuit device for the three-dimensional memory device; the second semiconductor device includes the other of the three-dimensional memory device or the driver circuit device for the three-dimensional memory device; each second bonding pad among the second bonding pads contacts a corresponding second dielectric diffusion barrier portion and is laterally surrounded thereby; the second dielectric diffusion barrier portion and the second bonding pads are embedded in a pad-level dielectric material layer; and the first pad, the via-level dielectric material layer, and the pad-level dielectric material layer do not contact each other and are vertically spaced apart from each other by at least one horizontally extending diffusion barrier portion that laterally connects the first dielectric diffusion barrier portion or laterally connects the second dielectric diffusion barrier portion.

30. A method of forming a semiconductor structure, the method comprising forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a first interconnect-level dielectric layer embedding a first metal interconnect structure over the first semiconductor device; forming a first proximal dielectric diffusion barrier layer, a first pad, and a via-level dielectric material layer over the first semiconductor device; forming a first integrated pad and via cavity through the first pad and via-level dielectric material layer; forming a first distal dielectric diffusion barrier layer in the first integrated pad and via cavity and over the first pad and via-level dielectric material layer; removing a horizontal portion of the first distal dielectric diffusion barrier layer within the region of the first integrated pad and via cavity, wherein the top surface of a subgroup of the first metal interconnect structure is physically exposed; and forming a first integrated pad and via structure in the remaining volume of the first integrated pad and via cavity; and wherein the first semiconductor die includes at least one edge-sealing structure, the at least one edge-sealing structure includes a corresponding subgroup of the first metal interconnect structure, and the at least one edge-sealing structure provides a corresponding continuous barrier layer that laterally surrounds the first semiconductor device without any lateral opening and extends vertically from the first substrate to the first proximal dielectric diffusion barrier layer.

31. The method according to claim 30, further comprising: forming a photoresist layer over the first distal dielectric diffusion barrier layer; forming an opening through the photoresist layer in a region of the bottom surface of the first integrated pad and via cavity by lithographically patterning the photoresist layer; and and anisotropically etching an unmasked portion of the first distal dielectric diffusion barrier layer by performing an anisotropic etching process.

32. The method according to claim 31, wherein the remaining portion of the first distal dielectric diffusion barrier layer after the anisotropic etching process includes: a first dielectric diffusion barrier portion formed on sidewalls of a pad cavity portion of the first integrated pad and via cavity; and A first tubular dielectric diffusion barrier liner formed on sidewalls of the first integrated pad and a via cavity portion of the via cavity that is below the pad cavity portion.

33. The method of claim 30, wherein a top surface of the subgroup of the first metal interconnect structures is physically exposed to the first integrated pad and the via cavity when forming the first integrated pad and the via cavity; and the first distal dielectric diffusion barrier layer is deposited on the first pad and via level dielectric material layer and on the top surface of the subgroup of the first metal interconnect structures.

34. The method of claim 30, further comprising: after removing the horizontal portion of the first distal dielectric diffusion barrier layer, depositing a first metal liner layer comprising a metal nitride material on the subgroup of the first metal interconnect structures and on the remaining portion of the first distal dielectric diffusion barrier layer; depositing a first metal pad fill material layer on the first metal liner layer; and removing portions of the first metal pad fill material layer and the first metal liner layer that overlie a horizontal plane including a top surface of the first distal dielectric diffusion barrier layer, wherein remaining portions of the first metal pad fill material layer and the first metal liner layer constitute the first integrated pad and via structure.

35. The method of claim 30, further comprising: providing a second semiconductor die including a second semiconductor device on a second substrate and a second pad level dielectric material layer embedding and electrically connecting to a second bond pad of the second semiconductor device; and bonding the second bond pad to the first bond pad.

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