A three-dimensional stacked integrated circuit using an immersion cooling method based on a semiconductor package and an open via interposer

Abstract

This application discloses a three-dimensional stacked integrated circuit, wherein a package having a semiconductor chip and an interposer substrate having an opening are alternately stacked through their respective electrode terminals and electrode pads. The package and the interposer substrate have electrode terminals with shapes that create gaps between the electrode terminals in the stacking direction and between the electrode terminals when stacked, electrode pads for connecting the electrode terminals, and guide holes for maintaining accurate positioning and connection during stacking. An interlayer communication path is formed through the connection between the package and the interposer substrate, and immersion cooling is performed by allowing coolant to flow in the gaps.

Description

Technical Field

[0001] This invention relates to a three-dimensional stacked integrated circuit with refrigerant-based cooling function and a cooling method for the three-dimensional stacked integrated circuit. Background Technology

[0002] There are mounting technologies for semiconductors with three-dimensional stacks. For example, the applicant disclosed a three-dimensional stacked integrated circuit, which has an interposer layer between each integrated circuit and below the bottom integrated circuit, and a refrigerant movement path is provided in each of the multiple interposer layers, and the multiple refrigerant movement paths provided in the multiple interposer layers are interconnected (see Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2019 / 146724 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] Originally, even when inserted between stacked semiconductors, heat sinks cannot function effectively. Extending the metal plate laterally for heat dissipation would result in excessive thermal resistance. Although it is a metal, the thermal resistance (Ψjt) is proportional to the thermal conductivity distance of the metal, Tj = Ψjt × P + Tcl (Tj is the junction temperature, Ψjt is the thermal resistance, P is the power consumption, and Td is the ambient temperature). When Ψjt increases, no power consumption is applied.

[0008] Figure 15 This is a cross-sectional view showing how heat is transferred after a heat sink is placed on a heat-generating semiconductor chip. The entire semiconductor chip becomes the heat-generating body, but to illustrate the heat transfer towards the heat sink, the heat-generating portion is designated as point heat sources A, B, and C. Heat flows from the point heat sources in a hemispherical shape relative to the heat sink (due to...). Figure 15 It is a sectional view, so it is represented by a semicircle.

[0009] Heat propagates concentrically from the central heating point B. However, due to the presence of heat from the heating points A or B located to the left and right, the thermal resistance in the lateral direction is high, resulting in almost no heat propagation. On the other hand, due to the lower thermal resistance in the upward direction, heat sink B and the surrounding heat sinks function effectively.

[0010] On the other hand, at heating point A, the heat from the central heating point B creates a greater thermal resistance to the right, causing the heat to propagate upwards and to the left. Similarly, at heating point C, the heat from the central heating point B creates a greater thermal resistance to the left, causing the heat to propagate upwards and to the right.

[0011] Since the heat sink releases heat to the outside with a surface area larger than that of the heat-generating element, it is large enough compared to the semiconductor chip. Therefore, there is no heat source to the left of heat-generating point A and to the right of heat-generating point C, resulting in low thermal resistance. Thus, heat dissipation through the surface area of ​​the heat sink itself is sufficient. There is a possibility that the outer edge of heat sink A or heat sink C may not be effectively utilized.

[0012] Furthermore, in order to maximize the effectiveness of a heat sink, such as heat sink B, which is located directly above the semiconductor chip that serves as the heat source, as long as... Figure 16 That would simply make the heat sink thinner, bringing the heat-generating point closer to the heat sink fins. However, if the heat sink is made thinner, its thermal resistance increases, making it difficult to conduct heat from the heat-generating point to the heat sink fins above. Therefore, this would be putting the cart before the horse.

[0013] Therefore, regardless of whether the heat sink is thick or thin, especially when the semiconductor chip is not housed in a BGA package and is instead immersed in a three-dimensional structure, the effectiveness of the heat sink is questionable even if it is sandwiched between the semiconductor chips.

[0014] In the efficient method of immersion-based three-dimensional semiconductors (three-dimensional mounting of high-heat-generating computing circuits such as CPUs and GPUs) based on FC-BGA packages with electrode pads on the surface, without the aforementioned three-dimensional TSV process, immersion is performed directly without installing heat sinks. The semiconductor substrate bottom (the part opposite the circuit mounting part of the semiconductor, cut as thin as possible) is directly immersed (in this case, the FC part is sealed with bottom filler), or a composite is coated and immersed with a thin package metal with good thermal conductivity. W = J / s, therefore, the refrigerant is pressurized to obtain m 2 / s (because the surface area of ​​a semiconductor is 1cm) 2 The effective surface area is approximately 1 / s, therefore, for example, if boiling heat dissipation is taken as the premise, then one square centimeter is less than 10 times the effective surface area. Therefore, using 10cm² as an example... 2 (A flow rate of / s is sufficient), only the surface area flow rate of the necessary effective surface area needs to be set.

[0015] For example, when the refrigerant is a liquid fluoride, it is approximately 0.5 W / cm². 2 The thermal conductivity is given by ℃, but if the above formula is rearranged, then P = (Tj - Tcl) x 1 / Ψjt. Therefore, if Tj is 85℃, then with the boiling point of the fluoride liquid being 56℃, Tj - Tcl results in a temperature difference of 29℃. However, when P becomes 58W, for example, 200W, 1cm 2With a CPU, a flow rate of approximately 4 cm / s can be compressed to make it flow.

[0016] In semiconductors, 1 kW at 1 cm 2 In the case of GPGPUs, a flow rate of approximately 20 cm / s and boiling cooling would be sufficient. This is certainly a groundbreaking statement; even in a supercomputer formed by stacking 10 layers of 1kW GPGPUs, immersion cooling with a flow rate of approximately 20 cm / s applied laterally to all layers would be adequate. This is commonly used in applications such as laser oscillators and is not particularly unique.

[0017] According to the present invention, when stacking an FC-BGA package having electrode pads on its surface, by inserting an open-hole interposer substrate, space for accommodating the stacked ceramic capacitor can be ensured on the back side (the hole portion) of the semiconductor of the FC-BGA package having electrode pads on its surface, and space can be ensured to stably guarantee the required flow rate.

[0018] Current technology treats a three-dimensional semiconductor as a single unit, focusing on the flow path of the coolant used to cool the semiconductor within it. However, it does not consider where to place the ceramic capacitors to enable the operation of high-current-consuming semiconductor chips such as CPUs (Central Processing Units), GPGPUs (General-purpose computing on graphics processing units), BBUs (Base Band Units), and supercomputer cores. Although placing ceramic capacitors on the top or bottom of the three-dimensional semiconductor is considered, for the central layer semiconductor chip, the power supply path through each layer becomes longer, resulting in increased impedance and making it impossible to supply high current to the semiconductor chip.

[0019] This invention is a proposal to eliminate the defects of reference WO2019 / 146724, in which the BGA (Ball Grid Array) terminals of the circuit from each layer of the semiconductor package substrate (also known as FC-BGA (Flip Chip-Ball Grid Array) substrate) carrying the processor to the ceramic capacitor are removed, and ceramic capacitors are installed on each layer of the semiconductor package substrate, thereby reducing the impedance of the circuit and enabling high current supply, and three-dimensional cooling is achieved by impregnation.

[0020] General Public

[0021] In reference WO2019 / 146724, by overlapping an FC-BGA package with electrode pads on the surface, the gap between the ceramic capacitor at the bottom of the package and the heat sink at the top of the package becomes narrower, and even if impregnation is performed, there is a risk that the flow rate cannot be expected.

[0022] In this invention, an apparatus and method are proposed for constructing an impregnated three-dimensional computing device by inserting a substrate with pads and BGA electrodes on the top and bottom, which is not equipped with semiconductor chips, into a heat sink portion of the substrate. This substrate has a pad and BGA electrode with a quadrilateral hole, and the BGA electrode is electrically connected to the heat sink portion. This ensures the spacing between the ceramic capacitor and the heat sink, thereby ensuring the flow rate of the impregnating Fluorinert liquid and the space for placing the ceramic capacitor in the lower part of the BGA package. This process does not significantly change the existing FC-BGA package configuration.

[0023] (1) A three-dimensional stacked integrated circuit, wherein the impregnation process involves alternately stacking a package containing a semiconductor chip and an interposer substrate having an opening at the location where the semiconductor chip is mounted, using their respective electrode terminals and electrode pads, wherein,

[0024] The package and the interposer substrate are shaped such that gaps are created between them in the stacking direction through the electrode terminals on the lower surface.

[0025] The upper surfaces of the package and the interposer substrate are provided with electrode pads of geometric shape for connecting the electrode terminals.

[0026] The electrode terminals and electrode pads of the package and the interposer substrate are electrically connected vertically in a 1:1 ratio.

[0027] The package and the interposer substrate are provided with guide holes for accurate positioning and maintaining connection during stacking.

[0028] Through the connection between the package and the interposer substrate, an interlayer communication path is formed by the electrode terminals and electrode pads.

[0029] Immersion cooling is performed by allowing coolant to flow through the gaps created between the electrode terminals of the package and the interposer substrate.

[0030] (2) According to the three-dimensional stacked integrated circuit described in (1) above, multiple interlayer substrates inserted between the packages are continuously inserted.

[0031] (3) According to the three-dimensional stacked integrated circuit described in (1) or (2) above, the semiconductor chip mounted in the package is a stacked three-dimensional semiconductor with two or more layers (HBM, i.e., High Bandwidth Memory or Wide I / O DRAM, etc.).

[0032] (4) According to any one of (1) to (3) above, the three-dimensional stacked integrated circuit is a NUMA (Non-Uniform Memory Access) structure formed by cross-connection, and the interconnection of the packages is a bus connection.

[0033] (5) In any one of (1) to (4) above, the three-dimensional stacked integrated circuit has the vias serving as electrodes for supplying power to the semiconductor chip mounted on the package and the vias also serving as electrodes for supplying power to the semiconductor chip mounted on the package. In order to reduce impedance so as to supply power directly to the ceramic capacitor mounted on the package, two vias are provided adjacent to each other.

[0034] (6) According to any one of (1) to (5) above, the data transmission mode of the interlayer communication path formed by the electrode terminals and electrode pads is set to LVD (Low Voltage Differential) with two adjacent electrode terminals as a pair.

[0035] (7) According to any one of (1) to (5) above, the data transmission mode of the interlayer communication path formed by the electrode terminals and electrode pads is set to PCI Express (External Component Interconnect High Speed) with two adjacent electrode terminals as a pair.

[0036] (8) The three-dimensional stacked integrated circuit described in (7) uses a clock-up PCI Express.

[0037] (9) In order to reduce the adverse effects of reflection of high-frequency signals flowing in the interlayer communication path, a bidirectional tri-state gate driver is mounted adjacent to the electrode terminals of the package in the three-dimensional stacked integrated circuit according to any one of (1) to (8) above.

[0038] (10) In the three-dimensional stacked integrated circuit according to any one of (1) to (9) above, in order to prevent cavitation based on intermittent boiling during immersion cooling, the heat sink that is in close contact with the semiconductor chip mounted on the package is sintered metal or metal oxide.

[0039] (11) A three-dimensional stacked integrated circuit, wherein,

[0040] The bottom layer of the three-dimensional stacked integrated circuit described in (1) to (10) above is composed of a bus driver switch or a bus driver buffer switch of DMA with address bus snooping and buffer in page units.

[0041] Invention Effects

[0042] According to the present invention, since immersion cooling can be performed while ensuring isolation on the back side of each layer of the semiconductor package substrate carrying the processor to ensure the gap for mounting ceramic capacitors, the impedance of the circuit can be reduced and a large current can be supplied. Attached Figure Description

[0043] Figure 1 This is a perspective view of three layers stacked and combined in a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0044] Figure 2 This is a perspective view showing the overlap between an FC-BGA package with electrode pads on its surface and an open-hole interposer substrate in a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0045] Figure 3 This is a perspective view of the surface of an FC-BGA package having electrode pads on its surface, as an example of this embodiment.

[0046] Figure 4 This is a perspective view of the back side of an FC-BGA package having electrode pads on its surface, as an example of this embodiment.

[0047] Figure 5 This is a schematic diagram of a bidirectional tri-state gate driver and circuit of an FC-BGA package having electrode pads on its surface, as an example of this embodiment.

[0048] Figure 6 This is a schematic diagram of the internal and external circuitry of the bidirectional tri-state gate driver.

[0049] Figure 7 This is a schematic diagram of a bidirectional tri-state gate drive circuit.

[0050] Figure 8 This is a perspective view showing a structure in an FC-BGA package with electrode pads on the surface, in which a heat sink covers a semiconductor chip, as an example of this embodiment.

[0051] Figure 9 This is a cross-sectional view showing a structure in an FC-BGA package with electrode pads on the surface, in which a heat sink covers a semiconductor chip, as an example of this embodiment.

[0052] Figure 10 This is a perspective view of the surface of an open-hole interposer substrate, which is an example of this embodiment.

[0053] Figure 11 This is a perspective view of the back side of an open-hole interposer substrate, which is an example of this embodiment.

[0054] Figure 12 This is a schematic diagram of an inter-layer communication path in a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0055] Figure 13 This is a schematic diagram of the interlayer communication path of a bidirectional tri-state gate driver of a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0056] Figure 14 This is a diagram showing a semiconductor chip with thickness mounted in a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0057] Figure 15 This is a schematic diagram of heat transfer from a semiconductor chip to a heat sink.

[0058] Figure 16 This is a schematic diagram showing the heat from a semiconductor chip spreading to a thinner heat sink.

[0059] Figure 17 This is a side view showing the mounting location of a bidirectional tri-state gate driver in a three-dimensional stacked integrated circuit, which is an example of this embodiment.

[0060] Figure 18 It is a diagram that represents the names of communication paths in a bus connection method. Detailed Implementation

[0061] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention will be described through embodiments, but the following embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily necessary for the solution of the invention.

[0062] In the three-dimensional stacked integrated circuit of this embodiment shown in the figure, an FC-BGA package with electrode pads on its surface and one or more open-hole interposer substrates thereon are collectively arranged as one layer, while the FC-BGA package with electrode pads on its uppermost surface is arranged as a separate layer. Furthermore, the FC-BGA package is an example of a package having terminals with a shape that creates gaps between the electrode terminals in the stacking direction when connected to the lower substrate, and the electrode pads are an example of pads with a geometric shape. Additionally, BGA electrodes, etc., are examples of electrode terminals with a shape that creates gaps between the electrode terminals in the stacking direction. Furthermore, in each figure, portions labeled with the same reference numerals have the same or identical structures.

[0063] Reference Figure 1 as well as Figure 2 The following describes this implementation method. Figure 1 This is a perspective view of this embodiment. Figure 2 This is a perspective view showing the stacked structure of this embodiment.

[0064] (BGA, gaskets, interlayer communication paths, immersion cooling)

[0065] In reference WO2019 / 146724, by overlapping an FC-BGA package with electrode pads on its surface, the gap between the ceramic capacitor at the bottom of the package and the heat sink at the top of the package becomes narrower. Even with impregnation, there is a risk that the current flow cannot be expected. Alternatively, there is a risk that interference may occur, preventing overlapping.

[0066] This invention proposes an apparatus and method for constructing an impregnated three-dimensional computing device by inserting, in a manner similar to wooden clogs used in a hot tub, a substrate with pads and BGA electrodes on the top and bottom, and with quadrilateral holes, through which the BGA electrodes, which originally housed the IC and heat sink, are electrically connected. This ensures the spacing between the ceramic capacitor and the heat sink, thereby ensuring the flow rate of the impregnating Fluorinert liquid and the space for placing the ceramic capacitor in the lower part of the BGA package. This allows for the construction of an impregnated three-dimensional computing device without significantly altering the existing FC-BGA package.

[0067] In this embodiment, such as Figure 1 As shown, it is constructed by stacking an FC-BGA package 110 with electrode pads on the surface and an open-hole interposer substrate 120 on which a semiconductor chip 100 is mounted.

[0068] (Multiple pads can be used consecutively).

[0069] The perforated interlayer substrate 120 is a substrate used to regulate the flow of refrigerant and to isolate the upper and lower layers. It can also be a single substrate or multiple substrates stacked continuously.

[0070] (Features both electrode and guide hole)

[0071] The FC-BGA package 110 with electrode pads on its surface and the open-hole interposer substrate 120 are designed to supply power to the ceramic capacitor 350 under low impedance conditions, such as... Figure 3 and Figure 10 As shown, a power supply electrode 240 having an anode for raising the guide pin and a power supply electrode 250 having a cathode for raising the guide pin are provided adjacent to each other.

[0072] (Inter-layer communication is LVD)

[0073] like Figure 11 As shown, in this embodiment, the three-dimensional stacked integrated circuit forms an interlayer communication path by bonding electrode pads 140 to electrode terminals 340. The communication path connecting multiple layers is designated as a local bus 420. Signal reflection issues are mitigated by using pairs of adjacent electrode terminals and driving the local bus 420 with LVD (Low Voltage Differential).

[0074] (Inter-layer communication is PCI Express)

[0075] In the communication mode of the local bus 420, two adjacent electrode terminals can also be used in pairs to adopt the PCI Express standard.

[0076] (PCI Express with increased inter-layer communication frequency)

[0077] In the communication mode of the local bus 420, the PCI Express standard, which uses two adjacent electrode terminals in pairs and increases the frequency, can also be used. In this case, since inter-layer communication is turned off in this system, clock tuning can be performed freely without regard to the following list.

[0078] In addition, for reference, the following represents the PCI Express revision, the physical layer transmission bandwidth per link width / one-way (in gigabit per second (GT / sec)).

[0079] Gen1 2.5GT / sec

[0080] Gen2 5GT / sec

[0081] Gen3 8GT / sec

[0082] Gen4 16GT / sec

[0083] Gen5 32GT / sec

[0084] Gen6 64GT / sec

[0085] (A bidirectional tri-state gate driver is attached next to the local bus that is coupled between layers via BGA balls)

[0086] In the aforementioned local bus 420, to prevent adverse effects caused by reflections from the leads within each layer formed in a comb shape, such as... Figure 17 As shown, bidirectional tri-state gate drivers 130 are provided at each layer's electrode terminals 340 or adjacent to the electrode pads 140 and spaced apart from each other. The bidirectional tri-state gate drivers ensure that reflections of interlayer communication signals remain within the vertical interconnect range of the BGA balls formed by the interposer layers. Therefore, further clock tuning is possible.

[0087] (Sintered metal or oxide metal is used in the radiator for boiling cooling)

[0088] like Figure 8 and Figure 9 As shown, the semiconductor chip 100 is covered by a heat sink 260, which is sealed using a composite material with high thermal conductivity. While typical VLSIs have heat sink fins on top of the heat sink, both the previous and current inventions involve direct impregnation, necessitating consideration of preventing intermittent boiling on the heat sink surface. The heat sink 260 is characterized by having a surface of metal oxide or sintered metal to prevent cavitation caused by intermittent boiling.

[0089] (The bus driver switch at the bottom layer)

[0090] The lowest layer of this embodiment may not simply relay the local bus 420 and external peripheral devices, but may be a bus driver switch or a bus driver buffer switch for DMA with address bus snooping and buffers, which is implemented on a page-by-page basis.

[0091] (Characteristics of open-hole interposer substrates)

[0092] Figure 10 The shown open-hole interposer substrate 120 includes: a centrally located opening 270; geometrically shaped electrode pads 140 for bonding electrode terminals 340 of the FC-BGA package 110 or the open-hole interposer substrate 120 stacked on the upper surface and having electrode pads on the surface; and as shown in the figure. Figure 11The electrode terminal 340 on the back side is shown. The electrode pad 140 on the surface is electrically connected to the electrode terminal 340 on the back side in a 1:1 ratio. Furthermore, a power supply electrode 240 is provided for the anode of the through hole for erecting the guide pin, and a power supply electrode 250 is provided for the cathode of the through hole for erecting the guide pin.

[0093] (A bidirectional tri-state gate driver is located next to the semiconductor chip)

[0094] Figure 5 This is a simplified diagram showing a portion of the internal circuitry of an FC-BGA package 110 with surface electrode pads. To illustrate the circuitry, [the diagram is shown in the original text]. Figures 1 to 3 Compared to the FC-BGA package 110 with electrode pads on its surface, a portion of the appearance is omitted, but the same structure is shown. (See also...) Figure 5 As shown, the FC-BGA package 110 with electrode pads on its surface has a bidirectional tri-state gate driver 130 near the electrode pads 140 or the electrode terminals 340.

[0095] The FC-BGA package 110, which has electrode pads on its surface, includes, in addition to the semiconductor 100, a bidirectional tri-state gate driver 130, electrode pads 141 to 145, a gate control signal line 600, and data signal lines 610 to 611. Furthermore, in... Figure 5 In this embodiment, seven electrode terminals, one gate control signal line, and two data control signal lines are used as an example, but it is not limited to this. There can be one or more electrode terminals, one or more gate control signal lines, and two or more data signal lines.

[0096] The bidirectional tri-state gate driver 130 controls the direction of the signals flowing in the data signal lines 610 and 611 based on the signals from the gate control signal line 600 of the semiconductor chip 100.

[0097] Figure 6 This is a schematic diagram illustrating the circuitry of the bidirectional tri-state gate driver 130. The bidirectional tri-state gate driver 130 is composed of a tri-state buffer. The bidirectional tri-state gate driver becomes... Figure 7 The circuit structure is shown. When the gate control signal line 710 is "1", the tri-state buffer 731 causes the signal on the data signal line 720 to flow in the direction of the data signal line 721. At this time, "0" is transmitted through the NOT circuit 730 in the tri-state buffer 732, thus becoming a high impedance. Therefore, the data signal flows from left to right. Conversely, when the gate control signal line 710 is "0", the tri-state buffer 731 becomes a high impedance, and "1" is transmitted through the NOT circuit 730 in the tri-state buffer 732, so the data signal flows from the data signal line 721 to the data signal line 720 (from right to left).

[0098] (Characteristics of FC-BGA packages with surface electrode pads: having electrodes that also serve as guide holes)

[0099] like Figure 3 As shown, the FC-BGA package 110 with electrode pads on its surface includes: a semiconductor chip 100; geometrically shaped electrode pads 140 for bonding electrode terminals 340 of the FC-BGA package 110 or the open-hole interposer substrate 120 stacked on the upper surface; a power supply electrode 240 for the anode of the through-hole for erecting the guide pin; and a power supply electrode 250 for the cathode of the through-hole for erecting the guide pin.

[0100] FC-BGA package 110 with electrode pads on its surface, such as Figure 4 As shown, by inserting the aperture interposer substrate shown in this invention, a ceramic capacitor 350 can be provided on the back side of the FC-BGA package 110, which has electrode pads on its surface, as in the past.

[0101] (Cooling is performed by immersion boiling cooling)

[0102] In this embodiment, by performing boiling cooling using an immersion solution such as Fluorinert, it is also possible to cool semiconductors up to 100W.

[0103] (The effect of this implementation method: the use of guide pins makes the alignment during stacking more precise)

[0104] like Figure 1 As shown, in this embodiment, it is necessary to accurately position and bond the electrode terminals 340 and electrode pads 140 of the stacked FC-BGA package 110 or open-hole interposer substrate 120, which have electrode pads on their surfaces. Therefore, by inserting the power supply electrode 280 (anode) and the power supply electrode 290 (cathode) of the guide pin into the through-hole (anode) power supply electrode 240 (cathode) and the through-hole (cathode) power supply electrode 250 (cathode) of the FC-BGA package 110 or open-hole interposer substrate 120, which have electrode pads on their surfaces, the electrode pads 140 and electrode terminals 340 can be accurately positioned during stacking.

[0105] (The effect of this implementation: By having ceramic capacitors in each layer, it is possible to supply a large current to the semiconductor chip.)

[0106] like Figure 4As shown, the FC-BGA package 110 with electrode pads on its surface can have a ceramic capacitor 350 on the back side of the semiconductor of the FC-BGA package 110 with electrode pads on its surface. Therefore, by having ceramic capacitors on each layer to enable the operation of semiconductor chips that consume high current, such as CPUs, GPGPUs, BBUs, and supercomputer cores, the power supply path can be minimized by not using the electrode terminals 340, and high current power supply can be provided while suppressing impedance.

[0107] (The effect of this embodiment: sufficient refrigerant can be ensured by the opening of the perforated interlayer substrate and the multilayer stacking.)

[0108] like Figure 10 As shown, the through-hole interposer substrate 120 in this embodiment has an opening 270. By mounting electrode terminals 340 and stacking them on the FC-BGA package 110 with electrode pads on its surface, space above and around the semiconductor chip 100 can be ensured. Therefore, the refrigerant flowing in from the gaps between the electrode terminals 340 can ensure the required capacity for cooling the semiconductor chip 100.

[0109] When the cooling capacity around the semiconductor chip 110 is insufficient when the aperture interposer substrate 120 is a single sheet, stacking two or three aperture interposer substrates in multiple layers can ensure more space above and around the semiconductor chip 110.

[0110] (Two-layered structure within a layer)

[0111] The semiconductor chip 100 placed within the FC-BGA package 110 with electrode pads may not be a single layer, but rather two or more layers. The packages of the three-dimensional stacked integrated circuit in this embodiment may also be cross-connected NUMA (Non-Uniform Memory Access) structures. The interlayer connections are constrained by the number of pins and thus become bus connections.

[0112] (To illustrate the effectiveness of this implementation method, two inter-layer communication paths will be explained.)

[0113] The three-dimensional stacked integrated circuit in this embodiment is achieved by making... Figure 2 The electrode pad 140 shown is coupled to the electrode terminal 340, as shown. Figure 12 As shown, an inter-layer communication path is formed for communicating with other layers stacked on top of each other. The inter-layer communication path includes a communication path connecting a layer to its adjacent layer in a 1:1 ratio (hereinafter referred to as a "layer skipping connection"), and as shown... Figure 13 The two types of communication paths (hereinafter referred to as "local bus") are shown as follows: one branching out from a certain layer in a comb-like manner and connecting to each layer.

[0114] (No problem in 1:1 skip connections)

[0115] Figure 12 The skip-level connection 430 shown (a local connection that links two adjacent CPUs / GPGPUs to level 2 or level 3 caches or local memory) is located horizontally in... Figure 5 The data signal lines 640 within the FC-BGA package 110 shown have electrode pads on their surface, and in the vertical direction Figure 2 The electrode pad 140 and electrode terminal 340 are coupled as shown. The path of the jumper connection 430 is P2P (Point to Point), with no branches and a 1:1 ratio between the start and end points. Therefore, reflection occurs, but there are no special signal reflection problems such as slight overlap of reflected waves.

[0116] (There is a signal reflection problem in the local bus)

[0117] On the other hand, regarding Figure 12 as well as Figure 13 The local bus 420 shown is configured to couple multiple layers in parallel, with horizontal connections... Figure 5 The data signal lines 610 and bidirectional tri-state gate drivers 130 within the FC-BGA package 110, which has electrode pads on its surface, are shown in the diagram. In the vertical direction, they are composed of... Figure 2 The electrode pads 140 and electrode terminals 340 shown are configured as follows. At this time, since the communication path is coupled not only vertically to the electrode terminals and electrode pads 140, but also contains signal lines in each FC-BGA package connected horizontally within the semiconductor chip 110, a comb-shaped circuit is formed, resulting in a complex signal reflection pattern, which becomes a problem.

[0118] (Reasons for reducing the adverse effects of reflection)

[0119] Figure 18 This is a schematic diagram of a typical bus circuit. In this embodiment, the central main bus in the comb-shaped bus circuit... Figure 13 The communication path is a vertical path formed by electrode terminals and electrode pads. Then, the communication path from the main bus to the horizontally extending element that receives signals (in this embodiment, the bidirectional tri-state gate driver 130) is called a stub. Without the bidirectional tri-state gate driver 130, in... Figure 13The high-frequency signal flowing in the main bus has the characteristic of being reflected at the endpoints of each communication path. However, this causes the reflected signal within the stub to return to the main bus and mix with the original signal. The more stubs there are, the more times the signal is reflected. When reflected waves from multiple stubs overlap poorly, the signal wave becomes too large, posing a risk of malfunction. Therefore, by minimizing the stub length by placing the bidirectional tri-state gate driver 130 adjacent to the electrode terminals, the problem caused by reflection is suppressed by approaching a single communication path rather than a comb-like structure.

[0120] (The effect of this implementation is that the comb-like diffuse reflection problem is solved by driving it with a bidirectional tri-state gate driver)

[0121] Therefore, such as Figure 5 As shown, a bidirectional tri-state gate driver 130 is configured to suppress signal reflection only in the vertical direction, without affecting the communication path in the horizontal direction. Furthermore, by using pairs of adjacent terminals, such as electrode pads 141 and 142, and driving with LVD (Low Voltage Differential) for asynchronous transmission on a pair-by-pair basis, the signal reflection problem is mitigated. Therefore, the system utilizing this embodiment can perform high-speed operation without serious malfunctions simply by ensuring consistent line lengths for the inter-layer communication paths. Alternatively, the PCI Express standard can be used in inter-layer communication. In cases where communication speed is insufficient, a higher frequency version of the PCI Express standard can be used.

[0122] (The effect of this implementation method: summarization of inter-layer communication paths: enables high-speed communication)

[0123] Therefore, the impact of signal reflection in the inter-layer communication path is minimized, enabling high-speed and stable local bus connections. Specifically, this involves the flexible use of common inter-processor bus technologies.

[0124] (Semiconductors include HBM in addition to CPUs.)

[0125] The semiconductor 100 mounted on the FC-BGA package 110 with electrode pads can be not only a computing device such as a CPU or GPGPU, but also a HBM (High Bandwidth Memory) or Wide I / O DRAM in which memory elements are vertically stacked.

[0126] Vertical stacking within HBM, but as Figure 14As shown, low-latency coupling can be further achieved in this invention by mounting on a vertically stacked FC-BGA package 110 with vertically arranged electrode pads. This can be not only the bottom layer, but also any layer. A NUMA structure is achieved by using HBM and Wide I / O DRAM connected via a jump layer as local memory. The jump-layer connected local memory described above is NUMA-connected to the local bus via the integrated circuit (CPU, GPGPU) in the internal bus of the three-dimensional integrated circuit. Throughput is improved by using the local memory, which becomes part of the NUMA structure, as a fallback region for cache memory backoff. It is used as a workgroup in case of cache failure. It is used as a secondary cache. Its use as a jump layer is as a fallback region for HBM-based cache areas. As a NUMA structure, when the page buffer is full in a multiprocessor system, if the buffer is placed in NUMA memory, the throughput is greatly improved.

[0127] (The effect of this implementation: By setting the bottom layer as an external bus driver switch, high-speed operation is possible)

[0128] The lowest layer of this implementation may not simply relay the local bus 420 and external peripheral devices, but may become a DMA with address bus snooping and buffers on a page-by-page basis.

[0129] In constructing a system using this embodiment, an external bus connection is required to connect to the main storage device, peripheral devices, etc. However, if the FC-BGA package 110 with electrode pads on its surface is set as the external bus driver switch at the bottom layer of this embodiment, the external bus can be electrically disconnected. By setting the external bus driver switch to high impedance, the signal propagation distance becomes extremely short when the external bus connected to this embodiment is disconnected, thus enabling the high-speed clock operation of this embodiment. Furthermore, since the signal is a non-terminated connection, it operates in a manner that takes signal reflection into account, similar to the PCI bus.

[0130] (The effect of this embodiment: improving cooling efficiency by making the surface of the semiconductor chip a metal oxide or sintered metal)

[0131] Boiling cooling achieves cooling by changing the refrigerant from a liquid phase to a gas phase. In boiling cooling, generating as much gas (bubbles) as possible within the refrigerant and vigorously diffusing it around the refrigerant contributes to improved cooling efficiency. Although it is difficult to predict where the bubbles will form, the probability of them forming from tiny scratches on the heat source surface is relatively high; therefore, covering with porous sintered metals or oxide metals is preferred. Thus, as... Figure 8 and Figure 9As shown, cooling efficiency is improved by making the surface of the heat sink 260 covering the semiconductor chip 100 an oxide metal or a sintered metal.

[0132] The embodiments described above are intended to facilitate understanding of the present invention and are not intended to limit the scope of the invention. The elements, configurations, materials, conditions, shapes, and dimensions of the embodiments are not limited to the examples and can be appropriately modified. Furthermore, the structures shown in different embodiments can be partially interchanged or combined with each other.

[0133] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specification, and drawings can be implemented in any order, unless explicitly stated as "before" or "preceding," or unless the output of a previous process is used in a later process. Even if terms such as "firstly" or "next" are used to describe the flow of actions in the claims, specification, and drawings for convenience, this does not mean that the actions must be performed in that order.

[0134] Explanation of reference numerals in the attached figures

[0135] 100. Semiconductor chip; 101. HBM, Wide I / O DRAM, and other stacked semiconductor chips; 110. FC-BGA package with electrode pads on the surface; 120. Open-hole interposer substrate; 130. Bidirectional tri-state gate driver; 131. Bidirectional tri-state gate driver; 132. Bidirectional tri-state gate driver; 133. Bidirectional tri-state gate driver; 140. Electrode pad; 141. Electrode pad; 142. Electrode pad; 145. Electrode pad; 240. Power supply electrode for the anode of a through-hole for erecting guide pins; 250. Power supply electrode for the cathode of a through-hole for erecting guide pins; 260. Heat sink; 270. Opening; 280. Power supply electrode for the anode of a guide pin; 290. Power supply electrode for the cathode of a guide pin; 340. Electrode terminal; 350. Ceramic capacitor; 410. One layer of this embodiment; 420, Schematic diagram of local bus; 421, main bus; 422, stub; 430, Schematic diagram of jumper connection; 560, bidirectional tri-state gate driver; 561, bidirectional tri-state gate driver; 600, gate control signal line; 610, data signal line; 611, data signal line; 640, data signal line; 700, bidirectional tri-state gate driver; 710, gate control signal line; 720, data signal line; 721, data signal line; 730, NOT circuit; 731, tri-state buffer; 732, tri-state buffer; 800, heat sink; 801, heat sink A; 802, heat sink B; 803, heat sink C; 901, heat source A; 902, heat source B; 903, heat source C.

Claims

1. A three-dimensional stacked integrated circuit, wherein the impregnation process involves alternately stacking a package containing a semiconductor chip and an interposer substrate having an opening at the location where the semiconductor chip is mounted, using their respective electrode terminals and electrode pads, wherein... The package and the interposer substrate are shaped such that gaps are created between them in the stacking direction through the electrode terminals on the lower surface. The upper surfaces of the package and the interposer substrate are provided with electrode pads of geometric shape for connecting the electrode terminals. The electrode terminals and electrode pads of the package and the interposer substrate are electrically connected vertically in a 1:1 ratio. The package and the interposer substrate are provided with guide holes for accurate positioning and maintaining connection during stacking. Through the connection between the package and the interposer substrate, an interlayer communication path is formed by the electrode terminals and electrode pads. Immersion cooling is performed by allowing coolant to flow through the gaps created between the electrode terminals of the package and the interposer substrate.

2. The three-dimensional stacked integrated circuit according to claim 1, wherein, Multiple interposer substrates are continuously inserted between the packages.

3. The three-dimensional stacked integrated circuit according to claim 1, wherein, The semiconductor chip mounted in the package is a stacked three-dimensional semiconductor with two or more layers (HBM, which stands for High Bandwidth Memory or Wide I / O DRAM, etc.).

4. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, The package is a NUMA (Non-Uniform Memory Access) structure formed by cross-connection, and the interconnection of the packages forms a bus connection.

5. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, The guide holes also function as electrodes for supplying power to the semiconductor chip mounted on the package, and in order to reduce impedance so as to directly supply power to the ceramic capacitor mounted on the package, two guide holes are provided adjacent to each other.

6. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, Using two adjacent electrode terminals as a pair, the data transmission mode of the interlayer communication path formed by the electrode terminals and electrode pads is set to LVD (Low Voltage Differential).

7. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, Using two adjacent electrode terminals as a pair, the data transmission mode of the interlayer communication path formed by the electrode terminals and electrode pads is set to PCI Express.

8. The three-dimensional stacked integrated circuit according to claim 7, wherein, Use the increased frequency of PCI Express.

9. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, To reduce the adverse effects of reflections of high-frequency signals flowing in the interlayer communication path, a bidirectional tri-state gate driver is mounted adjacent to the electrode terminals of the package.

10. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, To prevent cavitation based on intermittent boiling during immersion cooling, the heat sink that is in close contact with the semiconductor chip mounted on the package is made of sintered metal or metal oxide.

11. The three-dimensional stacked integrated circuit according to any one of claims 1 to 3, wherein, The bottom layer of the three-dimensional stacked integrated circuit consists of a bus driver switch or a DMA bus driver buffer switch with address bus snooping and buffers on a page-by-page basis.

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