Bonded memory device and method of making the same

Abstract

The present disclosure relates to forming at least a portion of a memory cell over a first substrate and forming at least a portion of a steering element or word line or bit line of the memory cell over a second substrate. The at least a portion of the memory cell is bonded to the at least a portion of the steering element or word line or bit line. At least one of the first substrate or the second substrate can be removed after bonding.

Description

[0001] Related applications

[0002] This application claims priority to the following patent applications: U.S. Nonprovisional Patent Application No. 16 / 913,717, filed June 26, 2020; and U.S. Nonprovisional Patent Application No. 16 / 913,766, filed June 26, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates in general to the field of memory devices, and more particularly to bonded memory devices and methods for manufacturing the same. Background Technology

[0004] Ferroelectric materials are materials that exhibit spontaneous polarization charges in the absence of an applied electric field. The net polarization P of the charge within a ferroelectric material is non-zero in its minimum energy state. Therefore, spontaneous ferroelectric polarization occurs, and the ferroelectric material accumulates surface charges of opposite polarities on two opposing surfaces. The polarization P of a ferroelectric material exhibits hysteresis with changes in the applied voltage V. The product of the remanent polarization and the coercive field of a ferroelectric material is a measure of its effectiveness. Ferroelectric memory devices are memory devices containing ferroelectric material for storing information. Ferroelectric materials act as memory materials in memory devices. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed with two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the lattice (such as oxygen and / or metal atom positions)) to store information within the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. Summary of the Invention

[0005] According to one aspect of this disclosure, a memory device includes a first conductive line extending laterally along a first horizontal direction, a memory pillar structure covering and contacting the first conductive line, and a second conductive line, wherein the memory pillar structure includes a single-crystal ferroelectric material plate, wherein the entire ferroelectric material is single-crystal, and the second conductive line extends laterally along a second horizontal direction and covers and contacts the memory pillar structure.

[0006] According to another aspect of this disclosure, a method of forming a memory device includes: providing a first substrate having a single-crystal semiconductor layer therein or thereon; epitaxially growing a single-crystal ferroelectric material layer on the single-crystal semiconductor layer; forming a first metal material layer on the single-crystal ferroelectric material layer to form a first layer stack including at least the single-crystal ferroelectric material layer and the first metal material layer; forming a second layer stack including a gate material layer and a second metal material layer over a second substrate; and bonding the second layer stack to the first layer stack.

[0007] According to another embodiment, a method of forming a memory device includes: providing a first component including a first substrate, the first substrate containing first conductive lines including word lines or bit lines; forming at least a portion of a memory cell above the first conductive lines; providing a second component including a second substrate, the second substrate containing second conductive lines including the other of word lines or bit lines; and bonding the first component to the second component such that the memory cell is positioned between the first conductive lines and the second conductive lines. One of the first conductive lines includes a word line or bit line of the memory cell, and one of the second conductive lines includes the other of word lines or bit lines of the memory cell.

[0008] According to another embodiment, a method of forming a memory device includes: providing a first component including at least a portion of a memory cell positioned over a first substrate, providing a second component including at least a portion of a gate element positioned over a second substrate, and bonding the first component to the second component such that the memory cell is bonded to its respective gate element. Attached Figure Description

[0009] Figure 1A This is a vertical cross-sectional view of the first substrate after a single-crystal semiconductor layer has been formed on the first substrate according to the first embodiment of the present disclosure.

[0010] Figure 1B This is a vertical cross-sectional view of an assembly comprising a first substrate after a semiconductor oxide layer has been formed on a first substrate, according to a first embodiment of the present disclosure.

[0011] Figure 1C This is a vertical cross-sectional view of an assembly comprising a first substrate after the formation of a hydrogen implantation layer and the removal of a semiconductor oxide layer, according to a first embodiment of the present disclosure.

[0012] Figure 1D This is a vertical cross-sectional view of an assembly comprising a first substrate after the formation of a single-crystal ferroelectric material layer and a first metal material layer, according to a first embodiment of the present disclosure.

[0013] Figure 2A It is along Figure 2B The vertical cross-sectional view of plane A-A' shows the second substrate after the formation of first conductive lines laterally spaced apart by first dielectric rails on the second substrate according to the first embodiment of the present disclosure.

[0014] Figure 2B yes Figure 2A A top view of the structure.

[0015] Figure 3This is a vertical cross-sectional view of an assembly of a second substrate after a lower electrode layer, a selector material layer, an upper electrode layer, and a second metal material layer have been formed on the second substrate, according to a first embodiment of the present disclosure.

[0016] Figure 4 This is a vertical cross-sectional view of a first exemplary structure after the second metal material layer has been bonded to the first metal material layer, according to a first embodiment of the present disclosure.

[0017] Figure 5 This is a vertical cross-sectional view of a first exemplary structure after removing the components of the first substrate and the proximal single-crystal semiconductor sublayer by cutting the single-crystal semiconductor layer at the hydrogen implantation layer, according to a first embodiment of the present disclosure.

[0018] Figure 6 This is a vertical cross-sectional view of a first exemplary structure after the formation of a metal capping layer, according to a first embodiment of the present disclosure.

[0019] Figure 7 This is a vertical cross-sectional view of a first exemplary structure after forming a memory column array according to a first embodiment of the present disclosure.

[0020] Figure 8A It is along Figure 8B The vertical cross-sectional view of plane A-A' shows a first exemplary structure after the formation of the dielectric isolation structure according to a first embodiment of the present disclosure.

[0021] Figure 8B yes Figure 8A A top view of the first exemplary structure.

[0022] Figure 9A It is along Figure 9B The vertical cross-sectional view of plane A-A' shows a first exemplary structure according to a first embodiment of the present disclosure after the formation of second conductive lines spaced laterally by second dielectric rails.

[0023] Figure 9B yes Figure 9A A top view of the first exemplary structure.

[0024] Figure 10A It is along Figure 10B The vertical cross-sectional view of plane A-A' shows an alternative configuration of the first exemplary structure after the formation of the second conductive lines laterally spaced apart by the second dielectric rails, according to a first embodiment of the present disclosure.

[0025] Figure 10B yes Figure 10A A top view of the first exemplary structure.

[0026] Figure 11AThis is a vertical cross-sectional view of the first substrate after a single-crystal semiconductor layer has been formed on the first substrate according to the second embodiment of this disclosure.

[0027] Figure 11B This is a vertical cross-sectional view of an assembly comprising a first substrate after the formation of a single-crystal ferroelectric material layer and a first metal material layer, according to a second embodiment of the present disclosure.

[0028] Figure 12 This is a vertical cross-sectional view of a second exemplary structure following an assembly of a second substrate, a first conductive line spaced laterally by a first dielectric rail, a lower electrode layer, a selector material layer, an upper electrode layer, and a second metal material layer, according to a second embodiment of this disclosure.

[0029] Figure 13 This is a vertical cross-sectional view of a second exemplary structure after thinning of the first substrate, according to a second embodiment of the present disclosure.

[0030] Figure 14 This is a vertical cross-sectional view of a second exemplary structure after the removal of the thinned first substrate, according to a second embodiment of the present disclosure.

[0031] Figure 15 This is a vertical cross-sectional view of a second exemplary structure after the formation of the metal capping layer, according to a second embodiment of the present disclosure.

[0032] Figure 16 This is a vertical cross-sectional view of a second exemplary structure after forming a memory column array according to a second embodiment of the present disclosure.

[0033] Figure 17A This is a vertical cross-sectional view of a second exemplary structure after the formation of a dielectric isolation structure, according to a second embodiment of the present disclosure.

[0034] Figure 17B yes Figure 17A A top view of the second exemplary structure.

[0035] Figure 18A This is a vertical cross-sectional view of a second exemplary structure after the formation of second conductive lines spaced laterally by second dielectric rails, according to a second embodiment of the present disclosure.

[0036] Figure 18B yes Figure 18A A top view of the second exemplary structure.

[0037] Figure 19 This is a vertical cross-sectional view of an alternative configuration of a second exemplary structure after the removal of the single-crystal semiconductor layer, according to a second embodiment of the present disclosure.

[0038] Figure 20AThis is a vertical cross-sectional view of an alternative configuration of a second exemplary structure after the formation of second conductive lines laterally spaced apart by second dielectric rails, according to a second embodiment of the present disclosure.

[0039] Figure 20B yes Figure 20A A top view of the second exemplary structure.

[0040] Figure 21A and Figure 21B This is a schematic diagram of the electrostatic potential band profile of the ferroelectric tunnel junction device according to the first and second embodiments of this disclosure.

[0041] Figure 22A , Figure 23 , Figure 24 , Figure 25A , Figure 26 and Figure 27 This is a vertical cross-sectional view of the steps in a method for forming a third exemplary structure according to a third embodiment of the present disclosure.

[0042] Figure 22B and Figure 25B They are Figure 22A and Figure 25A A top view of the third exemplary structure.

[0043] Figure 28A , Figure 29 , Figure 30 , Figure 31A , Figure 32 and Figure 33 This is a vertical cross-sectional view of the steps in a method for forming a fourth exemplary structure according to a fourth embodiment of the present disclosure.

[0044] Figure 28B and Figure 31B They are Figure 28A and Figure 31A A top view of the fourth exemplary structure.

[0045] Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 and Figure 39 This is a vertical cross-sectional view of the steps in a method for forming a fourth exemplary structure according to an alternative aspect of a fourth embodiment of the present disclosure.

[0046] Figure 40 , Figure 41 , Figure 42 , Figure 43 and Figure 44 This is a vertical cross-sectional view of steps in a method for forming a fourth exemplary structure according to other alternative aspects of the fourth embodiment of this disclosure. Detailed Implementation

[0047] Embodiments of this disclosure provide bonded memory devices and methods for fabricating bonded memory devices by bonding different portions of the same memory cell to each other. In a first and second embodiment, a ferroelectric tunnel junction device is formed by wafer bonding to obtain a high-quality crystalline ferroelectric tunnel dielectric layer, which is epitaxially grown on a template layer, and then the ferroelectric tunnel dielectric layer is bonded to a selector element formed on a separate substrate. In a third and fourth embodiment, magnetoresistive random access memory (MRAM) and phase-change memory (PCM) memory devices are bonded to one of a word line or a bit line and / or bonded to a selector element formed on a separate substrate to avoid damage to the MRAM and PCM layers during reactive ion etching of the word line or bit line.

[0048] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0049] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0050] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0051] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0052] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the topmost surface of the memory element array and a second horizontal plane that includes the bottommost surface of the memory element array. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0053] The ferroelectric properties of ferroelectric materials depend on the specific crystalline phase that stabilizes the ferroelectric material. For example, hafnium dioxide substrates exhibit ferroelectricity only in orthorhombic phases (e.g., non-centrosymmetric orthorhombic phases). First and second embodiments of this disclosure relate to memory devices comprising crystalline ferroelectric memory elements and methods for fabricating the same, aspects of which are described below. The crystalline layer of the memory device stabilizes the ferroelectric crystallographic phase of the ferroelectric material to provide a high-performance ferroelectric device. In one embodiment, the crystalline ferroelectric material comprises a relatively thin epitaxial hafnium dioxide substrate exhibiting an orthorhombic phase. The hafnium dioxide substrate is epitaxially grown on a germanium-based buffer layer. After growth, the epitaxial hafnium dioxide substrate is transferred to another substrate using wafer bonding and layer transfer methods.

[0054] refer to Figure 1AA first exemplary structure according to a first embodiment of the present disclosure includes a first substrate 10L. The first substrate 10L may be a single-crystal substrate on which a single-crystal semiconductor material may subsequently be grown. For example, the first substrate 10L may be a commercially available single-crystal silicon wafer. A single-crystal semiconductor layer 20L may be formed on the top surface of the first substrate 10L by an epitaxial semiconductor deposition process. The single-crystal semiconductor layer 20L may contain a germanium-containing single-crystal semiconductor material. For example, the single-crystal semiconductor layer 20L may contain germanium or a silicon-germanium alloy. In one embodiment, the single-crystal semiconductor layer 20L may contain germanium in the atomic percentage range of 50% to 100%. The single-crystal semiconductor layer 20L may be formed by performing an epitaxial semiconductor deposition process. In one embodiment, the bottom portion of the single-crystal semiconductor layer 20L may have a vertically graded material composition such that the atomic concentration of germanium increases with distance from the top surface of the first substrate 10L. In one embodiment, the top portion of the single-crystal semiconductor layer 20L may contain germanium in the atomic percentage range of 50% to 100%, such as 80% to 90%. In one embodiment, the top portion of the single-crystal semiconductor layer 20L may contain 100% germanium atomically. The thickness of the single-crystal semiconductor layer 20L may be in the range of 50 nm to 600 nm, such as 100 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0055] refer to Figure 1B An optional semiconductor oxide layer 25 can be formed on the top surface of the single-crystal semiconductor layer 20L. In one embodiment, the semiconductor oxide layer 25 can be formed by oxidation of a surface portion of the single-crystal semiconductor layer 20L. In one embodiment, the semiconductor oxide layer 25 may comprise germanium dioxide, silicon oxide, or silicon-germanium oxide. The thickness of the semiconductor oxide layer 25 can be from 5 nm to 50 nm, such as in the range of 10 nm to 30 nm, but smaller and larger thicknesses are also possible.

[0056] refer to Figure 1CHydrogen or deuterium atoms can be implanted into the single-crystal semiconductor layer 20L through the semiconductor oxide layer 25 to form an implantation layer (i.e., a hydrogen or deuterium implantation region) 23. The single-crystal semiconductor layer 20L is divided into a proximal single-crystal semiconductor layer 22L and a distal single-crystal semiconductor layer 24L. The thickness of the proximal single-crystal semiconductor layer 22L can be in the range of 25 nm to 300 nm, such as 50 nm to 150 nm, but smaller and larger thicknesses are also possible. The thickness of the distal single-crystal semiconductor layer 24L can be in the range of 25 nm to 300 nm, such as 50 nm to 150 nm, but smaller and larger thicknesses are also possible. In one embodiment, the distal single-crystal semiconductor layer 24L may comprise germanium or a silicon-germanium alloy, and / or may be substantially composed of germanium or a silicon-germanium alloy comprising germanium in the atomic percentage range of 50% to 100%. The semiconductor oxide layer 25 can be removed, for example, by a selective wet etching process. A suitable surface cleaning process can be performed on the physically exposed top surface of the distal single-crystal semiconductor layer 24L.

[0057] refer to Figure 1D A memory material layer, such as a single-crystal ferroelectric material layer 30L, can be epitaxially grown on the top surface of the distal single-crystal semiconductor layer 24L. The single-crystal ferroelectric material layer 30L contains single-crystal ferroelectric material, which is epitaxially aligned with the single-crystal semiconductor material of the distal single-crystal semiconductor layer 24L.

[0058] In one embodiment, the single-crystal ferroelectric material layer 30L may comprise a transition metal oxide material. In one embodiment, the transition metal oxide material comprises a hafnium dioxide-based material, which includes doped or undoped hafnium dioxide. In an exemplary example, the single-crystal ferroelectric material layer 30L may comprise single-crystal hafnium dioxide doped with zirconium (also known as hafnium-zirconium oxide), silicon, strontium, aluminum, yttrium, germanium, and / or gadolinium.

[0059] In another embodiment, the transition metal oxide material includes perovskite materials, such as barium titanate (e.g., BaTiO3; BT), barium europium titanate, and lead scandium tantalate (e.g., Pb(Sc)). x Ta 1-x Lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN), (LaAlO3), potassium niobate (such as KNbO3), sodium bismuth titanate (such as Na) 0.5 Bi 0.5TiO3), lithium tantalate (such as LiTaO3(LT)), lead lanthanum titanate (such as (Pb,La)TiO3(PLT)), or lanthanum lead zirconate titanate (such as (Pb,La)(Zr,Ti)O3(PLZT)). In the case of perovskite materials, a strontium titanate (SrTiO3) or strontium ruthenate (SrRuO3) layer can be used as the distal crystalline layer 24L.

[0060] The single-crystal ferroelectric material layer 30L can be epitaxially grown by atomic layer deposition or another suitable method. Dopants can be introduced in situ or ex-situ (e.g., by ion implantation). The thickness of the single-crystal ferroelectric material layer 30L can range from 2 nm to 30 nm, such as from 5 nm to 15 nm, for example, about 10 nm, but smaller and larger thicknesses are also possible. Thermal annealing can be performed to improve the crystallinity of the material in the single-crystal ferroelectric material layer 30L and enhance the ferroelectric properties (such as polarization amplitude) of the ferroelectric material in the single-crystal ferroelectric material layer 30L. For example, layer 30L can be a hafnium dioxide-based ferroelectric layer having a ferroelectric non-centrosymmetric orthorhombic phase after annealing.

[0061] The first metal material layer 40L can be formed by depositing a first metal material on the top surface of the single-crystal ferroelectric material layer 30L. The first metal material layer 40L may contain elemental metals such as W, Mo, or Ru, and / or conductive metal compound materials such as MoN, TiN, TaN, or WN. The first metal material layer 40L can be formed by chemical vapor deposition or by physical vapor deposition. The first metal material layer 40L may have a thickness in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses are also possible.

[0062] refer to Figure 2A A second substrate 110L may be provided. The second substrate 110L may include an insulating material layer at its topmost portion. In one embodiment, the second substrate 110L may include a semiconductor substrate (such as a silicon wafer) and a semiconductor device (not explicitly shown), such as a field-effect transistor formed on the semiconductor substrate. A dielectric material layer (not explicitly shown) may be formed over the semiconductor device, embedding a metal interconnect structure (not explicitly shown). The metal interconnect structure may provide electrical interconnects between the various nodes of the semiconductor device.

[0063] A dielectric material layer can be deposited over a second substrate 110L. The dielectric material layer comprises a dielectric material, such as silicon oxide, and can be formed by chemical vapor deposition. The thickness of the dielectric material layer can range from 50 nm to 500 nm, but smaller and larger thicknesses are also possible. A photoresist layer (not shown) can be applied over the dielectric material layer and can be photolithographically patterned to form line and spacing patterns. Elongated openings extending laterally along a first horizontal direction hd1 and laterally spaced from each other along a second horizontal direction hd2 can be formed in the photoresist layer. The width of each opening along the second horizontal direction hd2 can range from 10 nm to 50 nm, such as 15 nm to 25 nm, but smaller and larger widths are also possible. The pitch of the line and spacing patterns can range from 20 nm to 100 nm, such as 30 nm to 50 nm, but smaller and larger pitches are also possible. The pattern in the photoresist layer can be transferred through the dielectric material layer using an anisotropic etching process. During this anisotropic etching process, the photoresist layer can be used as an etching mask. First line trenches can be formed through the dielectric material layer. The photoresist layer can then be removed, for example, by ashing. The remaining portion of the dielectric material layer forms the first dielectric rail 122.

[0064] An optional metal liner layer comprising a metal barrier material can be deposited in the first trench and above the first dielectric rail 122. The metal liner layer may comprise a conductive metal barrier material, such as a conductive metal nitride material (e.g., TiN, TaN, and / or WN) and / or a conductive metal carbide material (e.g., TiC, TaC, and / or WC). The metal liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metal filler layer can be deposited above the metal liner layer. The metal filler layer comprises a metallic material with high resistivity. For example, the metal filler layer may comprise copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or combinations thereof.

[0065] Excess portions of the metal filler layer and the metal liner layer can be removed from above a horizontal plane including the top surface of the first dielectric rail. Retained portions of the metal filler layer constitute a first metal filler portion. Retained portions of the metal liner layer constitute a first metal liner. Successive combinations of the first metal liner and the first metal filler portion constitute a first conductive line 120. The first conductive lines 120 extend laterally along a first horizontal direction hd1 and are laterally spaced along a second horizontal direction hd2. Generally, the first conductive lines 120, laterally spaced by the first dielectric rails 122, are formed above the second substrate 110L.

[0066] Alternatively, the first conductive lines 120 can be formed by first depositing one or more conductive layers over the second substrate 110L, and then patterning the one or more conductive layers by reactive ion etching (RIE) to form the lines 120. First dielectric rails 122 are then formed between the first conductive lines 120 by depositing dielectric material layers between the first conductive lines 120 and planarizing the dielectric material layers.

[0067] refer to Figure 3 A layer stack including a selector material layer 134L and a second metal material layer 140L can be formed above the first conductive line 120. In one embodiment, the layer stack may include, from bottom to top, a lower electrode layer 132L, a selector material layer 134L, an upper electrode layer 136L, and a second metal material layer 140L. The combination of the lower electrode layer 132L, the selector material layer 134L, and the upper electrode layer 136L is referred to herein as the selector-level layer 130L.

[0068] Each of the lower electrode layer 132L and the upper electrode layer 136L comprises at least one conductive material. This at least one conductive material may include a non-metallic conductive material. Exemplary non-metallic conductive materials that may be used in the lower electrode layer 132L and the upper electrode layer 136L include amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, amorphous silicon, amorphous germanium, alloys or mixtures thereof, and stacks thereof. Each of the lower electrode layer 132L and the upper electrode layer 136L may be free of transition metal elements. Each of the lower electrode layer 132L and the upper electrode layer 136L may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Each of the lower electrode layer 132L and the upper electrode layer 136L may have a thickness ranging from 0.5 nm to 10 nm, such as from 1 nm to 5 nm, but smaller and larger thicknesses are also possible.

[0069] The selector material layer 134L contains a material that can be used as a voltage-dependent switch. Generally, the selector material layer 134L may contain any suitable threshold switching material exhibiting nonlinear electrical behavior, such as a bidirectional threshold switching material or a diode threshold switching material (e.g., material used in pn semiconductor diodes, pin semiconductor diodes, Schottky diodes, or metal-insulator-metal diodes). In one embodiment, the selector material layer 134L contains a bidirectional threshold switching material.

[0070] As used herein, a bidirectional threshold switch (OTS) is a device that does not crystallize in a low-resistivity state at voltages above a threshold voltage and returns to a high-resistivity state at the ends of the OTS material layer when not subjected to voltages above the threshold voltage. As used herein, a "bidirectional threshold switch material" refers to a material that exhibits a non-linear resistivity profile under an applied external bias voltage, such that the resistivity of the material decreases with the magnitude of the applied external bias voltage. In other words, a bidirectional threshold switch material is non-ohmic and becomes more conductive at higher external bias voltages than at lower external bias voltages.

[0071] A bidirectional threshold-switching material (OTS material) may be amorphous (e.g., amorphous) in a high-resistance state and remain amorphous (e.g., amorphous) in a low-resistance state during a voltage applied across the OTS material above its threshold voltage. When the high voltage above its threshold voltage is removed, the OTS material may return to a high-resistance state. The bidirectional threshold-switching material may remain amorphous (e.g., amorphous) throughout the resistance state transition. In one embodiment, the bidirectional threshold-switching material may include a chalcogenide material layer that exhibits hysteresis in both the write and read states. The chalcogenide material may be a GeTe compound or a Ge-Se compound doped with a dopant selected from As, N, and C, such as a Ge-Se-As compound semiconductor material. The bidirectional threshold-switching material layer may include a gate material layer 134L containing any bidirectional threshold-switching material. In one embodiment, the selector material layer 134L may comprise and / or may consist substantially of the following materials: GeSeAs alloy, GeSe alloy, SeAs alloy, GeTe alloy, or SiTe alloy.

[0072] In one embodiment, the material of the selector material layer 134L can be selected such that the resistivity of the selector material layer 134L decreases by at least two orders of magnitude (i.e., more than 100 times) when an external bias voltage exceeding a critical bias voltage value (also known as a threshold voltage) is applied. In one embodiment, the composition and thickness of the selector material layer 134L can be selected such that the critical bias voltage value can be in the range of 1V to 4V, but smaller and larger voltages are also possible. The thickness of the selector material layer 134L can be, for example, in the range of 5nm to 40nm, such as 10nm to 20nm, but smaller and larger thicknesses are also possible.

[0073] The second metal material layer 140L can be formed by depositing a second metal material on the top surface of the gate stage layer 130L. The second metal material layer 140L may comprise an elemental metal (such as W or Ru) and / or a conductive metal compound material (such as TiN, TaN, or WN). The second metal material layer 140L can be formed by chemical vapor deposition or by physical vapor deposition. The second metal material layer 140L may have a thickness in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses are also possible. Generally, the materials of the first metal material layer 40L and the second metal material layer 140L can be selected such that the first metal material layer 40L and the second metal material layer 140L can subsequently be bonded to each other. The material of the second metal material layer 140L may be the same as or different from the material of the first metal material layer 40L.

[0074] refer to Figure 4 , Figure 3 Structure and Figure 1D The structure can be positioned such that the second metal layer 140L contacts the first metal layer 40L. A first thermal annealing process is performed to bond the second metal layer 140L to the first metal layer 40L. The temperature of the first thermal annealing process can be in the range of 200 degrees Celsius to 500 degrees Celsius, such as 250 degrees Celsius to 400 degrees Celsius. The temperature of the first thermal annealing process may be limited by the thermal stability of the ferroelectric material of the single-crystal ferroelectric material layer 30L and the thermal stability of the implanted layer 23. Alternatively, the second metal layer 140L can be omitted, and metal-hybrid bonding can be used instead.

[0075] refer to Figure 5 The single-crystal semiconductor layer 20L (i.e., 22L, 24L) can be cut (i.e., separated) at the hydrogen or deuterium implantation layer 23. A second thermal annealing process can be performed to induce hydrogen or deuterium atoms to bubble into the hydrogen implantation layer 23. For example, the temperature of the second thermal annealing process can be in the range of 500 degrees Celsius to 700 degrees Celsius. The assembly of the first substrate 10L and the proximal single-crystal semiconductor layer 22L can be detached from the assembly including the second substrate 110L, the first conductive line 120 and the first dielectric rail 122, the selector stage layer 130L, the second metal material layer 140L, the first metal material layer 40L, the single-crystal ferroelectric material layer 30L, and the distal single-crystal semiconductor layer 24L (hereinafter referred to as the single-crystal semiconductor layer 24L).

[0076] If necessary, the single-crystal semiconductor layer 24L can be selectively etched away to expose the single-crystal ferroelectric material layer 30L. Alternatively, the single-crystal semiconductor layer 24L can be partially or completely retained as part of the electrodes of a ferroelectric tunnel junction memory device. Reference Figure 6Optionally, a metal capping layer 50L can be deposited on the top surface of the single-crystal semiconductor layer 24L (if layer 24L is retained). If layer 24L is removed, the metal capping layer 50L can optionally be deposited on the top surface of the single-crystal ferroelectric material layer 30L, such that... Figure 10A and Figure 10B The device shown is in Figures 7 to 8B It is shown and formed after the steps described below.

[0077] The metal capping layer 50L comprises and / or is substantially composed of materials selected from and / or substantially composed of: elemental metals, intermetallic alloys, conductive metal nitride materials, conductive metal carbide materials, and conductive carbon-based materials. Exemplary elemental metals that can be used in the metal capping layer 50L include transition metals. Exemplary conductive metal nitride materials include TiN, TaN, MoN, and WN. Exemplary conductive metal carbide materials include TiC, TaC, and WC. Conductive carbon-based materials include amorphous carbon or diamond-like carbon doped with suitable dopant atoms (such as nitrogen) to increase conductivity. For example, the metal capping layer 50L may be substantially composed of W, TiN, TaN, MoN, or WN. The metal capping layer 50L can be formed by physical vapor deposition or chemical vapor deposition. The thickness of the metal capping layer 50L can be in the range of 10 nm to 80 nm, such as 20 nm to 50 nm and / or 30 nm to 40 nm, but smaller and larger thicknesses are also possible.

[0078] refer to Figure 7 A photoresist and a hard mask layer can be applied over the metal capping layer 50L and photolithographically patterned to form a two-dimensional array of discrete photoresist material portions 57. In one embodiment, the two-dimensional array of discrete photoresist and hard mask material portions 57 can be formed as a two-dimensional periodic rectangular array. In one embodiment, the two-dimensional array of discrete photoresist and hard mask material portions 57 can have a pitch along a second horizontal direction hd2, which is the same as the pitch of the first conductive line 120 along the second horizontal direction, and can have a pitch along a first horizontal direction hd1, which is the same as the pitch of the second conductive line to be formed subsequently along the first horizontal direction hd1.

[0079] An anisotropic etching process can be performed to transfer patterns in a two-dimensional array of discrete photoresist material portions 57 through a layer stack including a metal capping layer 50L, a distal single-crystal semiconductor layer 24L (if present), a single-crystal ferroelectric material layer 30L, a first metal material layer 40L, a second metal material layer 140L, and a selector stage layer 130L. Each patterned portion of the layer stack including the metal capping layer 50L, the distal single-crystal semiconductor layer 24L, the single-crystal ferroelectric material layer 30L, the first metal material layer 40L, the second metal material layer 140L, and the selector stage layer 130L includes memory pillar structures (130, 140, 40, 30, 24, 50). Generally, at least one memory pillar structure (130, 140, 40, 30, 24, 50) can be formed by patterning a stack of layers including a metal capping layer 50L, a distal single-crystal semiconductor layer 24L, a single-crystal ferroelectric material layer 30L, a first metal material layer 40L, a second metal material layer 140L, and a selector stage layer 130L. In one embodiment, a two-dimensional periodic rectangular array of memory pillar structures (130, 140, 40, 30, 24, 50) can be formed.

[0080] Each memory pillar structure (130, 140, 40, 30, 24, 50) can include, from bottom to top, a selector element 130, a second metal material plate 140, a first metal material plate 40, a single-crystal ferroelectric material plate 30, an optional single-crystal semiconductor plate 24, and a metal cover plate 50. Each selector element 130 is a patterned portion of the selector stage layer 130L. Each selector element 130 can include, from bottom to top, a lower electrode plate 132, a selector material plate 134, and an upper electrode plate 136. Each second metal material plate 140 is a patterned portion of the second metal material layer 140L. Each first metal material plate 40 is a patterned portion of the first metal material layer 40L. Each single-crystal ferroelectric material plate 30 is a patterned portion of the single-crystal ferroelectric material layer 30L. Each single-crystal semiconductor plate 24 (if present) is a patterned portion of the single-crystal semiconductor layer 24L. Each metal cover plate 50 is a patterned portion of the metal cover layer 50L.

[0081] Each memory pillar structure (130, 140, 40, 30, 24, 50) may have at least one sidewall extending from the top surface of the respective memory pillar structure (130, 140, 40, 30, 24, 50) to the bottom surface of the memory pillar structure (130, 140, 40, 30, 24, 50). Each sidewall may be vertical, substantially vertical, or may have a tapered angle in the range of 1 to 15 degrees. The discrete photoresist and hard mask material portions 57 may subsequently be removed, for example, by ashing. The memory pillar structures (130, 140, 40, 30, 24, 50) may have a horizontal cross-sectional shape that is rectangular, rounded rectangular, circular, elliptical, or any generally curved two-dimensional closed shape.

[0082] refer to Figure 8A and Figure 8B Optionally, a dielectric diffusion barrier liner (not shown) can be formed on the physically exposed surfaces of the memory pillar structures (130, 140, 40, 30, 24, 50). The dielectric filler material may be, for example, undoped silicate glass, doped silicate glass, or organosilicon glass. The covering of the dielectric filler material and the dielectric diffusion barrier liner, including portions of the horizontal plane of the top surface of the memory pillar structures (130, 140, 40, 30, 24, 50), is processed by a planarization process (such as chemical mechanical planarization). The top surface of the metal cover 50 may be used as a stop surface for the planarization process. The retained portions of the dielectric filler material and the dielectric diffusion barrier liner constitute a dielectric isolation structure 60. The dielectric isolation structure 60 may be laterally arranged around a two-dimensional array of memory pillar structures (130, 140, 40, 30, 24, 50).

[0083] refer to Figure 9A and Figure 9B A dielectric material layer can be deposited over a two-dimensional array of memory pillar structures (130, 140, 40, 30, 24, 50). The dielectric material layer contains a dielectric material, such as silicon oxide, and can be formed by chemical vapor deposition. The thickness of the dielectric material layer can range from 50 nm to 500 nm, but smaller and larger thicknesses are also possible. A photoresist layer (not shown) can be applied over the dielectric material layer and can be photolithographically patterned to form line and spacing patterns. Elongated openings extending laterally along a second horizontal direction hd2 and laterally spaced from each other along a first direction hd1 can be formed in the photoresist layer. The width of each opening along the first horizontal direction hd1 can range from 10 nm to 50 nm, such as 15 nm to 25 nm, but smaller and larger widths are also possible. The pitch of the line and spacing patterns can range from 20 nm to 100 nm, such as 30 nm to 50 nm, but smaller and larger pitches are also possible. The pitch of the line and spacing pattern can be the same as the pitch of the two-dimensional array of memory cylinder structures (130, 140, 40, 30, 24, 50) along the first horizontal direction hd1. The pattern in the photoresist layer can be transferred through the dielectric material layer by an anisotropic etching process. The photoresist layer can be used as an etching mask during this anisotropic etching process. Optionally, an additional hard mask layer (not shown) can be used in conjunction with the photoresist layer to define the line and spacing pattern. A second line trench can be formed through the dielectric material layer. The photoresist layer and hard mask layer can then be removed, for example, by ashing. The remaining portion of the dielectric material layer forms a second dielectric rail 90.

[0084] A metal liner layer comprising a metal barrier material can be deposited in the second trench and above the second dielectric rail 90. The metal liner layer may comprise a conductive metal barrier material, such as a conductive metal nitride material (e.g., TiN, TaN, MoN, and / or WN) and / or a conductive metal carbide material (e.g., TiC, TaC, and / or WC). The metal liner layer can be deposited by chemical vapor deposition or physical vapor deposition. A metal filler layer can be deposited above the metal liner layer. The metal filler layer comprises a metallic material with high resistivity. For example, the metal filler layer may comprise copper, tungsten, titanium, tantalum, molybdenum, ruthenium, cobalt, or combinations thereof.

[0085] Excess portions of the metal filler layer and the metal liner layer can be removed from above a horizontal plane including the top surface of the second dielectric rail 90. Retained portions of the metal filler layer constitute a second metal filler portion. Retained portions of the metal liner layer constitute a second metal liner. Successive combinations of the second metal liner and the second metal filler portion constitute a second conductive line 80. The second conductive line 80 extends laterally along a second horizontal direction hd2 and is laterally spaced along a first horizontal direction hd1.

[0086] Alternatively, the second conductive lines 80 can be formed by first depositing one or more conductive layers, and then patterning the one or more conductive layers by reactive ion etching (RIE) to form lines 80. Second dielectric rails 90 are then formed between the second conductive lines 80 by depositing dielectric material layers between the second conductive lines 80 and planarizing the dielectric material layers.

[0087] refer to Figure 10A and Figure 10B It can be done in Figure 5 After the processing steps, in Figure 6 Before depositing the metal capping layer 50L, the distal single-crystal semiconductor layer 24L is removed, and from... Figure 9A and Figure 9B The first exemplary structure is further configured in an alternative manner. In this case, the metal capping layer 50L can be formed directly on the top surface of the single-crystal ferroelectric material layer 30L. Therefore, each memory pillar structure (130, 140, 40, 30, 24, 50) may include a selector element 130, a second metal material plate 140, a first metal material plate 40, a single-crystal ferroelectric material plate 30, and a metal capping layer 50, and is composed of them.

[0088] In a second embodiment of this disclosure, chemical or mechanical substrate removal is used instead of cutting along the implantation layer 23. (See reference...) Figure 11A An exemplary structure according to a second embodiment of this disclosure includes a first substrate 10L, which can be coupled with... Figure 1AThe first substrate 10L is identical. A single-crystal semiconductor layer 20L can be formed on the top surface of the first substrate 10L by an epitaxial semiconductor deposition process. The single-crystal semiconductor layer 20L may contain a germanium-containing single-crystal semiconductor material. For example, the single-crystal semiconductor layer 20L may contain germanium or a silicon-germanium alloy. In one embodiment, the single-crystal semiconductor layer 20L may contain germanium in the atomic percentage range of 50% to 100%. The single-crystal semiconductor layer 20L can be formed by performing an epitaxial semiconductor deposition process. In one embodiment, the bottom portion of the single-crystal semiconductor layer 20L may have a vertically graded material composition such that the atomic concentration of germanium increases with distance from the top surface of the first substrate 10L. In one embodiment, the top portion of the single-crystal semiconductor layer 20L may contain germanium in the atomic percentage range of 50% to 100%, such as 80% to 90%. In one embodiment, the top portion of the single-crystal semiconductor layer 20L may contain 100% germanium. The thickness of the single-crystal semiconductor layer 20L can range from 25nm to 300nm, such as from 50nm to 150nm, but smaller and larger thicknesses are also possible.

[0089] refer to Figure 11B A single-crystal ferroelectric material layer 30L can be epitaxially grown on the top surface of the single-crystal semiconductor layer 20L. The single-crystal ferroelectric material layer 30L comprises a single-crystal ferroelectric material, which is epitaxially aligned with the single-crystal semiconductor material of the single-crystal semiconductor layer 20L. In one embodiment, the single-crystal ferroelectric material layer 30L may comprise a transition metal oxide material, as described with respect to the first embodiment. Thermal annealing can be performed to improve the crystallinity of the material in the single-crystal ferroelectric material layer 30L and enhance the ferroelectric properties (such as polarization amplitude) of the ferroelectric material in the single-crystal ferroelectric material layer 30L.

[0090] The first metal material layer 40L can be formed by depositing a first metal material on the top surface of the single-crystal ferroelectric material layer 30L. The first metal material layer 40L may contain elemental metals such as W, Mo, or Ru, and / or conductive metal compound materials (such as TiN, TaN, or WN). The first metal material layer 40L can be formed by chemical vapor deposition or by physical vapor deposition. The first metal material layer 40L may have a thickness in the range of 5 nm to 50 nm, such as 10 nm to 25 nm, but smaller and larger thicknesses are also possible.

[0091] refer to Figure 12 ,supply Figure 3 The structure is such that the second metal material layer 140L is bonded to the first metal material layer 40L by performing a hot annealing process.

[0092] refer to Figure 13The first substrate 10L can be thinned from the back side by performing a thinning process. The thinning process may include grinding, wet etching, dry etching, and / or polishing. The thickness of the thinned first substrate 10L can range from 100 nm to 5,000 nm.

[0093] refer to Figure 14 Alternatively, a thinning process can be used to selectively remove a portion of the first substrate 10L relative to the single-crystal semiconductor layer 20L. This additional thinning process may include a chemical mechanical polishing process. The top surface of the single-crystal semiconductor layer 20L can be physically exposed.

[0094] refer to Figure 15 Executable Figure 6 The processing steps are to form a 50L metal capping layer.

[0095] refer to Figure 16 It can be executed Figure 7 The processing steps are used to form a two-dimensional array of memory column structures (130, 140, 40, 30, 24, 50).

[0096] refer to Figure 17A and Figure 17B It can be executed Figure 8A and Figure 8B The processing steps are to form a dielectric isolation structure 60.

[0097] refer to Figure 18A and Figure 18B It can be executed Figure 9A and Figure 9B The processing steps are to form the second conductive line 80 and the second dielectric rail 90.

[0098] refer to Figure 19 By selectively removing the single-crystal semiconductor layer 20L relative to the material of the single-crystal ferroelectric material layer 30L, it is possible to... Figure 14 The second exemplary structure leads to an alternative configuration of the second exemplary structure. The metal capping layer 50L can be deposited directly on the top surface of the single-crystal ferroelectric material layer 30L.

[0099] refer to Figure 20A and 20B It can be executed Figure 16 , Figure 17A and Figure 17B as well as Figure 18A and Figure 18B The processing steps are used to provide an alternative configuration of the second exemplary structure.

[0100] like Figure 9A , Figure 10A , Figure 18A and Figure 20AAs shown, memory cells of a ferroelectric tunnel junction memory device according to the first and second embodiments are formed in each memory pillar structure. The memory cell of the ferroelectric tunnel junction memory device includes a ferroelectric tunneling dielectric layer comprising a single-crystal ferroelectric material plate 30 positioned between a lower electrode and an upper electrode. The lower electrode and the upper electrode respectively comprise a first metal material plate 40 and a metal cover plate 50. A single-crystal semiconductor plate 24 (if present, such as...) Figure 9A (As shown) may include a portion of the upper electrode. The memory cell of the ferroelectric tunnel junction memory device may also include a selector element (e.g., a manipulation element) 130. Each selector element 130 may include, from bottom to top: a lower electrode including a lower electrode plate 132, an upper electrode including an upper electrode plate 136, and a selector material (e.g., an OTS or a diode) including a selector material plate 134 positioned between the lower electrode 132 and the upper electrode 136. Conductors (120, 80) may include corresponding bit lines and word lines of the memory cell.

[0101] The tunneling resistance of the memory cell is adjusted according to the polarization direction of the electric dipole moment in the ferroelectric tunneling dielectric layer 30. The polarization direction of the electric dipole moment in a portion of the ferroelectric tunneling dielectric layer 30 can be programmed by applying a programming voltage across the ferroelectric tunneling memory element. The magnitude of the programming voltage can be selected such that the selector element 130 is turned on at an external bias voltage having the programming voltage magnitude, and not turned on at an external bias voltage less than the programming voltage magnitude (e.g., half the programming voltage magnitude). The programming voltage applied to the bit line relative to the word line can have a magnitude sufficient to turn on the selector element 130, and can be positive or negative depending on the target polarization direction of the electric dipole moment in the programmed portion of the ferroelectric tunneling dielectric layer 30.

[0102] By applying a sensing voltage between the selected bit line and the selected word line, the direction of the electric dipole moment in a portion of the ferroelectric tunneling dielectric layer 30 between the selected bit line and the selected word line can be sensed. The magnitude of the sensing voltage can be selected such that the selector element 130 is turned on at an external bias voltage having the magnitude of the sensing voltage, and not turned on at an external bias voltage less than the magnitude of the sensing voltage (e.g., half the magnitude of the sensing voltage). Furthermore, the magnitude of the sensing voltage is lower than the magnitude of the programming voltage and insufficient to program a portion of the ferroelectric tunneling dielectric layer 30. In one embodiment, the magnitude of the sensing voltage can be approximately 50 mV to 200 mV, higher than the turn-on voltage of the selector element 130. The selected portion of the ferroelectric tunneling dielectric layer 30 provides resistance adjustment according to the polarization direction of the electric dipole moment. Therefore, the selected portion of the ferroelectric tunneling dielectric layer 30 between the selected bit line and the selected word line in the array can be sensed without interfering with unselected memory cells.

[0103] refer to Figure 21A and Figure 21B Electrostatic potential band profiles are shown for ferroelectric tunnel junction devices according to the first and second embodiments. These devices include a first conductor, a tunneling ferroelectric dielectric, and a second conductor with two different polarization directions for tunneling the ferroelectric dielectric. The first and second conductors may be different, and the magnitude and lateral extent of the distortion in the conduction band caused by the dipole moment P in the ferroelectric tunneling dielectric may be asymmetric. The asymmetric band adjustment induced in the ferroelectric tunnel junction can change the tunneling resistance of the ferroelectric tunnel junction according to the direction of the electric dipole moment in the ferroelectric tunneling dielectric. In general, polarization reversal of the ferroelectric tunnel junction can adjust the tunneling transmission coefficient induced by two different average barrier heights. Therefore, the electrostatic potential band profiles for the two different polarization states of the ferroelectric tunneling dielectric provide two different resistance states that can be used for programming and storing data bits. The ratio of conductance in the low-resistance state to conductance in the high-resistance state can be in the range of 10 to 1,000, such as 30 to 300, but smaller and larger ratios are also possible. The polarization state of the ferroelectric tunneling dielectric exhibits a hysteresis curve depending on the external voltage bias across the first and second conductors, and is capable of storing data bits. The programmable resistive states of the ferroelectric tunnel junction are used in various ferroelectric memory devices according to the first and second embodiments of this disclosure.

[0104] Referring to all figures and according to the first and second embodiments of this disclosure, the memory device includes a first conductive line 120 extending laterally along a first horizontal direction hd1, a memory pillar structure (130, 140, 40, 30, optionally 24, 50) covering and contacting the first conductive line 120, and a second conductive line 80, wherein the memory pillar structure includes a single-crystal ferroelectric material plate 30, wherein the entire ferroelectric material is single-crystal, and the second conductive line extends laterally along a second horizontal direction hd2 and covers and contacts the memory pillar structure.

[0105] In one embodiment, the memory pillar structure (130, 140, 40, 30, optionally 24, 50) includes a first metallic material plate 40 contacting the bottom surface of the single-crystal ferroelectric material plate 30. In one embodiment, the memory pillar structure (130, 140, 40, 30, optionally 24, 50) also includes a selector material plate 134 beneath the first metallic material plate 40. A bonding interface is located between the selector material plate 134 and the single-crystal ferroelectric material plate 30. The bonding interface may be located between the first metallic material plate 40 and the second metallic material layer 140.

[0106] In one embodiment, the memory device includes: a lower electrode plate 132 that contacts the bottom surface of a selector material plate 134 and comprises a first non-metallic conductive material; and an upper electrode plate 136 that contacts the top surface of the selector material plate 134 and comprises a second non-metallic conductive material. In one embodiment, the selector plate comprises a bidirectional threshold switching material. In one embodiment, each of the first and second non-metallic conductive materials is selected from amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, amorphous silicon, amorphous germanium, alloys thereof, or stacks thereof.

[0107] In one embodiment, the memory pillar structure (130, 140, 40, 30, optionally 24, 50) includes a second metal material plate 140 that contacts and is bonded to the bottom surface of a first metal material plate 40. In one embodiment, the ferroelectric material of the single-crystal ferroelectric material plate 30 comprises doped or undoped hafnium oxide having an orthorhombic phase.

[0108] In one embodiment, the memory pillar structure (130, 140, 40, 30, optionally 24, 50) includes a semiconductor plate (such as a single-crystal semiconductor plate 24) contacting the top surface of the single-crystal ferroelectric material plate 30. In one embodiment, the semiconductor plate comprises a single-crystal semiconductor material. In one embodiment, the single-crystal semiconductor material of the semiconductor plate is epitaxially aligned with the ferroelectric material of the single-crystal ferroelectric material plate 30. In one embodiment, the semiconductor plate comprises single-crystal germanium or silicon-germanium.

[0109] In one embodiment, the memory pillar structure (130, 140, 40, 30, optionally 24, 50) includes a metal cover plate 50 covering a single-crystal ferroelectric material plate 30 and contacting a second conductive wire 80. In one embodiment, the memory device includes a ferroelectric tunnel junction memory device.

[0110] The first and second embodiments of this disclosure provide a single-crystal ferroelectric tunneling dielectric layer in a ferroelectric tunnel junction (FTJ) memory device, which provides excellent ferroelectric properties due to its single-crystal structure. Furthermore, instead of a more difficult-to-deposit perovskite template layer, an easily depositable single-crystal semiconductor layer can be used as the epitaxial template for a hafnium oxide-based single-crystal ferroelectric tunneling dielectric layer.

[0111] In a third embodiment of this disclosure, the memory material layer comprises a phase-change memory material layer instead of a ferroelectric tunneling dielectric layer, and the memory device comprises a phase-change memory (PCM) device, such as a phase-change random access memory (“PCRAM” or “PRAM”) device instead of an FTJ memory device. The phase-change memory material layer may be used to pattern thick stacked word lines or bit lines to prevent reactive ion etching (RIE) damage. Therefore, in the third embodiment, the phase-change memory material layer is formed over a first set of patterned lines (e.g., word lines or bit lines) positioned over a first substrate. The first set of patterned lines is patterned by RIE prior to depositing the phase-change memory material layer. A second set of patterned lines (e.g., another of word lines or bit lines) is formed over a second substrate, and then the second set of patterned lines is bonded to the layer stack containing the phase-change memory material layer. In the third embodiment, the phase-change memory material layer is not exposed to extended reactive etching processes that etch thick conductive lines. This reduces or prevents damage to the phase-change memory material layer.

[0112] refer to Figure 22A and Figure 22B A second conductive line 80 and a second dielectric material rail 90 are formed over the first substrate 10L. The second conductive line 80 can be formed by depositing one or more conductive layers as described in the previous embodiment, and then patterning the one or more conductive layers by reactive ion etching (RIE) to form the line 80. The second dielectric rail 90 is then formed between the second conductive lines 80 by depositing dielectric material layers between the second conductive lines 80 and planarizing the dielectric material layers.

[0113] refer to Figure 23 A layer stack is formed over a second conductive line 80 positioned above a first substrate 10L and a second dielectric material rail 90. The layer stack includes a non-metallic conductive material layer 326L. Exemplary non-metallic conductive materials that can be used for layer 326L include amorphous carbon, amorphous boron-doped carbon, or amorphous nitrogen-doped carbon. The thickness of the non-metallic conductive material layer 326L is in the range of 10 nm to 50 nm, such as 20 nm to 30 nm, but smaller and larger thicknesses are also possible.

[0114] A relatively thin second metallic material layer 342L can be formed by depositing a second metallic material on the top surface of the non-metallic conductive material layer 326L. The second metallic material layer 342L may contain elemental metals (such as W or Ru) and / or conductive metal compound materials (such as TiN, TaN, or WN). The second metallic material layer 342L can be formed by chemical vapor deposition or by physical vapor deposition. The second metallic material layer 342L may have a thickness in the range of 1 nm to 5 nm, such as 2 nm to 3 nm, but smaller and larger thicknesses are also possible.

[0115] A memory material layer, including a phase change memory material layer 330L, is formed on the second metallic material layer 342. As used herein, "phase change memory material" refers to a material having at least two distinct phases that provide different resistivities. These at least two distinct phases can be provided, for example, by controlling the cooling rate from a heated state to provide an amorphous state with higher resistivity and a polycrystalline state with lower resistivity. In this case, the higher resistivity state of the phase change memory material can be achieved by faster quenching of the phase change memory material after heating to the amorphous state, and the lower resistivity state of the phase change memory material can be achieved by slower cooling of the phase change memory material after heating to the amorphous state.

[0116] Exemplary phase-change memory materials include, but are not limited to, germanium antimony telluride compounds such as Ge2Sb2Te5 (GST), germanium antimony compounds, indium germanium telluride compounds, aluminum selenide telluride compounds, indium selenide telluride compounds, and aluminum indium selenide telluride compounds. These compounds (e.g., compound semiconductor materials) may be doped (e.g., nitrogen-doped GST) or undoped. Therefore, the resistive memory material layer may comprise and / or may be substantially composed of materials selected from and / or substantially composed of: germanium antimony telluride compounds, germanium antimony compounds, indium germanium telluride compounds, aluminum selenide telluride compounds, indium selenide telluride compounds, or aluminum indium selenide telluride compounds. In this case, the thickness of the at least one material layer 15L may be in the range of 10 nm to 60 nm, such as 20 nm to 50 nm and / or 25 nm to 35 nm, but smaller and larger thicknesses are also possible.

[0117] A relatively thin first metal material layer 340L can be formed by depositing a first metal material on the top surface of the phase change memory material layer 330L. The first metal material layer 340L may contain elemental metals (such as W or Ru) and / or conductive metal compound materials (such as TiN, TaN, or WN). The first metal material layer 340L can be formed by chemical vapor deposition or by physical vapor deposition. The first metal material layer 340L may have a thickness in the range of 1 nm to 5 nm, such as 2 nm to 3 nm, but smaller and larger thicknesses are also possible.

[0118] A selector stage layer 130L is stacked over a first metal material layer 340L. The selector stage layer 130L includes the same layers as in the first embodiment (i.e., a lower electrode layer 132L, a selector material layer 134L, and an upper electrode layer 136L stacked in reverse order compared to the first and second embodiments), and this third embodiment will be described in more detail.

[0119] refer to Figure 24The aforementioned layers (326L, 342L, 330L, 340L, and 130L) are then patterned into memory pillar structures (326, 342, 330, 340, and 130), each containing a corresponding PRAM memory cell (330, 340, 342). Any suitable patterning method (such as photolithography and etching) can be used to form the memory pillar structures, as described above with respect to the first and second embodiments. An etching process for etching the memory pillar structures can be selected such that it does not significantly damage the phase-change memory material layer 130L. A dielectric isolation structure 60 is then formed such that it laterally surrounds a two-dimensional array of the memory pillar structures (326, 342, 330, 340, and 130).

[0120] Each memory column structure (326, 342, 330, 340, and 130) includes a phase-change memory material plate 330 positioned between a first electrode plate and a second electrode plate (340, 342) of the PRAM memory cell (330, 340, 342). A non-metallic conductive material plate 326 is positioned between the second electrode 342 and a second conductive line 80 (i.e., a word line or bit line). A selector element 130 is positioned above the first electrode plate 340. The selector element includes a selector material plate 134 positioned between the first electrode plate and the second electrode plate (132, 136) of the selector element 130.

[0121] refer to Figure 25A and Figure 25B The first conductive lines 120 can be formed by depositing one or more conductive layers over the second substrate 110L and then patterning the one or more conductive layers by reactive ion etching (RIE) to form the lines 120. First dielectric rails 122 are then formed between the first conductive lines 120 by depositing dielectric material layers between the first conductive lines 120 and planarizing the dielectric material layers.

[0122] refer to Figure 26 The first conductive line 120 and the first dielectric rail 122, positioned above the second substrate 110L, are bonded to an array of dielectric isolation structures 60 and memory pillar structures (326, 342, 330, 340, and 130) positioned above the first substrate 10L. Any suitable bonding can be used, such as metal-to-metal bonding, dielectric-to-dielectric bonding, or combinations thereof (i.e., hybrid bonding).

[0123] refer to Figure 27Optionally, the first substrate 10L can be removed from the second conductive line 80 and reused to form an additional memory device. The first substrate can be removed by any suitable method. For example, similar to the method described in the first embodiment, the first substrate 10L can be removed by implanting hydrogen or deuterium into the bottom of the first substrate to form an implantation layer, and then annealing the first substrate to cut along the implantation layer. Alternatively, the first substrate 10L can be removed by grinding and polishing, as described in the second embodiment. Alternatively, a release layer (e.g., a silicon oxide or silicon nitride layer) can be formed between the first substrate 10L and the second conductive line 80, and then the release layer can be selectively etched to remove the first substrate 10L.

[0124] In a fourth embodiment of this disclosure, the memory device includes a magnetoresistive random access memory (“MRAM”) device instead of an FTJ memory device. Each memory cell of the MRAM device may contain a magnetic tunnel junction (MTJ). In one embodiment, the MRAM device may include a spin-transfer torque (STT) type MRAM device.

[0125] MTJs can be used to prevent reactive ion etching (RIE) damage to patterned thick stacked word lines or bit lines. Therefore, in a fourth embodiment, the MTJ is formed over a first set of patterned lines (e.g., word lines or bit lines) positioned above a first substrate. The first set of patterned lines is patterned by RIE prior to MTJ deposition. A second set of patterned lines (e.g., another of word lines or bit lines) is formed over a second substrate, and then the second set of patterned lines is bonded to the layer stack containing the MTJ. In the fourth embodiment, the MTJ is not exposed to extended reactive etch processes that etch thick conductive lines. This reduces or prevents damage to the MTJ.

[0126] refer to Figure 28A and Figure 28B A second conductive line 80 and a second dielectric material rail 90 are formed over the first substrate 10L. The second conductive line 80 can be formed by depositing one or more conductive layers as described in the previous embodiment, and then patterning the one or more conductive layers by reactive ion etching (RIE) to form the line 80. The second dielectric rail 90 is then formed between the second conductive lines 80 by depositing dielectric material layers between the second conductive lines 80 and planarizing the dielectric material layers.

[0127] refer to Figure 29A layer stack including an optional metal capping layer 158L and an MTJ stack 150L is formed above a second conductive line 80 positioned above a first substrate 10L and a second dielectric material rail 90. The stack, from bottom to top or top to bottom, includes a metal capping layer 158L, a reference layer 152L (also called a magnetic pinning layer), a tunnel barrier layer 154L, and a free layer 156L, which together form the MTJ stack 150L of the STT MRAM memory cell. The thickness of the MTJ can range from 10 nm to 40 nm, such as 20 nm to 30 nm.

[0128] The metal capping layer 158L comprises a non-magnetic metallic material, such as at least one non-magnetic transition metal or a non-magnetic transition metal alloy. For example, the metal capping layer 158L may comprise, or be substantially composed of, the following materials: Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, their alloys, or conductive metal nitrides (e.g., TaN) or conductive metal carbides thereof. The metal capping layer 158L can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the metal capping layer 158L can range from 1 nm to 20 nm, such as from 2 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0129] The reference layer 152L may have a fixed magnetization direction, which may be horizontal or vertical. The reference layer 152L may be formed as a single ferromagnetic material layer or multiple ferromagnetic material layers magnetically coupled to each other to provide the same magnetization direction throughout. The reference layer 152L may include a Co / Ni multilayer structure or a Co / Pt multilayer structure. In one embodiment, the reference layer 152L may further include a thin nonmagnetic layer of tantalum or tungsten having a thickness in the range of 0.2 nm to 0.5 nm, and a thin CoFeB layer having a thickness in the range of 0.5 nm to 3 nm. The thickness of the reference layer 152L may be in the range of 2 nm to 5 nm.

[0130] Optionally, a reference layer 152L may be disposed in a synthetic antiferromagnetic (SAF) structure comprising a hard magnetization layer (not explicitly shown), an antiferromagnetic coupling layer (e.g., a Ru layer, not explicitly shown), and the reference layer 152L. When the reference layer 152L is provided as a component of the SAF structure, the magnetization of the hard magnetization layer and the magnetization of the magnetic pinning layer can be antiferromagnetically coupled through the antiferromagnetic coupling layer.

[0131] The tunnel barrier layer 154L may comprise a tunnel barrier dielectric material, such as magnesium oxide or aluminum oxide. The tunnel barrier layer 154L may have a thickness ranging from 0.6 nm to 2 nm, such as from 0.8 nm to 1.2 nm. The tunnel barrier layer 154L contacts the reference layer 152L and provides spin-sensitive tunneling of current between the reference layer 152L and the free layer 156L. In other words, the amount of current passing through the tunnel barrier layer 154L depends on the relative alignment of the magnetization between the reference layer 152L and the free layer 156L, i.e., whether the magnetization directions are parallel or antiparallel to each other.

[0132] The free layer 156L can be formed as a single ferromagnetic material layer or multiple ferromagnetic material layers magnetically coupled to each other to provide the same magnetization direction throughout. The thickness of the free layer 156L is less than 2 nm, and preferably less than 1.5 nm, such as 0.8 nm to 1.5 nm. For example, the free layer 156L may include a CoFeB layer and / or a CoFe layer. The free layer 156L can be programmed by allowing current to flow vertically upwards or downwards. Additional layers (not shown) may be included in the MTJ 150.

[0133] A selector-level layer 130L is formed on top of the MTJ stack 150L. The selector-level layer 130L includes the same layers as in the first embodiment (i.e., the lower electrode layer 132L, selector material layer 134L, and upper electrode layer 136L are stacked in reverse order compared to the first and second embodiments), and this fourth embodiment will be described in more detail. The deposition order of the metal capping layer 158L and the stacking of the selector-level layer 130L can be reversed, such that the stack of the selector-level layer 130L is formed between the MTJ stack 150L and the first substrate 10L, while the metal capping layer 158L is formed on top of the MTJ stack 150L.

[0134] refer to Figure 30 The aforementioned layers (158L, 152L, 154L, 156L, and 130L) are then patterned into memory pillar structures (158, 152, 154, 156, and 130). Any suitable patterning method can be used. For example, the stack of gate-level layers 130L can be patterned using photolithography and etching, while the MTJ stack 150L and the metal capping layer 158L can be patterned using ion beam milling to form the MTJ 150 and the metal capping layer 158. A dielectric isolation structure 60 is then formed such that it laterally surrounds a two-dimensional array of memory pillar structures (158, 152, 154, 156, and 130).

[0135] Each memory pillar structure (158, 152, 154, 156, and 130) includes an MRAM memory cell containing an MTJ 150, wherein a tunnel barrier 154 is positioned between a reference layer 152 and a free layer 156. A metal cover 158 is positioned on one side of the MTJ 150. A selector element 130 is positioned above or below the MTJ 150. The selector element includes a selector material plate 134 positioned between a first electrode plate and a second electrode plate (132, 136) of the selector element 130.

[0136] refer to Figure 31A and Figure 31B The first conductive lines 120 can be formed by depositing one or more conductive layers over the second substrate 110L, and then patterning the one or more conductive layers by reactive ion etching (RIE) to form the lines 120. First dielectric rails 122 are then formed between the first conductive lines 120 by depositing dielectric material layers between the first conductive lines 120 and planarizing the dielectric material layers.

[0137] refer to Figure 32 The first conductive line 120 and the first dielectric rail 122, positioned above the second substrate 110L, are bonded to an array of dielectric isolation structures 60 and memory pillar structures (158, 152, 154, 156, and 130) positioned above the first substrate 10L. Any suitable bonding can be used, such as metal-to-metal bonding, dielectric-to-dielectric bonding, or combinations thereof (i.e., hybrid bonding).

[0138] refer to Figure 33 Optionally, the first substrate 10L can be removed from the second conductive line 80 and reused to form an additional memory device. The first substrate can be removed by any suitable method. For example, similar to the method described in the first embodiment, the first substrate 10L can be removed by implanting hydrogen or deuterium into the bottom of the first substrate to form an implantation layer, and then annealing the first substrate to cut along the implantation layer. Alternatively, the first substrate 10L can be removed by grinding and polishing, as described in the second embodiment. Alternatively, a release layer (e.g., a silicon oxide or silicon nitride layer) can be formed between the first substrate 10L and the second conductive line 80, and then the release layer can be selectively etched to remove the first substrate 10L.

[0139] exist Figure 34In a first alternative aspect of the fourth embodiment shown, the stack of selector level layers 130L is formed over a first conductive line 120 positioned over a second substrate 110L, rather than over an MTJ stack 150L positioned over a first substrate 10L. If desired, the stack of selector level layers 130L can be patterned (e.g., by photolithography and etching) into selector elements 130 while positioned over a second substrate 100L, as... Figure 35 As shown. Then a dielectric isolation structure 160 is formed around the gate element 130.

[0140] In this alternative aspect, an MTJ stack 150L and an optional metal capping layer 158L are formed over a second conductive line 80 positioned above a first substrate 10L, as shown. Figure 36 As shown. The MTJ stack 150L and the metal capping layer 158L are patterned (e.g., by ion beam milling) while they are positioned above the first substrate 10L, as shown. Figure 37 As shown above and regarding Figure 24 The dielectric isolation structure 60 is then formed around the MTJ 150 pillar.

[0141] Then, as Figure 38 As shown, a second component, comprising a gate level layer 130L, a first conductive line 120, and a second substrate 110L, is bonded to a first component comprising a second conductive line 80, at least a portion of a memory cell (e.g., MTJ 150), and the first substrate 10L. After bonding, the MTJ 150 is positioned between the word line and the bit line.

[0142] Finally, as Figure 39 As shown, the first substrate 10L is then removed. Each corresponding MTJ 150 forms a memory cell positioned in the same memory pillar structure (130, 150, 158) as its corresponding selector element 130.

[0143] In other alternative aspects of the fourth embodiment, after the bonding step, the stack of selector level layers 130L can be patterned (e.g., by photolithography and etching) into selector element 130. In these other alternative aspects of the fourth embodiment, the MTJ stack 150L can be patterned into MTJ 150 before or after the bonding step. Therefore, MTJ 150 is not damaged during the high-temperature deposition of the stack of selector level layers 130L, and vice versa. Furthermore, if the MTJ stack 150L is patterned over a substrate different from the substrate supporting the stack of selector level layers 130L, the selector element 130 is not damaged during the ion beam polishing of the MTJ stack 150L.

[0144] For example, MTJ stack 150L can be patterned into MTJ 150 before the bonding step, such as... Figure 37 As shown. An unpatterned stack of the gate stage layer 130L is disposed above the second substrate 110L, as... Figure 40 As shown. In this alternative aspect, the first conductive line 120 can be omitted from the second substrate 110L. Then, the unpatterned stack of the selector stage layer 130L is bonded to the MTJ 150 positioned above the first substrate 10L, as shown. Figure 41 As shown. The second substrate 110L can be removed from the bonded assembly, and the stacked pattern of the gate level layer 130L is patterned (e.g., by photolithography and etching) into the gate element 130 after the bonding step. A dielectric isolation structure 160 is then formed around the gate element 130, as shown. Figure 42 As shown. Then, as described above, a first conductive line 120 is formed above the selector element 130.

[0145] Alternatively, the MTJ stack 150L positioned above the first substrate 10L is bonded to an unpatterned stack of the selector stage layer 130L positioned above the first conductive line 120 above the first substrate 10L, as shown below. Figure 43 As shown. In this embodiment, the second conductive line 80 can be omitted from above the first substrate 10L. For example... Figure 44 As shown, the first substrate 10L can be removed from the bonded components. After the bonding step, the MTJ stack 150L is patterned (e.g., by ion beam milling) into MTJ 150, and the stack of the selector level layer 130L is patterned (e.g., by photolithography and etching) into selector element 130. If the MTJ stack 150L is patterned into MTJ 150 after the bonding step, the stack of the selector level layer 130L and the MTJ stack 150L can be patterned sequentially during the common patterning step using different etching or milling steps for each set of layers. A second conductive line 80 is then formed over the MTJ 150 as described above to form Figure 33 The structure shown.

[0146] The third and fourth embodiments provide a method of forming a memory device (such as a PCM or MRAM device), the method comprising: providing a first component including a first substrate 10L, the first substrate including first conductive lines (e.g., 120 or 80) including word lines or bit lines; forming at least a portion of memory cells (330, 150) above the first conductive lines; providing a second component including a second substrate 110L, the second substrate including second conductive lines (e.g., 80 or 120) including the other of word lines or bit lines; and bonding the first component to the second component such that the memory cells are positioned between the first conductive lines and the second conductive lines. One of the first conductive lines includes a word line or bit line of the memory cell, and one of the second conductive lines includes the other of the word line or bit line of the memory cell.

[0147] The memory cells can be located in a memory column structure, which may further include a selector element 130 for the memory cells (330, 150) located in the memory column structure. The selector element 130 may include a bidirectional threshold switch.

[0148] In Figure 22 to Figure 27 In the third embodiment shown, the memory device includes a phase-change memory (PCM) device, and the memory cell includes a phase-change memory cell that includes a phase-change memory material plate 330. As discussed above, the method of the third embodiment includes: forming a selector level layer 130L over a phase-change material layer 330L positioned over conductive lines 80 and a first substrate 10L; patterning the selector level layer 130L to form a selector element 130; and patterning the phase-change material layer 30L to form a phase-change material plate 330 before bonding the first component to the second component, wherein the selector element 130 is positioned between the conductive lines 120 and the phase-change material plate 330.

[0149] In a fourth embodiment, the memory device includes a magnetoresistive random access memory (MRAM) device, and the memory cell includes an MRAM memory cell that includes a magnetic tunnel junction (MTJ) 150, the magnetic tunnel junction including a tunnel barrier plate 154 positioned between a ferromagnetic reference plate 152 and a ferromagnetic free plate 156. As discussed above, Figures 28A to 33The method of the fourth embodiment shown includes: forming an MTJ stack 150L including a tunnel barrier layer 154L positioned between a ferromagnetic reference layer 152L and a ferromagnetic free layer 156L, the ferromagnetic reference layer and the ferromagnetic free layer being positioned over a conductive line 90 and a first substrate 10; forming a selector stage layer 130L over the MTJ stack 150L; and patterning the selector stage layer and the MTJ stack to form selector elements 130 and MTJ 150. The step of bonding the first component to the second component occurs after the formation of the selector elements and the MTJ.

[0150] As discussed above, Figures 34 to 39 An alternative method of the fourth embodiment shown includes: forming an MTJ stack 150L including a tunnel barrier layer 154L positioned between a ferromagnetic reference layer 152L and a ferromagnetic free layer 156L, the ferromagnetic reference layer and the ferromagnetic free layer being positioned over conductive lines 80 and a first substrate 10L; patterning the MTJ stack to form an MTJ 150; forming a selector level layer 130L over conductive lines 120 positioned over a second substrate 110L; and patterning the selector level layer to form a selector element 130. The step of bonding the first component to the second component occurs after the formation of the selector element 130 and the formation of the MTJ 150, such that the selector element is bonded to the MTJ.

[0151] According to the first, second, and fourth embodiments, a method of forming a memory device (such as an FTJ or MRAM device) includes: providing a first component including at least a portion of memory cells (30, 150) positioned above a first substrate 10L; providing a second component including at least a portion of a selector element 130 positioned above a second substrate 110L; and bonding the first component to the second component such that the memory cells are bonded to their respective selector elements.

[0152] Memory cells and selector elements can be positioned within a memory pillar structure, and the selector elements can include a bidirectional threshold switch board, as described above. The method may also include removing at least one of the first substrate 10L or the second substrate 110L after the step of bonding the second layer stack to the first layer stack.

[0153] exist Figures 1A to 21B In the first and second embodiments shown, the memory device includes a ferroelectric tunnel junction (FTJ) memory device, and the memory cell includes a ferroelectric material layer 30 positioned between the first electrode and the second electrode (40, 50).

[0154] In the fourth embodiment, the memory device includes a magnetoresistive random access memory (MRAM) device, and the memory cell includes an MRAM memory cell that includes a magnetic tunnel junction (MTJ) 150 that includes a tunnel barrier 154 positioned between a ferromagnetic reference plate 152 and a ferromagnetic free plate 156.

[0155] Figures 34 to 39 An alternative aspect of the fourth embodiment shown includes: forming an MTJ stack 150L comprising a tunnel barrier layer 154L positioned between a ferromagnetic reference layer 152L and a ferromagnetic free layer 156L, the ferromagnetic reference layer and the ferromagnetic free layer being positioned over a first substrate 10L; patterning the MTJ stack 150L to form an MTJ 150 over the first substrate 10L; forming a selector level layer 130L over a second substrate 110L; and patterning the selector level layer 130L to form a selector element 130 over the second substrate 110L. The step of bonding the first component to the second component occurs after the formation of the selector element 130 and the formation of the MTJ 150, such that the selector element is bonded to the MTJ.

[0156] Figures 40 to 42 Another alternative aspect of the fourth embodiment shown includes: forming an MTJ stack 150L including a tunnel barrier layer 154L positioned between a ferromagnetic reference layer 152L and a ferromagnetic free layer 156L, the ferromagnetic reference layer and the ferromagnetic free layer being positioned over a first substrate 10L; patterning the MTJ stack 150L to form an MTJ 150; forming a selector level layer 130L over a second substrate 110L; removing the second substrate 110L; and patterning the selector level layer 130L after removing the second substrate 110L to form a selector element 130. The step of bonding the first component to the second component occurs after forming the MTJ 150 and before patterning the selector level layer 130L, such that the selector level layer 130L is bonded to the MTJ 150.

[0157] Figures 43 to 44Another alternative aspect of the fourth embodiment shown includes: forming an MTJ stack 150L including a tunnel barrier layer 154L positioned between a ferromagnetic reference layer 152L and a ferromagnetic free layer 156L, the ferromagnetic reference layer and the ferromagnetic free layer being positioned over a first substrate 10L; removing the first substrate 10L; forming a gate level layer 130L over a second substrate 110L; patterning the MTJ stack 150L to form an MTJ 150 and patterning the gate level layer 130L to form a gate element 130 after removing the first substrate 10L; and bonding the first component to the second component before patterning the MTJ stack 150L and before patterning the gate level layer 130L, such that the gate level layer 130L is bonded to the MTJ stack 150L.

[0158] The stacked and bonded memory devices of any embodiment of this disclosure can be repeated multiple times in the vertical direction to obtain a stacked memory device having multiple memory cell levels between multiple word line levels and bit line levels. For example, a second memory cell level (130, 140, 40, 30, 24, 50) can be formed by bonding over a second line 80 and then providing an additional first line 120 over the second memory cell level. Three or more memory levels can also be formed by continuing the bonding process.

[0159] While specific preferred embodiments have been mentioned above, it will be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. While embodiments employing specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, the memory device comprising: A first conductive line extends laterally along a first horizontal direction; A memory pillar structure that covers and contacts the first conductive line, wherein the memory pillar structure comprises, from bottom to top: A stack of a first metal material plate and a second metal material plate, wherein the first metal material plate is composed of a first element metal and the second metal material plate is composed of a second element metal, and is bonded to the first metal material plate at a bonding interface; Single-crystal ferroelectric material plates, including ferroelectric dielectric metal oxide materials having a first single-crystal structure; and A single-crystal semiconductor plate includes a semiconductor material having a second single-crystal structure, wherein the second single-crystal structure of the semiconductor material is epitaxially aligned with the first single-crystal structure of the ferroelectric dielectric metal oxide material at the interface between the semiconductor material and the ferroelectric dielectric metal oxide material; and The second conductive line extends laterally along a second horizontal direction and covers and contacts the memory pillar structure.

2. The memory device according to claim 1, wherein: The memory pillar structure also includes a selector material plate located below the first metal material plate; and The bonding interface is located between the gate material plate and the single-crystal ferroelectric material plate.

3. The memory device according to claim 2, further comprising: The lower electrode plate contacts the bottom surface of the selector material plate and comprises a first non-metallic conductive material; and The upper electrode plate contacts the top surface of the selector material plate and contains a second non-metallic conductive material.

4. The memory device according to claim 3, wherein: The selector material plate comprises a bidirectional threshold switch material; and Each of the first non-metallic conductive material and the second non-metallic conductive material is selected from amorphous carbon, amorphous boron-doped carbon, amorphous nitrogen-doped carbon, amorphous silicon, amorphous germanium, alloys thereof, or stacked layers thereof.

5. The memory device of claim 1, wherein the second metal material plate contacts the bottom surface of the first metal material plate.

6. The memory device of claim 5, wherein the second metal material plate is not in direct contact with the first conductive line.

7. The memory device of claim 1, wherein the ferroelectric material of the single-crystal ferroelectric material plate comprises doped or undoped hafnium dioxide having an orthorhombic phase.

8. The memory device of claim 1, wherein the single-crystal semiconductor plate contacts the entire top surface of the single-crystal ferroelectric material plate.

9. The memory device of claim 8, wherein the single-crystal semiconductor plate comprises single-crystal germanium or silicon germanium.

10. The memory device of claim 1, wherein the memory pillar structure includes a metal cover plate covering the single-crystal ferroelectric material plate and contacting the second conductive wire.

11. The memory device of claim 1, wherein the memory pillar structure further comprises a selector material plate.

12. The memory device of claim 11, wherein the selector material plate comprises a bidirectional threshold switch material.

13. The memory device of claim 1, wherein the memory pillar structure includes straight sidewalls, each sidewall extending perpendicularly from the first conductive line to the second conductive line.

14. The memory device of claim 1, further comprising a dielectric isolation structure that laterally surrounds and contacts the memory pillar structure.

15. A method of forming a memory device, the method comprising: A first substrate having a single-crystal semiconductor layer therein or thereon is provided; A single-crystal ferroelectric material layer is epitaxially grown on the single-crystal semiconductor layer; A first metal material layer is formed on the single crystal ferroelectric material layer to form a first layer stack including at least the single crystal ferroelectric material layer and the first metal layer; A second layer stack comprising a gate material layer and a second metal material layer is formed over the second substrate; as well as Bond the second layer stack to the first layer stack; and The step of bonding the second layer stack to the first layer stack includes bonding the second metal material layer to the first metal material layer; and The first metal material layer is composed of a first element metal, and the second metal material layer is composed of a second element metal, and is bonded to the first metal material layer at the bonding interface.

16. The method of claim 15, further comprising forming a memory pillar structure by patterning at least the single-crystal ferroelectric material layer and the first metal material layer.

17. The method of claim 16, further comprising forming a hydrogen implantation layer or a deuterium implantation layer within the single-crystal semiconductor layer, wherein the single-crystal semiconductor layer is divided into a proximal single-crystal semiconductor layer and a distal single-crystal semiconductor layer by the hydrogen implantation layer, and wherein the single-crystal ferroelectric material layer is formed on the distal single-crystal semiconductor layer.

18. The method of claim 17, further comprising dicing the first layer stack comprising the distal single-crystal semiconductor layer, the single-crystal ferroelectric material layer, and the first metal material layer from the assembly comprising the near-side single-crystal semiconductor layer and the first substrate.

19. The method of claim 18, wherein: At least one memory pillar structure is formed by further patterning the second layer stack, which includes the gate material layer and the second metal material layer.

20. The method of claim 16, further comprising forming a first conductive line over the second substrate, wherein a second layer stack of the selector material layer and the second metal material layer is formed over the first conductive line.

21. The method of claim 20, further comprising forming a second conductive line above the memory pillar structure.

22. The method of claim 15, further comprising removing the second substrate after the step of bonding the second layer stack to the first layer stack.

23. A method of forming a memory device, the method comprising: A first component is provided, including a first substrate, the first substrate comprising a first conductive line including a word line or a bit line; At least a portion of a memory cell is formed above the first conductive line; A second component is provided, including a second substrate, the second substrate comprising a second conductive line including another of word lines or bit lines; as well as The first component is bonded to the second component such that the memory cell is positioned between the first conductive line and the second conductive line, wherein one of the first conductive lines includes a word line or a bit line of the memory cell, and one of the second conductive lines includes the other of the word line or bit line of the memory cell; and The memory device includes a ferroelectric tunnel junction (FTJ) memory device, and the memory cell includes a ferroelectric material layer positioned between a first electrode and a second electrode; and The method further includes: The ferroelectric material layer is epitaxially grown over the first substrate; A first metallic material layer is formed on the ferroelectric material layer to form a first layer stack including at least the ferroelectric material layer and the first metallic layer; and A second layer stack comprising a gate material layer and a second metal material layer is formed over the second substrate, wherein the step of bonding the first component to the second component includes bonding the second layer stack to the first layer stack; and The first metal material layer is composed of a first element metal, and the second metal material layer is composed of a second element metal, and is bonded to the first metal material layer at the bonding interface.

24. The method of claim 23, wherein the memory cell is located in a memory column structure.

25. The method of claim 24, further comprising a gate element of the memory cell located in the memory column structure.

26. The method of claim 25, wherein the selector element comprises a bidirectional threshold switch board.

27. The method of claim 25, wherein the memory device comprises a phase-change memory device, and the memory cell comprises a phase-change memory cell, the phase-change memory cell comprising a phase-change memory material plate.

28. The method of claim 27, further comprising: A gate-level layer is formed above a phase change material layer positioned above the first conductive line and the first substrate; as well as Before bonding the first component to the second component, the gate level layer is patterned to form the gate element and the phase change material layer is patterned to form a phase change material plate, wherein the gate element is positioned between the second conductive line and the phase change material plate.

29. The method of claim 25, wherein the memory device comprises a magnetoresistive random access memory (MRAM) device, and the memory cell comprises an MRAM memory cell comprising a magnetic tunnel junction (MTJ) including a tunnel barrier plate positioned between a ferromagnetic reference plate and a ferromagnetic free plate.

30. The method according to claim 29, further comprising: An MTJ stack is formed, the MTJ stack including a tunnel barrier layer positioned between a ferromagnetic reference layer and a ferromagnetic free layer, the ferromagnetic reference layer and the ferromagnetic free layer being positioned above a first conductive line and a first substrate; A gate-level layer is formed above the MTJ stack; as well as The gating layer and the MTJ stack are patterned to form the gating element and the MTJ, wherein the step of bonding the first component to the second component occurs after the gating element and the MTJ are formed.

31. The method according to claim 29, further comprising: An MTJ stack is formed, the MTJ stack including a tunnel barrier layer positioned between a ferromagnetic reference layer and a ferromagnetic free layer, the ferromagnetic reference layer and the ferromagnetic free layer being positioned above a first conductive line and a first substrate; The MTJ stack is patterned to form the MTJ; A gate-level layer is formed above the second conductive line positioned above the second substrate; as well as The gating layer is patterned to form the gating element, wherein the step of bonding the first component to the second component occurs after the gating element is formed and the MTJ is formed, such that the gating element is bonded to the MTJ.

32. A method of forming a memory device, the method comprising: A first component is provided, comprising at least a portion of a memory cell positioned above a first substrate; A second assembly is provided, including at least a portion of a selector element positioned above a second substrate; as well as The first component is bonded to the second component, such that the memory cell is bonded to its corresponding gate element; and The memory cells and the selector elements are positioned within a memory column structure; and The memory device includes a ferroelectric tunnel junction (FTJ) memory device, and the memory cell includes a ferroelectric material layer positioned between a first electrode and a second electrode; and The method further includes: The ferroelectric material layer is epitaxially grown over the first substrate; A first metallic material layer is formed on the ferroelectric material layer to form a first layer stack including at least the ferroelectric material layer and the first metallic layer; and A second layer stack comprising a gate material layer and a second metal material layer is formed over the second substrate, wherein the step of bonding the first component to the second component includes bonding the second layer stack to the first layer stack; and The first metal material layer is composed of a first element metal, and the second metal material layer is composed of a second element metal, and is bonded to the first metal material layer at the bonding interface.

33. The method of claim 32, wherein the selector element comprises a bidirectional threshold switch board.

34. The method of claim 32, further comprising forming the memory pillar structure by patterning at least the ferroelectric material layer, the first metal material layer, the selector material layer and the second metal material layer.

35. The method of claim 32, wherein the memory device comprises a magnetoresistive random access memory (MRAM) device, and the memory cell comprises an MRAM memory cell comprising a magnetic tunnel junction (MTJ) including a tunnel barrier plate positioned between a ferromagnetic reference plate and a ferromagnetic free plate.

36. The method according to claim 35, further comprising: An MTJ stack is formed, including a tunnel barrier layer positioned between a ferromagnetic reference layer and a ferromagnetic free layer, wherein the ferromagnetic reference layer and the ferromagnetic free layer are positioned above the first substrate; The MTJ stack is patterned to form the MTJ over the first substrate; A gate-level layer is formed above the second substrate; as well as The gate level layer is patterned to form the gate element over the second substrate, wherein the step of bonding the first component to the second component occurs after the formation of the gate element and the formation of the MTJ, such that the gate element is bonded to the MTJ.

37. The method according to claim 36, further comprising: An MTJ stack is formed, including a tunnel barrier layer positioned between a ferromagnetic reference layer and a ferromagnetic free layer, wherein the ferromagnetic reference layer and the ferromagnetic free layer are positioned above the first substrate; The MTJ stack is patterned to form the MTJ; A gate-level layer is formed above the second substrate; Remove the second substrate; as well as After the second substrate is removed, the gate level layer is patterned to form the gate element, wherein the step of bonding the first component to the second component occurs after the MTJ is formed and before the gate level layer is patterned, such that the gate level layer is bonded to the MTJ.

38. The method according to claim 36, further comprising: An MTJ stack is formed, including a tunnel barrier layer positioned between a ferromagnetic reference layer and a ferromagnetic free layer, wherein the ferromagnetic reference layer and the ferromagnetic free layer are positioned above the first substrate; Remove the first substrate; A gate-level layer is formed above the second substrate; After the first substrate is removed, the MTJ stack is patterned to form the MTJ and the gate level layer is patterned to form the gate element, wherein the step of bonding the first component to the second component occurs before the MTJ stack is patterned and before the gate level layer is patterned, such that the gate level layer is bonded to the MTJ stack.

39. The method of claim 32, further comprising removing at least one of the first substrate or the second substrate after the step of bonding the first component to the second component.

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