Bilateral Majorana fermion quantum computing device fabricated using ion implantation

Abstract

A quantum computing device is fabricated by forming a first resist pattern defining a device region and a sensing region within the device region on a superconducting layer (410). The superconducting layer within the sensing region is removed, thereby exposing a region of a first surface of an underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted to form an isolation region surrounding the device region. The sensing region and a portion of the device in the superconducting layer are exposed. A sensing region contact (202) is formed by coupling the first surface of the semiconductor layer to a first metal layer. Nanopillar contacts (206, 212) are formed using a first metal within the portion of the device region outside the sensing region. A tunnel junction gate (204) is formed by depositing a second metal layer on a second surface of the semiconductor layer within the sensing region.

Description

Technical Field

[0001] This invention generally relates to superconducting devices, manufacturing methods, and manufacturing systems for superconducting quantum devices. More specifically, this invention relates to devices, methods, and systems for fabricating two-side Majorana fermion quantum computing devices using ion implantation. Background Technology

[0002] In the following text, unless explicitly distinguished in use, the “Q” prefix in a word or phrase indicates a reference to that word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, the branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, simultaneously existing in more than one state and interacting with other particles very far away. Quantum computing utilizes these quantum phenomena to process information.

[0004] The computers we use today are called classic computers (also referred to in this article as “traditional” computers or traditional nodes, or “CN”). Traditional computers use traditional processors, which are manufactured using semiconductor materials and technologies, semiconductor memory, and magnetic or solid-state storage devices, a process known as the von Neumann architecture. Specifically, the processors in traditional computers are binary processors, meaning they operate on binary data represented by 1s and 0s.

[0005] Quantum processors (q-processors) utilize the exotic properties of entangled qubit devices (concisely referred to as "qubits" in this paper) to perform computational tasks. In specific areas of quantum mechanics, particles of matter can exist in multiple states, such as "on," "off," and simultaneously "on" and "off." Where binary computation using semiconductor processors is limited to using only on and off states (equivalent to 1 and 0 in binary code), quantum processors leverage these quantum states of matter to output signals that can be used for data computation.

[0006] Traditional computers encode information using bits. Each bit can take the value 1 or 0, and these 1s and 0s are used as on / off switches that ultimately drive the computer's functionality. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can simultaneously represent 1 and 0. Entanglement means that qubits in a superposition can be correlated with each other in a non-classical way; that is, the state of one qubit (either 1 or 0 or both) can depend on the state of the other qubit, and when two qubits are entangled, more information about the two qubits can be determined than when they are treated individually.

[0007] Using these two principles, qubits function as more sophisticated information processors, enabling quantum computers to solve problems that are difficult to handle with conventional computers. IBM has successfully built and demonstrated the operability of a quantum processor using superconducting qubits (IBM is a registered trademark of International Business Machines Corporation in the U.S. and other countries).

[0008] In the superconducting state, firstly, the material does not resist the passage of electric current. When the resistance drops to zero, the current can circulate within the material without any energy dissipation. Secondly, the material exhibits the Meissner effect, meaning that external magnetic fields will not penetrate the superconductor, but will remain on its surface, provided they are weak enough. When a material no longer exhibits one or both of these properties, it is said to be in the normal state and no longer superconducting.

[0009] The critical temperature of a superconducting material is the temperature at which the material begins to exhibit superconducting properties. Superconducting materials exhibit very low or zero resistivity to electric current. For a given temperature, the critical magnetic field is the highest magnetic field at which the material maintains its superconductivity.

[0010] Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical magnetic field. When the critical magnetic field is reached, a Type I superconductor transitions from a non-superconducting state to a superconducting state. Type II superconductors involve two critical magnetic fields and two transitions. At or below the lower critical magnetic field, a Type II superconductor exhibits superconductivity. Above the upper critical magnetic field, a Type II superconductor does not exhibit superconductivity. Between the upper and lower critical magnetic fields, a Type II superconductor exhibits a mixed state. In the mixed state, a Type II superconductor exhibits an incomplete Meissner effect, meaning that an external magnetic field penetrates the superconducting material in quantized clusters at specific locations.

[0011] Information processed by qubits is carried or transmitted as microwave signals / photons in the microwave frequency range. These microwave signals are captured, processed, and analyzed to decipher the quantum information encoded within them. A readout circuit is a circuit coupled to the qubit to capture, read, and measure its quantum state. The output of the readout circuit is information that can be used by a q-processor to perform calculations.

[0012] Superconducting qubits possess two quantum states – |0> and |1>. These two states can be the two energy states of an atom, for example, the ground state (|g>) and the first excited state (|e>) of a superconducting artificial atom (superconducting qubit). Other examples include spin-up and spin-down of the nucleus or electron spin, the two locations of crystal defects, and the two states of a quantum dot. Due to the quantum nature of the system, any combination of the two states is permissible and valid.

[0013] In known semiconductor manufacturing techniques, superconducting devices such as qubits are fabricated using superconducting and semiconductor materials. Superconducting devices typically use one or more layers of different materials to implement the device's performance and function. The layers of material can be superconducting, conductive, semiconducting, insulating, resistive, inductive, capacitive, or possess any number of other properties. Given the properties of the material, its shape, size, or arrangement, other materials adjacent to it, and many other considerations, different layers of material can be formed using different methods.

[0014] Software tools used to design semiconductor and superconducting devices are manufactured, operated, or otherwise integrated with electrical layouts and device assemblies on a very small scale. When formed in a suitable substrate, these tools can manipulate some of the components that may only measure spans of a few nanometers.

[0015] Layout includes shape, the shape and position of which are selected in the tooling according to the target of the device. Once the design layout (also simply called layout) for a device or a group of devices has been completed, the design is converted into a set of masks or photomasks. A set of masks or photomasks is one or more masks or photomasks. During manufacturing, a semiconductor wafer is exposed to light or radiation through a mask to form microscopic components including structures. This process is called photolithography. Photomasks are used to fabricate or print the contents of a mask onto a wafer. During the photolithography printing process, radiation is focused through the mask and at a desired intensity. This intensity of radiation, combined with any material used for radiation deposition, is often referred to as the "dose." The focusing and configuration of the dose of radiation are controlled to achieve the desired shape and electrical properties on the wafer.

[0016] A manufacturing process for semiconductor or superconducting devices includes not only the application of a dosage but also other methods of depositing and / or removing materials having various electrical and / or mechanical properties. For example, an ion beam of a conductive material can be used to deposit the conductive material; hard insulators can be dissolved using chemicals or etched using mechanical design. Examples of operations in these manufacturing processes are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other operations that can be used in the manufacturing process for fabricating devices according to the illustrative embodiments, and these operations can be conceived within the scope of the illustrative embodiments.

[0017] Superconducting devices are typically planar, meaning the superconducting structure is fabricated on a plane. Non-planar devices are three-dimensional (3D) devices, where some parts of the structure are formed above or below a given fabrication plane.

[0018] Quantum gates perform operations on qubits. Quantum gates are analogous to basic operations in classical computing, such as AND, OR, and NOT gates, and are often used as building blocks for more complex operations on qubits. Topological quantum computing is a method of quantum computing in which quantum gates are generated by braiding anyons, a specific type of topological quantum object. Devices implementing topological quantum computing offer the possibility of longer coherence times than conventional quantum computing devices, and therefore provide greater fault tolerance while possessing computational capabilities similar to conventional quantum computing devices.

[0019] One implementation of anyon suitable for topological quantum computing is the Majorana quasiparticle, also known as a Majorana zreo mode (MZM) or Majorana fermion. Therefore, topological quantum computing involves manipulating MZMs and measuring their states, and Majorana fermion quantum computing devices realize MZM manipulation and state measurement. Summary of the Invention

[0020] Illustrative embodiments provide quantum computing devices. Embodiments include a device region on a superconducting layer located above a first surface of a semiconductor layer. Embodiments include a sensing region within the device region, comprising a portion of the device region in which the superconducting layer has been removed. Embodiments include sensing region contacts comprising a first metal coupled to the first surface of the semiconductor layer within the sensing region. Embodiments include nanopillar contacts comprising a first metal coupled to a portion of the semiconductor layer outside the sensing region of the device region. Embodiments include a tunnel junction gate comprising a second metal within the sensing region, the tunnel junction gate being disposed on a second surface of the semiconductor layer. Embodiments include a chemical potential gate comprising a second metal within a portion of the device region outside the sensing region, the chemical potential gate being disposed on the second surface of the semiconductor layer.

[0021] The embodiments include a method for manufacturing a quantum computing device. The embodiments include a manufacturing system for manufacturing a quantum computing device. Attached Figure Description

[0022] The appended claims set forth novel features that are considered characteristic of the invention. However, the invention itself, its preferred modes of use, further objects and advantages will be best understood by referring to the following detailed description of illustrative embodiments taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 A block diagram of a network in which an illustrative embodiment of a data processing system may be implemented is depicted;

[0024] Figure 2A bilateral Majorana fermion quantum computing device fabricated by ion implantation according to an illustrative embodiment is depicted;

[0025] Figure 3 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0026] Figure 4 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0027] Figure 5 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0028] Figure 6 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0029] Figure 7 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0030] Figure 8 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0031] Figure 9 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0032] Figure 10 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0033] Figure 11 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0034] Figure 12 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0035] Figure 13 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0036] Figure 14 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0037] Figure 15 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0038] Figure 16 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0039] Figure 17 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0040] Figure 18 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0041] Figure 19 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0042] Figure 20 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0043] Figure 21 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0044] Figure 22 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0045] Figure 23 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0046] Figure 24 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0047] Figure 25 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0048] Figure 26 A block diagram depicts an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment;

[0049] Figure 27A block diagram depicts an example construction achieved in the fabrication of a Majorana fermionic quantum computing device according to an illustrative embodiment; and

[0050] Figure 28 A flowchart depicts an example process for fabricating a Majorana fermion quantum computing device according to an illustrative embodiment. Detailed Implementation

[0051] The illustrative embodiments recognize that while devices for realizing topological quantum computing are desirable, there are difficulties in fabricating such devices. For Majorana fermion quantum computing devices to function correctly, the films and interfaces between device layers must be above a particularly high quality threshold; however, conventional device processing techniques such as reactive ion etching (RIE), cleaning processes, and air oxidation can damage film and layer surfaces, causing the quality to drop below this threshold. Furthermore, if a dielectric film is used in the discrete structure, trapped charges in the dielectric film can generate quasiparticles, resulting in uncontrolled electron densities that can cause qubit quenching. In addition, multiple structures, including semiconductor and superconductor components, regions for measuring MZM states, gates, contacts, and wires, must be integrated into a single device. Therefore, the illustrative embodiments recognize an unmet need to fabricate Majorana fermion quantum computing devices using techniques that produce sufficiently high-quality films and surfaces, avoid damaging RIE and cleaning processes, and avoid using dielectric films. Furthermore, the illustrative embodiments recognize that, for efficient manufacturing, the process flow for fabricating Majorana fermion quantum computing devices should have as few masking steps as possible. Additionally, the illustrative embodiments recognize that arranging the device gates and contacts on both sides of the device improves the wiring routing between devices.

[0052] The illustrative embodiments used to describe the present invention generally address and resolve the aforementioned problems or needs, as well as other related problems or needs, by providing a bilateral Majorana fermion quantum computing device fabricated by ion implantation. The illustrative embodiments also provide a novel method for fabricating the bilateral Majorana fermion quantum computing device fabricated by ion implantation. The illustrative embodiments also provide a system for fabricating the bilateral Majorana fermion quantum computing device fabricated by ion implantation. In particular, exemplary embodiments provide in-situ growth of semiconductor and superconductor structures using known epitaxial processes for III-V quantum wells to generate high-quality films and interfaces between films. The illustrative embodiments provide the use of low-dose ion implantation to define circuit regions, thereby avoiding damage to the RIE and cleaning processes, and altering film conductivity, thereby avoiding the use of dielectric films. Furthermore, gentle wet etching is used to remove the superconductor from the desired regions, and gentle lift-off patterning is used to form the wiring structure.

[0053] Refer to the attached diagram, and specifically refer to... Figure 1 These figures are example diagrams of a data processing environment in which illustrative embodiments can be implemented. Figure 1 This is merely an example and is not intended to assert or imply any limitation regarding the environments in which different embodiments may be implemented. Specific implementations may make many modifications to the depicted environment based on the following description.

[0054] Figure 1 A block diagram of a network in which an illustrative embodiment of a data processing system may be implemented is described. Data processing environment 100 is a computer network in which the illustrative embodiment may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0055] The client or server are merely example roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Servers 104 and 106 are coupled to network 102 along with storage unit 108. Software applications can execute on any computer in the data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. Data processing systems such as server 104 or 106 or clients 110, 112, or 114 can contain data and can have software applications or software tools executing on them.

[0056] Device 132 is an example of a mobile computing device. For example, device 132 may take the form of a smartphone, tablet computer, laptop computer, client 110 in fixed or portable form, wearable computing device, or any other suitable device. Described as being in Figure 1 Any software application executing in another data processing system within the device can be configured to execute in a similar manner in device 132. Figure 1 Any data or information stored or generated in another data processing system can be configured to be stored or generated in device 132 in a similar manner.

[0057] Application 105 implements the embodiments described herein. Manufacturing system 107 is a software component of any suitable system for manufacturing quantum devices. Typically, manufacturing systems and corresponding software components for manufacturing superconducting devices, including devices for quantum computing purposes, are known. Application 105 provides instructions to such a known manufacturing system via manufacturing application 107 for assembling a novel bilateral Majorana fermion quantum computing device fabricated using the ion implantation method considered in the illustrative embodiments, in a manner described herein.

[0058] The embodiments provide a bilateral Majorana fermion quantum computing device fabricated using ion implantation according to an illustrative embodiment. The device includes a superconducting layer above a semiconductor layer, a sensing region, sensing region contacts within the sensing region, and nanopillar contacts outside the sensing region, both disposed on a first surface of the device. The device also includes a tunnel junction gate within the sensing region and a chemical potential gate outside the sensing region, both disposed on a second surface of the device. The device is surrounded by an isolation region.

[0059] The embodiments provide a novel design and fabrication method for a bilateral Majorana fermion quantum computing device fabricated by ion implantation according to illustrative embodiments. In this embodiment, a design / fabrication system designs and fabricates a bilateral Majorana fermion quantum computing device fabricated by ion implantation.

[0060] Another embodiment provides a method for fabricating a bilateral Majorana fermion quantum computing device using ion implantation, such that the method can be implemented as a software application. Applications implementing this fabrication method embodiment can be configured to operate in conjunction with existing superconducting fabrication systems (e.g., photolithography systems).

[0061] For clarity of description, and without implying any limitation thereof, an illustrative embodiment is described using an example number of Majorana fermion manipulation and measurement structures arranged on a substrate. Within the scope of the illustrative embodiment, an embodiment may be implemented with different numbers of structures, different arrangements of structures, superconducting devices other than those used to form qubits, or other types of quantum computing devices, or some combination thereof.

[0062] Furthermore, simplified diagrams of the exemplary structures are used in the accompanying drawings and illustrative embodiments. In the actual fabrication of Majorana fermion quantum computing devices, additional structures not shown or described herein, or structures different from those shown and described herein, may exist without departing from the scope of the illustrative embodiments. Similarly, within the scope of the illustrative embodiments, the structures shown or described in the exemplary devices may be fabricated differently to produce similar operations or results as described herein.

[0063] As described herein, the different shaded areas in the two-dimensional diagrams of the exemplary structures, layers, and formations are intended to represent different structures, layers, materials, and formations in exemplary fabrication. Different structures, layers, materials, and constructions can be fabricated using suitable materials known to those skilled in the art.

[0064] The specific shapes, positions, orientations, or dimensions described herein are not intended to limit the exemplary embodiments unless such features are explicitly described as characteristics of the embodiments. The shapes, positions, dimensions, quantities, or combinations thereof were chosen solely for clarity of the drawings and description and may have been exaggerated, minimized, or otherwise modified relative to the actual shapes, positions, orientations, or dimensions that might be used in actual lithography to achieve the objectives according to the illustrative embodiments.

[0065] Furthermore, illustrative embodiments are described, by way of example only, with respect to specific real or hypothetical superconducting devices, such as currently feasible qubits. The steps described by the various illustrative embodiments can be adapted to fabricate various quantum computing devices in a similar manner, and such adaptations are contemplated within the scope of the illustrative embodiments.

[0066] When implemented in an application, the embodiments cause the manufacturing process to perform certain steps as described herein. The steps of the manufacturing process are illustrated in several accompanying drawings. Not all steps are necessary in a particular manufacturing process. Some manufacturing processes may implement steps in a different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other steps without departing from the scope of the illustrative embodiments.

[0067] These illustrative embodiments are described by way of example only, relating to certain types of materials, electrical properties, thermal properties, structures, formations, shapes, layer orientations, directions, steps, operations, planes, dimensions, quantities, data processing systems, environments, components, and applications. Any particular manifestation of these and other similar human-made elements is not intended to limit the invention. Any suitable manifestation of these and other similar products may be chosen within the scope of the exemplary embodiments.

[0068] Illustrative embodiments have been described using specific designs, architectures, layouts, diagrams, and tools. These are merely examples and not intended to limit the scope of the illustrative embodiments. The illustrative embodiments may be used in conjunction with other equivalent or similar designs, architectures, layouts, diagrams, and tools for similar purposes.

[0069] The examples in this disclosure are for illustrative purposes only and are not intended to limit the scope of the illustrative embodiments. Any advantages listed herein are merely examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be achieved through specific illustrative embodiments. Furthermore, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0070] refer to Figure 2 The figure depicts a bilateral Majorana fermion quantum computing device fabricated using ion implantation according to an illustrative embodiment.

[0071] In particular, Figure 2A top view and cross-sectional view of device 200 are depicted. Device 200 is a Majorana fermion quantum computing device fabricated by ion implantation according to an illustrative embodiment. Device 200 includes at least two nanopillar structures 230 and 232 configured as a superconducting island surrounded by an isolation region 240. Both nanopillar structures 230 and 232 are connected to a sensing region. In one embodiment, nanopillar structures 230 and 232 are substantially parallel to each other, and one end of each of nanopillar structures 230 and 232 is connected to the sensing region. In another embodiment, nanopillar structures 230 and 232 are substantially perpendicular to each other. In yet another embodiment, nanopillar structures 230 and 232 intersect at an angle. Each nanopillar structure includes a semiconductor portion of a semiconductor layer 340 whose surface is covered by a protective layer 350 and a superconducting portion of a superconducting layer 410.

[0072] Each nanopillar structure has dimensions suitable for enabling the nanowire to act as a one-dimensional topological superconductor, wherein the chemical potential and magnetic field are tuned such that when the metal in the superconducting portions of nanopillar structures 230 and 232 is made superconducting (e.g., by lowering the temperature of the metal to a specified cryogenic temperature), the nanopillars accommodate MZMs at each end, and device 200 is operable. Specifically, layers 330 and 350 help confine charge carriers within layer 340, which functions as a type of quantum well. In one embodiment, each nanopillar structure is 200 nanometers wide and 1 micrometer long, although smaller dimensions and different aspect ratios are also possible and considered within the scope of the exemplary embodiments.

[0073] Using MZMs in quantum computing devices requires the ability to perform parity measurements of MZM pairs. An illustrative embodiment uses a quantum dot-based measurement scheme to perform MZM parity measurements. Specifically, quantum dot 220, a portion of the sensing region of device 200, is a semiconductor line connected to one end of each of nanopillar structures 230 and 232. A tunnel junction gate 204 is used to control the amplitude of electron tunneling between the quantum dot 220 and the MZMs in nanopillar structures 230 and 232, to which the quantum dot 220 can be selectively coupled. When not measuring MZM states, all coupling is turned off, leaving the MZM islands and quantum dots with a fixed charge. In the decoupled state, ambient noise coupled to the charge has no effect on the MZMs. Therefore, noise cannot measure the qubit states unless a measurement is in progress, and thus causes the qubit states to collapse. To measure MZM states, the tunnel junction gate is activated, causing an energy shift observable using, for example, the quantum dot charge.

[0074] Sensing region contact 202 is coupled to quantum dot 220 and is used to sense the electron density in the quantum dot. Nanopillar contacts 206 and 212 are coupled to the superconducting portion of nanopillar structure 230 and are used to guide current through the superconducting portion of nanopillar structure, thereby imparting superconductivity to the surface of the semiconductor portion of nanopillar structure to enable device 200 to function. Chemical potential gates 208 and 210 are used to modulate the chemical potential of nanopillars such that the nanopillars accommodate MZM at each end. Tunnel junction gate 204 also includes a dielectric portion coupled to the superconducting portion and a metallic portion coupled to the dielectric portion, and is used to pinch off the conductivity of the nanopillars during device operation. Sensing region contact 202, tunnel junction gate 204, and quantum dot 220 together constitute the sensing region of device 200.

[0075] refer to Figure 3 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 300 as described herein. Semiconductor layer 340 and protective layer 350... Figure 2 The semiconductor layer 340 and the protective layer 350 are the same.

[0076] Substrate 310 comprises a material that, when operating in a low-temperature range, exhibits a residual resistance ratio (RRR) of at least 100 and a thermal conductivity greater than 1 W / (cm×K) at 4 Kelvin. RRR is the ratio of the resistivity of the material at room temperature to that at 0 K. Because 0 K cannot be reached in practice, an approximation at 4 K is used. For example, substrate 310 may be formed using sapphire, silicon, quartz, gallium arsenide (GaAs), fused silica, amorphous silicon, indium phosphide (InP), or diamond to operate in a temperature range from 77 K to 0.01 K. These examples of substrate materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming substrate 310, and such materials are contemplated within the scope of the illustrative embodiments.

[0077] The embodiments enable the fabrication system to epitaxially grow a buffer layer 320, an epitaxial semiconductor, on a substrate 310. The material of the buffer layer 320 is selected based on the composition of the substrate 310 and the protective layer 330. In one embodiment, the buffer layer 320 is formed of indium aluminum arsenide (InAlAs) to match the lattice of the adjacent protective layer 330. In one embodiment, the buffer layer 320 has a gradually changing composition from the substrate 310 to the protective layer 330 to avoid the formation of crystal defects, such as dislocations, in the protective layer 330. In one embodiment, the gradual change in composition is linear. For example, if the substrate 310 comprises GaAs and the protective layer 330 comprises InAs, it is difficult to grow a sufficiently high-quality InAs layer directly on the GaAs of the substrate 310. Therefore, the buffer layer 320 begins with the substrate 310 having GaAs, and the gallium is gradually replaced by indium to eventually match the InAs of the protective layer 330. These examples of materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the buffer layer 320, and such materials can be envisioned within the scope of the exemplary embodiments.

[0078] The embodiments allow the manufacturing system to epitaxially grow a protective layer 330, an epitaxial semiconductor, on a buffer layer 320. The materials used for protective layers 330 and 350 are selected based on the composition of semiconductor layer 340 to provide crystal quality above a specific quality threshold. In embodiments where semiconductor layer 340 uses InAs in a 1:1 ratio, protective layers 330 and 350 use indium gallium arsenide (InGaAs) in a ratio of 0.8In:1Ga:0.2As. In embodiments where semiconductor layer 340 uses indium gallium arsenide (InGaAs) in a ratio of 0.7In:1Ga:0.3As, protective layers 330 and 350 use indium gallium arsenide (InGaAs) in a ratio of 0.53In:1Ga:0.47As or 0.52In:1Ga:0.48As. In embodiments where semiconductor layer 340 uses InSb, protective layers 330 and 350 use In0.80-0.90Al0.1-0.2Sb (InAlSb in a ratio of 1 In to 0.8-0.9 Al to 0.1-0.2 Sb). In embodiments using InP as the substrate, protective layer 330 is lattice-matched to the InP of substrate 310. However, protective layers 330 and 350 need not be formed of the same material. Furthermore, protective layer 350 is not required. These examples of materials are not limiting. From this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming protective layers 330 and 350, and such materials are contemplated within the scope of the exemplary embodiments. In one embodiment, protective layer 330 is approximately 4 nm thick, although thicker or thinner layers are also possible and contemplated within the scope of the illustrative embodiments.

[0079] The embodiments allow the manufacturing system to epitaxially grow a semiconductor layer 340 on a protective layer 330. In these embodiments, the semiconductor layer 340 is formed of indium arsenide (InAs) in a 1:1 In:As ratio, indium gallium arsenide (InGaAs) in a 0.7In:1Ga:0.3As ratio, or indium antimony (InSb). These examples of substrate materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the substrate 310, and such materials are contemplated within the scope of the illustrative embodiments. In one embodiment, the semiconductor layer 340 is approximately 7 nm thick, although thicker or thinner layers are also possible and considered to be within the scope of the exemplary embodiments.

[0080] The embodiment enables the manufacturing system to epitaxially grow a protective layer 350 on a semiconductor layer 340, and an epitaxial semiconductor.

[0081] In one embodiment, the protective layer 350 is approximately 5 nm thick, although thicker or thinner layers are also possible and considered within the scope of the exemplary embodiments. Protective layers 330 and 350 protect the surface of the semiconductor layer 340 from damage during manufacturing. Damaged portions of the semiconductor layer 340 can degrade device performance. Therefore, if the risk of damage during manufacturing is sufficiently low, the protective layer 350 may not be necessary on top of the quantum dot structure. Furthermore, protective layers 330 and 350 need not be made of the same material.

[0082] refer to Figure 4 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 400 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, and protective layer 350... Figure 3 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340 and protective layer 350 are the same.

[0083] The embodiments employ a manufacturing system using physical vapor deposition (PVD), such as evaporation or sputtering, to deposit a superconducting layer 410 on a protective layer 350 (or a semiconductor layer 340, if a protective layer 350 is not used). The superconducting layer 410 is formed of a material that is superconducting in a low-temperature range of 77 K to 0.01 K. Aluminum (Al), niobium, lead, tantalum nitride, titanium, titanium nitride, and vanadium are non-limiting examples of suitable materials for the superconducting layer 410, although many other materials are suitable for forming the superconducting layer 410, and the same materials are contemplated within the scope of the exemplary embodiments. In the embodiments, the thickness of the superconducting layer 410 is between 5 and 50 nm, preferably between 20 and 30 nm, although thicker or thinner layers are also possible and considered to be within the scope of the exemplary embodiments.

[0084] refer to Figure 5 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 500 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, and superconductor layer 410... Figure 4 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350 and superconductor layer 410 are the same.

[0085] The embodiment allows the fabrication system to deposit a resist layer 510 formed with a resist pattern on the superconductor layer 410. The resist pattern protects the nanopillar regions 520 and 530 and the sensing region 540 from upcoming device processing steps. The resist layer 510 can be formed from any resist material used in photolithography.

[0086] The depiction of the resist layer formed in the resist pattern and the depiction of the photolithography technique should not be construed as limiting the manner in which the structures described herein are formed. The depicted patterns are merely simplified and generalized examples. The depicted structures can be photolithographically shaped in many ways. For example, the described structures are currently achieved by patterning the resist with photolithography (light) or electron beam lithography (electron beam), developing the resist, and then subtracting the deposited material from openings in the resist or depositing material in openings in the resist. Finally, the resist is removed. Manufacturing processes and techniques are constantly evolving, and other methods of forming the described structures are within the scope of consideration for the illustrative embodiments, provided that the resulting structures have the electrical, mechanical, thermal, and operational properties as described herein.

[0087] refer to Figure 6 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 600 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and resist layer 510... Figure 5 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and resist layer 510 are the same.

[0088] The embodiment causes the manufacturing system to perform an etching process to remove portions of the superconductor layer 410 and expose the protective layer 350 in areas not protected by the resist layer 510. The etching process also creates etched regions 610, which are undercut regions within the superconductor layer 410 beneath the resist layer 510. The etching process is selected to minimize surface damage during manufacturing. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0089] refer to Figure 7 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 700 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and resist layer 510... Figure 6 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and resist layer 510 are the same.

[0090] The embodiments enable the manufacturing system to perform an ion implantation process. The ion implantation process disrupts the crystal structure of exposed portions of the semiconductor layer 340, forming an implantation region 710. In the implantation region 710, the semiconductor layer 340 is non-conductive, thereby forming an isolation region surrounding the device being manufactured. The ion implantation process uses ions from any material suitable for forming the isolation region. Some non-limiting examples of suitable ion implantation materials include hydrogen, oxygen, helium, gallium, argon, and neon. Other ion implantation materials are also possible and are considered to be within the scope of the exemplary embodiments.

[0091] refer to Figure 8 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 800 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, and implantation region 710 are... Figure 7 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510 and implantation region 710 are the same.

[0092] The embodiment allows the manufacturing system to deposit a resist layer 810 patterned with resist onto a resist layer 510 and portions of the underlying surface exposed through openings in the resist layer 510. The resist pattern protects areas other than the resist openings 820 from upcoming device processing steps. The resist layer 810 can be formed from any resist material used in photolithography and can be the same or a different material from the resist layer 510.

[0093] refer to Figure 9 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 900 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, implantation region 710, resist layer 810, and resist opening 820 are... Figure 8 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, resist layer 510, implantation region 710, resist layer 810 and resist opening 820 are the same.

[0094] The embodiment causes the manufacturing system to perform an etching process to remove the superconductor layer 410 to expose the protective layer 350 in areas not protected by the resist layer 810. The etching process also creates etched regions 910, or undercut regions, within the superconductor layer 410 beneath the resist layers 510 and 810. The etching process is selected to minimize surface damage during manufacturing and can be the same as or different from the process used to form the structure 600. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0095] refer to Figure 10 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 1000 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710... Figure 9 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0096] The embodiment involves performing a resist removal process on the manufacturing system to remove resist layers 510 and 810, exposing portions of the superconductor layer 410 and the protective layer 350. The embodiment uses any resist removal process used in photolithography. As a result, in configuration 1100, portions of the protective layer 350 are exposed in a region on one side of the superconductor layer 410.

[0097] refer to Figure 11 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1100 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710... Figure 10 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0098] Construction 1100 is optionally from Figure 7 The configuration achievable in configuration 700 is achieved by using a mask with an appropriate configuration in the resist layer 510 during the photolithography process, omitting the fabrication steps described in reference configurations 800 and 900. In configuration 1100, a portion of the protective layer 350 is exposed in the region surrounding the superconductor layer 410. Configurations 1000 and 1100 are performed similarly; however, configuration 1100 is preferred because it uses fewer process steps than configuration 1000.

[0099] refer to Figure 12 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 1200 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710... Figure 11 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same. Structure 1200 is described as a result of manipulating structure 1000, but it can also be a result of manipulating structure 1100.

[0100] The embodiment allows the fabrication system to deposit a resist layer 1210, which includes an opening in an exposed region 1220, comprising portions of a protective layer 350 and a superconductor layer 410. Region 1220 is intended to serve as a sensing region of device 200. The resist layer 1210 can be formed from any resist material used in photolithography and can be the same as or different from resist layers 510 and 810.

[0101] refer to Figure 13 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1300 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, and resist layer 1210 are... Figure 12 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710 and resist layer 1210 are the same.

[0102] The embodiment involves an etching process in the manufacturing system to remove the superconductor layer 410 to expose the protective layer 350 in region 1310, including the undercut region within the superconductor layer 410 beneath the resist layer 1210. The etching process is selected to minimize surface damage during manufacturing and may be the same as or different from the process used to form the structure 600. In one embodiment, the etching process is a wet etching process, such as using tetramethylammonium hydroxide (TMAH).

[0103] refer to Figure 14 The figure depicts a block diagram of an example construction achieved in the fabrication of a Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 1400 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710... Figure 13 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0104] The embodiment enables the manufacturing system to perform a resist removal process, removing the resist layer 1210 and exposing portions of the superconductor layer 410 and the protective layer 350. The embodiment uses any resist removal process used in photolithography. Alternatively, the resist, etching, and resist removal steps described with reference to configurations 1200 and 1300 can be combined with a mask of appropriate configuration used in the photolithography process for resist layers 510 or 810.

[0105] refer to Figure 15 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate structure 1500 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, and implantation region 710... Figure 14 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410 and implantation region 710 are the same.

[0106] The embodiment allows the manufacturing system to deposit resist 1510 on configuration 1400, wherein openings are provided at exposed areas 1520 and 1530. Resist 1510 can be formed from any resist material used in photolithography and can be the same as or different from other resist layers described herein.

[0107] refer to Figure 16 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1600 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, photoresist 1510, and exposed regions 1520 and 1530 are... Figure 15 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, resist 1510, and exposed regions 1520 and 1530 are the same.

[0108] The embodiments allow the manufacturing system to form metal 1610 on a portion of configuration 1500 exposed by openings in the resist layer. Metal 1610 is deposited using any photolithography process for metal deposition. Metal 1610 comprises materials having high electrical and thermal conductivity (above threshold RRR and above threshold thermal conductivity) in a low-temperature range for operation in a temperature range from 77 K to 0.01 K. While superconducting metals are preferred in the low-temperature range because such metals have very low thermal resistance, non-superconducting metals may also be used. Some non-limiting examples of materials for metal 1610 are gold, palladium, vanadium, aluminum, lead, tin, platinum, niobium, tantalum, tantalum nitride, titanium, and titanium nitride. These examples of layer materials are not limiting. Many other materials suitable for forming metal 1610 will be conceived by those skilled in the art based on this disclosure, and these materials are contemplated within the scope of the illustrative embodiments.

[0109] The metal 1610 on the protective layer 350 forms the sensing area contact 202. The metal 1610 on the superconducting layer 410 forms the nanopillar contacts 206 and 212.

[0110] refer to Figure 17 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1700 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing contact 202, and nanopillar contacts 206 and 212 are... Figure 16 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, and nanopillar contacts 206 and 212 are the same.

[0111] The embodiment enables the manufacturing system to perform a resist removal process, removing resist 1510 from structure 1600 and exposing the underlying portion of structure 1700. The embodiment uses any resist removal process used in photolithography.

[0112] refer to Figure 18 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1800 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing contact 202, and nanopillar contacts 206 and 212 are... Figure 17 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, and nanopillar contacts 206 and 212 are the same.

[0113] The embodiment allows a manufacturing system to deposit an encapsulation film 1810 on a structure 1700. The encapsulation film 1810 protects structures on one surface of the structure 1800 while allowing further processing to be performed on the opposite surface. The encapsulation film 1810 can be formed from any encapsulation film material used for photolithography, such as germanium, silicon germanium (SiGe) oxide, tungsten oxide, or gallium oxide. Examples of these materials are not limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the encapsulation film 1810, and these materials are considered to be within the scope of the exemplary embodiments.

[0114] refer to Figure 19 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 1900 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing contact 202, nanopillar contacts 206 and 212, and encapsulation film 1810 and... Figure 18 The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, and encapsulation film 1810 are the same.

[0115] The embodiments allow the manufacturing system to form a carrier wafer 1910 on a packaging film 1810. The carrier wafer 1910 provides structural support for the device during further processing. The carrier wafer 1910 can be any suitable carrier wafer or substrate material as described herein. These examples of carrier wafer and substrate materials are not intended to be limiting. Based on this disclosure, those skilled in the art will be able to conceive of many other materials suitable for forming the carrier wafer 1910, and such materials can be envisioned within the scope of the exemplary embodiments.

[0116] refer to Figure 20 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2000 as described herein. Substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, and carrier wafer 1910 are... Figure 19The substrate 310, buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, injection region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810 and carrier wafer 1910 are the same.

[0117] The embodiment allows the manufacturing system to remove substrate 310, exposing buffer layer 320 for further processing.

[0118] refer to Figure 21 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2100 as described herein. This includes buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, and carrier wafer 1910. Figure 20 The buffer layer 320, protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, injection region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810 and carrier wafer 1910 are the same.

[0119] The embodiment allows the manufacturing system to remove the buffer layer 320, exposing the protective layer 330 for further processing.

[0120] refer to Figure 22 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2200 as described herein. This includes a protective layer 330, a semiconductor layer 340, a protective layer 350, a superconductor layer 410, an implantation region 710, a metal 1610, sensing contact 202, nanopillar contacts 206 and 212, an encapsulation film 1810, and a carrier wafer 1910. Figure 21 The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, and carrier wafer 1910 are identical. The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same as those in the original text. Figure 2 The tunnel junction gate 204 and chemical potential gates 208 and 210 are the same.

[0121] The embodiment describes a manufacturing system that forms a resist 2210 on the now-exposed protective layer 330, followed by the formation of metal 2220 on the resist 2210 and the exposed area of ​​the protective layer 330. The resist 2210 can be formed from any resist material used in photolithography and can be the same or different from other resist layers described herein. The metal 2220 is deposited using any suitable metal deposition process and can be formed from any metal material described herein and can be the same or different from other metal layers described herein. The metal 2220 in the sensing region forms a tunnel junction gate 204. Outside the sensing region, the metal 2220 adjacent to the superconductor layer 410 forms chemical potential gates 208 and 210.

[0122] refer to Figure 23 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2300 as described herein. Protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, and chemical potential gates 208 and 210 are... Figure 22 The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, and chemical potential gates 208 and 210 are the same.

[0123] The embodiment enables the manufacturing system to perform a resist removal process, thereby removing the resist 2210 from the configuration 2200. The embodiment uses any resist removal process used in photolithography.

[0124] refer to Figure 24 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2400 as described herein. Protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, and chemical potential gates 208 and 210 are... Figure 23The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, and chemical potential gates 208 and 210 are the same.

[0125] The embodiment allows the manufacturing system to form resist 2410 on the implantation region 710, the protective layer 330, the tunnel junction gate 204, and the exposed portions of the chemical potential gates 208 and 210, wherein the opening exposes a portion of the implantation region 710 outside the active portion of the device 200. Resist 2210 can be formed from any resist material used in photolithography and can be the same as or different from the other resist layers described herein.

[0126] refer to Figure 25 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2500 as described herein. This includes a protective layer 330, a semiconductor layer 340, a protective layer 350, a superconductor layer 410, an implantation region 710, a metal 1610, sensing region contacts 202, nanopillar contacts 206 and 212, an encapsulation film 1810, a carrier wafer 1910, a metal 2220, a tunnel junction gate 204, chemical potential gates 208 and 210, and a photoresist 2410. Figure 24 The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, chemical potential gate 208 and 210, and resist 2410 are the same.

[0127] The embodiment causes the manufacturing system to perform an etching process to remove the exposed portion of the implantation region 710 to create an exposed region 2510, thereby allowing access to the encapsulation film 1810. The etching process may be the same as or different from those described elsewhere herein. In one embodiment, the etching process uses a re-etching process (RIE).

[0128] refer to Figure 26 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2600 as described herein. This includes a protective layer 330, a semiconductor layer 340, a protective layer 350, a superconductor layer 410, an implantation region 710, a metal 1610, sensing region contacts 202, nanopillar contacts 206 and 212, an encapsulation film 1810, a carrier wafer 1910, a metal 2220, a tunnel junction gate 204, chemical potential gates 208 and 210, and an exposure region 2510. Figure 25 The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, chemical potential gate 208 and 210, and exposure region 2510 are the same.

[0129] The embodiment allows the manufacturing system to form contact regions 2610 in some exposed areas 2510, leaving other exposed areas 2510. Contact regions 2610 provide electrical coupling to sensing area contacts 202, nanopillar contacts 206 and 212, and other structures on one surface of device 200. Contact regions 2610 are formed of any suitable conductive material, deposited using any suitable deposition process, and can be the same as or different from other metallic materials described herein.

[0130] refer to Figure 27 The figure depicts a block diagram of an example construction achieved in the fabrication of a bilateral Majorana fermion quantum computing device according to an illustrative embodiment. Figure 1 Application 105 interacts with manufacturing system 107 to produce or manipulate the structure 2700 as described herein. This includes a protective layer 330, a semiconductor layer 340, a protective layer 350, a superconductor layer 410, an implantation region 710, a metal 1610, sensing region contacts 202, nanopillar contacts 206 and 212, an encapsulation film 1810, a carrier wafer 1910, a metal 2220, a tunnel junction gate 204, chemical potential gates 208 and 210, and an exposure region 2510. Figure 25 The protective layer 330, semiconductor layer 340, protective layer 350, superconductor layer 410, implantation region 710, metal 1610, sensing region contact 202, nanopillar contacts 206 and 212, encapsulation film 1810, carrier wafer 1910, metal 2220, tunnel junction gate 204, chemical potential gate 208 and 210, and exposure region 2510 are the same.

[0131] The embodiment allows the manufacturing system to remove most of the encapsulation film 1810 through the exposed region 2510, leaving sufficient encapsulation film 1810 in the region near the superconductor layer 410 to serve as a bonding layer with the carrier wafer 1910. In the embodiment, the encapsulation film 1810 is removed by a wet process, such as using water or an organic solvent, or using a mild wet etching or mild plasma etching process. Other removal methods for the encapsulation film 1810 are also possible and are considered to be within the scope of the exemplary embodiments. Configuration 2700 is the complete form of device 200.

[0132] refer to Figure 28 The figure depicts a flowchart of an example process for fabricating a Majorana fermion quantum computing device according to an illustrative embodiment. In one or more embodiments, process 2800 is implemented in application 105, which enables, for example... Figure 1 Manufacturing systems such as manufacturing system 107 perform the operations described in this article.

[0133] In block 2802, the application causes the manufacturing system to sequentially form a buffer layer, a first protective layer, a semiconductor layer, and a superconductor layer on a substrate surface. In block 2804, the application causes the manufacturing system to form a first resist pattern defining a device region and a sensing region within the device region on the superconductor layer. In block 2806, the application causes the manufacturing system to use an etching process to remove the superconductor layer within the sensing region and expose a region of the underlying semiconductor layer outside the device region not protected by the first resist pattern. In block 2808, the application causes the manufacturing system to implant the exposed region of the semiconductor layer to form an isolation region surrounding the device region. In block 2810, the application causes the manufacturing system to use an etching process to expose portions of the isolation region adjacent to the sensing region and the device region of the superconductor layer. In block 2812, the application causes the manufacturing system to form a sensing region gate within the sensing region by depositing a metal layer and to form nanopillar contacts within a portion of the sensing region outside the device region. In block 2814, the application causes the manufacturing system to protect the sensing region contacts, nanopillar contacts, and the superconductor layer using an encapsulation film and a carrier wafer. In block 2816, the application causes the fabrication system to form a tunnel junction gate within the sensing region by depositing a second metal layer on the surface of the semiconductor layer opposite to the sensing region gate and nanopillar contacts, and to form a chemical potential gate in the portion of the device region outside the sensing region. In block 2818, the application causes the fabrication system to remove a portion of the encapsulation film. Then, process 2800 ends.

[0134] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., top, bottom, above, below, adjacent, etc.) between elements are illustrated in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, provided that the described function is maintained even if the orientation is changed. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, the reference in this specification to forming layer "A" on layer "B" includes cases where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," provided that the relevant characteristics and functions of layer "A" and layer "B" are substantially not altered by the intermediate layers.

[0135] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprising,” “including,” “having,” “containing,” or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such compositions, mixtures, processes, methods, articles, or apparatus.

[0136] Additionally, the term "illustrative" is used herein to mean "serving as an example, illustration, or description." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0137] References to "an embodiment," "an exemplary embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may or may not include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, regardless of whether it is explicitly described.

[0138] The terms “about,” “substantially,” “approximately,” and variations thereof are intended to include a degree of error associated with a measurement of a specific quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0139] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. A quantum computing device, comprising: a device region over a first surface of a semiconductor layer and comprising a superconductor layer; a sensing region within the device region, the sensing region comprising a portion of the device region that does not include the superconductor layer; a sensing region contact comprising a first metal coupled to the first surface of the semiconductor layer within the sensing region; a nanocolumn contact comprising a first metal coupled to the superconductor layer within a portion of the device region outside the sensing region; a tunnel junction gate comprising a second metal within the sensing region, the tunnel junction gate disposed on a second surface of the semiconductor layer; and a chemical potential gate comprising the second metal within a portion of the device region outside the sensing region, the chemical potential gate disposed on the second surface of the semiconductor layer; an isolation region surrounding the device region, the isolation region comprising a region in which the superconductor layer has been removed and the semiconductor layer has been implanted.

2. The quantum computing device of claim 1, further comprising: a buffer layer formed on a first surface of a substrate; a first protective layer formed below a second surface of the semiconductor layer; and the semiconductor layer formed on the first protective layer. The buffer layer comprises indium aluminum arsenide. The first protective layer comprises indium gallium arsenide.

3. The quantum computing device of claim 2, wherein, The superconductor layer comprises aluminum.

4. The quantum computing device of any one of claims 2-3, wherein, 6. The quantum computing device of claim 1, further comprising:

5. The quantum computing device of claim 1, wherein, a second protective layer formed between a first surface of the semiconductor layer and the superconductor layer.

7. A computer-implemented method for fabricating a quantum computing device, the method comprising: forming a first resist pattern on a superconductor layer, the first resist pattern defining a device region and a sensing region within the device region; removing the superconductor layer within the sensing region using an etching process, the etching exposing a region of a first surface of an underlying semiconductor layer outside the device region that is not protected by the first resist pattern; implanting the exposed region of the first surface of the semiconductor layer, the implanting forming an isolation region surrounding the device region; after the implanting, exposing a portion of the sensing region and the device region of the superconductor layer adjacent to the isolation region using an etching process; forming a sensing region contact by coupling a first surface of the semiconductor layer with a first metal layer; forming a nanocolumn contact using the first metal coupled to the superconductor layer within a portion of the device region outside the sensing region; and forming a tunnel junction gate by depositing a second metal layer on a second surface of the semiconductor layer within the sensing region. The first device region comprises a first nanocolumn region, a second nanocolumn region substantially parallel to the first nanocolumn region, and the sensing region connecting the first nanocolumn region and the second nanocolumn region.

9. The computer-implemented method of any of claims 7-8, further comprising: forming a buffer layer on a first surface of a substrate; 8. The computer-implemented method of claim 7, wherein, forming a first protective layer on the buffer layer; forming the semiconductor layer on the first protective layer; and forming the superconductor layer on a first surface of the semiconductor layer. ​ ​ ​ ​ 10. The computer-implemented method of claim 9, wherein, The buffer layer includes indium aluminum arsenide.

11. The computer-implemented method of claim 9, wherein, The first protective layer includes indium gallium arsenide.

12. The computer-implemented method of claim 7, wherein the superconductor layer includes aluminum.

13. The computer-implemented method of claim 7, further comprising: forming a second protective layer between a first surface of the semiconductor layer and the superconductor layer.

14. The computer-implemented method of claim 7, further comprising: removing the first resist pattern prior to depositing the first metal layer.

15. The computer-implemented method of claim 7, wherein, depositing the first metal layer is performed in a region defined by a second resist pattern.

16. The computer-implemented method of claim 7, further comprising, prior to depositing the second metal layer: protecting the sensing region contact, the nanopillar contact, and the superconductor layer using an encapsulation film; and depositing a carrier wafer over the encapsulation film.

17. The computer-implemented method of claim 7, further comprising forming by depositing the second metal layer on a second surface of the semiconductor layer.

18. A superconductor fabrication system comprising a photolithography assembly, the superconductor fabrication system when operating on at least one die to fabricate a quantum computing device performs operations comprising: forming a first resist pattern on a superconductor layer, the first resist pattern defining a device region and a sensing region within the device region; removing the superconductor layer within the sensing region using an etching process, the etching exposing a region of a first surface of an underlying semiconductor layer outside the device region that is not protected by the first resist pattern; implanting the exposed region of the first surface of the semiconductor layer, the implanting forming an isolation region surrounding the device region; after the implanting, exposing a portion of the device region of the superconductor layer adjacent the isolation region using an etching process; forming a sensing region contact by coupling the first surface of the semiconductor layer with a first metal layer; forming a nanopillar contact using the first metal coupled to the superconductor layer within a portion of the device region outside the sensing region; and forming a tunnel junction gate by depositing a second metal layer on a second surface of the semiconductor layer within the sensing region.

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