Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate having a transistor portion and a diode portion, the semiconductor substrate having a first-conductivity-type drift region provided inside, the transistor portion having a transistor region separated from the diode portion when viewed from the semiconductor substrate, and a boundary region located between the transistor region and the diode portion when viewed from the semiconductor substrate, and the boundary region having a current suppression structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Conventional techniques include: in a semiconductor device formed by depositing transistor portions such as insulated-gate bipolar transistors (IGBTs) and diode portions on the same substrate, a lifetime control region containing a lifetime control agent is formed by irradiating a particle beam such as helium ions at a predetermined depth position of the semiconductor substrate. Furthermore, to suppress the increase of charge carriers from the transistor portions, the lifetime control region is provided in a portion of a region extending from the diode portion to adjacent transistor portions (e.g., Patent Document 1 and Patent Document 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-135339

[0004] Patent Document 2: Japanese Patent Application Publication No. 2014-175517 Summary of the Invention

[0005] Technical issues

[0006] In such semiconductor devices, the exposure of the transistor section to a lifetime control agent damages the gate oxide film, causing a decrease in the threshold voltage. This decrease in threshold voltage leads to current concentration, resulting in latch-up and damage during overcurrent operation when the transistor is turned off.

[0007] Technical solution

[0008] In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a transistor portion and a diode portion. The semiconductor substrate has a drift region of a first conductivity type disposed therein. The transistor portion has: a transistor region that is disposed separately from the diode portion when viewed from above the semiconductor substrate; and a boundary region that is located between the transistor region and the diode portion when viewed from above the semiconductor substrate. In the drift region, a lifetime control region is provided on the front side of the semiconductor substrate, and the boundary region has a current suppression structure.

[0009] The transistor portion may further include at least one gate trench portion and at least one dummy trench portion disposed from the front side of the semiconductor substrate to the drift region. In the boundary region, the dummy ratio may be greater than 1, wherein the dummy ratio is the ratio of the number of dummy trench portions to the number of gate trench portions.

[0010] The dummy ratio in the boundary region can be higher than that in the transistor region.

[0011] The dummy ratio in the boundary region can be more than 1 and less than 9 times that in the transistor region.

[0012] The transistor section may also have an emitter region of a first conductivity type on the front side of the semiconductor substrate, and the ratio of emitter regions in the boundary region may be lower than the ratio of emitter regions in the transistor region.

[0013] When viewed from above, the width of the boundary region in the direction of the arrangement of the transistor and diode portions can be more than 50 μm and less than 150 μm.

[0014] The width of the boundary region can be 100μm or more.

[0015] When viewed from above, the area of ​​the boundary region can be more than three times the area of ​​the transistor region.

[0016] The lifetime control region can contain a doping concentration of 1×10⁻⁶. 10 cm -3 Above and 1×10 13 cm -3 The following are life control agents.

[0017] In the drift region, a lifetime control region may also be provided on the back side of the semiconductor substrate, covering the entire transistor section and the entire diode section.

[0018] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute separate inventions. Attached Figure Description

[0019] Figure 1A This is a partial top view of the semiconductor device 100 of Embodiment 1.

[0020] Figure 1B It is shown Figure 1A The diagram of section a-a' in the figure.

[0021] Figure 1C This is a partial top view of the semiconductor device 100 of Embodiment 1.

[0022] Figure 1D This is a partial top view of the semiconductor device 100 of Embodiment 1.

[0023] Figure 1E This is a partial top view of the semiconductor device 100 of Embodiment 1.

[0024] Figure 2 This is a graph showing the relationship between gate voltage Vge and current.

[0025] Figure 3 This is a partial top view of the semiconductor device 200 of Embodiment 2.

[0026] Symbol Explanation

[0027] 10 Substrate, 11 Trap area, 12 Launch area, 14 Base area, 15 Extraction area, 16 Accumulation area, 17 Insertion area, 18 Drift zone, 20 Buffer, 21 Front, 22 Collection area, 23 Back, 24 Collector, 25 Connecting part, 29 Straight line section, 30 False trench section, 31 Front end, 32 Fake insulation film, 34 Virtual conductive part, 38 Interlayer insulating film, 39 Straight line section, 40 Gate trench, 41 Front end, 42 Gate insulating film, 44 Gate conductive part, 48 Gate channel, 49 Contact hole, 50 Gate metal layer, 52 emitter, 54 Contact hole, 56 Contact hole, 58 Contact hole, 60 Stage face, 61 Tabletop, 70 Transistor section, 72 Transistor region, 74 Boundary area, 80 Diode section, 82 Cathode region, 85 Life control area, 86 Life control area, 100 Semiconductor devices, 200 Semiconductor devices Detailed Implementation

[0028] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0029] In this specification, the side parallel to the depth direction of the semiconductor substrate is referred to as "upper" and the other side as "lower". Of the two main surfaces of a substrate, layer, or other component, one is referred to as the front surface and the other as the back surface. The directions "upper" and "lower" are not limited to the direction of gravity or the actual orientation of the semiconductor device during mounting.

[0030] In this specification, rectangular coordinate axes, namely the X-axis, Y-axis, and Z-axis, are sometimes used to illustrate technical matters. Rectangular coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the direction of height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0031] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the front and back surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction including the X-axis and Y-axis and parallel to the front and back surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0032] In this specification, the terms "same" or "equal" may also include cases with errors due to manufacturing deviations, etc. Such errors are, for example, within 10%.

[0033] In this specification, the conductivity type of doped regions containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopant. In this specification, doping refers to introducing a donor or acceptor into a semiconductor substrate, thereby designating it as a semiconductor representing an N-type conductivity type or a semiconductor representing a P-type conductivity type.

[0034] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the polarities of the charges, taking the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions. For example, if the donor concentration is set to N... D And set the acceptor concentration to N A Then the actual net doping concentration at any position is N. D -N A .

[0035] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of taking electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, act as electron donors.

[0036] When referred to as P+ or N+ type in this specification, it means that the doping concentration is higher than that of P- or N- type. When referred to as P- or N- type, it means that the doping concentration is lower than that of P- or N- type. Furthermore, when referred to as P++ or N++ type in this specification, it means that the doping concentration is higher than that of P+ or N+ type.

[0037] In this specification, chemical concentration refers to the concentration of impurities measured independently of the state of electrical activation. Chemical concentration can be measured using, for example, secondary ion mass spectrometry (SIMS). The net doping concentration can be measured using voltage-capacitance measurement (CV). Alternatively, the carrier concentration measured using extended resistance measurement (SR) can be used as the net doping concentration. The carrier concentration measured by CV or SR can be set to a value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is much greater than the acceptor concentration; therefore, the carrier concentration in this region can also be set as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be set as the acceptor concentration.

[0038] Furthermore, when the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be set as the concentration of donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can also be set as the concentration of donor, acceptor, or net dopant.

[0039] For carrier concentration measured by the SR method, the carrier concentration in regions with crystal defects is sometimes lower than that in the semiconductor substrate. During the measurement of extended resistance, the carrier mobility of the semiconductor substrate is lower than that of silicon within the current flow range. This decrease in carrier mobility is due to the disorder (disorder) of the crystal structure caused by lattice defects, which disperses the carriers.

[0040] [Example 1]

[0041] Figure 1A This is a partial top view of the semiconductor device 100 according to Embodiment 1 of this invention. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). Figure 1AThe boundary periphery of the transistor section 70 and the diode section 80 is presented at the center.

[0042] It should be noted that the term "top view" in this specification refers to the view from the front side of the semiconductor substrate. In this example, the arrangement direction of the transistor section 70 and the diode section 80 in the top view is referred to as the X-axis, the direction perpendicular to the X-axis on the front side of the semiconductor substrate is referred to as the Y-axis, and the direction perpendicular to the front side of the semiconductor substrate is referred to as the Z-axis.

[0043] The transistor section 70 and the diode section 80 may each have a length in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the length directions of the trench sections described later.

[0044] The diode section 80 has an N+ type cathode region on the back side of the semiconductor substrate. In this specification, the region where the cathode region is located is referred to as the diode section 80. That is, the diode section 80 is the region that overlaps with the cathode region when viewed from above. On the other hand, the transistor section 70 has a P+ type collector region on the back side of the semiconductor substrate.

[0045] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and an extraction region 15 disposed inside the front side of a semiconductor substrate. The gate trench 40 and the dummy trench 30 are examples of trench portions.

[0046] Furthermore, in this example, the semiconductor device 100 has a gate metal layer 50 and an emitter 52 on the upper surface of the semiconductor substrate. The gate metal layer 50 and the emitter 52 are disposed separately from each other.

[0047] Although interlayer insulating films are provided between the emitter 52 and the front side of the semiconductor substrate, and between the gate metal layer 50 and the front side of the semiconductor substrate, in Figure 1A (Omitted). In this example, contact holes 49, 54, 56, and 58 are provided through the interlayer insulating film. Figure 1A In the middle, the shading of the diagonal lines marks each contact hole.

[0048] The emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the extraction region 15. The emitter 52 is electrically connected to the emitter region 12, the base region 14, and the extraction region 15 on the front side of the semiconductor substrate through the contact hole 54.

[0049] The emitter 52 is electrically connected to the dummy conductive portion within the dummy trench portion 30 via contact hole 56 or contact hole 58. A connection portion 25 formed of a conductive material such as polycrystalline silicon doped with impurities may be provided between the emitter 52 and the dummy conductive portion. The connection portion 25 is respectively provided on the insulating film. An interlayer insulating film such as BPSG (Boro PhosphoSilicate Glass) and the emitter 52 are provided on the upper surface of the insulating film.

[0050] The gate metal layer 50 is electrically connected to the gate channel 48 through the contact hole 49. The gate channel 48 may be formed of polysilicon or the like, which is doped with impurities. The gate channel 48 is electrically connected to the gate conductive portion within the gate trench portion 40 on the front side of the semiconductor substrate. The gate metal layer 50 is not electrically connected to the dummy conductive portion within the dummy trench portion 30 or to the emitter 52.

[0051] The gate channel 48 and the emitter 52 can be electrically separated by insulating materials such as interlayer insulating films and oxide films. In this example, the gate channel 48 is disposed from below the contact hole 49 to the front end of the gate trench portion 40. At the front end of the gate trench portion 40, the gate conductive portion is exposed on the front side of the semiconductor substrate and connected to the gate channel 48.

[0052] The emitter 52 and the gate metal layer 50 are formed of a conductive material containing metal. For example, the emitter 52 and the gate metal layer 50 are formed of aluminum or an alloy with aluminum as the main component (aluminum-silicon, aluminum-silicon-copper, etc.). Each of these electrodes may have a barrier metal formed of titanium or titanium compounds in the lower layer of the region formed of aluminum or the like.

[0053] Each electrode may also have a plug made of tungsten or the like within the contact hole. The plug may be embedded in the contact hole, or it may be formed by placing a barrier metal on the side in contact with the semiconductor substrate and embedding tungsten in contact with the barrier metal.

[0054] The well region 11 is disposed overlapping with the gate channel 48 and the dummy trench portion 30. In this example, the well region 11 is disposed separated from the end of the contact hole 54 in the Y-axis direction toward the gate channel 48. In addition, the well region 11 is disposed in such a way that it covers the dummy trench portion 30. The well region 11 is a region of the second conductivity type with a higher doping concentration than the base region 14.

[0055] In this example, the base region 14 is P-type and the well region 11 is P+ type. In addition, the well region 11 is formed from the front side of the semiconductor substrate to a position that is deeper than the lower end of the base region 14 and deeper than the gate trench portion 40 and the dummy trench portion 30.

[0056] The transistor section 70 and the diode section 80 each have multiple trench sections arranged along the arrangement direction (X-axis direction). In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 along the X-axis direction. In this example, the diode section 80 has multiple dummy trench sections 30 along the X-axis direction. In this example, the diode section 80 does not have gate trench sections 40.

[0057] In this example, the gate trench portion 40 may have two straight portions 39 (the trench portion that is straight along the Y-axis direction) extending along an extension direction perpendicular to the arrangement direction, and a front end portion 41 connecting the two straight portions 39.

[0058] At least a portion of the front end portion 41 may be configured as curved in top view. As described later, the front end portion 41 connects the ends of the two straight portions 39 in the Y-axis direction to each other with the gate channel 48.

[0059] The dummy trench portion 30 may have a straight shape extending in the extension direction, or it may have a straight portion 29 and a front end portion 31, similar to the gate trench portion 40. Figure 1A The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31, and a dummy trench portion 30 with a front end portion 31.

[0060] The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the end of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction (Z-axis direction) is covered by the well region 11. As a result, the electric field concentration at the bottom of each trench portion can be alleviated.

[0061] Figure 1B It is shown Figure 1A The diagram shows the a-a' cross-section. The a-a' cross-section is the XZ plane that includes the gate trench portion 40 and the dummy trench portion 30 and passes through the extraction region 15 and the base region 14. In this example, the semiconductor device 100 has a substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in the a-a' cross-section.

[0062] In the X-axis direction, a mezzanine portion is provided between adjacent groove portions. The mezzanine portion refers to the area inside the substrate 10 that is held by the groove portion. As an example, the depth of the mezzanine portion is from the front surface 21 of the substrate 10 to the lower end of the groove portion.

[0063] In this example, the mesa portion is held between adjacent trench portions in the X-axis direction and is provided on the front side 21 of the substrate 10, extending along the trench portions in the Y-axis direction. As described later, in this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0064] A base region 14 is provided on each stage surface. On each stage surface of the transistor section 70, at least one of a first conductivity type emitter region 12 and a second conductivity type extractor region 15 may be provided in the area sandwiched by the base region 14 when viewed from above. For example... Figure 1A As shown, the emitter region 12 is of type N+ and the extractor region 15 is of type P+. The emitter region 12 and the extractor region 15 can be disposed between the base region 14 and the front surface 21 of the substrate 10 in the Z-axis direction.

[0065] The mesa of the transistor section 70 has an emitter region 12 exposed on the front side 21 of the substrate 10. In this example, the emitter region 12 exposed on the front side 21 of the substrate 10 and the extraction region 15 are provided on the mesa of the transistor section 70.

[0066] As described later, if a gate voltage is applied to the gate conductive portion of the gate trench portion 40, a channel formed by an N+ type inversion layer is formed in the base region 14 disposed between the emitter region 12 and the drift region in the Z-axis direction. The extraction region 15 can extract the hole current flowing from the P+ type collector region 22 to the front side 21 of the substrate 10, thereby suppressing latch-up.

[0067] The emitter region 12 and the extraction region 15 in the mesa of the transistor section 70 are respectively disposed from one trench portion to another in the X-axis direction. As an example, the emitter region 12 and the extraction region 15 in the mesa are arranged alternately along the Y-axis direction.

[0068] In other examples, the emitter region 12 and the extraction region 15 in the mesa of the transistor section 70 may also be arranged in a stripe pattern along the Y-axis direction. For example, the emitter region 12 is provided in the area that contacts the trench section, and the extraction region 15 is provided in the area that is held by the emitter region 12.

[0069] In the transistor section 70, the emitter region 12 is not provided on the mesa adjacent to the diode section 80, but an extractor region 15 exposed on the front side 21 of the substrate 10 is provided in the area held by the base region 14 when viewed from above.

[0070] The emitter region 12 is not provided on the mesa of the diode section 80. A base region 14 exposed on the front side 21 of the substrate 10 may be provided on the mesa of the diode section 80. The base region 14 may be disposed on the entire mesa of the diode section 80.

[0071] A contact hole 54 is provided above each stage surface. Viewed from above, the contact hole 54 is positioned in the area held by the base region 14 in the extending direction (Y-axis direction). In this example, the contact hole 54 is positioned above the extraction area 15, the base region 14, and the emission area 12. The contact hole 54 can be positioned at the center of each stage surface in the arrangement direction (X-axis direction) of the stage surfaces.

[0072] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface 23 of the substrate 10. On the back surface 23 of the substrate 10, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. Figure 1A In the diagram, dashed lines are used to represent the boundary between the cathode region 82 and the collector region 22.

[0073] The cathode region 82 is configured separately from the well region 11 in the Y-axis direction. Thus, by ensuring a relatively high doping concentration and a deep P-type well region 11 with a sufficient distance between it and the cathode region 82, hole injection from the well region 11 can be suppressed, and reverse recovery loss can be reduced.

[0074] In this example, the end of the cathode region 82 in the Y-axis direction is configured to be further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may also be configured between the well region 11 and the contact hole 54.

[0075] The substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the substrate 10 is a silicon substrate.

[0076] The substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining in the substrate 10 where no other doped regions are formed.

[0077] Above the drift region 18, one or more accumulation regions 16 can be provided in the Z-axis direction. The accumulation region 16 is a region where the same dopant as the drift region 18 is accumulated at a higher concentration than the drift region 18. The accumulation region 16 is an N-type region with a higher doping concentration than the drift region 18. By providing the accumulation region 16, the amount of holes accumulated from the back side of the substrate 10 is increased from the P-type base region 14 of the transistor section 70 to the bottom of the trench section. This improves the electron-based carrier injection promotion effect (IE effect) and reduces the on-state voltage.

[0078] An interlayer insulating film 38 is disposed on the front side 21 of the substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass with added impurities such as boron or phosphorus. The interlayer insulating film 38 can be in contact with the front side 21, and other films such as an oxide film can also be disposed between the interlayer insulating film 38 and the front side 21. The interlayer insulating film 38 has... Figure 1A Contact hole 54 as described in the diagram.

[0079] An emitter 52 is disposed on the front surface 21 of the substrate 10 and the upper surface of the interlayer insulating film 38. The emitter 52 is formed of a material containing metal. The emitter 52 is electrically connected to the front surface 21 of the substrate 10 through a contact hole 54 in the interlayer insulating film 38.

[0080] Tungsten (W) or other contact plugs may also be provided inside the contact hole 54. The plugs are located in the areas of the contact hole 54 that contact the extraction area 15, the base area 14, and the emitter area 12, respectively.

[0081] A plug region 17 is formed at the bottom (the end on the positive Z-axis side) of the contact hole where the plug is located. The plug region 17 is a region of the second conductivity type with a higher doping concentration than the extraction region 15. In this example, the plug region 17 is of the P++ type. This improves the contact resistance between the barrier metal and the extraction region 15. In addition, the thickness (distance in the Z-axis direction) of the plug region 17 is approximately 0.5 μm or less, and it is a region smaller than the extraction region 15 when viewed from above.

[0082] In the operation of the transistor section 70, the latch-up withstand is improved by increasing the contact resistance of the plug region 17. On the other hand, in the operation of the diode section 80, without the plug region, the contact resistance between the blocking metal and the base region 14 is high, and the conduction loss and switching loss increase. However, by providing the plug region 17, the increase in conduction loss and switching loss is suppressed.

[0083] Collector 24 is disposed on the back side 23 of substrate 10. Collector 24 is formed of a material containing metal.

[0084] In the transistor section 70, a mesa 60 is provided between adjacent trench sections in the X-axis direction. On the mesa 60, above the base region 14, in contact with the front surface 21, at least one of an emitter region 12 and an extractor region 15 is provided. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0085] In this example, on the isthmus 60 of the transistor section 70, the emitter region 12 and the extraction region 15 exposed on the front side 21 of the substrate 10 are alternately arranged along the Y-axis direction. It should be noted that, because... Figure 1B The a-a' section shown passes through the position where the extraction zone 15 is configured along the X-axis, so the emission zone 12 is not shown.

[0086] In this case, the mesa 60 on the diode section 80 side does not have an emission region 12, but has an extraction region 15 exposed on the front side 21 of the substrate 10.

[0087] In the diode section 80, a mesa 61 is provided between adjacent trench sections. A base region 14 exposed on the front side 21 is provided on the mesa 61. The base region 14 of the diode section 80 operates as an anode.

[0088] A buffer 20 of a first conductivity type can be disposed below the drift region 18. In this example, the buffer 20 is N-type. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the back side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0089] In the transistor section 70, a collector region 22 is provided below the buffer zone 20. In the diode section 80, a cathode region 82 is provided below the buffer zone 20. The collector region 22 and the cathode region 82 can be set to the same depth. The collector region 22 and the cathode region 82 can be provided in contact with the back surface 23 of the substrate 10. When the transistor section 70 is turned off, the diode section 80 can function as a freewheeling diode (FWD) that allows reverse-conducting return current to flow.

[0090] A gate trench portion 40 and a dummy trench portion 30 are provided on the substrate 10. The gate trench portion 40 and the dummy trench portion 30 are configured to penetrate the base region 14 and the accumulation region 16 from the front side 21 and reach the drift region 18.

[0091] The trench portion through-doped region is not limited to being manufactured in the order of forming the doped region after forming the trench portion. It also includes the case where the doped region is formed between the trench portions after the trench portions are formed.

[0092] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 disposed on the front side 21. The gate insulating film 42 is disposed covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position further inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 can be located in the same XY plane as the front side 21 of the substrate 10. The gate insulating film 42 insulates the gate conductive portion 44 from the substrate 10. The gate conductive portion 44 is formed of a semiconductor such as polysilicon doped with impurities.

[0093] The gate conductive portion 44 can be disposed at a depth greater than that of the base region 14 in the Z-axis direction. The gate trench portion 40 is covered by an interlayer insulating film 38 on the front side 21. When a gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface of the base region 14 disposed between the emitter region 12 and the drift region 18 in the Z-axis direction at the interface in contact with the gate trench portion 40.

[0094] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench provided on the front side 21 of the substrate 10, a dummy insulating film 32, and a dummy conductive portion 34.

[0095] A dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the dummy trench. A dummy conductive portion 34 is disposed inside the dummy trench, further inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 can be located in the same XY plane as the front side 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44.

[0096] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the front side 21 of the substrate 10. It should be noted that the bottom of the gate trench portion 40 and the dummy trench portion 30 in the Z-axis direction can be a downwardly convex curved surface (curved in cross-section).

[0097] In the drift region 18, on the front side 21 of the substrate 10, a lifetime control region 85 containing a lifetime control agent is provided extending from at least a portion of the transistor section 70 and across the diode section 80. In the transistor section 70, the region without the lifetime control region 85 is referred to as the transistor region 72, and the region with the lifetime control region 85 is referred to as the boundary region 74. The transistor region 72 is the region separated from the diode section 80 when viewed from above the semiconductor substrate. The boundary region 74 is the region located between the transistor region 72 and the diode section 80 when viewed from above the semiconductor substrate.

[0098] Protons or helium can be irradiated from either the front side 21 or the back side 23 of the substrate 10. The lifetime control region 85 is formed deeper than the bottom of the trench in the direction from the front side 21 towards the back side 23 of the substrate 10. A lifetime control agent forms crystal defects inside the substrate 10 by, for example, injecting helium or protons to a predetermined depth. In this example, the lifetime control region has a doping concentration of 1 × 10⁻⁶. 10 cm -3 Above and 1×10 13 cm -3 The following doping levels are formed.

[0099] As an example, when protons or helium are irradiated from the front side 21 of the substrate 10, a metal or resist mask is used to block the area where the lifetime control region 85 does not form, and protons or helium are irradiated onto the transistor section 70 and the diode section 80. The protons or helium do not irradiate the area blocked by the mask.

[0100] exist Figure 1B In the diagram, the position of the lifetime control region 85 along the Z-axis is indicated by an "×" symbol. The position of the lifetime control region 85 along the Z-axis represents the peak position of the lifetime control agent concentration distribution along the Z-axis.

[0101] The position of the lifetime control region 85 in the Z-axis direction can be equal to the position of the back side of the well region 11 in the Z-axis direction, and the position of the lifetime control region 86 in the Z-axis direction can be lower than the position of the back side of the well region 11 in the Z-axis direction.

[0102] The end K on the negative X-axis side of the lifetime control region 85, when viewed from above, becomes the boundary between the transistor region 72 and the boundary region 74 of the transistor section 70.

[0103] When the diode section 80 is turned on, an electron current flows from the cathode region 82 to the base region 14, which operates as the anode layer. When the electron current reaches the base region 14, conductivity modulation occurs, and a hole current flows from the anode layer. Since the base region 14 is also provided in the transistor section 70, an electron current diffuses from the cathode region 82 toward the base region 14 of the transistor section 70.

[0104] Therefore, hole current is generated not only from the base region 14 of the diode section 80 toward the cathode region 82, but also from the base region 14 of the transistor section 70 toward the cathode region 82. Furthermore, the electron current diffusing toward the transistor section 70 promotes hole injection from the extraction region 15 of the transistor section 70.

[0105] The boron doping concentration in the extraction region 15 is two orders of magnitude higher than that in the base region 14, thus increasing the hole density of the substrate 10 through hole injection from the extraction region 15. Consequently, the time consumed until the holes disappear when the diode section 80 is turned off increases, resulting in a larger reverse recovery peak current and a larger reverse recovery loss.

[0106] In this example, the lifetime control region 85 promotes the recombination of holes generated in the base region 14 with electrons injected from the cathode region 82 during turn-off. Thus, the lifetime control region 85 reduces reverse recovery losses by promoting carrier disappearance during turn-off and suppressing peak current during reverse recovery.

[0107] In this example, the lifetime control region 85 is provided from the diode section 80 to the boundary region 74. Therefore, compared to the case where the lifetime control region is only provided in the diode section 80, the distance between the end K of the lifetime control region 85 and the cathode region 82 is longer. As a result, the recombination of the hole current generated in the base region 14 in the boundary region 74 and the electrons flowing in from the cathode region 82 can be further promoted, and the peak current of the diode section 80 during reverse recovery can be suppressed.

[0108] In the region where the lifetime control region 85 is set, the trench oxide film is damaged and the interface state changes due to protons or helium irradiated from the front side 21 of the substrate 10.

[0109] In the gate trench 40 irradiated with protons or helium, when a gate voltage is applied to the gate conductive portion 44, damage remains in the gate insulating film 42 of the gate trench 40, increasing the tunneling current. Therefore, in the boundary region 74, the threshold voltage is lower compared to the transistor region 72. Consequently, because current tends to concentrate in the boundary region 74 during turn-off, the semiconductor device 100 is susceptible to latch-up damage.

[0110] In this example, the boundary region 74 has a current suppression structure that suppresses tunneling current generated when a gate voltage is applied. In one example, the boundary region 74 has a dummy trench portion 30 as a current suppression structure instead of a portion of the gate trench portion 40. In one example, in the boundary region 74, the dummy ratio, which is the ratio of the number of dummy trench portions 30 to the number of gate trench portions 40, is greater than 1. Furthermore, the dummy ratio in the boundary region 74 can be higher than the dummy ratio in the transistor region 72.

[0111] Thus, the boundary region 74 in this example has a current suppression structure that changes the dummy ratio of the gate trench portion 40 to the dummy trench portion 30, thereby suppressing the increase of tunneling current while maintaining its function as a transistor portion 70. On the other hand, by reducing the proportion of electron current in the boundary region 74, the threshold voltage of the boundary region 74 can be made higher than the threshold voltage of the transistor portion 70.

[0112] Therefore, by reducing the proportion of electron current, the decrease in the threshold voltage of the boundary region 74 caused by the increase in tunneling current can be suppressed. Furthermore, by reducing the current density in the boundary region 74, the decrease in the threshold voltage of the boundary region 74 can be suppressed, and the decrease or deviation in the threshold voltage of the entire transistor section 70 can be suppressed.

[0113] Furthermore, the drift region 18 can extend across the entire transistor portion 70 and the entire diode portion 80 on the back side 23 of the substrate 10 to form a lifetime control region 86. The lifetime control region 86 can be formed by irradiating protons or helium from the back side 23 of the substrate 10.

[0114] When helium or protons are irradiated from the back surface 23 of the substrate 10, the helium or protons do not pass through the trench oxide film, and the interface sequence of the trench oxide film remains unchanged. In addition, since the distance from the back surface 23 of the substrate 10 to the depth position of the lifetime control region 86 is short, the lifetime control region 86 can be formed by irradiation in a low-energy state.

[0115] Thus, in addition to the lifetime control region 85, the semiconductor device 100 in this example also has a lifetime control region 86, which can promote the disappearance of charge carriers during turn-off. For example, the lifetime control region 85 can suppress the peak current during reverse recovery, and the lifetime control region 86 can accelerate the current cut-off, thereby further reducing reverse recovery losses.

[0116] Figure 1C This is a partial top view of the semiconductor device 100 of Embodiment 1 of this invention. Figure 1C Transistor region 72 in transistor section 70 is presented at the center.

[0117] In transistor region 72, dummy trench portions 30 can be provided between each straight portion 39 of gate trench portion 40. One dummy trench portion 30 can be provided between each straight portion 39, or multiple dummy trench portions 30 can be provided.

[0118] Alternatively, gate trenches 40 can be provided between each straight section 39 instead of dummy trenches 30. With this structure, compared to setting all boundary regions 74 as dummy trenches 30, the electron current from the emitter region 12 can be increased, thus reducing the on-state voltage.

[0119] In this example, in transistor region 72, one gate trench 40 and two dummy trenches 30 are alternately arranged in the X-axis direction. It should be noted that... Figure 1C In this process, although a dummy trench portion 30 is provided on the boundary region 74 side of the transistor region 72, a gate trench portion 40 may also be provided.

[0120] exist Figure 1C In the example shown, in transistor region 72, two straight sections 29 of dummy trenches 30 are arranged between the straight sections 39 of the two gate trenches 30. The ends of the two straight sections 39 in the Y-axis direction are connected to each other by a front end 41 to the gate channel 48, thereby enabling the gate metal layer 50 to function as a gate electrode for the gate trenches 40. On the other hand, by making the front end 41 curved, the electric field concentration at the end is alleviated more effectively than if it terminates at a straight section 39.

[0121] Figure 1D This is a partial top view of the semiconductor device 100 of Embodiment 1 of this invention. Figure 1DThe boundary region 74 in the transistor section 70 is presented at the center.

[0122] Boundary region 74 has a lifetime control region 85 disposed in drift region 18. In this example, in boundary region 74, one gate trench portion 40 and five dummy trench portions 30 are alternately arranged in the X-axis direction. In boundary region 74, the dummy ratio, which is the ratio of the number of dummy trench portions 30 to the number of gate trench portions 40, is greater than 1.

[0123] exist Figure 1D In the example shown, in the boundary region 74, one gate trench portion 40 and five dummy trench portions 30 are arranged sequentially from the boundary between the boundary region 74 and the transistor region 72 toward the positive X-axis.

[0124] exist Figure 1D In the example shown, in the boundary region 74, five straight sections 29 of the dummy trench 30 are arranged between the straight sections 39 of the two gate trenches 40. The ends of the two straight sections 39 in the Y-axis direction are connected to each other by the front end 41 to the gate channel 48, thereby enabling the gate metal layer 50 to function as a gate electrode for the gate trench 40. On the other hand, by making the front end 41 curved, the electric field concentration at the end is alleviated more effectively than if it terminates at the straight section 39.

[0125] In this example, in transistor region 72, one gate trench portion 40 and two dummy trench portions 30 are alternately arranged in the X-axis direction. In contrast, in boundary region 74, one gate trench portion 40 and five dummy trench portions 30 are alternately arranged in the X-axis direction. Thus, the dummy ratio in boundary region 74 is higher than that in transistor region 72.

[0126] That is, in this example, the transistor section 70 varies the dummy ratio between the transistor region 72 and the boundary region 74. The boundary region 74 has a dummy trench section 30, which serves as a current suppression structure, instead of the gate trench section 40. By making the dummy ratio of the boundary region 74 higher than that of the transistor region 72, the proportion of electron current flowing through it can be reduced. Therefore, the threshold voltage of the boundary region 74 can be made higher than that of the transistor section 70, and the decrease in threshold voltage caused by the increase in tunneling current can be suppressed. Thus, the effect of threshold voltage reduction caused by the lifetime control region 85 can be suppressed.

[0127] The width of the boundary region 74 in the X-axis direction can be 50 μm or more and 150 μm or less. Alternatively, the width of the boundary region 74 in the X-axis direction can be 100 μm or more and 150 μm or less. In addition, the area of ​​the boundary region 74 can be more than three times the area of ​​the transistor region 72.

[0128] Thus, since the boundary region 74 with lifetime control region 85 has a current suppression structure, it is possible to suppress the effect of threshold reduction caused by lifetime control region 85.

[0129] Figure 1E This is a partial top view of the semiconductor device 100 of Embodiment 1 of this invention. Figure 1E A variation of the configuration of the gate trench portion 40 and the dummy trench portion 30 in the boundary region 74 is shown.

[0130] exist Figure 1E In the example shown, in transistor region 72, one gate trench portion 40 and two dummy trench portions 30 are alternately arranged in the X-axis direction; in boundary region 74, one gate trench portion 40 and five dummy trench portions 30 are alternately arranged in the X-axis direction. Figure 1D The example shown is the same. In this example, in the boundary region 74, five dummy trench portions 30 and one gate trench portion 40 are arranged sequentially from the boundary between the boundary region 74 and the transistor region 72 toward the positive X-axis.

[0131] In this example, in boundary region 74, the dummy ratio, which is the ratio of the number of dummy trench portions 30 to the number of gate trench portions 40, is also greater than 1. Furthermore, the dummy ratio in boundary region 74 is higher than the dummy ratio in transistor region 72.

[0132] Thus, since the boundary region 74 has a current suppression structure, it is possible to suppress the effect of threshold reduction caused by the lifetime control region 85, and the gate trench portion 40 and the dummy trench portion 30 can be configured with a high degree of freedom without being constrained by the order or regularity of the configuration.

[0133] It should be noted that the width and area of ​​the boundary region 74 in this example are related to... Figure 1D The examples shown are the same, so the explanation is omitted here.

[0134] Figure 2 This is a graph showing the relationship between gate voltage Vge and current. Figure 2 In the diagram, the horizontal axis represents the gate voltage Vge [V] applied to the gate conductive portion 44 of the gate trench portion 40, and the vertical axis represents the current [A] generated when the gate voltage Vge is applied. As a condition for calculation, in a semiconductor device 100 with a rated current of 30A, helium is irradiated from the front side 21 of the substrate 10 to form a lifetime control region 85 in a range extending 100 μm from the boundary between the transistor portion 70 and the diode portion 80 toward the transistor portion 70 side.

[0135] Furthermore, by setting the area ratio of transistor region 72 to boundary region 74 to 1:3, the relationship between gate voltage Vge and current is calculated. Here, the gate voltage Vge with a current of 22.5mA in transistor region 72 is defined as the threshold voltage, and the gate voltage Vge with a current of 7.5mA in boundary region 74 is defined as the threshold voltage.

[0136] exist Figure 2 In the diagram, solid lines represent the current in the entire transistor section 70, dashed lines represent the current in the transistor region 72, and dashed lines represent the current in the boundary region 74. The calculated results show that the threshold voltage in the entire transistor section 70 is 6.2V, the threshold voltage in the transistor region 72 is 6.52V, and the threshold voltage in the boundary region 74 is 5.92V.

[0137] Under the above calculation conditions, the following results were obtained: compared with the threshold voltage in transistor region 72, the threshold voltage is reduced by 0.3V in the entire transistor section 70 and by 0.6V in the boundary region 74.

[0138] The current density in the boundary region 74 is approximately nine times that in the transistor region 72. Thus, if the dummy ratio in the transistor region 72 is set to 1, the dummy ratio in the boundary region 74 is set to more than 1 and less than nine, thereby preventing an increase in current density and suppressing a decrease in threshold voltage.

[0139] [Example 2]

[0140] Figure 3 This is a partial top view of the semiconductor device 200 of Embodiment 2. Here, elements common to the semiconductor device 100 are labeled with the same symbols, and descriptions are omitted. Figure 3 The boundary region 74 in the transistor section 70 is presented at the center.

[0141] In the boundary region 74 of the semiconductor device 200, two straight portions 29 of dummy trenches 30 are disposed between the straight portions 39 of the two gate trench portions 40. That is, in the boundary region 74 of the semiconductor device 200, similarly to the transistor region 72, one gate trench 40 and two dummy trenches 30 are alternately disposed in the X-axis direction.

[0142] Transistor region 72 and boundary region 74 have emitter region 12 and extractor region 15 exposed on the front side 21 of substrate 10. In transistor region 72, emitter region 12 and extractor region 15 are alternately arranged in the Y-axis direction, but in boundary region 74, a portion of emitter region 12 is removed. That is, the ratio of emitter region 12 in boundary region 74 is lower than the ratio of emitter region 12 in transistor region 72.

[0143] In this example, the boundary region 74 is provided with an extraction region 15 to replace a portion of the emitter region 12, or the base region 14 is exposed on the front side 21 of the substrate 10. It can be configured such that the extraction region 15 is arranged when the area of ​​the emitter region 12 that is rejected is adjacent to the emitter region 12, and the base region 14 is exposed on the front side 21 of the substrate 10 when the area of ​​the emitter region 12 that is rejected is not adjacent to the emitter region 12.

[0144] In the boundary region 74, for a portion of the gate trench 40, the emitter region 12 is removed from the adjacent mesa 60 without contacting the emitter region 12. Such a gate trench 40 becomes a so-called active dummy trench that does not allow current to flow when a gate voltage is applied, even when connected to the gate metal layer 50, and functions as a current suppression structure.

[0145] In this example, the boundary region 74, having effective dummy trenches as a current suppression structure, achieves the same effect as the boundary region 74 of the semiconductor device 100. In this example, the number of effective dummy trenches in the boundary region 74 can be greater than the number of gate trench portions 40. Furthermore, in this example, the ratio of the total number of dummy trench portions 30 to the total number of effective dummy trenches relative to the number of gate trench portions 40 can be increased in the boundary region 74.

[0146] Thus, in the semiconductor device 200, by reducing the ratio of the emitter region 12 in the boundary region 74, the electron current density flowing from the emitter region 12 can be reduced, and the same effect as that of the semiconductor device 100, which reduces the number of gate trench portions 40 in the boundary region 74, can be obtained.

[0147] It should be noted that in the semiconductor device 200, in the boundary region 74, similar to the transistor region 72, one gate trench portion 40 and two dummy trench portions 30 are alternately arranged in the X-axis direction, but this is not a limitation. Similarly to the semiconductor device 100, in the boundary region 74 of the semiconductor device 200, one gate trench portion 40 and five dummy trench portions 30 may be alternately arranged in the X-axis direction, and different dummy ratios may also be used.

[0148] While the present invention has been described above using embodiments, its technical scope is not limited to that described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0149] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that they must be implemented in that order.

Claims

1. A semiconductor device, characterized in that, It includes a semiconductor substrate, which has a transistor section and a diode section. The semiconductor substrate has a drift region of a first conductivity type disposed inside. The transistor section has: The transistor region, when viewed from above on the semiconductor substrate, is disposed separately from the diode region; and The boundary region, when viewed from above, is located between the transistor region and the diode region, and within the drift region, a lifetime control region is present on the front side of the semiconductor substrate. The boundary region has a current suppression structure. The transistor portion further includes at least one gate trench portion and at least one dummy trench portion extending from the front side of the semiconductor substrate to the drift region. The transistor portion also has an emitter region of a first conductivity type on the front side of the semiconductor substrate. The boundary region has: The first face, when viewed from above the boundary region, has a base region of a second conductivity type; The second facepiece is adjacent to the first facepiece in such a way that it clamps the dummy groove portion, and has a second conductive extraction area. A third facepiece, sandwiched between the second facepieces, alternately comprises the emitter region and the extractor region along the extending direction of the gate trench and the dummy trench. When viewed from above, the first, second, and third facets are arranged along the arrangement direction of the transistor and diode portions.

2. The semiconductor device according to claim 1, characterized in that, In the boundary region, the dummy ratio is greater than 1, whereby the dummy ratio is the ratio of the number of dummy trenches to the number of gate trenches.

3. The semiconductor device according to claim 2, characterized in that, The dummy ratio in the boundary region is higher than the dummy ratio in the transistor region.

4. The semiconductor device according to claim 2, characterized in that, The dummy ratio in the boundary region is more than 1 and less than 9 times the dummy ratio in the transistor region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The ratio of the emitter region in the boundary region is lower than the ratio of the emitter region in the transistor region.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the width of the boundary region in the direction in which the transistor portion and the diode portion are arranged is more than 50 μm and less than 150 μm.

7. The semiconductor device according to claim 6, characterized in that, The width of the boundary region is 100 μm or more.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, When viewed from above, the area of ​​the boundary region is more than three times the area of ​​the transistor region.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that, The lifetime control region contains a doping concentration of 1×10⁻⁶. 10 cm -3 Above and 1×10 13 cm -3 The following are life control agents.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that, In the drift region, a back-side lifetime control region is also provided on the back side of the semiconductor substrate, extending throughout the entire transistor portion and the entire diode portion.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that, The gate trench portion of the boundary region has a first gate trench portion connected to the emitter region and a second gate trench portion not connected to the emitter region.

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