A fast oscillator oscillation frequency test system and method

Abstract

The present invention discloses a fast oscillator oscillation frequency test system and method. The test system comprises: a chip to be tested, comprising an oscillator to be tested and / or an oscillation frequency correction circuit, used for generating an oscillation output to be tested; an overshoot enhancement network, used for converting the oscillation output of the chip to be tested into an overshoot oscillation with a required specific damping; and a tester, used for sampling the oscillator output with overshoot by using its high-speed digital channel, loading a test program to perform normalization processing on the sampled jump data to filter redundant sampling information, and calculating and obtaining the test frequency according to the normalization processing result of the jump data.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fast oscillator oscillation frequency testing system and method. Background Art

[0002] In modern smart devices, oscillators (OSC) are essential components. With the continuous improvement of circuit integration and design accuracy, more and more oscillators are integrated into the chip, and even 2-3 oscillators with different oscillation frequencies are designed on one chip. For example, in order to further reduce the power consumption of smart devices, many devices will enable sleep mode to save energy. The typical way to save energy in sleep mode is to use a lower frequency oscillator to generate the system clock during sleep. Since the system clock is related to the work of the entire system, the reliability of the oscillator that generates the system clock is very high. On the basis of careful design, the oscillator of each chip must be strictly tested and normal before entering the back-end test program during mass production, that is, the oscillator oscillation frequency is a must-test item for the chip before it leaves the factory. In order to ensure the accuracy of the chip oscillation frequency, the oscillator frequency needs to be modified by modifying the parameters of the correction circuit for trimming during wafer testing (CP testing, Chip Probing). After trimming, it needs to be retested to verify the correction result until it is confirmed that the oscillator oscillation frequency of the chip is qualified or the chip is confirmed to be a bad chip.

[0003] In the digital integrated circuit process, a memory tester is usually used to test the oscillator. The traditional test method is to use the digital channel of the tester to oversample the output signal of the oscillator, and store the sampling results (the high level and low level at the sampling time, recorded as pass P and fail F) in the tester's capture error storage area (ECR, Error Capture RAM). When performing logical judgment, the data is recovered / retrieved from the ECR to the memory for processing through the data call statement TPEGetEcrData (TPE_PG2,2,i,&ecr_temp), such as Figure 1 As shown, within the set time period, the output of the oscillator (the square wave above) is oversampled (the upward arrow below), and the sampling period is Ts, the number of samples is Ns, and the number of pass / fail toggle numbers (P / F toggle numbers) is N. P / F , then the oscillator frequency is

[0004]

[0005] In order to obtain stable, reliable and accurate test results, the number of sampling points of the output waveform in a single test is generally large, such as 50,000 times, which requires a large storage space. The calculation of the number of failed flips requires reading out all the data. A large amount of data not only wastes storage space and even affects the test process due to storage space limitations, but also wastes a lot of test time to recover / read out a large amount of data, especially when oscillation frequency correction is required. Summary of the invention

[0006] In order to overcome the deficiencies of the prior art, the present invention aims to provide a fast oscillator oscillation frequency test system and method, so as to achieve the purpose of fast testing the oscillation frequency of the oscillator of the chip to be tested.

[0007] To achieve the above and other purposes, the present invention provides a fast oscillator oscillation frequency test system, comprising:

[0008] The chip to be tested includes an oscillator to be tested and / or an oscillation frequency correction circuit to be tested, and is used to generate an oscillation output to be tested;

[0009] An overshoot enhancement network, used for converting the oscillation output of the chip under test into an overshoot oscillation with a required specific damping;

[0010] The tester is used for sampling the output of an oscillator with overshoot by using its high-speed digital channel, loading a test program to normalize the sampled transition data to filter redundant sampling information, and calculating the test frequency according to the normalized processing result of the transition data.

[0011] Preferably, the overshoot enhancement network generates an overshoot with specific damping by utilizing a test probe and testing inherent parasitic capacitance and inductive load of a PCB board.

[0012] Preferably, the overshoot enhancement network increases the overshoot by additionally adding an RLC mismatch network on the test PCB board.

[0013] Preferably, the parameters of the overshoot enhancement network are adjusted according to the oscillation output of the chip to be tested to produce overshoot, so that it produces high-order damped oscillation, the amplitude V1 of the first peak at the rising edge is detected, the time difference between the two troughs after the peak is obtained to determine the frequency of the damped oscillation, and the amplitude V2 of the second peak after the rising edge is measured to set the high and low level thresholds.

[0014] Preferably, by increasing the damping coefficient of the overshoot enhancement network, the oscillation output of the chip under test has only a large overshoot.

[0015] To achieve the above object, the present invention also provides a method for testing the oscillation frequency of a fast oscillator, comprising the following steps:

[0016] Step S1, connecting the test system, reliably pressing the test probe onto the chip to be tested, and adjusting the parameters of the overshoot enhancement network so that the waveform output by the overshoot enhancement network has only one high-amplitude narrow pulse;

[0017] Step S2, sampling the oscillation output of the chip to be tested according to a preset sampling period;

[0018] Step S3, finding the transition point according to the sampled data and normalizing the single transition data;

[0019] Step S4, recover data and obtain the total number of failures during the test (N F ), calculate the normalized jump number (N P / Fnormal ), and according to the normalized number of jumps (N P / Fnormal ) and the number of sampling times (N S ) and sampling period (T S ) to get the test frequency.

[0020] Preferably, in step S1, the narrow pulse refers to an overshoot whose first peak value is significantly higher than the second peak value, and whose minimum width is based on what the tester can distinguish.

[0021] Preferably, the calculation formula of the test frequency is as follows:

[0022]

[0023] Preferably, after step S4, the following steps are also included:

[0024] Step S5, compare the test frequency with the inspection standard to determine whether calibration is required, if necessary, perform calibration and return to step S3, otherwise return to step S1 to test the next chip to be tested.

[0025] Preferably, in step S5, if calibration is required, it is determined whether the number of calibration times reaches the calibration upper limit threshold. If not, it returns to step S3; otherwise, the chip to be tested is marked as a bad chip, and then it returns to step S1 to test the next chip to be tested.

[0026] Compared with the prior art, the present invention provides a fast oscillator oscillation frequency testing system and method, which utilizes an overshoot enhancement network to convert the oscillation output of the chip to be tested into an overshoot oscillation with a required specific damping, samples the oscillator output with overshoot by using a tester using its high-speed digital channel, loads a test program to normalize the sampled jump data to filter out redundant sampling information, and calculates the test frequency based on the normalized processing result of the jump data, thereby achieving the purpose of quickly testing the oscillation frequency of the oscillator of the chip to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the traditional testing method;

[0028] Figure 2 A system structure diagram of a fast oscillator oscillation frequency test system of the present invention;

[0029] Figure 3 A schematic diagram of setting sampling points and thresholds in a specific embodiment of the present invention;

[0030] Figure 4 It is a schematic diagram of an oscillation output waveform of a specific embodiment of the present invention;

[0031] Figure 5 The present invention is a flowchart of the steps of a method for testing the oscillation frequency of a fast oscillator. DETAILED DESCRIPTION

[0032] The following describes the implementation of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Figure 2 FIG. 1 is a system structure diagram of a fast oscillator oscillation frequency test system of the present invention. Figure 2 As shown, a fast oscillator oscillation frequency test system of the present invention includes: a chip to be tested 10, an overshoot enhancement network 20 and a tester 30.

[0034] Among them, the chip to be tested 10 is one or more chips on the wafer, which includes an oscillator to be tested and / or an oscillation frequency correction circuit, which is used to generate an oscillation output OSCout to be tested; the overshoot enhancement network 20 is composed of a test probe (Probing), a parasitic capacitive and inductive load inherent in the test PCB board, and an RLC network additionally added on the PCB, which is used to generate an overshoot oscillation (Overshot) with the required specific damping; the tester 30 is used to sample the oscillator output OSCoutOV with overshoot using its high-speed digital channel, and load the test program to normalize the sampled jump data (togglenormalization) to filter out redundant sampling information, so as to achieve the purpose of reducing stored data, saving storage space and reducing test time.

[0035] Generally, circuits do not want overshoot to exist in order to avoid affecting circuit performance. The present invention uses a test probe and a test PCB board and an added RLC mismatch network to generate a specific overshoot, increase the judgment tolerance of high and low levels, and improve the sampling accuracy. Figure 3 As shown, an oscilloscope is used to observe the oscillation output OSCout of the oscillator of the chip under test, and the parameters of the overshoot enhancement network 20 are adjusted to generate overshoot, so that it generates high-order damped oscillation. The amplitude V1 of the first peak at the rising edge (at cursor T) is measured, and the time difference between the two troughs after the peak (cursor points a and b, a time 6.22ns, b time 13.06ns, and the interval between the two points Δ=6.84ns) is measured to determine the frequency of the damped oscillation. The amplitude V2 of the second peak after the rising edge is measured, and the high and low level thresholds are set to Connect the tester 30 to perform the test.

[0036] Preferably, in order to avoid the second peak being too high and affecting the accuracy of the test data, the damping coefficient of the overshoot enhancement network 20 can be increased so that the waveform observed by the oscilloscope has only one large overshoot, and its overshoot amplitude is ΔV, which exceeds the high level average VOH by 10-30% or 0.3V, and the other overshoot amplitudes are small, and their amplitudes exceed the high level amplitude by less than 5% or 100mV, such as Figure 4 As shown, the high level average value VOH = 5V, the overshoot amplitude of the high amplitude overshoot ΔV = 1.4V, and the high and low level discrimination threshold is set to V T =VOH+α×ΔV, the coefficient α is adjusted according to the actual test situation and is generally 0.5.

[0037] Figure 5 This is a flow chart of the steps of a method for testing the oscillation frequency of a fast oscillator according to the present invention. Figure 5 As shown, the present invention provides a method for testing the oscillation frequency of a fast oscillator, comprising the following steps:

[0038] Step S1, connect the test system, reliably press the test probe against the chip to be tested, adjust the parameters of the overshoot enhancement network, so that the waveform observed by the oscilloscope has only one high-amplitude narrow pulse at the rising edge, that is, the first peak of the overshoot is significantly higher than the second peak, such as the difference between the two peak amplitudes is greater than 100-500mV, and the minimum width of the narrow pulse is based on the criterion that the tester can distinguish. After the adjustment, the oscilloscope can be removed, but it may be necessary to compensate for the distributed parameters of the oscilloscope probe such as capacitance;

[0039] Step S2, start the test program to test, according to the preset sampling period T S Sample the oscillation output OSCout of the chip under test;

[0040] Step S3, finding the transition point according to the sampled data, and normalizing the single transition data, wherein the single transition refers to the transition P / F from 0 (P, Pass) to 1 (F, Fail) sampled within one oscillation cycle to be measured.

[0041] Specifically, the jump point is determined according to the sampled data. Within a measured oscillation cycle, these jump data are counted, and the number of consecutive failures (fail, the tester corresponds to data 1) is calculated as one normalized failure, and the number of consecutive failures is recorded as the normalized jump parameter N. normal , that is, the number of 1s in a measured oscillation cycle, writes the failure data to the ECR of the tester;

[0042] Step S4, recover data and obtain the total number of failures N during the test from the tester F (number of fails), calculate the normalized number of transitions N P / Fnormal =N F / N normal , and according to the normalized jump number N P / Fnormal and the number of sampling times N S , sampling period T S The test frequency is obtained, and the calculation formula of the test frequency is as follows:

[0043]

[0044] Of course, in step S3, it is more reliable to normalize multiple cycles to be tested, such as m cycles, that is, the number of 1s (failures) in the m oscillation cycles to be tested is divided by m to obtain the normalized jump parameter N normal ;

[0045] Preferably, after step S4, the following steps are also included:

[0046] Step S5, compare the test frequency with the inspection standard to determine whether calibration is required, if necessary, perform calibration and return to step S3, otherwise return to step S1 to test the next chip to be tested.

[0047] Preferably, in step S5, if calibration is required, it is determined whether the number of calibration times reaches the calibration upper limit threshold. If not, it returns to step S3; otherwise, the chip to be tested is marked as a bad chip, and then it returns to step S1 to test the next chip to be tested.

[0048] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art may modify and change the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A fast oscillator oscillation frequency test system, comprising: The chip to be tested includes an oscillator to be tested and / or an oscillation frequency correction circuit to be tested, and is used to generate an oscillation output to be tested; An overshoot enhancement network, used for converting the oscillation output of the chip under test into an overshoot oscillation with a required specific damping; The tester is used for sampling the output of an oscillator with overshoot by using its high-speed digital channel, loading a test program to normalize the sampled transition data to filter redundant sampling information, and calculating the test frequency according to the normalized processing result of the transition data.

2. A fast oscillator oscillation frequency test system as claimed in claim 1, characterized in that: The overshoot enhancement network generates an overshoot with specific damping by using the inherent parasitic capacitance and inductive load of the test probe and the test PCB board.

3. A fast oscillator oscillation frequency test system as claimed in claim 2, characterized in that: The overshoot enhancement network increases the overshoot by additionally adding an RLC mismatch network on the test PCB board.

4. A fast oscillator oscillation frequency test system as claimed in claim 3, characterized in that: According to the oscillation output of the chip to be tested, the parameters of the overshoot enhancement network are adjusted to generate overshoot, so that it produces high-order damped oscillation, the amplitude V1 of the first peak at the rising edge is detected, the time difference between the two troughs after the peak is obtained to determine the frequency of the damped oscillation, and the amplitude V2 of the second peak after the rising edge is measured to set the high and low level thresholds.

5. A fast oscillator oscillation frequency test system as claimed in claim 4, characterized in that: By increasing the damping coefficient of the overshoot enhancement network, the oscillation output of the chip under test has only a large overshoot.

6. A method for testing the oscillation frequency of a fast oscillator, comprising the following steps: Step S1, connecting the test system, reliably pressing the test probe onto the chip to be tested, and adjusting the parameters of the overshoot enhancement network so that the waveform output by the overshoot enhancement network has only one high-amplitude narrow pulse; Step S2, sampling the oscillation output of the chip to be tested according to a preset sampling period; Step S3, finding the transition point according to the sampled data and normalizing the single transition data; Step S4, recover data and obtain the total number of failures during the test (N F ), calculate the normalized jump number (N P / Fnormal ), and according to the normalized jump number (N P / Fnormal ) and the number of sampling times (N S ) and sampling period (T S ) to get the test frequency.

7. A fast oscillator oscillation frequency testing method as claimed in claim 6, characterized in that: In step S1, the waveform output by the overshoot enhancement network has only one high-amplitude narrow pulse, which means that the first peak of the overshoot is significantly higher than the second peak, and its minimum width is based on what the tester can distinguish.

8. A fast oscillator oscillation frequency testing method as claimed in claim 6, characterized in that: The calculation formula of the test frequency is as follows: 。 9. A fast oscillator oscillation frequency testing method as claimed in claim 6, characterized in that: After step S4, the method further includes the following steps: Step S5, compare the test frequency with the inspection standard to determine whether calibration is required, if necessary, perform calibration and return to step S3, otherwise return to step S1 to test the next chip to be tested.

10. A fast oscillator oscillation frequency testing method as claimed in claim 9, characterized in that: In step S5, if calibration is required, it is determined whether the number of calibration times reaches the calibration upper limit threshold. If not, it returns to step S3. Otherwise, it marks the chip under test as a bad chip, and then returns to step S1 to test the next chip under test.

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