Storage device, flash memory controller and control method thereof

Abstract

The present invention relates to a storage device, a flash memory, and a control method therefor. A control method applied to a flash memory controller for accessing a flash memory module, the control method comprising: receiving a setting instruction from a host device to set at least a part of the flash memory module as a namespace; receiving a write instruction from the host device to write data corresponding to a first region to a plurality of blocks in the flash memory module, wherein the access mode for writing the data of the first region to the plurality of blocks is determined according to the size of each region and each block.

Description

Technical Field

[0001] The present invention relates to a flash memory. Background Art

[0002] In the Non-Volatile Memory express (NVMe) specification, a zoned namespace is defined. However, since the above-mentioned zoned namespace and each zone therein are viewed solely from the perspective of the host device, the size of each zone defined by the host device does not have a fixed relationship with the size of each block in the flash memory module of the storage device. Therefore, when the host device is ready to write data corresponding to a zone into the flash memory module, the flash memory controller needs to establish a large number of logical address and physical address mapping tables, for example, recording the mapping relationship between logical addresses and physical addresses in units of data pages, thus causing a burden on the flash memory controller in data processing and also occupying the storage space of Static Random Access Memory (SRAM) and / or Dynamic Random Access Memory (DRAM). Summary of the Invention

[0003] Therefore, one object of the present invention is to provide a flash memory controller that can efficiently manage data in the zoned namespace written by the host device into the flash memory module, and the established logical address and physical address mapping table has a smaller size to solve the problems described in the prior art.

[0004] In an embodiment of the present invention, a control method applied to a flash memory controller is disclosed. The flash memory controller is used to access a flash memory module. The flash memory module includes a plurality of blocks, and each block includes a plurality of data pages. The control method includes: receiving a setting instruction from a host device, where the setting instruction sets at least a part of the flash memory module as a regional namespace. The regional namespace logically includes a plurality of regions. The host device must write and access data in the regional namespace in units of regions. The size of each region is the same. The logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions; using one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device into the flash memory module, where the data is all the data of a specific region; if the first access mode is used: write the data into a plurality of specific blocks of the flash memory module in sequence according to the order of the logical addresses of the data; and after the data is written, write invalid data into the remaining data pages of the last specific block of the plurality of specific blocks, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasure; if the second access mode is used: write the data into the plurality of specific blocks of the flash memory module in sequence according to the order of the logical addresses of the data; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region; if the third access mode is used: write the data into a single specific block of the flash memory module in sequence according to the order of the logical addresses of the data; and after the data is written, write invalid data into the remaining data pages of the specific block, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasure; if the fourth access mode is used: write the data into a single specific block of the flash memory module in sequence according to the order of the logical addresses of the data; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region.

[0005] In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module. The flash memory module includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller includes a read-only memory, a microprocessor, and a buffer memory. The read-only memory is used to store a program code, and the microprocessor is used to execute the program code to control the access to the flash memory module. In the operation of the flash memory controller, the microprocessor receives a setting instruction from a host device. The setting instruction sets at least a part of the flash memory module as a regional namespace. The regional namespace logically includes a plurality of regions. The host device must perform data write access to the regional namespace in units of regions. The size of each region is the same. The logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions. The microprocessor uses one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device to the flash memory module, where the data is all the data of a specific region. When the microprocessor uses the first access mode: according to the order of the logical addresses of the data, the data is sequentially written into a plurality of specific blocks of the flash memory module; and after the data is written, the remaining data pages of the last specific block among the plurality of specific blocks are written with invalid data, or the remaining data pages are kept blank and no data from the host device is written according to the write instruction of the host device before erasure. When the microprocessor uses the second access mode: according to the order of the logical addresses of the data, the data is sequentially written into the plurality of specific blocks of the flash memory module; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region. When the microprocessor uses the third access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module; and after the data is written, the remaining data pages of the specific block are written with invalid data, or the remaining data pages are kept blank and no data from the host device is written according to the write instruction of the host device before erasure. When the microprocessor uses the fourth access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region.

[0006] In another embodiment of the present invention, a storage device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller is used to access the flash memory module. During the operation of the storage device, the flash memory controller receives a setting instruction from a host device. The setting instruction is to set at least a part of the flash memory module as a regional namespace. The regional namespace logically includes a plurality of regions. The host device must write and access data in the regional namespace in units of regions. The size of each region is the same. The logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions. The flash memory controller uses one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device into the flash memory module. The data is all the data of a specific region. When the flash memory controller uses the first access mode: according to the order of the logical addresses of the data, the data is sequentially written into a plurality of specific blocks of the flash memory module. After the data is written, the remaining data pages of the last specific block among the plurality of specific blocks are written with invalid data, or the remaining data pages are kept blank and no data from the host device is written according to the write instruction of the host device before erasure. When the flash memory controller uses the second access mode: according to the order of the logical addresses of the data, the data is sequentially written into the plurality of specific blocks of the flash memory module. Only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region. When the flash memory controller uses the third access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module. After the data is written, the remaining data pages of the specific block are written with invalid data, or the remaining data pages are kept blank and no data from the host device is written according to the write instruction of the host device before erasure. When the flash memory controller uses the fourth access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module. Only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present invention.

[0008] Figure 2ASchematic diagram of a flash memory controller in a storage device according to an embodiment of the present invention.

[0009] Figure 2B Schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0010] Figure 3 Schematic diagram of a flash memory module including a general storage space and a regional namespace.

[0011] Figure 4 Schematic diagram of a regional namespace divided into multiple regions.

[0012] Figure 5 Flowchart of writing data from a host device to a regional namespace according to an embodiment of the present invention.

[0013] Figure 6 Schematic diagram of writing data of a region to a block in a flash memory module.

[0014] Figure 7A Schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0015] Figure 7B Schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0016] Figure 7C Schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0017] Figure 7D Schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0018] Figure 8 Flowchart of reading data from a regional namespace according to an embodiment of the present invention.

[0019] Figure 9 Flowchart of writing data from a host device to a regional namespace according to another embodiment of the present invention.

[0020] Figure 10 Schematic diagram of writing data of a region to a block in a flash memory module.

[0021] Figure 11A Schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention.

[0022] Figure 11B Schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention.

[0023] Figure 12 Schematic diagram of a shared block table according to another embodiment of the present invention.

[0024] Figure 13 It is a flowchart for reading data from a self - region namespace according to an embodiment of the present invention.

[0025] Figure 14 It is a flowchart for writing data from a host device to a region namespace according to another embodiment of the present invention.

[0026] Figure 15 It is a schematic diagram of writing data of a region to a block in a flash memory module.

[0027] Figure 16 It is a schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0028] Figure 17 It is a flowchart for reading data from a self - region namespace according to another embodiment of the present invention.

[0029] Figure 18 It is a flowchart for writing data from a host device to a region namespace according to another embodiment of the present invention.

[0030] Figure 19 It is a schematic diagram of writing data of a region to a block in a flash memory module.

[0031] Figure 20 It is a schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0032] Figure 21 It is a flowchart for reading data from a self - region namespace according to an embodiment of the present invention.

[0033] Figure 22 It is a schematic diagram of a superblock in a general storage space.

[0034] Figure 23 It is a flowchart of a method for configuring a flash memory module according to an embodiment of the present invention.

[0035] Figure 24 It is a schematic diagram of a superblock in a region namespace.

[0036] Figure 25 It is a flowchart of a control method applied to a flash memory controller according to an embodiment of the present invention.

[0037]

Symbol Description

[0038] 100: Electronic device

[0039] 110: Host device

[0040] 120_1, 120_2, 120_N: Storage device

[0041] 122: Flash Memory Controller

[0042] 124: Flash Memory Module

[0043] 212: Microprocessor

[0044] 212C: Program Code

[0045] 212M: Read-Only Memory

[0046] 214: Control Logic

[0047] 216: Buffer Memory

[0048] 218: Interface Logic

[0049] 232: Encoder

[0050] 234: Decoder

[0051] 240: Dynamic Random Access Memory

[0052] 200: Block

[0053] BL1, BL2, BL3: Bit Line

[0054] WL0~WL2, WL4~WL6: Word Line

[0055] 310_1, 310_2: Region Namespace

[0056] 320_1, 320_2: General Storage Space

[0057] Z0, Z1, Z2, Z3: Region

[0058] LBA_k~LBA_(k+x-1): Logical Address

[0059] 500~508: Step

[0060] B3, B7, B8, B12, B99, B6: Block

[0061] P1~PM: Data Page

[0062] 700, 710, 720, 730: L2P Mapping Table

[0063] 800~806: Step

[0064] 900~906: Step

[0065] 1100A, 1100B: L2P Mapping Table

[0066] 1130A, 1130B: Shared Block Table

[0067] 1230: Shared Block Table

[0068] 1300~1306: Steps

[0069] 1400~1408: Steps

[0070] B20, B30, B35: Blocks

[0071] 1600: L2P Mapping Table

[0072] 1700~1706: Steps

[0073] 1800~1806: Steps

[0074] 2000: L2P Mapping Table

[0075] 2100~2106: Steps

[0076] 2210, 2220, 2230, 2240: Flash Memory Chips

[0077] 2212, 2214, 2222, 2224, 2232, 2234, 2242, 2244: Data Surfaces

[0078] 2261, 2262: Super Blocks

[0079] 2300~2306: Steps

[0080] 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444: Data Surfaces

[0081] 2461, 2462: Super Blocks Detailed Implementation Manner

[0082] Figure 1 Schematic diagram of an electronic device 100 according to an embodiment of the present invention. As Figure 1As shown, the electronic device includes a main device 110 and a plurality of storage devices 120_1 to 120_N. Taking the storage device 120_1 as an example, each storage device includes a flash memory controller 122 and a flash memory module 124. In this embodiment, each of the plurality of storage devices 120_1 to 120_N can be a solid-state drive (SSD) or any storage device having a flash memory module. The main device can be a central processing unit or other electronic devices or components that can be used to access the storage devices 120_1 to 120_N, and the electronic device 100 itself can be a server, a personal computer, a notebook computer, or any portable electronic device. It should be noted that although Figure 1 a plurality of storage devices 120_1 to 120_N are shown, in an embodiment, the electronic device 100 can have only a single storage device 120_1.

[0083] Figure 2A FIG. is a schematic diagram of the flash memory controller 122 in the storage device 120_1 according to an embodiment of the present invention. As Figure 2A shown, the flash memory controller 122 includes a microprocessor 212, a read-only memory (ROM) 212M, a control logic 214, a buffer memory 216, and an interface logic 218. The read-only memory 212M is used to store a program code 212C, and the microprocessor 212 is used to execute the program code 212C to control the access to the flash memory module 124. The control logic 214 includes an encoder 232 and a decoder 234. The encoder 232 is used to encode the data written into the flash memory module 220 to generate a corresponding check code (or, error correction code (ECC)), and the decoder 234 is used to decode the data read from the flash memory module 124.

[0084] Typically, the flash memory module 124 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 122 erases data from the flash memory module 124 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 122 writes data to the flash memory module 124 in units of data pages. In this embodiment, the flash memory module 124 is a three-dimensional NAND-type flash memory (3D NAND-type flash) module.

[0085] In practice, the flash memory controller 210 that executes the program code 212C through the microprocessor 212 can utilize its own internal components to perform various control operations. For example, it uses the control logic 214 to control the access operations of the flash memory module 124 (especially the access operations to at least one block or at least one data page), uses the buffer memory 216 to perform the required buffering process, and uses the interface logic 218 to communicate with the host device 110. The buffer memory 216 is implemented with a random access memory (RAM). For example, the buffer memory 216 can be SRAM, but the present invention is not limited thereto. In addition, the flash memory controller 122 is coupled to a DRAM 240. Note that the DRAM 240 can also be included within the flash memory controller 122, for example, existing in the same package as the flash memory controller 122.

[0086] In this embodiment, the storage device 120_1 supports the NVMe specification. That is, the interface logic 218 can conform to a specific communication standard (such as the Peripheral Component Interconnect (PCI) standard or the PCIe standard), and can communicate according to the specific communication standard, for example, communicate with the host device 110 through a connector.

[0087] Figure 2B FIG. is a schematic diagram of a block 200 in a flash memory module 124 according to an embodiment of the present invention, where the flash memory module 124 is a three-dimensional NAND flash memory. As Figure 2B shown, the block 200 includes a plurality of memory cells (such as the illustrated floating gate transistors 202 or other charge trap elements), which constitute a three-dimensional NAND flash memory architecture through multiple bit lines (only BL1 to BL3 are illustrated in the figure) and multiple word lines (such as WL0 to WL2, WL4 to WL6 illustrated in the figure). In Figure 2BAmong them, taking the topmost plane as an example, all the floating-gate transistors on the word line WL0 constitute at least one data page, all the floating-gate transistors on the word line WL1 constitute another at least one data page, and all the floating-gate transistors on the word line WL2 constitute yet another at least one data page, and so on. In addition, according to the different writing methods of the flash memory, the definition between the word line WL0 and the data page (logical data page) will also be different. Specifically, when writing in the single-level cell (SLC) mode, all the floating-gate transistors on the word line WL0 only correspond to a single logical data page; when writing in the multi-level cell (MLC) mode, all the floating-gate transistors on the word line WL0 correspond to two logical data pages; when writing in the three-level cell (TLC) mode, all the floating-gate transistors on the word line WL0 correspond to three logical data pages; and when writing in the quad-level cell (QLC) mode, all the floating-gate transistors on the word line WL0 correspond to four logical data pages. Since those with ordinary knowledge in the technical field should be able to understand the structure of the three-dimensional NAND flash memory and the relationship between the word line and the data page, the relevant details are not elaborated here.

[0088] In this embodiment, the host device 110 can set at least a part of the flash memory module 124 as a zoned namespace by sending a set of commands, such as the Zoned Namespaces Command Set. Refer to Figure 3 As shown, the host device 110 can send a set of commands to the flash memory controller 122 so that the flash memory module 124 has at least one zoned namespace (taking the zoned namespaces 310_1 and 310_2 as examples in this embodiment) and at least one general storage space (taking the general storage spaces 320_1 and 320_2 as examples in this embodiment). The access to the zoned namespace 310_1 is divided into multiple zones, and the host device 110 must write data to the zoned namespace 310_1 in units of logical block addresses (LBA). A logical block address (or simply referred to as a logical address) can represent a data volume of 512 bytes, and the host device 110 needs to perform continuous writing to a zone. Specifically, refer to Figure 4, the region namespace 310_1 is divided into multiple regions (e.g., Z0, Z1, Z2, Z3, etc.), where the size of each region is set by the host device 110, and the size of each region is the same. The logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions (i.e., a logical address can only exist in one region). For example, assume that the size of each region is x logical addresses, and the starting logical address of region Z3 is LBA_k. Then region Z3 is used to store data corresponding to logical addresses LBA_k, LBA_(k + 1), LBA_(k + 2), LBA_(k + 3), …, LBA_(k + x - 1). In one embodiment, the logical addresses of adjacent regions are also continuous. For example, region Z0 is used to store data with logical addresses LBA_1 to LBA_2000, region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, region Z2 is used to store data with logical addresses LBA_4001 to LBA_6000, region Z3 is used to store data with logical addresses LBA_6001 to LBA_8000, and so on. In addition, the amount of data corresponding to a logical address can be determined by the host device 110. For example, the amount of data corresponding to a logical address can be 4 kilobytes (KB).

[0089] In addition, when writing data for each region, it must be done in the order of logical addresses. Specifically, the flash memory controller 122 sets a write pointer according to the data to be written to control the write order of the data. Specifically, assume that region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000. After the host device 110 transfers data corresponding to logical addresses LBA_2001 to LBA_2051 to the flash memory controller 122, the flash memory controller 122 sets the write pointer to the next logical address LBA_2052. If the host device 110 subsequently transfers data belonging to the same region but not with logical address LBA_2052, such as data with logical address LBA_3000, the flash memory controller 122 will reject this data write and send a write failure message back to the host device 110. In other words, only when the logical address of the received data is the same as the logical address pointed to by the write pointer, the flash memory controller 122 will allow the data to be written. Additionally, when writing data from multiple regions alternately, each region can have its own write pointer.

[0090] As described above, the main device 110 communicates with the storage device 120_1 in units of regions to access the regional namespace 310_1. However, since the above regional namespace 310_1 and each region are viewed from the perspective of the main device 110, the size of each region defined by the main device 110 does not have a fixed relationship with the size of each physical block in the flash memory module 124 of the storage device 120_1. Specifically, flash memory modules manufactured by different flash memory module manufacturers are not the same. Different memory modules have different-sized physical blocks, and the sizes of these physical blocks are not necessarily integer multiples. For example, the physical block size of flash memory module of model A may be 1.3 times that of the physical block of flash memory module of model B, and the physical block size of flash memory module of model C may be 3.7 times that of the physical block of flash memory module of model B. As a result, it is very difficult for the regions set by the main device 110 to align with the physical blocks. At this time, the flash memory controller 122 will face great difficulties when mapping logical blocks to physical blocks. For example, there may be a lot of redundant space in the storage device 120_1 that cannot be used by the user, or when the main device 110 is about to write the data corresponding to a region into the flash memory module 124, it will increase the complexity of the flash memory controller 122 in establishing a logical address to physical address (L2P) mapping table. The present invention proposes a method in the following embodiments that can enable the flash memory controller 122 to efficiently access the regional namespace 310_1 according to the access instructions of the main device 110.

[0091] Figure 5 FIG. is a flowchart of writing data from the main device 110 to the regional namespace 310_1 according to an embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each physical block in the flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each physical block in the flash memory module 124. In step 500, the process starts. The main device 110 and the storage device 120_1 are powered on and the initialization operation is completed. The main device 110 sets basic settings such as the size of each region, the number of regions, and the logical block address size for at least a part of the storage regions in the storage device 120_1, for example, by using the Zoned Namespaces Command Set. In step 502, the main device 110 sends a write instruction and the corresponding data to the flash memory controller 122, where the above data is the data corresponding to one or more regions, such as Figure 4Data corresponding to logical addresses LBA_k to LBA_(k+x-1) in the middle region Z3. In step 504, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124, and sequentially writes the data from the host device 110 into the at least one block. Since it is very difficult for the size of the region set by the host device 110 to match the size of the physical block, when the host device issues write commands to all the logical addresses in region Z3, the data that the host device 110 wants to write usually still cannot fill the storage space of the physical block. Or rather, generally, the amount of data stored corresponding to a region is usually not an integer multiple of the size of the region in a physical block used to store the data written by the host device 110. In step 506, when the data is written to the last block and the data writing is completed, the flash memory controller 122 writes invalid data to the remaining data pages of the last block, or directly keeps the remaining data pages blank. Note that each block usually reserves several data pages to store system management information, such as data required for management such as write schedules, logical-physical mapping tables, check bits of error correction codes, RAID parity of disk arrays, etc. The remaining data pages referred to here are the data pages that are still left after writing the system management information and the data that the host device 110 wants to store.

[0092] For example, referring to Figure 6, assuming that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124, the flash memory controller 122 can, in response to the write command sent by the host device 110 for region Z1, sequentially write the data of region Z1 into blocks B3, B7, and B8. Note that, in one embodiment, the write instruction sent by the host device 110 for region Z1 includes the starting logical address of region Z1, and the flash memory controller 122 maps the starting logical address of region Z1 to the starting physical storage space of physical block B3, such as the first physical data page. Moreover, the flash memory controller 122 stores the data corresponding to the starting logical address of region Z1 in the starting physical storage space of physical block B3, such as the first physical data page. Blocks B3, B7, and B8 all contain data pages P1 to PM, and the data of region Z1 is sequentially written starting from the first data page P1 of block B3 according to the logical address until the last data page PM. After the data writing in block B3 is completed, the writing continues from the first data page P1 of block B7 until the last data page PM. Note that even if the host device 110 continuously writes to the logical addresses within region Z1, the flash memory controller 122 can still choose non - consecutive blocks B3 and B7 to store the logically consecutive data. After the data writing in block B7 is completed, the writing continues from the first data page P1 of block B8 until the data of region Z1 ends; in addition, the remaining data pages of block B8 will remain blank or be written with invalid data. Similarly, the flash memory controller 122 can sequentially write the data of region Z3 into blocks B12, B99, and B6, where blocks B12, B99, and B6 all contain data pages P1 to PM, and the data of region Z3 is sequentially written starting from the first data page P1 of block B12 according to the logical address until the last data page PM. After the data writing in block B12 is completed, the writing continues from the first data page P1 of block B99 until the last data page PM, and after the data writing in block B99 is completed, the writing continues from the first data page P1 of block B6 until the data of region Z3 ends; in addition, the remaining data pages of block B6 will remain blank or be written with invalid data. Note that the flash memory controller 122 may not establish the logical page - to - physical page link relationship for the physical data pages where the invalid data is located. And the physical blocks with physical data pages that remain blank or are written with invalid data are usually mapped by the flash memory controller 122 to the last part of each region, or rather, the flash memory controller 122 stores the data corresponding to the last logical address of the region in a physical block with blank pages or pages written with invalid data. For example Figure 7BAs shown in (to be described later), the logical address Z1_LBA + S + 2*y corresponds to the physical block address PBA8. Moreover, if the data of the last logical address of a region is stored in the Xth storage unit (such as a physical storage page or section) of a physical block, the (X + 1)th storage unit of that physical block is reserved as a blank page or written with invalid page data, that is, the blank page or the data page written with invalid data follows the physical storage unit where the data of the last logical address of the corresponding region is stored. In another embodiment, the host device 110 defines a larger zone size and a smaller zone capacity. For example, the zone size is 512 MB and the zone capacity is 500 MB. In this example, the flash memory controller 122 may not directly follow the physical storage unit where the data of the last logical address of the corresponding region is stored with a blank page or a data page written with invalid data.

[0093] In another embodiment, the host device 110 sends write commands for consecutive logical addresses in regions Z1 and Z2, and the flash memory controller 122 selects blocks B3, B7, B8, B12, B99, and B6 to store data belonging to regions Z1 and Z2. Since the size of the region set by the device 110 does not match the size of the physical block, the data that the host device 110 desires to write still cannot fill the storage space of the physical block. For example, the storage space in physical block B8 for storing host data cannot be filled. Therefore, the flash memory controller 122 still has to leave the storage space in physical block B8 blank or fill it with invalid data. So, even though the host device 110 sends write commands for consecutive logical addresses in regions Z1 and Z2 and there is still space in physical block B8 to store data, the flash memory controller 122 still will not store the data corresponding to the starting logical address of region Z2 in physical block B8. In other words, even if the host device 110 sends a write command for consecutive logical addresses (such as a write command that includes the last logical address of region Z1 and the first logical address of region Z2), and a specific physical block (such as physical block B8) has enough space to store the data for these consecutive logical addresses, the flash memory controller 122 still will not store the data corresponding to these consecutive logical addresses continuously in the specific physical block, but will jump to write the data corresponding to the first logical address of region Z2 into another physical block, such as block B20. Correspondingly, if the host device 110 sends a read command for consecutive logical addresses in regions Z1 and Z2 (such as a read command that includes the last logical address of region Z1 and the first logical address of region Z2), after the flash memory controller 122 reads the data corresponding to the last logical address of region Z1 stored in physical block P8, it will also jump to read the first storage location of block B20 to obtain the data corresponding to the first logical address of region Z2.

[0094] In step 508, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent use when reading data from the region namespace 310_1. Figure 7A FIG. is a schematic diagram of an L2P mapping table 700 according to an embodiment of the present invention. The L2P mapping table 700 includes two fields, one field records the starting logical address of the region, and the other field records the physical block address of the block. Referring also to Figure 6, since the data in region Z1 is sequentially written to blocks B3, B7, and B8, and the data in region Z3 is sequentially written to blocks B12, B99, and B6, the L2P mapping table 700 records the starting logical address Z1_LBA_S of region Z1 and the physical block addresses PBA3, PBA7, and PBA8 of blocks B3, B7, and B8, and records the starting logical address Z3_LBA_S of region Z3 and the physical block addresses PBA12, PBA99, and PBA6 of blocks B12, B99, and B6. For example, assume that region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, and region Z3 is used to store data with logical addresses LBA_6001 to LBA_8000. Then the starting logical address Z1_LBA_S of region Z1 is LBA_2001, and the starting logical address Z3_LBA_S of region Z3 is LBA_6001. Note that the steps in the flowchart of writing data from the host device 110 to the region namespace 310_1 do not necessarily have to be performed in a fixed order as long as the same purpose can be achieved. For example, step 508 can be executed after step 502, and those skilled in the art can understand this under the teaching of the present invention. Note that in this embodiment, each physical block corresponds to only one region. For example, blocks B3, B7, and B8 only correspond to region Z1, and blocks B12, B99, and B6 only correspond to region Z3. Or rather, a single block stores data of only a single region. For example, blocks B3, B7, and B8 only store the data corresponding to region Z1, and blocks B12, B99, and B6 only store the data corresponding to region Z3.

[0095] In addition, if the main device 110 wants to reset a region, for example, reset region Z1, the flash memory controller 122 usually modifies the L2P mapping table 700 to delete the fields of the physical block addresses corresponding to region Z1. For example, delete the physical block addresses PBA3, PBA7, and PBA8 in the L2P mapping table 700, indicating that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can then erase these physical blocks at a later time. Note that the physical block B8 stores the data and invalid data that the main device 110 wants to store. Although the region Z1 that the main device 110 wants to reset does not contain this invalid data. For management convenience, after receiving the reset instruction from the main device 110 for region Z1, the flash memory controller 122 still deletes the physical block address PBA8 in the L2P mapping table 700 as a whole, even though the region Z1 that the main device 110 wants to reset does not contain the invalid data stored in the physical block B8. Also, before erasing the physical block B8, the flash memory controller 122 does not move the invalid data not included in the reset instruction issued by the main device 110 to other physical blocks, but directly deletes the entire physical block.

[0096] In the above embodiments, the data stored in any physical block within the region namespace 310_1 must belong to the same region. That is, the logical addresses corresponding to all the data stored in any physical block will belong to the same region. And because the main device 110 can only write continuously to the logical addresses within a region. Therefore, the L2P mapping table 700 of this embodiment can only contain the physical block addresses of the region namespace 310_1, and will not contain any data page addresses. That is, the L2P mapping table 700 does not record the data page numbers or related data page information within any block. In addition, the L2P mapping table 700 only records the starting logical address of each region. Therefore, the L2P mapping table 700 itself has a very small amount of data. So, the L2P mapping table 700 can be resident in the cache memory 216 or the DRAM 240 without imposing too much burden on the storage space of the cache memory 216 or the DRAM 240. Note that since the starting logical addresses of each region are fixed after the main device 110 sets the region size and the number of regions, the L2P mapping table 700 can be further simplified to a single field, that is, only the physical block address field. And the starting logical address field of the region can be represented by the entries of the table, as Figure 7B shown in the L2P mapping table 710, without actually storing the starting logical addresses of multiple regions.

[0097] In the above embodiments, the L2P mapping table 700 may only contain the physical block addresses of the entity blocks in the region namespace 310_1, and does not contain any data page addresses. However, in another embodiment, the L2P mapping table 700 may contain the starting logical address of each region, the corresponding physical block address, and the physical data page address of the first data page. Since one region in the L2P mapping table only contains one physical block address and one physical data page address, the data volume is also very small.

[0098] Figure 7C FIG. is a schematic diagram of an L2P mapping table 720 according to an embodiment of the present invention. The L2P mapping table 720 includes two fields, one field records the logical address, and the other field records the physical block address of the block. Referring also to Figure 6, since the data in region Z1 is sequentially written to blocks B3, B7, and B8, and the data in region Z3 is sequentially written to blocks B12, B99, and B6, the L2P mapping table 720 records the starting logical address Z1_LBA_S of region Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S + y) of region Z1 and the physical block address PBA7 of block B7, and the logical address (Z1_LBA_S + 2*y) of region Z1 and the physical block address PBA8 of block B8. Here, the logical address (Z1_LBA_S + y) can be the first logical address of the data written to block B7 (i.e., the logical address corresponding to data page P1 of block B7), and the logical address (Z1_LBA_S + 2*y) can be the first logical address of the data written to block B8 (i.e., the logical address corresponding to data page P1 of block B8); similarly, the L2P mapping table 720 records the starting logical address Z3_LBA_S of region Z3 and the physical block address PBA12 of block B12, the logical address (Z3_LBA_S + y) of region Z3 and the physical block address PBA99 of block B99, and the logical address (Z3_LBA_S + 2*y) of region Z6 and the physical block address PBA6 of block B6. Here, the logical address (Z3_LBA_S + y) can be the first logical address of the data written to block B99 (i.e., the logical address corresponding to data page P1 of block B99), and the logical address (Z3_LBA_S + 2*y) can be the first logical address of the data written to block B6 (i.e., the logical address corresponding to data page P1 of block B6). It should be noted that the above "y" can represent how many logical address data a block can store, especially the data that the host device 110 sends to the storage device 120_1 and hopes the storage device 120_1 to store. Note that after the host device 110 sets the region size and the number of regions, the starting logical addresses of each region are fixed, and the starting logical addresses of each sub-region are also fixed, such as Z1_LBA_S, Z1_LBA_S + y, Z1_LBA_S + 2*y, Z2_LBA_S, Z2_LBA_S + y, Z2_LBA_S + 2*y... etc. Therefore, similarly, the L2P mapping table 720 can be further simplified to a single field, that is, only the physical block address field. And the logical address field can be represented by the entries of the table without actually storing the starting logical addresses of multiple sub-regions, such as Figure 7D as shown in the L2P mapping table 740 of

[0099] Note that the L2P mapping table 720 of this embodiment only contains the physical block addresses of the region namespace 310_1, and does not contain any data page addresses. That is, the L2P mapping table 720 does not record the data page numbers or related data page information within any block. In addition, the L2P mapping table 720 only records the first logical address corresponding to each block. Therefore, the L2P mapping table 720 itself has a very small amount of data, so the L2P mapping table 720 can be resident in the cache memory 216 or the DRAM 240, without imposing too much burden on the storage space of the cache memory 216 or the DRAM 240. In one embodiment, the physical block addresses recorded in the above L2P mapping table 720 can be additionally paired with the physical data page addresses of the first data page, and adding an additional physical data page address will not impose too much burden on the storage space in practice.

[0100] Figure 8 FIG. is a flowchart for reading data from the region namespace 310_1 according to an embodiment of the present invention, where it is assumed in this embodiment that the region namespace 310_1 has stored Figure 6 the data of regions Z1 and Z3 shown. In step 800, the process starts, and the host device 110 and the storage device 120_1 are powered on and complete the initialization operation (e.g., the boot program). In step 802, the host device 110 sends a read instruction to request reading of data with a specific logical address. In step 804, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates a physical data page address corresponding to the specific logical address according to the logical addresses recorded in the L2P mapping table 700 or the L2P mapping table 720. Taking Figure 7A the L2P mapping table 700 as an example, since the L2P mapping table 700 records the starting logical addresses of each region, and the number of logical addresses in each region is known, therefore, the microprocessor 212 can know which region the specific logical address belongs to from the above information, in order to Figure 6 、 7AAn embodiment will be used for illustration. Assume that the specific logical address is LBA_2500 and a region contains 2000 logical addresses. The L2P mapping table 700 records that the starting logical address Z1_LBA_S of region Z1 is LBA_2001. Then, the microprocessor 212 can determine that this specific logical address belongs to region Z1. Next, based on the difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1, and according to how many logical addresses' worth of data each data page of the block can store, the microprocessor 212 determines the physical data page address corresponding to this specific logical address. For the sake of illustration, assume that each data page in the block can only store the data of one logical address. Then, the difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1 is five hundred logical addresses. Then, the microprocessor 212 can calculate that the physical data page address corresponding to this specific logical address is the five-hundredth data page P500 of block B3. If the number of data pages in block B3 is less than five hundred, then starting from the first data page P1 of block B3, count to the five-hundredth data page to obtain the physical data page address located in block B7.

[0101] On the other hand, taking Figure 7B the L2P mapping table 720 as an illustration, since the L2P mapping table 720 records multiple logical addresses of a region, and these logical addresses respectively correspond to the first data page P1 of blocks B3, B7, and B8. Therefore, the microprocessor 212 can learn from the above information which region and which block this specific logical address belongs to. Next, based on the difference between this specific logical address and the logical address of region Z1 (for example, Z1_LBA_S, (Z1_LBA_S + y), or (Z1_LBA_S + 2y)), and according to how many logical addresses' worth of data each data page of the block can store, the microprocessor 212 determines the physical data page address corresponding to this specific logical address. For the sake of illustration, assume that each data page in the block can only store the data of one logical address. Then, the difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1 is five hundred logical addresses. Then, the microprocessor 212 can calculate that the physical data page address corresponding to this specific logical address is the five-hundredth data page P500 of block B3.

[0102] In step 806, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the physical block address and the physical data page address determined in step 804, and returns the read data to the host device 110.

[0103] As described above, through the content of the above embodiments, the flash memory controller 122 can still effectively complete the data writing and reading of the regional namespace 310_1 when only a very small-sized L2P mapping table 700 / 710 / 720 / 730 is established. However, in this embodiment, there will be many remaining data pages in physical blocks wasted, such as the blank or invalid data pages in physical block B8 and physical block B6. These remaining data pages will greatly reduce the memory space that can be used by the user. Although this method can reduce the management burden of the flash memory controller 122, it will reduce the memory space that can be used by the user. Even in some extreme cases, due to the too high proportion of the remaining data pages, it may even cause the flash memory controller 122 to be unable to allocate enough memory space for the user to use.

[0104] Figure 9 A flowchart for writing data from the host device 110 to the regional namespace 310_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each block in the flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each block in the flash memory module 124. In step 900, the process starts. The host device 110 and the storage device 120_1 are powered on and complete the initialization operation. The host device 110 sets basic settings such as the size of each region, the number of regions, and the logical block address size for the storage device 120_1, for example, by using the Zoned Namespaces Command Set. In step 902, the host device 110 sends a write command and the corresponding data to the flash memory controller 122, where the above data is the data corresponding to one or more regions, such as Figure 4 the data corresponding to the logical addresses LBA_k to LBA_(k+x-1) in region Z3. In step 904, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124, or selects at least one blank block or at least one common block, and sequentially writes the data from the host device 110 into these blocks. For example, referring to Figure 10, assuming that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124, the flash memory controller 122 can sequentially write the data of region Z1 into blocks B3, B7, and B8, where block B3 stores the first part of the data Z1_0 of region Z1, block B7 stores the second part of the data Z1_1 of region Z1, and block B8 stores the third part of the data Z1_2 of region Z1. In this embodiment, since the data stored in blocks B3 and B7 is completely the data of region Z1, and only some data pages in block B8 store the data of region Z1, therefore, in order to make full use of the remaining data pages of block B8, the microprocessor 212 will set block B8 as a shared block, that is, the remaining data pages of block B8 can be used to store the data of other regions. Continue to refer to Figure 10 , the flash memory controller 122 is ready to write the data of region Z3 into the region namespace 310_1. Since there is still remaining space in the shared block B8, the microprocessor 212 selects two blank blocks B12, B99 and the shared block B8 to store the data of region Z3. Specifically, the flash memory controller 122 sequentially writes the data of region Z3 into blocks B12, B99, and B8, where block B12 stores the first part of the data Z3_0 of region Z3, block B99 stores the second part of the data Z3_1 of region Z3, and block B8 stores the third part of the data Z3_2 of region Z3. In this embodiment, the data stored in blocks B12 and B99 is completely the data of region Z3, and block B8 will record both the third part of the data Z1_2 of region Z1 and the third part of the data Z3_2 of region Z3. Note that for management convenience, the flash memory controller 122 will not store the first data of any region into the shared block, because this will increase the complexity of the flash memory controller 122 in establishing the L2P mapping table. The flash memory controller 122 will store the first data of each region in an exclusive block, such as blocks B3 and B12. These exclusive blocks will only store the data belonging to the same region, so they are called exclusive blocks. And the last data of any region (the data corresponding to the last logical address of the region) will be stored in the shared block, such as block B8, and in this shared block, the last data of another region will also be stored. In this embodiment, the shared block stores the data of more than one region, or in other words, the shared block stores the last data of more than one region, and the exclusive block only stores the data of a single region.

[0105] In step 906, the flash memory controller 122 establishes or updates an L2P mapping table to record the mapping relationship between the logical address and the physical address, and records a shared block table for use when reading data from the region namespace 310_1 subsequently.Figure 11A Schematic diagram of the L2P mapping table 1100A and the common block table 1130A according to an embodiment of the present invention. The L2P mapping table 1100A includes two fields, one field records the logical address, and the other field records the physical block address of the block. Referring also to Figure 10, since the data in region Z1 is sequentially written to blocks B3, B7, and B8, and the data in region Z3 is sequentially written to blocks B12, B99, and B8, therefore, the L2P mapping table 1100A records the starting logical address Z1_LBA_S of region Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S + y) of region Z1 and the physical block address PBA7 of block B7, and the logical address (Z1_LBA_S + 2*y) of region Z1 and the physical block address PBA8 of block B8. Among them, the logical address (Z1_LBA_S + y) can be the first logical address of the data written to block B7 (i.e., the first logical address of the second part of data Z1_1, and also the logical address corresponding to the first data page P1 of block B7), and the logical address (Z1_LBA_S + 2*y) can be the first logical address of the data written to block B8 (i.e., the first logical address of the third part of data Z1_2); similarly, the L2P mapping table 1100A records the starting logical address Z3_LBA_S of region Z3 and the physical block address PBA12 of block B12, the logical address (Z3_LBA_S + y) of region Z3 and the physical block address PBA99 of block B99, and the logical address (Z3_LBA_S + 2*y) of region Z6 and the physical block address PBA6 of block B6. Among them, the logical address (Z3_LBA_S + y) can be the first logical address of the data written to block B99 (i.e., the first logical address of the second part of data Z3_1, and also the logical address corresponding to the first data page P1 of block B99), and the logical address (Z3_LBA_S + 2*y) can be the first logical address of the data written to block B8 (i.e., the first logical address of the third part of data Z3_2). It should be noted that the above "y" can represent how many logical addresses of data from the host a block can store. Notice that after the main device 110 sets the region size and the number of regions, the starting logical addresses of each region are fixed, and the starting logical addresses of each sub-region are also fixed, such as Z1_LBA_S, Z1_LBA_S + y, Z1_LBA_S + 2*y, Z2_LBA_S, Z2_LBA_S + y, Z2_LBA_S + 2*y... etc. Therefore, similarly, the L2P mapping table 1100 can be further simplified into a field, that is, only the physical block address field. And the logical address field can be represented by the entries of the table, without actually storing the starting logical addresses of multiple sub-regions. Please refer to Figure 11BThe L2P mapping table 1100B has fixed fields for each logical address, and these are sorted from the lowest to the highest (or from the highest to the lowest) logical address. For example, Z0_LBA_S represents the starting logical address of region 0, which is the lowest logical address in the system. Z0_LBA_S + y represents the starting logical address of the second sub-region of region 0, where y represents the number of addresses in each physical block for storing host data. Z0_LBA_S + 2*y represents the starting logical address of the third sub-region of region 0. Since the region size is fixed and the value of y is also fixed, Figure 11B the values in the logical address fields in Figure 11B are quite predictable. Therefore, this field can also be omitted, and only the entries in the L2P mapping table 1100B are used to represent it.

[0106] In addition, the shared block table 1130A contains two fields. One field records the logical address, and the other field records the physical block address and the physical data page address corresponding to the logical address. In Figure 11A Figure 11A , the shared block table 1130A records the first logical address (Z1_LBA_S + 2*y) of the third part of data Z1_2 in region Z1 and the corresponding physical block address PBA8 and physical data page address P1. That is, the data corresponding to the first logical address in the third part of data Z1_2 is written on the first data page P1 of block B8. And the shared block table 1130A records the first logical address (Z3_LBA_S + 2*y) of the third part of data Z3_2 in region Z3 and the corresponding physical block address PBA8 and physical data page address P120. That is, the data corresponding to the first logical address in the third part of data Z3_2 is written on the one-hundred-and-twentieth data page P120 of block B8 (note that here it is assumed that each data page in the block can store the data of only one logical address, and the actual situation can be adjusted according to how many logical addresses' data can be stored in one data page). Similar to Figure 11B the L2P mapping table 1100B in Figure 11B , the shared block table 1130A in Figure 11A can also be Figure 11B presented in the form of the shared block table 1130B in Figure 11B . The reason is the same and will not be elaborated here.

[0107] In addition, it should be noted that during the process of writing the data in Region Z1 and Region Z3, the writing process may not start writing the data in Region Z3 to the Region Namespace 310_1 only after all the data in Region Z1 has been written. In other words, it is possible that when the data in Region Z1 has not been completely written, the Flash Memory Controller 122 needs to start writing the data in Region Z3 to the Region Namespace 310_1. Therefore, in another embodiment of the present invention, the Shared Block Table 1130 may additionally include a Completion Indicator Field, which is used to indicate whether the data in the region has been completely written in the shared block. Refer to Figure 12 as shown, where Figure 12 the Shared Block Table 1230 shown is a continuation of Figure 10 the embodiment. In Figure 12 (a), after all the third part of the data Z1_2 in Region Z1 has been written to the common block B8, the microprocessor 212 will change the completion indicator from '0' to '1'. Then, when the microprocessor 212 needs to write the third part of the data Z3_2 in Region Z3 to the Region Namespace 310_1, since the completion indicator of the third part of the data Z1_2 in Region Z1 corresponding to the common block B8 is '1', the microprocessor 212 can determine that the common block B8 is currently available for data writing. Therefore, the microprocessor 212 writes the third part of the data Z3_2 in Region Z3 to the common block B8, and records the third part of the data Z3_2 and the corresponding physical block address and physical data page address in the Shared Block Table 1230. On the other hand, in Figure 12 (b), when the third part of the data Z1_2 in Region Z1 is being written to the common block B8, its corresponding completion indicator is '0' (indicating that the third part of the data Z1_2 in Region Z1 has not been completely written to the common block B8). If the microprocessor 212 needs to write the third part of the data Z3_2 in Region Z3 to the Region Namespace 310_1 at this time, since the completion indicator of the third part of the data Z1_2 in Region Z1 corresponding to the common block B8 is '0', the microprocessor 212 can determine that the common block B8 is not currently available for writing the third part of the data Z3_2. Therefore, the microprocessor 212 selects another blank block (such as block B15) and writes the third part of the data Z3_2 in Region Z3 to the block B15, and records the third part of the data Z3_2 and the corresponding physical block address PBA15 and physical data page address P1 in the Shared Block Table 1230. Note that Figure 12 the Shared Block Table 1230 in Figure 11B can also be presented in a form similar to that of the Shared Block Table 1130B in Figure 11B by adding a Completion Indicator Field, replacing the logical address field with a fixed logical address position. The reason is the same as that of the L2P Mapping Table 1100B and the Shared Block Table 1130B, which will not be elaborated here.

[0108] In one embodiment, if the host device 110 desires to reset a region, such as region Z1, the flash memory controller 122 typically modifies the L2P mapping table 1100A / 1100B to delete the fields of the physical block addresses corresponding to region Z1. For example, it deletes the physical block addresses PBA3, PBA7, and PBA8 in the L2P mapping table 1100A / 1100B, indicating that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can then erase these physical blocks at a later time. Note that the data that the host device 110 desires to store and the data of region Z3 are stored in physical block B8, although the region Z1 that the host device 110 desires to reset does not include the data of region Z3. For management convenience, after receiving the reset instruction from the host device 110 for region Z1, the flash memory controller 122 still needs to modify the physical block addresses and physical data page addresses in the common block table 1130A / 1130B / 1230, and delete PBA8 and P1, for example, rewrite them as FFFF. Note that the completion flag in the common block table 1230 remains 1 because the third part of region Z1, i.e., Z1_3, still occupies a part of the space in physical block B8, and this space cannot be written again until physical block B8 is erased. Also, before erasing physical block B8, the flash memory controller 122 does not have to move the valid data (such as the data of region Z3) that is not included in the reset instruction issued by the host device 110 to other physical blocks.

[0109] In the above embodiment, since a common block is used to store data corresponding to different regions, it can be considered that data with logical addresses belonging to different regions can be stored in the same physical block, so the space of the physical block can be effectively utilized, avoiding the situation where when the logical addresses corresponding to a region are fully written, the space of an integer number of physical blocks cannot be filled due to the mismatch between the region size and the physical block size, resulting in waste of the remaining data pages in the physical block without storing data.

[0110] Note that the L2P mapping tables 1100A / 1100B of this embodiment only contain the physical block addresses of the region namespace 310_1, and do not contain any data page addresses. That is, the L2P mapping tables 1100A / 1100B do not record the data page numbers or related data page information within any block. In addition, the common block tables 1130A / 1130B / 1230 only record a small number of logical addresses. Even because the logical addresses of the common block tables 1130A / 1130B / 1230 are extremely regular, the logical address fields can be omitted, and only the entries of the table are used to represent. Therefore, the L2P mapping tables 1100A / 1100B and the common block tables 1130A / 1130B / 1230 themselves only have a very small amount of data. Therefore, the L2P mapping tables 1100A / 1100B and the common block tables 1130A / 1130B / 1230 can be resident in the cache memory 216 or the DRAM 240, without imposing too much burden on the storage space of the cache memory 216 or the DRAM 240.

[0111] In addition, since the physical block addresses corresponding to the fields of the last part in this region, such as (Z1_LBA_S + 2*y), (Z3_LBA_S + 2*y), etc. of the L2P mapping tables 1100A / 1100B, are not accurate physical addresses, the microprocessor 212 needs to find the correct physical page address by looking up the common block tables 1130A / 1130B / 1230. Therefore, the physical addresses corresponding to the fields of the last part in this region, such as (Z1_LBA_S + 2*y), (Z3_LBA_S + 2*y), etc. of the L2P mapping tables 1100A / 1100B, such as PBA8, can be directly changed to the corresponding entry addresses of the common block tables 1130A / 1130B / 1230, so that the microprocessor 212 can directly access the corresponding entry addresses of the common block tables 1130A / 1130B / 1230. For example, the PBA8 corresponding to the (Z1_LBA_S + 2*y) field of the L2P mapping tables 1100A / 1100B is directly changed to the memory address corresponding to the (Z1_LBA_S + 2*y) field in the common block tables 1130A / 1130B, and the PBA8 corresponding to the (Z3_LBA_S + 2*y) field of the L2P mapping tables 1100A / 1100B is directly changed to the memory address corresponding to the (Z3_LBA_S + 2*y) field in the common block tables 1130A / 1130B (such as the address in the DRAM or SRAM), to accelerate the search speed.

[0112] Figure 13 FIG. is a flowchart for reading data from the region namespace 310_1 according to an embodiment of the present invention, where it is assumed in this embodiment that the region namespace 310_1 has stored Figure 10Data of the regions Z1 and Z3 shown. In step 1300, the process starts, and the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., boot programs). In step 1302, the main device 110 sends a read instruction to request reading data with a specific logical address. In step 1304, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates a physical data page address corresponding to the specific logical address according to the logical addresses recorded in the L2P mapping tables 1100A / 1100B and / or the common block tables 1130A / 1130B / 1230. With Figure 11ATake the L2P mapping table 1100A as an example. Since the L2P mapping table 1100A records multiple logical addresses in multiple regions, and these logical addresses respectively correspond to the data pages of the nth in block B3, B7, B8, plus the number of logical addresses that each block can store is known. Therefore, the microprocessor 212 can know which region and which block the specific logical address belongs to from the above information. Next, assume that the specific logical address belongs to region Z1. Then, the microprocessor 212 determines the physical data page address corresponding to the specific logical address according to the difference between the specific logical address and the logical address of region Z1 (for example, Z1_LBA_S, (Z1_LBA_S + y), or (Z1_LBA_S + 2y)), and according to how many logical address data each data page of the block can store. For the convenience of explanation, assume that each data page in the block can only store one logical address data. The difference between the specific logical address and the starting logical address Z1_LBA_S of region Z1 is 500 logical addresses, and the specific logical address is between Z1_LBA_S and (Z1_LBA_S + y) (where y represents the number of addresses used to store host data in each physical block, and in this example y > 500). Then, the microprocessor 212 can calculate that the physical data page address corresponding to the specific logical address is the 500th data page P500 of block B3. In this example, the microprocessor 212 divides the difference 500 by y, getting a quotient of 0 and a remainder of 500. Then, the microprocessor 212 can know that the physical block address corresponding to the specific logical address should be in the first entry of the L2P mapping table 1100A. After searching, the microprocessor 212 finds that the physical block address corresponding to the specific logical address is the physical block address PBA3. And since the remainder is 500, the microprocessor 212 can know that the physical page address corresponding to the specific logical address is P500. Note that in addition to addressing in units of physical pages, it is also possible to address with smaller read units, such as sectors or other addressing units that conform to the NVMe specification, such as 4Kbyte. On the other hand, assume that the specific logical address belongs to region Z3. Then, the microprocessor 212 determines the physical data page address corresponding to the specific logical address according to the difference between the specific logical address and the logical address of region Z3 (for example, Z3_LBA_S, (Z3_LBA_S + y), or (Z3_LBA_S + 2y)), and according to how many logical address data each data page of the block can store.For ease of explanation, assume that each data page in a block can store data of only one logical address, where the specific logical address is greater than (Z3_LBA_S + 2y) and less than or equal to the maximum logical address of region Z3, and the difference between the specific logical address and the logical address (Z3_LBA_S + 2y) of region Z3 is eighty logical addresses. Then, the microprocessor 212 can refer to the physical data page address P120 corresponding to the third part of the data Z3_2 of region Z3 recorded in the shared block table 1130, and calculate the physical data page address of the two-hundredth data page P200 of the shared block B8 corresponding to the specific logical address accordingly.

[0113] In step 1306, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the physical block address and the physical data page address determined in step 1304, and returns the read data to the host device 110.

[0114] As described above, through the content of the above embodiments, the flash memory controller 122 can still effectively complete the data writing and reading of the region namespace 310_1 while only creating very small-sized L2P mapping tables 1100A / 1100B and common data tables 1130A / 1130B / 1230.

[0115] In the above Figures 5 to 13 embodiment, it is assumed that the data volume corresponding to each region is greater than the size of each block in the flash memory module 124. However, the host device 110 can also have the data volume corresponding to each region be less than the size of each block in the flash memory module 124, and the related access method is described as follows.

[0116] Figure 14 FIG. is a flowchart for writing data from the host device 110 to the region namespace 310_1 according to another embodiment of the present invention, where in this embodiment, it is assumed that the data volume corresponding to each region is less than the size of each block in the flash memory module 124. In step 1400, the process starts, the host device 110 and the storage device 120_1 are powered on and complete the initialization operation. The host device 110 sets basic settings such as the size of each region, the number of regions, and the logical block address size for the storage device 120_1, for example, by using the Zoned Namespaces Command Set. In step 1402, the host device 110 sends a write command and the corresponding data to the flash memory controller 122, where the above data is data corresponding to one or more regions, for example Figure 4Data corresponding to the logical addresses LBA_k to LBA_(k+x-1) in the middle region Z3. In step 1404, the flash memory controller 122 selects at least one block (blank block, or spare block) from the region namespace 310_1, and sequentially writes the data from the host device 110 into the at least one block in the order of logical addresses. In this embodiment, one block is only used to write the data of a single region, for Figure 15 example, the flash memory controller 122 writes the data of region Z0 into block B20, writes the data of region Z1 into block B30, writes the data of region Z2 into block B35, and so on. In step 1406, after the data of each region is completely written, the flash memory controller 122 writes invalid data into the remaining data pages other than system control in each block, or directly keeps the remaining data pages blank. For Figure 15 example, after the flash memory controller 122 writes all the data of region Z0 into block B20, the remaining data pages of block B20 are kept blank or filled with invalid data. After the flash memory controller 122 writes all the data of region Z1 into block B30, the remaining data pages of block B30 are kept blank or filled with invalid data. And after the flash memory controller 122 writes all the data of region Z2 into block B35, the remaining data pages of block B35 are kept blank or filled with invalid data.

[0117] Note that, in one embodiment, the host device 110 sends write commands for consecutive logical addresses in regions Z0, Z1, and Z2, and the flash memory controller 122 selects blocks B20, B30, and B35 to store data belonging to regions Z0, Z1, and Z2. Since the size of the region set by the device 110 does not match the size of the physical block, the data that the host device 110 desires to write still cannot fill the storage space of the physical block. For example, it cannot fill the storage space of physical block B20 used to store host data. Therefore, the flash memory controller 122 still has to leave the storage space in the physical block B20 blank or fill it with invalid data. So, although the host device 110 sends write commands for consecutive logical addresses in regions Z0 and Z1, and there is still space in the physical block B20 to store data, the flash memory controller 122 still will not store the data corresponding to the starting logical address of region Z1 in the physical block B20. In other words, even if the host device 110 sends a write command for consecutive logical addresses (such as a write command including the last logical address of region Z0 and the first logical address of region Z1), and a specific physical block (such as physical block B20) has enough space to store the data for these consecutive logical addresses, the flash memory controller 122 still will not store the data corresponding to these consecutive logical addresses continuously in the specific physical block, but will jump and write the data corresponding to the first logical address of region Z1 into another physical block, such as block B30. Correspondingly, if the host device 110 sends a read command for consecutive logical addresses in regions Z0 and Z1 (such as a read command including the last logical address of region Z0 and the first logical address of region Z1), after the flash memory controller 122 reads the data corresponding to the last logical address of region Z1 stored in the physical block B20, it will also jump to read the first storage location of block B30 to obtain the data corresponding to the first logical address of region Z1.

[0118] In step 1408, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent use when reading data from the region namespace 310_1. Figure 16 FIG. is a schematic diagram of an L2P mapping table 1600 according to an embodiment of the present invention. The L2P mapping table 1600 includes two fields, one field records the region number or related recognizable content, and the other field records the physical block address of the block. Also refer to Figure 6, since the data of regions Z0, Z1, and Z2 are respectively written into blocks B20, B30, and B35, the L2P mapping table 1600 records the physical block address PBA20 of region Z0 and block B20, the physical block address PBA30 of region Z1 and block B30, and the physical block address PBA35 of region Z2 and block B35. In another embodiment, the above region numbers are represented by the starting logical addresses of the regions, or the block numbers can be linked to the starting logical addresses of the blocks through another lookup table. For example, assume that region Z0 is used to store data with logical addresses LBA_1 to LBA_2000, region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, and region Z2 is used to store data with logical addresses LBA_4001 to LBA_6000. Then the starting logical addresses of regions Z0, Z1, and Z2 are LBA_1, LBA_2001, and LBA_4001 respectively. Note that in this embodiment, each physical block corresponds to only one region. For example, blocks B20, B30, and B35 respectively correspond to regions Z0, Z1, and Z2. Or rather, a single block stores data of only a single region. For example, block B20 stores only the data corresponding to region Z0, block B30 stores only the data corresponding to region Z1, and block B35 stores only the data corresponding to region Z2.

[0119] In the above embodiments, the data stored in any one physical block within the region namespace 310_1 must belong to the same region, that is, the logical addresses of all the data stored in any one physical block will belong to the same region. Therefore, the L2P mapping table 1600 of this embodiment can only contain the physical block addresses of the region namespace 310_1 and will not contain any data page addresses, that is, the L2P mapping table 1600 does not record the data page numbers or related data page information within any block. In addition, the L2P mapping table 1600 will only record the region number or the starting logical address of each region. Therefore, the L2P mapping table 1600 itself only has a very small amount of data. Thus, the 2P mapping table 1600 can be resident in the cache memory 216 or the DRAM 240 without imposing too much burden on the storage space of the cache memory 216 or the DRAM 240. In one embodiment, the physical block address recorded in the above L2P mapping table 1600 can be additionally paired with the physical data page address of the first data page, and adding an additional physical data page address will not impose too much burden on the storage space in practice. Note that after the host device 110 sets the region size and the number of regions, the starting logical addresses of each region are fixed. Therefore, similarly, the L2P mapping table 1600 can be further simplified to a single field, that is, only the physical block address field. And the logical address field can be represented by the entries of the table without actually storing the starting logical addresses of multiple regions.

[0120] In addition, if the host device 110 desires to reset a region, such as resetting region Z1, the flash memory controller 122 will typically modify the L2P mapping table 1600 to delete the field of the physical block address corresponding to region Z1. For example, deleting the physical block address PBA30 in the L2P mapping table 1600 indicates that the host no longer needs the data stored in those physical blocks. And the flash memory controller 122 can erase those physical blocks at a later time. Note that the physical block B30 stores the data and invalid data that the host device 110 desires to store, although the region Z1 that the host device 110 desires to reset does not include those invalid data. For the convenience of management, after receiving the reset instruction from the host device 110 for region Z1, the flash memory controller 122 will still globally delete the physical block address PBA30 in the L2P mapping table 1600, even though the region Z1 that the host device 110 desires to reset does not include the invalid data stored in the physical block B30. And before erasing the physical block B30, the flash memory controller 122 will not move the invalid data not included in the reset instruction issued by the host device 110 to other physical blocks, but directly delete the entire physical block.

[0121] Figure 17 Flowchart for reading data from the self - regional namespace 310_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the regional namespace 310_1 has stored Figure 15 the data of regions Z0, Z1, and Z2 shown. In step 1700, the process starts. The main device 110 and the storage device 120_1 are powered on and complete the initialization operation (e.g., the boot program). In step 1702, the main device 110 sends a read instruction to request reading data with a specific logical address. In step 1704, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates the physical data page address corresponding to the specific logical address according to the logical addresses recorded in the L2P mapping table 1600. Taking Figure 16 the L2P mapping table 1600 as an example, since the L2P mapping table 1600 records the region numbers or starting logical addresses of each region, and the number of logical addresses in each region is known, the microprocessor 212 can know which region the specific logical address belongs to from the above information. For example, if a region contains 2000 logical addresses, the microprocessor 212 divides the logical address (specific logical address) that the host wants to access by 2000, and the quotient obtained is the region where the specific logical address is located. Taking Figure 15 、 16 the embodiment as an example, assume that after the microprocessor 212 divides the specific logical address by 2000 and finds that the quotient is 1, it can be determined that the specific logical address belongs to region Z1. Then, the microprocessor 212 determines the physical data page address corresponding to the specific logical address according to the difference between the specific logical address and the starting logical address of region Z1 (this difference is also the remainder after the microprocessor 212 divides the specific logical address by 2000), and according to how many logical addresses of data each data page in the block can store. For the sake of easy explanation, assume that each data page in the block can only store the data of one logical address, and the difference between the specific logical address and the starting logical address of region Z1 is two hundred logical addresses. Then the microprocessor 212 can calculate that the specific logical address corresponds to the physical data page address of the two - hundredth data page in block B20.

[0122] In step 1706, the microprocessor 212 reads the corresponding data from the regional namespace 310_1 according to the physical block address and physical data page address determined in step 1704, and returns the read data to the main device 110.

[0123] As described above, through the content of the above embodiments, the flash memory controller 122 can still effectively complete the data writing and reading of the regional namespace 310_1 when only creating a very small-sized L2P mapping table 700 / 720. However, in this embodiment, a large amount of physical block storage space will still be wasted, such as Figure 15 the blank or invalid data pages shown in

[0124] Figure 18 FIG. 18 is a flowchart of writing data from the host device 110 to the regional namespace 310_1 according to another embodiment of the present invention, where it is assumed in this embodiment that the amount of data corresponding to each region is less than the size of each block in the flash memory module 124. In step 1800, the process starts, the host device 110 and the storage device 120_1 are powered on and complete the initialization operation, and the host device 110 sets basic settings such as the size of each region, the number of regions, and the logical block address size for the storage device 120_1, for example, by using the Zoned Namespaces Command Set. In step 1802, the host device 110 sends a write command and the corresponding data to the flash memory controller 122, where the above data is the data corresponding to one or more regions, such as Figure 4 the data corresponding to the logical addresses LBA_k to LBA_(k+x-1) of region Z3 in Figure 19 . In step 1804, the flash memory controller 122 selects at least one block (blank block, or spare block) from the regional namespace 310_1, or selects multiple blank blocks and a common block, and sequentially writes the data from the host device 110 into these blocks in the order of the logical addresses within a region. For example, referring to Figure 19 , the flash memory controller 122 can sequentially write the data of regions Z0, Z2, and Z1 into blocks B20 and B30 in the order of logical addresses. Taking Figure 19 as an example, the first data of region Z0 is written starting from the first data page of block B20, and after all the data of region Z0 is written, please refer to Figure 20The L2P mapping table 2000, which will be described in detail below. The flash memory controller 122 changes the available index corresponding to the area number Z0 from 0 to 1, indicating that all the data corresponding to the area number Z0 has been written. The remaining space in the physical block PBA20 stored in the area number Z0 can be used to store other data. Since the remaining space in the physical block PBA20 can be used to store other data, the data in area Z2 can then be written to the remaining data pages of block B20. If the flash memory controller 122 cannot find any physical block with an available index of 1 when processing the write instruction for area Z2, the flash memory controller 122 should extract a blank block or a spare block to write the data in area Z2.

[0125] In this example, since the available index corresponding to the physical block PBA20 is 1, the flash memory controller 122 can directly use the physical block PBA20 to store the data in area Z2 without extracting another blank block or spare block. Since the number of remaining data pages in block B20 is not sufficient to store all the data in area Z2, the data in area Z2 is divided into a first part Z2_1 and a second part Z2_2. The first part Z2_1 is stored in block B20, and the second part Z2_2 is extracted by the flash memory controller 122 to another blank block, block B30, and is written starting from the first data page of block B30. Since the physical block PBA20 is full and cannot write data after writing the remaining data pages of block B20 with the first part Z2_1 of Z2, the flash memory controller 122 changes the available index corresponding to area Z0 to 0 and keeps the available index corresponding to area Z2_1 as 0. After all the data in the second part Z2_2 of area Z2 is written, the flash memory controller 122 changes the available index corresponding to the area number Z2_2 from 0 to 1. Similarly, the data in area Z1 then starts to be written to the remaining data pages of block B30.

[0126] In step 1806, the flash memory controller 122 creates or updates an L2P mapping table to record the mapping relationship between the logical address and the physical address for subsequent data reading from the area namespace 310_1. Figure 20 It is a schematic diagram of the L2P mapping table 2000 according to an embodiment of the present invention. The L2P mapping table 2000 includes two fields. One field records the block number or the logical address range, and the other field records the physical block address and the physical data page address corresponding to the first logical address of the logical address range. In Figure 20In it, the L2P mapping table 2000 records the first logical address of the logical address range of area Z0 or area Z0, and the corresponding physical block address PBA20 and physical data page address P1, the logical address range of the first part Z2_1 of area Z2 and the physical block address PBA20 and physical data page address Pa corresponding to the first logical address of this range, the logical address range of the second part Z2_2 of area Z2 and the physical block address PBA30 and physical data page address P1 corresponding to the first logical address of this range, and the logical address range of area Z1 or area Z1 and the physical block address PBA30 and physical data page address Pb corresponding to the first logical address of this range. It should be noted that, in this example, a physical block filled with data stores data of multiple areas.

[0127] In addition, it should be noted that during the writing process of the data of area Z0, Z2, and area Z1, the writing process may not start writing the data of area Z1 into the area namespace 310_1 after all the data of area Z0 is written. In other words, it is possible that when the data of area Z0 has not been completely written, the flash memory controller 122 needs to start writing the data of area Z1 into the area namespace 310_1. Therefore, as described above, in another embodiment of the present invention, the L2P mapping table 2000 may additionally include an available indicator field, which is used to indicate whether the data of the area has been completely written in the shared block.

[0128] In the above embodiment, since the L2P mapping table 2000 stores the address relationship within the block of data corresponding to different areas, it can be considered that data with logical addresses belonging to different areas can be stored in the same physical block, so the space of the physical block can be effectively utilized.

[0129] It should be noted that the L2P mapping table 2000 of this embodiment only records a small number of logical addresses (a small number of physical data page addresses). Therefore, the L2P mapping table 2000 itself only has a very small amount of data. Thus, the L2P mapping table 2000 can be resident in the cache memory 216 or the DRAM 240 without imposing too much burden on the storage space of the cache memory 216 or the DRAM 240.

[0130] Figure 21 It is a flowchart for reading data from the area namespace 310_1 according to an embodiment of the present invention, where in this embodiment it is assumed that the area namespace 310_1 has stored Figure 19Data of the indicated regions Z1, Z1, and Z2. In step 2100, the process starts, and the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., the boot program). In step 2102, the main device 110 sends a read instruction to request reading data with a specific logical address. In step 2104, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to and calculates a physical data page address corresponding to the specific logical address according to the region number or logical address recorded in the L2P mapping table 2000. Taking Figure 20 the L2P mapping table 2000 as an example, since the L2P mapping table 2000 records the block numbers or logical address ranges of each region, and the number of logical addresses that can be stored in each block is known, the microprocessor 212 can know which region and which block the specific logical address belongs to from the above information. Then, assuming that the specific logical address belongs to region Z0, the microprocessor 212 determines the physical data page address corresponding to the specific logical address according to the difference between the specific logical address and the starting logical address of region Z0, and according to how much logical address data can be stored in each data page of the block.

[0131] In step 2106, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the physical block address and physical data page address determined in step 2104, and returns the read data to the main device 110.

[0132] As described above, through the content of the above embodiments, the flash memory controller 122 can still effectively complete data writing and reading in the region namespace 310_1 when only creating a very small-sized L2P mapping table 2000.

[0133] Referring to the above Figures 5 to 21 illustrated embodiments, Figure 5 ~7 describe that the data amount corresponding to each region is greater than the size of each block in the flash memory module 124, and each block in the flash memory module 124 only stores data corresponding to a single region, that is, data of different regions will not be written into the same physical block. Figures 8 to 12 describe that the data amount corresponding to each region is greater than the size of each block in the flash memory module 124, and some blocks in the flash memory module 124 will store data corresponding to multiple regions, that is, data of different regions can be written into the same physical block. Figures 13 to 17It is described that the amount of data corresponding to each region is smaller than the size of each block in the flash memory module 124, and each block in the flash memory module 124 stores only the data corresponding to a single region, that is, the data of different regions is not written into the same physical block. Figures 18 to 21 It is described that the amount of data corresponding to each region is smaller than the size of each block in the flash memory module 124, and the blocks in the flash memory module 124 store the data corresponding to multiple regions, that is, the data of different regions can be written into the same physical block.

[0134] In one embodiment, the above four access modes can be selectively applied to the region namespace of the flash memory module 124, and if the flash memory module 124 has multiple region namespaces, these region namespaces can also adopt different access modes. Specifically, referring to Figure 3 as shown, the microprocessor 212 in the flash memory controller 122 can select the access mode to be adopted according to the size of each region of the region namespace 310_1. For example, if the amount of data corresponding to each region of the region namespace 310_1 is greater than the size of each block in the flash memory module 124, the microprocessor 212 can adopt Figure 5 the access mode mentioned in ~7 or Figures 8 to 12 the access mode mentioned in to access the region namespace 310_1; if the amount of data corresponding to each region of the region namespace 310_2 is smaller than the size of each block in the flash memory module 124, the microprocessor 212 can adopt Figures 13 to 17 the access mode mentioned in or Figures 18 to 21 the access mode mentioned in to access the region namespace 310_2. Similarly, the microprocessor 212 in the flash memory controller 122 can select the access mode to be adopted according to the size of each region of the region namespace 310_2, and the access mode adopted by the region namespace 310_2 does not necessarily have to be the same as that of the region namespace 310_1. For example, the region namespace 310_1 can adopt Figure 5 the access mode mentioned in ~7, while the region namespace 310_2 can adopt Figures 8 to 12 the access mode mentioned in.

[0135] Note that since the flash memory controller 122 cannot know in advance the region size to be set by the host device 110, in order for the flash memory controller 122 to be able to cooperate with all host devices that meet the specifications, the flash memory controller 122 must be capable of executing Figures 5 to 21All access methods of the illustrated embodiments. For example, after learning the single physical block size (or super block size, the concept of super block will be described in detail below) of the flash memory module 124 and the area size set by the host device 110, the flash memory controller 122 can plan the memory space actually available to the host device according to the physical block size and the area size, and select which one of the above four access modes should be used for access.

[0136] If the area size is smaller than the physical block size, the flash memory controller 122 has to select Figures 13 to 21 a way to perform access. Since Figures 13 to 17 the access modes mentioned above may waste more memory space, and may even cause the flash memory controller 122 to be unable to plan enough memory space for the host to use. For example, according to this access mode, the flash memory controller 122 can only plan 1.2TB of the capacity of the flash memory module with a total capacity of 2TB for the host device 110 to use, while the host device may expect to have at least 1.5TB of capacity available, then the flash memory controller 122 needs to change its access mode. For example, the flash memory controller 122 can change to Figures 18 to 21 a way to perform access. Since according to this access mode, the waste of flash memory space will be greatly reduced, the flash memory controller 122 can plan more capacity for the host device 110 to use. For example, the flash memory controller 122 can plan 1.8TB of the capacity of the flash memory module with a total capacity of 2TB for the host device 110 to use, so as to meet the usage requirements of the host device 110 for the memory storage space. In other words, the capacity that the above host device 110 may expect can be regarded as a standard. When the capacity planned when the area namespace adopts Figures 13 to 17 a certain access method is higher than this standard of the host device 110, the flash memory controller 122 can select Figures 13 to 17 a certain access method; in addition, if the capacity planned when the area namespace adopts Figures 13 to 17 a certain access method is lower than this standard of the host device 110, the flash memory controller 122 can select Figures 18 to 21 a certain access method.

[0137] If the area size is larger than the physical block size, the flash memory controller 122 has to select Figures 5 to 12 a way to perform access. Since Figure 5The access patterns mentioned in [[ID=]]~ may waste more memory space and may even cause the flash memory controller 122 to be unable to allocate enough memory space for the host to use. For example, according to this access pattern, the flash memory controller 122 can only allocate 1.2 TB of the capacity of a flash memory module with a total capacity of 2 TB for the main device 110 to use, while the main device may expect to have at least 1.5 TB of capacity available. Then, the flash memory controller 122 needs to change its access pattern. For example, the flash memory controller 122 can change to Figures 8 to 12 for access. Since this access pattern will greatly reduce the waste of flash memory space, the flash memory controller 122 can allocate more capacity for the main device 110 to use. For example, the flash memory controller 122 can allocate 1.8 TB of the capacity of a flash memory module with a total capacity of 2 TB for the main device 110 to use, thus meeting the memory storage space usage requirements of the main device 110. In other words, the capacity that the above-mentioned main device 110 may expect can be regarded as a standard. When the capacity planned by the regional namespace using the access method of Figure 5 ~ is higher than this standard of the main device 110, the flash memory controller 122 can select Figure 5 ~ for the access method; in addition, if the capacity planned by the regional namespace using the access method of Figure 5 ~ is lower than this standard of the main device 110, the flash memory controller 122 can select Figures 8 to 12 for the access method.

[0138] Figure 25 FIG.

[0139] Step 2500: The process starts.

[0140] Step 2502: Receive a setting instruction from a main device, where the setting instruction sets at least a part of the flash memory module as a regional namespace. The regional namespace logically includes multiple regions. The main device must write and access data in the regional namespace in units of regions. The size of each region is the same, the logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions.

[0141] Step 2504: Use one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the main device into the flash memory module, where the data is all data of a specific region.

[0142] Step 2506: If the first access mode is used, according to the order of the logical addresses of the data, the data is sequentially written into multiple specific blocks of the flash memory module.

[0143] Step 2508: After the data is completely written, write invalid data to the remaining data pages of the last specific block of the multiple specific blocks, or keep the remaining data pages blank without writing any data.

[0144] Step 2510: If the second access mode is used, according to the order of the logical addresses of the data, the data is sequentially written into the multiple specific blocks of the flash memory module.

[0145] Step 2512: After the data is completely written, use a completion indicator to mark the last specific block of the multiple specific blocks as written completed.

[0146] Step 2514: If the third access mode is used, according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module.

[0147] Step 2516: After the data is completely written, write invalid data to the remaining data pages of the specific block, or keep the remaining data pages blank without writing any data.

[0148] Step 2518: If the fourth access mode is used, according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module.

[0149] Step 2520: After the data is completely written, use a completion indicator to mark the specific block as written completed.

[0150] Note that in another embodiment, in order to simplify the design of the controller 122, the controller 122 may also support only a single access mode among the above four access modes, or the controller 122 may also support only two access modes among the above four access modes, or the controller 122 may also support only three access modes among the above four access modes, and the design shall be based on the specific flash memory module and the host device.

[0151] In addition, in an embodiment of the present invention, the storage device 120_1 may be a Secure Digital Memory Card, which supports data transmission in the traditional Secure Digital mode, that is, uses the UHS-I input / output communication interface standard to communicate with the host device 110, and also supports the PCIe mode that supports both the PCIe channel and the NVMe protocol.

[0152] In the implementation of the flash memory module 124, the flash memory controller 122 configures the blocks belonging to different data planes inside the flash memory module 124 into a super block to facilitate the management of data access. Specifically, refer to Figure 22 the schematic diagram of the general storage space 320_1 of the flash memory module 124 shown in Figure 22 As shown, the general storage space 320_1 includes two channels, channel 1 and channel 2, which are respectively connected to a plurality of flash memory chips 2210, 2220, 2230, 2240. Among them, the flash memory chip 2210 includes two data planes 2212, 2214, the flash memory chip 2220 includes two data planes 2222, 2224, the flash memory chip 2230 includes two data planes 2232, 2234, the flash memory chip 2240 includes two data planes 2242, 2244, and each data plane includes a plurality of blocks B0 to BN. During the process of configuring or initializing the general storage space 320_1, the flash memory controller 122 configures the first block B0 of each data plane as a super block 2261, the second block B1 of each data plane as a super block 2262, and so on. As Figure 22 shown, the super block 2261 includes eight physical blocks, and when the flash memory controller 122 accesses the super block 2261, it is similar to a general block. For example, the super block 2261 itself is an erasure unit, that is, although the eight blocks B0 of the super block 2261 can be erased separately, the flash memory controller 122 will definitely erase the eight blocks B0 together; in addition, when writing data to the super block 2261, the data can be written in sequence from the first data page of the data plane 2212, the first data page of the data plane 2214, the first data page of the data plane 2222, the first data page of the data plane 2224, and after the first data page of the data plane 2244 finishes writing data, then write the data in sequence to the second data page of 2212, the second data page of the data plane 2214, and so on. In other words, the flash memory controller 122 will write the first data page of each block B0 in the super block 2261 first, and then write the second data page of each block B0 in the super block 2261. The super block is a set of blocks logically set by the flash memory controller 122 to facilitate the management of the storage space 320_1, rather than a physical set of blocks. In addition, when performing garbage collection, calculating the valid pages of the block, and calculating the writing time length of the block, it can also be calculated in units of the super block. Under the teaching of the present invention, those skilled in the art can cooperate with Figures 5 to 21The illustrated embodiments are understood to be in Figures 5 to 21 an entity block mentioned in the illustrated embodiments may also be a super block, and all related embodiments can be implemented using super blocks, rather than being limited to a single entity block.

[0153] However, in the case where the flash memory controller 122 configures the blocks in the flash memory module 124 as super blocks, if the Figures 5 to 8 embodiment is used for data access, it is very likely that there will be many remaining data pages (blank data pages) in each block, thus wasting the internal space of the flash memory module 124. For example, assuming that the data volume of the area planned by the host device 110 is approximately the size of six entity blocks, the data volume stored in the super block 2261 containing eight blocks will only be the data volume of six entity blocks. That is, approximately two block storage spaces in the super block 2261 are wasted because they need to be kept blank or written with invalid data. Therefore, an embodiment of the present invention proposes a method for configuring the regional namespace 310_1 according to the data volume of the area set by the host device 110 to efficiently use the regional namespace 310_1.

[0154] Figure 23Flowchart of a method for configuring a zoned flash memory module 124 according to an embodiment of the present invention. In step 2300, the process starts, and the host device 110, the flash memory controller 122, and the flash memory module 124 have completed related initialization operations. In step 2302, the host device 110 sets at least a part of the flash memory module 124 as a zoned namespace by sending a set of configuration instructions. In the following description, the zoned namespace 310_1 is used as an example. For example, the host device 110 sets basic configurations such as the size of each zone, the number of zones, and the size of the logical block address in the zoned namespace 310_1 for the storage device 120_1, for example, by using the Zoned Namespaces Command Set. In step 2304, the microprocessor 212 in the flash memory controller 122 determines the number of blocks included in a superblock based on the size of the data volume of the zone set by the host device 110 and the size of each block (physical block) in the flash memory module 124. Specifically, assuming that the size of the data volume of the zone set by the host device 110 is A, and the size of the data volume used by the host stored in each physical block of the flash memory module 124 is B, if the remainder obtained by dividing A by B is not zero, then the quotient obtained by dividing A by B plus one is the number of blocks included in a superblock. If the remainder obtained by dividing A by B by the microprocessor 212 is zero, then the quotient obtained by dividing A by B is the number of blocks included in a superblock. Take Figure 24For example, the flash memory module 124 includes a plurality of flash memory chips 2410, 2420, 2430, 2440. The flash memory chip 2410 includes two data planes 2412, 2414. The flash memory chip 2420 includes two data planes 2422, 2424. The flash memory chip 2430 includes two data planes 2432, 2434. The flash memory chip 2440 includes two data planes 2442, 2444. And each data plane includes a plurality of blocks B0 to BN. If the quotient of A divided by B is '5' and the remainder is '3', the microprocessor 212 can determine that a super block includes six blocks. Therefore, during the process of configuring or initializing the area namespace 310_1, the flash memory controller 122 configures the first block B0 of the data planes 2412, 2414, 2422, 2424, 2432, 2434 as a super block 2461, the second block B1 of the data planes 2412, 2414, 2422, 2424, 2432, 2434 as a super block 2462, and so on. In addition, the blocks B0 to BN of the data plane 2442 and the data plane 2444 may not need to be configured as super blocks, or may form a super block independent of the data planes 2412, 2414, 2422, 2424, 2432, 2434. In another embodiment, during the process of configuring or initializing the area namespace 310_1, the flash memory controller 122 configures the first block B0 of the data planes 2412, 2414, 2422, 2424, 2432, 2434 as a super block 2461, and the second block B1 of the data planes 2422, 2424, 2432, 2434, 2442, 2444 as a super block 2462. As long as the blocks in the same super block can be accessed in parallel, the access speed of the super block can be improved. Therefore, the super block can be set arbitrarily under the condition of conforming to this concept.

[0155] In another embodiment, assume that the data volume size of the area set by the host device 110 is C, and the data volume size used to store the data of the host in each physical block of the flash memory module 124 is D. If the quotient of C divided by D is '3' and the remainder is '2', the microprocessor 212 can determine that a super block includes 4 blocks, that is, the quotient plus one. After receiving the command from the host device to set the area namespace 310_1, the flash memory controller 122 configures the first block B0 of the data planes 2412, 2414, 2422, 2424 as a super block 2461, and the first block B0 of 2432, 2434, 2442, 2444 as a super block 2462, and so on.

[0156] Note that when the storage devices 120_1, 120_2,..., 120_N, etc. perform the initialization settings before leaving the factory, they can perform preliminary super-block settings on the flash memory module. Taking the storage device 120_1 as an example, at this time, the super-block settings can configure the first block B0 of the simultaneously accessible data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444 as a super-block 2461, and configure the second block B1 of the simultaneously accessible data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444 as a super-block 2462 to obtain the maximum access bandwidth. After the storage device 120_1 is connected to the host device 110 and receives the command of the host device 110 for the regional namespace (such as setting the regional namespace 310_1), then for the size of the regional namespace, a specific storage area is delimited within the flash memory module 124 as the dedicated space of the regional namespace 310_1, and based on the setting of each regional size of the regional namespace 310_1 by the host device 110, the size and combination method of the super-blocks of the specific storage space are re-set. For example, configure the first block B0 of the data planes 2412, 2414, 2422, 2424 as a super-block 2461, and configure the first block B0 of 2432, 2434, 2442, 2444 as a super-block 2462, and so on. At this time, there will be two different sizes of super-blocks in the storage device 120_1. The super-block settings of the specific storage area dedicated to the regional namespace 310_1 will be different from the super-block settings of the specific storage area not dedicated to the regional namespace 310_1. Moreover, the super-block settings of the specific storage area dedicated to the regional namespace 310_1 are also different from the initialization settings of the storage device 120_1 before leaving the factory.

[0157] As described above, by determining the number of blocks included in the super-block according to the data volume of the region set by the host device 110, the super-block can achieve the best space utilization.

[0158] It should be noted that in Figure 22 , 24 the number of flash memory chips and the number of data planes included in each flash memory chip described in the embodiments of Figure 22 , 24In an embodiment, the flash memory chips 2410, 2420, 2430, 2440 included in the regional namespace 310_1 and the flash memory chips 2210, 2220, 2230, 2240 included in the general storage space 320_1 can be integrated. Specifically, the flash memory module 124 can include only four flash memory chips 2210, 2220, 2230, 2240, and the flash memory chips 2210, 2220, 2230, 2240 as a whole include Figure 3 the regional namespace 310_1 and the general storage space 320_1 shown. Therefore, the microprocessor 212 can configure the four flash memory chips 2210, 2220, 2230, 2240 to simultaneously include multiple super blocks with different numbers of blocks. For example, it includes Figure 22 the super block with eight blocks shown and Figure 24 the super block with six blocks shown.

[0159] On the other hand, Figure 3 the general storage space 320_1 shown can also be configured as a regional namespace by the host device 110 at a subsequent time point, and at this time, the sizes of the super blocks previously configured in the general storage space 320_1 will need to be changed. Specifically, at the first time point, the microprocessor will set the general storage space 320_1 to plan the size of each super block. Taking Figure 22 as an example, since a super block can contain at most eight blocks, the microprocessor 212 sets each super block to contain eight blocks. Then, if the host device 110 reconfigures the general storage space 320_1 as a regional namespace, the microprocessor 212 needs to reconfigure the number of blocks included in each super block, such as Figure 22 the six blocks shown.

[0160] Note that, in order to improve the access speed, the flash memory controller 122 can usually temporarily store the data that the host device 110 wants to store in the storage device 120_1 in the single-level storage memory cells of the flash memory module 124, or store it temporarily in the flash memory module 124 in the SLC storage mode, and finally still store the data in the multi-level storage memory cells, or store it in the flash memory module 124 in the MLC storage mode. In the embodiments of the present invention, the process of storing the data in the flash memory module 124 in the SLC storage mode is omitted, and the state of finally storing the data in the flash memory module 124 in the MLC storage mode is directly described. Those skilled in the art can combine the technology of the present invention with the technology of temporarily storing the data in the flash memory module 124 in the SLC storage mode under the teaching of the present invention.

[0161] Briefly summarize the present invention. In the control method of the present invention applied to a flash memory controller, by planning the mode of writing regional data into the flash memory, the size of the L2P mapping table can be effectively reduced to reduce the burden on the cache memory or DRAM. In addition, by determining the number of blocks included in the super block according to the data volume of the region and the size of the physical block, the space of the flash memory module can be utilized more effectively.

[0162] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A control method applied to a flash memory controller, where the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and each block includes a plurality of data pages, and the control method includes: Receiving a setting instruction from a host device, where the setting instruction sets at least a part of the flash memory module as a zoned namespace, and the zoned namespace logically includes a plurality of zones. The host device must perform data write access to the zoned namespace in units of zones. The size of each zone is the same, the logical addresses corresponding to each zone must be continuous, and there are no overlapping logical addresses between zones; Using one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device into the flash memory module, where the data is all the data of a specific zone; If the first access mode is used: According to the order of the logical addresses of the data, sequentially write the data into a plurality of specific blocks of the flash memory module; and After the data is written, write invalid data to the remaining data pages of the last specific block among the plurality of specific blocks, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasing; If the second access mode is used: According to the order of the logical addresses of the data, sequentially write the data into the multiple specific blocks of the flash memory module; And Only after the data is written, the remaining data pages of the last specific block can be used for writing data of another zone; If the third access mode is used: According to the order of the logical addresses of the data, sequentially write the data into a single specific block of the flash memory module; and After the data is written, write invalid data to the remaining data pages of the specific block, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasing; If the fourth access mode is used: According to the order of the logical addresses of the data, sequentially write the data into a single specific block of the flash memory module; And Only after the data is written, the remaining data pages of the last specific block can be used for writing data of another zone.

2. The control method according to claim 1, characterized in that, The step of using one of the first access mode, the second access mode, the third access mode, and the fourth access mode includes: If the size of each zone is greater than the size of each block, use the first access mode or the second access mode; and If the size of each zone is less than the size of each block, use the third access mode or the fourth access mode.

3. The control method according to claim 2, characterized in that, The step of using one of the first access mode, the second access mode, the third access mode, and the fourth access mode includes: If the size of each zone is greater than the size of each block, and the capacity planned when the first access mode is adopted for the zoned namespace is higher than a first standard of the host device, use the first access mode; If the size of each region is greater than the size of each block, and the capacity planned for the region namespace when adopting the first access mode is lower than the first standard of the host device, use the second access mode; If the size of each region is smaller than the size of each block, and the capacity planned for the region namespace when adopting the third access mode is higher than a second standard of the host device, use the third access mode; and If the size of each region is smaller than the size of each block, and the capacity planned for the region namespace when adopting the third access mode is lower than the second standard of the host device, use the fourth access mode.

4. The control method according to claim 1, characterized in that, It further includes: If using the first access mode: If the host device transmits the data and another data whose transfer logical address is consecutive to the last logical address of the data, write the another data to other blocks different from the plurality of specific blocks, and do not write the another data to the remaining data pages of the last specific block among the plurality of specific blocks.

5. The control method according to claim 4, wherein From the perspective of storing data from the host device, when using the first access mode, a single block only stores data of a single region.

6. The control method according to claim 1, wherein It further includes: If using the second access mode: Receive a first data from the host device, where the first data is all data of a first region; According to the order of the logical addresses of the first data, sequentially write the first data to at least one first specific block and a shared block of the flash memory module, where the content corresponding to the first logical address in the first data is stored in the at least one first specific block, and the content corresponding to the last logical address in the first data is stored in the shared block; Receive a second data from the host device, where the second data is all data of a second region; According to the order of the logical addresses of the second data, sequentially write the second data to at least one second specific block and the shared block of the flash memory module.

7. The control method according to claim 6, characterized in that, The content corresponding to the first logical address in the second data is stored in the at least one second specific block, and the content corresponding to the last logical address in the second data is stored in the shared block.

8. The control method according to claim 6, characterized in that From the perspective of storing data from the host device, where the at least one first specific block only stores data corresponding to the first region, and the at least one second specific block only stores data corresponding to the second region.

9. The control method according to claim 6, characterized in that, The first logical address of the second data is consecutive to the last logical address of the first data, and the host device continuously transmits the first data and the second data to the flash memory controller to request writing at least a part of the first data and at least a part of the second data to the shared block.

10. The control method according to claim 1, characterized in that, From the perspective of storing data from the host device, when using the third access mode, a single block only stores data of a single region.

11. The control method according to claim 1, characterized in that, It further includes: If using the fourth access mode: Receive a first data from the host device, where the first data is all data of a first region; Write the first data into a common block in sequence according to the order of the logical addresses of the first data; and Receive a second data from the host device, where the second data is all the data of a second region; Write the second data into the remaining data pages in the common block in sequence according to the order of the logical addresses of the second data.

12. The control method according to claim 11, wherein When using the fourth access mode, any block filled with data must store data of multiple regions.

13. A flash memory controller, where the flash memory controller is used to access a flash memory module, the flash memory module includes multiple blocks, each block includes multiple data pages, and the flash memory controller includes: A read-only memory for storing a program code; A microprocessor for executing the program code to control access to the flash memory module; and A buffer memory; The microprocessor receives a setting instruction from a host device, where the setting instruction sets at least a part of the flash memory module as a region namespace, the region namespace logically includes multiple regions, and the host device must perform data write access to the region namespace in units of regions. The size of each region is the same, the logical addresses corresponding to each region must be continuous, and there are no overlapping logical addresses between regions; The microprocessor uses one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device into the flash memory module, where the data is all the data of a specific region; When the microprocessor uses the first access mode: Write the data into multiple specific blocks of the flash memory module in sequence according to the order of the logical addresses of the data; and after the data is written, write invalid data into the remaining data pages of the last specific block of the multiple specific blocks, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasing; When the microprocessor uses the second access mode: Write the data into the multiple specific blocks of the flash memory module in sequence according to the order of the logical addresses of the data; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region; When the microprocessor uses the third access mode: Write the data into a single specific block of the flash memory module in sequence according to the order of the logical addresses of the data; and after the data is written, write invalid data into the remaining data pages of the specific block, or keep the remaining data pages blank and do not write data from the host device according to the write instruction of the host device before erasing; When the microprocessor uses the fourth access mode: Write the data into a single specific block of the flash memory module in sequence according to the order of the logical addresses of the data; and only after the data is written, the remaining data pages of the last specific block can be used for writing data of another region.

14. The flash memory controller as claimed in claim 13, wherein If the size of each region is greater than the size of each block, the microprocessor utilizes the first access mode or the second access mode; if the size of each region is less than the size of each block, the microprocessor utilizes the third access mode or the fourth access mode.

15. The flash memory controller as claimed in claim 13, wherein When the first access mode is selected: If the host device transmits the data and another data whose transfer logical address is consecutive to the last logical address of the data, the microprocessor writes the another data to a block other than the plurality of specific blocks, and does not write the another data to the remaining data pages of the last specific block of the plurality of specific blocks.

16. The flash memory controller according to claim 15, wherein When the first access mode is selected, only the data of a single region is stored in a single block.

17. The flash memory controller as claimed in claim 13, wherein, When the microprocessor utilizes the second access mode, the microprocessor performs the following operations: receiving a first data from the host device, where the first data is all the data of a first region; sequentially writing the first data to at least one first specific block and a common block of the flash memory module according to the order of the logical addresses of the first data, where the content corresponding to the first logical address in the first data is stored in the at least one first specific block, and the content corresponding to the last logical address in the first data is stored in the common block; and receiving a second data from the host device, where the second data is all the data of a second region; sequentially writing the second data to at least one second specific block and the common block of the flash memory module according to the order of the logical addresses of the second data, where the content corresponding to the first logical address in the second data is stored in the at least one second specific block, and the content corresponding to the last logical address in the second data is stored in the common block.

18. A storage device, comprising: a flash memory module, where the flash memory module includes a plurality of blocks, and each block includes a plurality of data pages; and a flash memory controller for accessing the flash memory module; where the flash memory controller receives a setting instruction from a host device, where the setting instruction sets at least a part of the flash memory module as a region namespace, the region namespace logically includes a plurality of regions, the host device must perform data write access to the region namespace in units of regions, the size of each region is the same, the logical addresses corresponding to within each region must be consecutive, and there are no overlapping logical addresses between regions; where the flash memory controller utilizes one of a first access mode, a second access mode, a third access mode, and a fourth access mode to write data from the host device to the flash memory module, where the data is all the data of a specific region; When the flash memory controller utilizes the first access mode: according to the order of the logical addresses of the data, the data is sequentially written into a plurality of specific blocks of the flash memory module; and after the data is completely written, the remaining data pages of the last specific block among the plurality of specific blocks are written with invalid data, or the remaining data pages are maintained blank and no data from the host device is written according to the write instruction of the host device before erasure; When the flash memory controller utilizes the second access mode: according to the order of the logical addresses of the data, the data is sequentially written into the plurality of specific blocks of the flash memory module; and only after the data is completely written, the remaining data pages of the last specific block can be used for writing data from another area; When the flash memory controller utilizes the third access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module; and after the data is completely written, the remaining data pages of the specific block are written with invalid data, or the remaining data pages are maintained blank and no data from the host device is written according to the write instruction of the host device before erasure; When the flash memory controller utilizes the fourth access mode: according to the order of the logical addresses of the data, the data is sequentially written into a single specific block of the flash memory module; and only after the data is completely written, the remaining data pages of the last specific block can be used for writing data from another area.

19. The storage device according to claim 18, wherein If the size of each area is greater than the size of each block, the flash memory controller selects the first access mode or the second access mode; if the size of each area is less than the size of each block, the flash memory controller selects the third access mode or the fourth access mode.

20. The storage device according to claim 18, wherein When the flash memory controller utilizes the second access mode, the flash memory controller performs the following operations: receiving a first data from the host device, where the first data is all the data of a first area; according to the order of the logical addresses of the first data, sequentially writing the first data into at least one first specific block and a common block of the flash memory module, where the content corresponding to the first logical address in the first data is stored in the at least one first specific block, and the content corresponding to the last logical address in the first data is stored in the common block; and receiving a second data from the host device, where the second data is all the data of a second area; according to the order of the logical addresses of the second data, sequentially writing the second data into at least one second specific block and the common block of the flash memory module, where the content corresponding to the first logical address in the second data is stored in the at least one second specific block, and the content corresponding to the last logical address in the second data is stored in the common block.

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