Memristor array integration structure based on 2d1r cell structure

Abstract

The application discloses a 2D1R unit structure-based memristor array integrated structure, which comprises m*n 2D1R unit structures and forms an m-row and n-column memristor array. ij Each 2D1R unit structure is recorded as U The 2D1R unit structure comprises a memristor R, a diode D1, a diode D2, the positive electrode of the diode D1 is connected with the negative electrode of the diode D2, and the negative electrode of the memristor R is connected with the connection node of the two diodes; the positive electrode of the memristor R is connected with a voltage signal input bus, the negative electrode of the diode D1 is connected with a positive current signal output bus, and the positive electrode of the diode D2 is connected with a negative current signal output bus. The technical scheme of the application can realize high-density integration and low-power consumption operation and effectively solve the current crosstalk problem between unit structures in the array.

Description

Technical Field

[0001] This invention relates to semiconductor devices and memories, and more specifically to memristor array integrated structures based on 2D1R cell structures. Background Technology

[0002] With the rise of new electronic application industries such as artificial intelligence and the Internet of Things, traditional von Neumann architecture processors, limited by the memory wall, are struggling to meet the ever-increasing computing power demands. In recent years, the development of hardware devices based on memristor arrays and novel in-memory computing architectures has attracted significant attention from academia and industry. However, the integration of memristor arrays faces the challenge of leakage current. Existing solutions include 1S1R, 1D1R, and 1T1R. The 1S1R solution integrates a selector and a memristor in the array unit. This solution suffers from strong nonlinearity in the output signal, which affects the accuracy of information processing. The 1D1R solution integrates a diode and a memristor in the array unit, but this solution is only suitable for unipolar memristors, limiting its application range. The 1T1R solution integrates a field-effect transistor and a memristor in the array unit. Due to the complex fabrication process of field-effect transistors and their large chip area requirements, increasing the array integration density in this area is challenging. Furthermore, field-effect transistors are active devices, increasing the power consumption of array operations. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to provide a memristor array integrated structure based on the 2D1R cell structure, which has the advantages of solving the problems of leakage current, low density and high power consumption faced by memristor array integration.

[0004] Technical solution: This invention comprises m*n 2D1R cell structures, forming an m-row, n-column memristor array, where m and n are both positive integers greater than 1. Each 2D1R cell structure is denoted as U. ij Where 1≤i≤m, 1≤j≤n, and i and j are positive integers; the 2D1R unit structure includes a memristor R, a diode D1, and a diode D2. The positive terminal of diode D1 and the negative terminal of diode D2 are connected together, and the negative terminal of memristor R is connected to the connection node of the two diodes; the positive terminal of memristor R is connected to the voltage signal input bus, the negative terminal of diode D1 is connected to the positive current signal output bus, and the positive terminal of diode D2 is connected to the negative current signal output bus.

[0005] For the i-th row and n-th 2D1R cell structure, they share a horizontally arranged voltage signal input bus, with the input voltage signal V. in-i To the positive terminal of the memristor R in each 2D1R cell structure.

[0006] For the jth column m 2D1R unit structure, a longitudinally arranged positive current signal output bus is shared, receiving the negative output current signal of the diode D1 in each 2D1R unit structure, and the total signal output by the positive current signal output bus is I out-p-j .

[0007] For the jth column m 2D1R unit structure, a longitudinally arranged negative current signal output bus is shared, receiving the positive output current signal of the diode D2 in each 2D1R unit, and the total signal output by the negative current signal output bus is I out-n-j .

[0008] When the write and erase operations are performed on the diode in the 2D1R unit U ij in the i-th row and j-th column of the array, the voltage signal V in-i is input to the i-th row voltage signal input bus, the j-th column positive current signal output bus and negative current signal output bus are grounded, and the other voltage signal input buses except the i-th row are open-circuited, and the positive current signal output bus and negative current signal output bus except the j-th column are open-circuited.

[0009] The diodes D1 and D2 are passive devices, achieving low power consumption.

[0010] Advantages: Compared with the prior art, the technical scheme of the present application has the following advantages: (1) by connecting a memristor and two unidirectional diodes to form a unit circuit structure, further integrating the array based on the unit structure, the leakage current problem in the array electrical operation process can be effectively suppressed, and precise erase and write operations on the memristor resistance value can be realized; (2) compared with existing memristor array integration schemes, this scheme simultaneously ensures the suitability of unipolar and bipolar operation of the memristor (compared with the 1D1R scheme), better I-V linear characteristic (compared with the 1S1R scheme), and simple unit structure processing technology (compared with the 1T1R scheme); (3) the diodes are passive devices, having the characteristics of low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a schematic diagram of the overall structure of the present application;

[0012] Figure 2 is Figure 1 a circuit diagram of a single 2D1R unit circuit in the present application;

[0013] Figure 3 is Figure 1 a current flow diagram of a 2*2 array of 2D1R unit circuits in the present application during a write operation of the memristor;

[0014] Figure 4 is Figure 1Current flow diagram of 2*2 array of 2D1R unit circuit when the memristor is erased. DETAILED DESCRIPTION

[0015] The technical solutions of the present application are further described below in combination with the specific embodiments and the accompanying drawings of the specification.

[0016] As shown in Figure 1 and Figure 2 , the present application comprises m*n 2D1R unit structures, m*n (m and n are both positive integers greater than 1) 2D1R unit structures form an array circuit of m rows and n columns, and each 2D1R unit structure is denoted as U ij (1≤i≤m, 1≤j≤n, i, j are positive integers); the 2D1R unit structure comprises a memristor R, a diode D1 with unidirectional conduction characteristics, and a diode D2 with unidirectional conduction characteristics, the anode of the diode D1 is connected to the cathode of the diode D2, and the cathode of the memristor R is connected to the connection node of the two diodes; the anode of the memristor R is connected to a voltage signal input bus, the cathode of the diode D1 is connected to a positive current signal output bus, and the anode of the diode D2 is connected to a negative current signal output bus. The two diodes cooperate to drive the memristor to complete the write and erase operations, and at the same time, the leakage current problem in the array is suppressed.

[0017] For the i-th row of n 2D1R unit structures, a voltage signal input bus arranged horizontally is shared, and a voltage signal V in-i is input to the anode of the memristor R in each 2D1R unit structure.

[0018] For the j-th column of m 2D1R unit structures, a positive current signal output bus arranged vertically is shared, and a current signal output by the cathode of the diode D1 in each 2D1R unit structure is received, and the total signal output by the positive current signal output bus is I out-p-j .

[0019] For the j-th column of m 2D1R unit structures, a negative current signal output bus arranged vertically is shared, and a current signal output by the anode of the diode D2 in each 2D1R unit structure is received, and the total signal output by the negative current signal output bus is I out-n-j .

[0020] When the memristor in the i-th row and j-th column 2D1R unit U ij is subjected to write and erase operations, a voltage signal V in-i is input to the voltage signal input bus in the i-th row, the positive current signal output bus and the negative current signal output bus in the j-th column are grounded, the voltage signal input buses in other rows except the i-th row are open, and the positive current signal output bus and the negative current signal output bus in other columns except the j-th column are open.

[0021] When performing signal processing based on an array, voltage signals (V) are sequentially input into the m-row voltage signal input bus. in-1 V in-2 V in-3 , ..., V in-m ), and sequentially read the current signal (I) from the n-column positive current signal output bus. out-p-1 I out-p-2 I out-p-3 , ..., I out-p-n ), and sequentially read the current signal (I) from the n-column negative current signal output bus. out-n-1 I out-n-2 I out-n-3 , ..., I out-n-n ).

[0022] like Figure 3 As shown in the figure, in this embodiment, a 2*2 memristor array based on a 2D1R cell structure is used as an example to illustrate the leakage current suppression during a write operation. When a write operation is performed on the memristor in cell 1-1, the write current is shown by the solid black line in the figure. There are two cases of bypass leakage current, as shown by the dashed line in the figure. Due to the unidirectional current conduction characteristic of the diode, both bypass leakage current paths are turned off and cannot conduct current.

[0023] like Figure 4 As shown in the figure, in this embodiment, a 2*2 memristor array based on a 2D1R cell structure is used as an example to illustrate the leakage current suppression during the erase operation. When the memristor in cell 1-1 is erased, the erase current is shown by the solid black line in the figure. There are two cases of bypass leakage current, as shown by the dashed line in the figure. Due to the unidirectional current conduction characteristic of the diode, both bypass leakage current paths are turned off and cannot conduct current.

[0024] Therefore, memristor arrays based on the 2D1R cell structure can effectively suppress bypass leakage current effects when performing memristor write and erase operations.

[0025] By fully utilizing the unidirectional conduction characteristics of diodes, the technical solution of this invention effectively solves the leakage current problem during the erase and write operations of memristors in the unit structure of memristor integrated arrays, enabling precise control of memristor resistance values. Compared with existing memristor integration solutions, the solution proposed in this invention has a simple structure, wide applicability, meets the requirements for high-density, low-cost integration of memristors, and also meets the needs of future low-power applications.

Claims

1. A memristor array integrated structure based on 2D1R unit structure, characterized in that: The 2D1R unit structure comprises a plurality of 1R units, and each 1R unit comprises a plurality of 1R cells. ij wherein 1≤i≤m, 1≤j≤n, i, j are positive integers. The 2D1R unit structure comprises a memristor R, a diode D1, a diode D2, the positive electrode of the diode D1 being connected with the negative electrode of the diode D2, and the negative electrode of the memristor R being connected with the connection node of the two diodes; the positive electrode of the memristor R is connected with a voltage signal input bus, the negative electrode of the diode D1 is connected with a positive current signal output bus, and the positive electrode of the diode D2 is connected with a negative current signal output bus.

2. The 2D1R cell structure based memristor array integrated structure of claim 1, wherein: For the nth 2D1R cell structure of the i-th row, a voltage signal input bus is shared, which inputs a voltage signal V in-i to the positive electrode of the memristor R in each 2D1R cell structure.

3. The 2D1 R unit structure based memristor array integrated structure of claim 1, wherein: For the m 2D1R unit structures in the jth column, a longitudinally arranged positive current signal output bus is shared, receiving the current signal output by the negative electrode of the diode D1 in each 2D1R unit structure, and the total signal output by the positive current signal output bus is I out-p-j .

4. The 2D1 R unit structure based memristor array integrated structure of claim 1, wherein: For the m 2D1R unit structures in the jth column, a longitudinally arranged negative current signal output bus is shared, receiving the positive electrode output current signal of the diode D2 in each 2D1R unit, and the total signal output by the negative current signal output bus is I out-n-j .

5. The 2D1 R unit structure based memristor array integrated structure according to any one of claims 1 to 4, characterized in that: When the 2D1R cell Uij in the i-th row and j-th column of the array is subjected to a write operation ij When the 2D1R cell Uij in the i-th row and j-th column of the array is subjected to an erase operation in-i , the positive and negative current signal output buses of the j-th column are both grounded, and the voltage signal input buses other than the i-th row are all open-circuited, and the positive and negative current signal output buses other than the j-th column are both open-circuited.

6. The 2D1 R unit structure based memristor array integrated structure according to any one of claims 1 to 4, characterized in that: The diode D1 and the diode D2 are passive devices.

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