Low leakage sensing circuit, memory circuit including low leakage sensing circuit, and method

Abstract

The present invention relates to low leakage sensing circuits, memory circuits including low leakage sensing circuits, and methods. A sensing circuit for a memory circuit includes sensing amplifiers that detect a difference in voltage levels on complementary bit lines during a read operation. Unlike sensing amplifiers with built-in tail devices that cause significant leakage, the sensing circuit includes a common tail device for all of the sensing amplifiers. To ensure that the tail device has sufficient drive strength for each sensing amplifier to perform voltage difference detection, the sensing circuit also includes a sensing signal generation and boost circuit (SSG&B circuit) that generates a sensing mode control signal (SEN) that controls the on / off state of the tail device and further boosts the SEN to increase drive current when appropriate. The use of a common tail device and the SSG&B circuit reduces leakage from the sensing circuit during a precharge mode of operation without sacrificing performance during a read mode of operation. Related method embodiments are also disclosed herein.

Description

Technical Field

[0001] This invention relates to sensing circuits, and more particularly, to various embodiments of low-leakage sensing circuits and memory circuits incorporating low-leakage sensing circuits. Background Technology

[0002] Memory circuits, such as static random access memory (SRAM) circuits, typically use double-ended sensing for read operations. For example, a memory circuit may include an array of memory cells arranged in columns and rows, and sensing circuitry. Each memory cell in a column may be connected to a pair of complementary bit lines (referred herein to as a bitline true (BLT) and a bitline complement (BLC)). The sensing circuitry may include discrete sensing amplifiers for each column, wherein each sensing amplifier is connected to and receives input from the BLT and BLC during a read operation. Specifically, prior to a read operation, the BLT and BLC of a column of memory cells are pre-charged. When a selected memory cell in the column is accessed during a read operation, the voltage level on the BLT or BLC drops, and the sensing amplifier detects the difference in voltage levels on the BLT and BLC (i.e., senses the voltage difference), thereby indicating the data value stored in the memory cell. While state-of-the-art sensing amplifiers currently available provide a solution for sensing voltage differences between bit lines, they are prone to leakage. As a result, when the sensing circuitry of the memory circuitry includes a relatively large number of sensing amplifiers, the leakage contribution of the sensing circuitry to the total memory circuitry leakage will be significant (e.g., up to 30% or more). Summary of the Invention

[0003] This document discloses an embodiment of a structure that includes low-leakage sensing circuitry for memory circuitry (e.g., static random access memory (SRAM) circuitry).

[0004] In some embodiments, the sensing circuit may include multiple sensing amplifiers, none of which have a conventional built-in footer. The sensing circuit may also include a common footer and a sense signal generation and boost (SSG&B) circuit. Specifically, the common footer may include: a source region, for example connected to a ground rail or a negative voltage supply rail; a drain region, respectively connected to each sensing amplifier and specifically to a pull-down node in the sensing amplifier; and a gate. The SSG&B circuit also has an output node connected to the gate of the footer. Furthermore, the SSG&B circuit can generate a sensing mode control signal at the output node, which can be applied to the gate of the common footer to control its on and off states. Once the common footer is switched to the on state, the sensing mode control signal can be boosted to increase the drive current. By combining the common tail device with the SSG&B circuitry (instead of the leakage-built-in tail device in the sense amplifier), leakage from the sense circuitry is significantly reduced during precharge operation mode without sacrificing performance during readout operation mode.

[0005] In some embodiments, the sensing circuit can be configured as described above, but may also include a common header device to further reduce leakage. That is, the sensing circuit may include multiple sensing amplifiers. The sensing circuit may also include a common tail device, a common header device, and a sensing signal generation and boost (SSG&B) circuit. Specifically, the common tail device may include: a first source region, for example connected to a ground rail or a negative voltage supply rail; a first drain region, each connected to a sensing amplifier and particularly to a pull-down node in the sensing amplifier; and a first gate. The common header device may include: a second source region connected to a positive voltage supply rail; a second drain region connected to each sensing amplifier, such that the sensing amplifiers are connected in parallel between the common tail device and the common header device; and a second gate. The SSG&B circuit may also have an output node connected to the first gate of the tail device. Furthermore, the SSG&B circuit can generate a sensing mode control signal at the output node. This signal can be applied to the first gate of the common tail device to control its on / off state. Once the common tail device is switched to the on state, the sensing mode control signal can be boosted to increase the drive current. As described above, by combining the common tail device with the SSG&B circuit (instead of the leakage-integrated tail device in the sensing amplifier), leakage from the sensing circuit is significantly reduced during the pre-charge operation mode without sacrificing performance during the readout operation mode. Additionally, by using the common tail device, the positive voltage supplied to the sensing amplifier can be selectively turned off (e.g., in response to the sleep mode control signal during sleep mode) to further reduce leakage from the sensing circuit.

[0006] This document also discloses method embodiments for operating the above-described structure. The method may include providing a structure (e.g., the low-leakage sensing circuit described above or a memory circuit including the low-leakage sensing circuit described above). The sensing circuit may include: a sensing amplifier; a common tail device including: a source region; a drain region connected to each sensing amplifier; and a gate; and a sensing signal generation and boost (SSG&B) circuit having an output node connected to the gate of the common tail device. The method may further include generating a sensing mode control signal via the SSG&B circuit. The method may further include applying the sensing mode control signal to the gate of the common tail device via the SSG&B circuit to control the on and off states of the common tail device. The method may further include boosting the sensing mode control signal via the SSG&B circuit to increase the drive current when the common tail device is on. Optionally, the provided sensing circuit may further include a header device. The header device may include: a second source region connected to a positive voltage supply rail; a second drain region connected to each sensing amplifier such that the sensing amplifiers are connected in parallel between the tail device and the header device; and a second gate. In this configuration, the method may further include applying a sleep mode control signal to the second gate to control the on and off states of the header device. As described above, by combining the common header device with the SSG&B circuitry (instead of a leakage-integrated header device in the sense amplifier), leakage from the sense circuitry is significantly reduced during the pre-charge operation mode without sacrificing performance during the readout operation mode. Additionally, by using the common header device, the positive voltage supplied to the sense amplifier can be selectively turned off (e.g., in response to a sleep mode control signal during sleep mode) to further reduce leakage from the sense circuitry. Attached Figure Description

[0007] The present invention will be better understood from the following detailed description of the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0008] Figure 1 A schematic diagram of a memory circuit is shown, for example, a static random access memory (SRAM) circuit.

[0009] Figure 2 It shows that it can be incorporated Figure 1 A schematic diagram of the sensing amplifier in the sensing circuit of the memory circuit;

[0010] Figure 3 A schematic diagram of memory circuitry (e.g., SRAM circuitry) configured for light sleep mode operation to limit leakage contributions from sensing circuitry;

[0011] Figure 4 This is a schematic diagram of a sense amplifier configured with a built-in tail device with stacked NFETs to reduce leakage contributions from the sensing circuit.

[0012] Figure 5A and Figure 5B Schematic diagrams of disclosed embodiments of memory circuits are shown, and a disclosed embodiment of a low-leakage sensing circuit that can be incorporated into the memory circuit embodiments is further shown;

[0013] Figure 6 A schematic diagram of an exemplary six-transistor (6T) SRAM cell that can be incorporated into a memory array of the disclosed memory circuit embodiments is shown;

[0014] Figure 7 A disclosed embodiment of a sensing amplifier is shown, which has no built-in tailing device and can be incorporated into a disclosed sensing circuit embodiment;

[0015] Figure 8A and Figure 8B Schematic diagrams of different common tail devices are shown, which can be incorporated into the sensing circuit control block of the disclosed sensing circuit embodiment;

[0016] Figure 9 A schematic diagram of an embodiment of a sensing signal generation and boost (SSG&B) circuit in a sensing circuit control block that can be incorporated into a disclosed sensing circuit embodiment is shown;

[0017] Figure 10A and Figure 10B Schematic diagrams of different common header devices are shown, which can be incorporated into the sensing circuit control block of the disclosed sensing circuit embodiment;

[0018] Figure 11 It is a diagram, specifically a timing diagram, illustrating the signal states within the sensing circuit control block and each sensing amplifier over a period of time (e.g., during pre-charge operation mode and subsequently during readout operation mode); and

[0019] Figure 12 A flowchart of a disclosed method embodiment for operating the disclosed memory circuitry and sensing circuitry embodiments is shown.

[0020] Symbol Explanation

[0021] 100 Memory Circuit

[0022] 101 Memory Unit

[0023] 110 Memory Array

[0024] 120 Sensing Circuit

[0025] 121, 121A to 121N Sensing Amplifiers

[0026] 122 latch

[0027] 123 Sensing Mode Control Signal (SEN)

[0028] 124 Access Transistor Control Signal (PASSB)

[0029] 125 Precharge Electronic Circuit Control Signal (PRECHB)

[0030] 129 Sensing Circuit Control Block

[0031] 131A to 131N First Line

[0032] 132A to 132N Second Line

[0033] Lines 133a to 133n (WL)

[0034] 140 Positive Voltage Supply Rail

[0035] 145 Grounding Rail

[0036] 170 Header Device

[0037] Line 191 control block

[0038] 192 Control Block

[0039] 195 Controller

[0040] 211 N-type field-effect transistor (NFET)

[0041] 213 Second cross-coupled node

[0042] 221 N-type field-effect transistor (NFET)

[0043] 223 First cross-coupled node

[0044] 231, 232 P-type field-effect transistors (PFETs)

[0045] 240 Precharge Electronic Circuit

[0046] 243, 244, 245 P-type field-effect transistors (PFETs)

[0047] Output nodes 251 and 252

[0048] 280 Tail-end Device

[0049] 281 N-type field-effect transistor (NFET)

[0050] 285 dropdown nodes

[0051] 500 memory circuit

[0052] 501 memory unit

[0053] 520 Low Leakage Sensing Circuit

[0054] 521 Sensing Amplifier

[0055] 522 latch

[0056] 523 Sensing Mode Control Signal (SEN)

[0057] 524 Access Transistor Control Signal (PASSB)

[0058] 525 Precharge Circuit Control Signal (PRECHB)

[0059] 526 Sensing Mode Trigger Signal (TRIG)

[0060] 527 Sensing Signal Generation and Boost (SSG&B) Circuit

[0061] 529 Sensing Circuit Control Block

[0062] 531 True Line (BLT)

[0063] 532 Complementary Bit Line (BLC)

[0064] 533 line (WL)

[0065] 540 VDD

[0066] 541 Common voltage pull-up cable

[0067] 545 voltage rail

[0068] 570 Public Header Device

[0069] 571 P-type field-effect transistor (PFET)

[0070] 573 Sleep Mode Control Signal (LSB)

[0071] 580 Public Poster Device

[0072] 581 N-type field-effect transistor (NFET)

[0073] 585 Common Voltage Pull-Down Cable

[0074] Line 591 control block

[0075] 592 column control blocks

[0076] 595 Controller

[0077] 602 First Pull-Up Transistor

[0078] 603 First pull-down transistor

[0079] 604 First-Gate Transistor

[0080] 605 First Data Node

[0081] 612 Second Pull-Up Transistor

[0082] 613 Second pull-down transistor

[0083] 614 Second gate transistor

[0084] 615 Second Data Node

[0085] 710 First Branch Road

[0086] 711 First pull-down transistor

[0087] 712 First Pull-Up Transistor

[0088] 713 Second cross-coupled node

[0089] 720 Second Branch Road

[0090] 721 Second Pull-Down Transistor

[0091] 722 Second Pull-Up Transistor

[0092] 723 Cross-coupled node

[0093] 731 First Access Transistor

[0094] 732 Second Access Transistor

[0095] 740 Precharge Electronic Circuit

[0096] 742 First Precharge Transistor

[0097] 743 Third Precharge Transistor

[0098] 751 First Output Node

[0099] 752 Second Output Node

[0100] 785 dropdown node

[0101] 901 NAND gate

[0102] 902 P-type field-effect transistor (PFET)

[0103] 903 Coupling Capacitor

[0104] 904 N-type field-effect transistor (NFET)

[0105] 905 Output Node

[0106] 906 Input Node

[0107] 910 Delay Circuit

[0108] 911 First Inverter

[0109] 912 Second Inverter

[0110] 913 Third Inverter

[0111] 914 Fourth Inverter

[0112] 921 First Delayed Signal

[0113] 922 Second Delay Signal

[0114] 923 Third Delay Signal

[0115] 924 Fourth Delayed Signal

[0116] 1202 and 1204 processing steps

[0117] Processing steps for 1206 and 1208

[0118] Processing steps for 1210 and 1212

[0119] BLC Complementary Bit Line

[0120] BLT True Line

[0121] PASSB access transistor control signals

[0122] PRECHB Precharge Circuit Control Signal

[0123] SEN Sensing Mode Control Signal

[0124] TRIG sensing mode trigger signal. Detailed Implementation

[0125] As mentioned above, when the sensing circuitry of a memory circuit typically includes a relatively large number of sensing amplifiers, the leakage contribution of the sensing circuitry to the total memory circuit leakage will be significant (e.g., up to 30% or more).

[0126] More specifically, Figure 1A schematic diagram of an exemplary memory circuit 100 (e.g., a static random access memory (SRAM) circuit) is shown, comprising an array 110 of memory cells 101 (e.g., SRAM cells) arranged in columns AN and rows an. The memory circuit 100 also includes first bit lines 131A-N (also referred to herein as true bit lines (BLTs)) and second bit lines 132A-N (also referred herein as two's complement bit lines (BLCs)) for column AN. Each pair of complementary bit lines (BLTs and BLCs) for a column is electrically connected to all memory cells 101 in that column. The memory circuit 100 also includes word lines (WLs) 133a-n for row an. Each WL in a row is electrically connected to all memory cells 101 in that row. The memory circuit 100 also includes a controller 195 and peripheral circuitry configured to operate in response to control signals from the controller 195. The peripheral circuitry includes a row control block 191 electrically connected to the WL of a row and including, for example, address decoding logic and a word line driver for activating selected word lines according to an operating mode (i.e., switching selected word lines from a low voltage level to a high voltage level). The peripheral circuitry also includes a column control block 192 electrically connected to the BLT and BLC for each column and including, for example, column address decoding logic and a bit line driver for appropriately biasing selected bit lines according to an operating mode. The peripheral circuitry also includes sensing circuitry 120 capable of reading stored data from the memory array 110.

[0127] The leakage of sensing circuit 120 can significantly contribute to the overall leakage of the memory circuitry. For example, sensing circuit 120 includes a sensing circuit control block 129, discrete sensing amplifiers 121A-121N for the column, and discrete latches 122A-122N for the sensing amplifiers 121A-121N. Before a read operation, the BLT and BLC of a column of memory cells are pre-charged to a high voltage level. When a selected memory cell in the column is accessed during a read operation, the voltage level on the BLT or BLC will decrease according to the stored data value. The sensing amplifiers 121 connected to the BLT and BLC (e.g., such as...) Figure 2 As shown, a drop will be detected, and specifically, the resulting difference in voltage levels across the BLT and BLC will be detected (i.e., the sensing amplifier 121 will sense the voltage difference). Then, a latch 122, having input nodes connected to the output nodes 251 and 252 of the sensing amplifier 121 respectively, will capture the voltage difference and output an output signal (Q) indicating the stored data value read from the memory cell. While state-of-the-art sensing amplifiers currently available provide a solution for sensing the voltage difference between the BLT and BLC, they are prone to leakage.

[0128] More specifically, see reference Figure 2 When the sense amplifier 121 is in precharge operation mode, a precharge electronic circuit control signal (PRECHB) 125 will be at logic "0" (i.e., at a low voltage level, e.g., ground), an access transistor control signal (PASSB) 124 will be at logic "1" (i.e., at a high voltage level, e.g., at VDD), a sense mode control signal (SEN) 123 will be at logic "0," and the bit lines (BLT and BLC) can both be at logic "1." As a result, the p-type field-effect transistors (PFETs) 243-245 of the precharge electronic circuit 240 within the sense amplifier 121 will be in the on state. Furthermore, each of the PFETs 231 and 232 used as pass-gates and the N-type FET 281 (NFET) used as a built-in tail device 280 will be in the off state. However, two discrete leakage current paths will still exist within the sense amplifier 121. The first leakage current path is from the positive voltage supply rail 140 (e.g., at VDD), through PFET 243 in the precharge electronic circuit 240 to the first cross-coupled node 223, through NFET 221, through pull-down node 285, and finally through NFET 281 to the ground rail 145. The second leakage current path is from the positive voltage supply rail 140 (e.g., at VDD), through PFET 244 in the precharge electronic circuit 240 to the second cross-coupled node 213, through NFET 211, through pull-down node 285, and finally through NFET 281 to the ground rail 145. As a result, when the sensing circuit 120 includes a relatively large number of sensing amplifiers (e.g., 128 sensing amplifiers for a 128-bit memory array), the leakage contribution of the sensing circuit to the total memory circuit leakage will be as high as 30% or more.

[0129] One technique for limiting leakage contribution of sensing circuit 120 includes configuring the sensing circuit such that when memory circuit 100 is idle for a predetermined effective time and therefore enters a light sleep mode, sensing circuit 120 also enters a light sleep mode. For example, as Figure 3As shown, each sense amplifier 121A-121N can be connected to the positive voltage supply rail 140 via a header device 170 (e.g., a PFET) in the sense circuit control block 129, rather than being directly connected to the positive voltage supply rail 140. The header device 170 can be controlled by a sleep mode control signal (LSB). When the memory circuit 100 is in idle mode for an extended period and enters a light sleep mode, the LSB can switch to logic "1", thereby turning off the header device 170 and simultaneously blocking the leakage current path through each sense amplifier. This solution reduces the leakage contribution of the sense circuit 120. However, the reduction in leakage current is limited because the leakage current path is blocked only when the memory circuit 100 enters a light sleep mode, not when it is in active mode (e.g., in precharge operation mode). Another technique for limiting the leakage contribution of the sense circuit 120 includes configuring each sense amplifier 121 such that the built-in tail device 280 includes multiple stacked NFETs (e.g., see NFETs 281a-282b, as shown). Figure 4 (As shown). This solution increases chip area consumption and may not adequately block leakage current during precharge operation mode.

[0130] In view of the foregoing, embodiments of a low-leakage sensing circuit for memory circuits, such as static random access memory (SRAM) circuits, are disclosed herein. The sensing circuit may include a sensing amplifier for detecting differences in voltage levels on complementary bit lines during a read operation. However, unlike sensing amplifiers with built-in tailing devices that cause significant leakage (as described above), the sensing circuit includes a common tailing device for all sensing amplifiers, thereby reducing leakage. To ensure that the common tailing device has sufficient drive strength to enable voltage difference detection for each sensing amplifier, the sensing circuit may also include a sensing signal generation and boost circuit (SSG&B circuit). This SSG&B circuit can generate a sensing mode control signal that controls the on and off states of the tailing device and can also boost the sensing mode control signal when appropriate to increase the drive current. By combining the common tailing device with the SSG&B circuit (instead of the leaky built-in tailing device in the sensing amplifier), leakage of the sensing circuit is significantly reduced during precharge operation mode without sacrificing performance during read operation mode. Related method embodiments are also disclosed herein.

[0131] More specifically, see reference Figure 5A and Figure 5B This document discloses several embodiments of the structure, including embodiments of low-leakage sensing circuits 520.1 and 520.2 and embodiments of memory circuits 500.1 and 500.2 incorporating such low-leakage sensing circuits 520.1 and 520.2.

[0132] Memory circuits 500.1 and 500.2 may be, for example, static random access memory (SRAM) circuits or any other suitable memory circuits, which use sensing circuits 520.1 and 520.2 with sensing amplifiers to detect differences in voltage levels on complementary bit lines during read operations. Specifically, memory circuits 500.1 and 500.2 may include an array 510 of memory cells 501 arranged in columns AN and rows an. Memory circuit 500 may also include at least a pair of complementary bit lines for each column (i.e., a true bit line (BLT) and a complementary bit line (BLC) for each column). For example, see BLT 531A and BLC 532A for column A, BLT 531B and BLC 532B for column B, and so on. Memory circuit 500 may also include at least one word line (WL) for each row. For example, see WL 533a for row a, WL 533b for row b, and so on. Those skilled in the art will recognize that the total number of bit lines per column and the total number of word lines per row will depend on the type of SRAM cell used.

[0133] For illustrative purposes, memory cell 501 is described below and is illustrated in the accompanying drawings as a six-transistor (6T) SRAM cell. Figure 6As shown, the 6T-SRAM cell 501 may include: two pass-gate transistors (e.g., two N-type field-effect transistors (NFETs)); two pull-up transistors (e.g., two P-type field-effect transistors (PFETs)); and two pull-down transistors (e.g., two additional NFETs). Specifically, the 6T-SRAM cell 501 may include a first inverter and a second inverter. The first inverter may include a first pull-up transistor 602 (e.g., a PFET) and a first pull-down transistor 603 (e.g., an NFET) connected in series between a positive voltage supply rail and a ground or negative voltage supply rail. It should be noted that, depending on the configuration of the memory circuitry 500, the positive voltage supply rail may be at the same positive voltage level (e.g., VDD 540) used to power the peripheral circuitry of the memory circuitry 500.1, 500.2, or at a higher voltage level (e.g., VCS 549) used only to power the memory cell. In any case, the second inverter may include a second pull-up transistor 612 (e.g., another PFET) and a second pull-down transistor 613 (e.g., another NFET) connected in series between the same voltage rails. The first and second inverters may be cross-coupled. That is, the gates of the second pull-up transistor 612 and the second pull-down transistor 613 may be connected to a first data node 605, which is the junction between the first pull-up transistor 602 and the first pull-down transistor 603. Additionally, the gates of the first pull-up transistor 602 and the first pull-down transistor 603 may be connected to a second data node 615, which is located at the junction between the second pull-up transistor 612 and the second pull-down transistor 613. The 6T-SRAM cell 501 may also include a pair of pass-gate transistors (e.g., NFETs), including a first pass-gate transistor 604 connected in series between the column BLT 531 and the first data node 605, and a second pass-gate transistor 614 connected in series between the same column BLC 532 and the second data node 615. For a specific row, the gates of the first pass-gate transistor 604 and the second pass-gate transistor 614 can be connected to WL 533.

[0134] Those skilled in the art will recognize that such a 6T SRAM cell 501 can operate in three different modes: standby, write, and read. In standby mode, the cell is idle. In write mode, data values ​​are written to the cell. Specifically, if a data value "1" (i.e., a high data value) is to be written to the first data node 605, BLC 532 is set to a first or low voltage level (e.g., discharged to ground (GND)), and BLT 531 is charged to a second voltage level (e.g., VDD) greater than the first voltage level. WL 533 is activated (i.e., switched from the first voltage level to the second voltage level) to turn on the first and second pass-gate transistors 604 and 614, thereby storing the data value "1" on the first data node 605. Conversely, if a data value "0" (i.e., a low data value) is to be written to the first data node 605, BLT 531 is discharged and BLC 532 is charged to the second voltage level. Then, WL 533 is activated to turn on the first and second pass-gate transistors 604 and 614, thereby storing a data value of "0" on the first data node 605. In read mode, the data value stored on the first data node 605 in the cell is read out. Specifically, BLT 531 and BLC 532 are both precharged to the second voltage level, and WL 533 is activated to turn on the first and second pass-gate transistors 604 and 614. When a data value of "1" is stored on the first data node 605, BLT 531 will remain charged at its precharge voltage level, and the voltage level on BLC 532 will be pulled down through the second pass-gate transistor 614 and the second pull-down transistor 613. When a data value of "0" is stored on the first data node 605, the voltage level on BLT 531 will be pulled down through the first pass-gate transistor 604, and the first pull-down transistor 603 and BLC 532 will remain charged at their precharge voltage levels. As discussed in more detail below with respect to the low-leakage sensing circuit 520, a sensing amplifier (for containing the column of selected memory cells to be read) connected to the BLT and BLC will detect the difference in voltage levels on the BLT and BLC (i.e., will sense the voltage difference), and a latch connected to the sensing amplifier will capture this voltage difference and output an output signal (Q) that indicates the data value stored in the selected memory cell.

[0135] The description of the 6T-SRAM cell above is for illustrative purposes only and is not intended to be limiting. It should be understood that the memory cell 501 incorporated into the memory array 510 may be a 6T SRAM cell with a different configuration, a different type of SRAM cell (e.g., an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell), or a different type of memory cell. Similarly, a sense amplifier is required during read operations to detect the voltage difference on the complementary bit line pairs.

[0136] The memory circuits 500.1 and 500.2 may further include a controller 595 and peripheral circuitry configured to operate in response to control signals from the controller 595. Specifically, the peripheral circuitry may include a row control block 591, which may be connected to the word lines of a row and may include, for example, address decoding logic for activating a selected word line and a word line driver (i.e., for switching the selected word line from a low voltage level to a high voltage level) according to an operating mode. The peripheral circuitry may include a column control block 592, electrically connected to the bit lines for a column, and may include, for example, column address decoding logic and a bit line driver for appropriately biasing the selected bit lines according to an operating mode. The peripheral circuitry may also include sensing circuits 520.1 and 520.2, which, as discussed in more detail below, are configured to read stored data from the memory array 510. Controllers, row control blocks, and column control blocks for memory array operation are well known in the art. Therefore, details have been omitted from this specification in order to allow the reader to focus on the significant aspects of the disclosed embodiments specifically related to the low-leakage sensing circuits 520.1, 520.2, as described below.

[0137] Like prior art sensing circuits, the low-leakage sensing circuits 520.1 and 520.2 may include sensing amplifiers for columns (e.g., see sensing amplifier 521A for column A, sensing amplifier 521B for column B, etc.); latches for the sensing amplifiers (e.g., see latch 522A for sensing amplifier 521A, latch 522B for sensing amplifier 521B, etc.); and a sensing circuit control block 529 configured to facilitate the reading of stored data values ​​from selected memory cells in response to various control signals (including, but not limited to, precharge circuit control signal (PRECHB), access transistor control signal (PASSB), and sensing mode trigger signal (TRIG) from controller 595). However, unlike prior art sensing circuits, each sensing amplifier in the low-leakage sensing circuits 520.1 and 520.2 disclosed herein may specifically lack a conventional built-in tailing device. Conversely, the sensing circuit control blocks 529.1 and 529.2 may include a common tail device 580 and additional circuitry (specifically, a sensing signal generation and boost (SSG&B) circuit 527) to compensate for the absence of a tail device within each sensing amplifier.

[0138] Figure 7A schematic diagram of an exemplary sensing amplifier 521 that can be incorporated into sensing circuits 520.1 and 520.2 is shown. As shown, sensing amplifier 521 may have a pull-down node 785, and the pull-down nodes of all sensing amplifiers in sensing circuits 520.1 and 520.2 may be electrically connected to a common voltage pull-down line 585 (instead of being electrically connected to a voltage rail 545, such as a ground rail or a negative voltage supply rail, via a built-in tail device). The remaining circuitry of sensing amplifier 521 may have any suitable configuration sufficient to detect the voltage difference on complementary bit line pairs.

[0139] For example, such as Figure 7 As shown, the sense amplifier 521 may include a first branch 710 (referred to herein as the data branch) and a second branch 720 (referred to herein as the reference branch). The first branch 710 may include a first pull-up transistor 712 (e.g., a PFET) and a first pull-down transistor 711 (e.g., an NFET) connected in series between a pull-up node 786 and a pull-down node 785. The second branch 720 may include a second pull-up transistor 722 (e.g., a PFET) and a second pull-down transistor 721 (e.g., an NFET) connected in series between the pull-up node 786 and the pull-down node 785.

[0140] The sense amplifier 521 may also include a pair of access transistors 731 and 732. The first access transistor 731 (e.g., a PFET) may have a source / drain region connected to the column BLT 531, and another source / drain region connected to the gate of the first pull-down transistor 711, to the gate of the first pull-up transistor 712, to the first output node 751, to a cross-coupled node 723 at the connection point between the second pull-up transistor 722 and the second pull-down transistor 721, and to the precharge circuit 740. The second access transistor 732 (e.g., a PFET) may have a source / drain region connected to the column BLC 532, and another source / drain region connected to the gate of the second pull-down transistor 721, to the gate of the second pull-up transistor 722, to the second output node 752, to a cross-coupled node 713 at the connection point between the first pull-up transistor 712 and the first pull-down transistor 711, and to the precharge circuit 740. The on and off states of the first and second access transistors 731 and 732 can be controlled by the access transistor control signal (PASSB) 524 from the controller 595 or the sensing circuit control blocks 529.1, 529.2 (e.g., Figure 5A and Figure 5B (As shown).

[0141] The precharge electronic circuit 740 may include three precharge transistors (e.g., PFETs) 741-743. A first precharge transistor 742 may be connected in series between a pull-up node 786 and a first access transistor 731. A second precharge transistor 742 may be connected in series between a pull-up node 786 and a second access transistor 732. A third precharge transistor 743 may have a source / drain region connected to the connection point between the first precharge transistor 741 and the first access transistor 731, and another source / drain region connected to the connection point between the second precharge transistor 742 and the second access transistor 732. The on and off states of the three precharge transistors 741-743 may be simultaneously controlled by a precharge electronic circuit control signal (PRECHB) 525 from a controller 595 or sensing circuit control blocks 529.1, 529.2 (e.g., ...). Figure 5A and Figure 5B (As shown).

[0142] Within the sensing circuits 520.1 and 520.2 of the memory circuits 500.1 and 500.2, the pull-down node 785 of the sensing amplifier can be electrically connected to a common voltage pull-down line 585, and the common voltage pull-down line 585 can be electrically connected to the sensing circuit control blocks 529.1 and 529.2. In some embodiments, within the sensing circuit 520.1 (for example, see...), Figure 5A The pull-up node of the sensing amplifier can be directly connected to an additional voltage rail, specifically the positive voltage supply rail 540. In other embodiments, within the sensing circuit 520.2 (see, for example, see...), the pull-up node can be connected to an additional voltage rail, specifically the positive voltage supply rail 540. Figure 5B The pull-up node 786 of the sensing amplifier can be electrically connected to the common voltage pull-up line 541, and the common voltage pull-up line 541 can be electrically connected to the sensing circuit control block 529.2.

[0143] In any case, in such Figure 7 In each of the sensing amplifiers 521 shown, the first output node 751 and the second output node 752 can be electrically connected to the first input node and the second input node of the corresponding latch 522, respectively.

[0144] The sensing circuit control blocks 529.1 and 529.2 may include a common tail device 580 electrically connected to a common voltage pull-down line 585. The common tail device 580 may be, for example, a single NFET device 581, such as... Figure 8A As shown. Alternatively, the common tail device 580 may include multiple stacked NFETs (e.g., 581a-581b) with a shared gate, as shown. Figure 8BAs shown. In any case, the common tail device 580 may include: a source region, for example connected to a voltage rail 545 (e.g., a ground rail or a negative voltage supply rail); a drain region, connected to a common voltage pull-down line 585, thereby connecting to a pull-down node 785 in each sense amplifier; and a gate. When the common tail device 580 is turned on, the voltage level on the pull-down nodes of all sense amplifiers will be pulled down simultaneously through the common voltage pull-down line 585 and the common tail device 580 (e.g., during readout operations, as discussed in more detail below). When the common tail device 580 is turned off, the voltage level on the pull-down nodes should remain constant (e.g., during precharge operation mode, as discussed in more detail below).

[0145] The sensing circuit control blocks 529.1 and 529.2 may further include a sensing signal generation and boost (SSG&B) circuit 527. The SSG&B circuit 527 may be electrically connected to the gate of the common tail device 580 and may be configured to generate a sensing mode control signal (SEN) 523 to apply SEN 523 to the gate of the common tail device 580 to control the on and off states of the common tail device 580, and to boost SEN 523 when the common tail device 580 has been switched to the on state to increase the drive current of the common tail device 580, such that in each sensing amplifier, the voltage level on one of the output nodes can be sufficiently pulled down through its pull-down node, the common voltage pull-down line 585, and the common tail device 580 to facilitate detection of voltage differences in complementary bit line pairs and avoid read failures.

[0146] Figure 9 This is a schematic diagram of an exemplary SSG&B circuit 527 that may be incorporated into sensing control blocks 529.1, 529.2. The SSG&B circuit 527 may include an input node 906 that receives a sensing mode trigger signal (TRIG) 526 (e.g., from controller 595).

[0147] SSG&B circuit 527 may also include delay circuit 910. Delay circuit 910 may include four inverter delay elements 911-914 connected in series, specifically a first inverter 911 that receives TRIG 526 from input node 906 and outputs a first delayed signal 921 (DL1); a second inverter 912 that receives DL1 921 and outputs a second delayed signal (DL2); a third inverter 913 that receives DL2 and outputs a third delayed signal (DL3) 923; and a fourth inverter 914 that receives DL3 923 and outputs a fourth delayed signal (DL4) 924.

[0148] The SSG&B circuit 527 may also include a coupling capacitor 903. The delay circuit 910 and the coupling capacitor 903 may be connected in series between the input node 906 and the output node 905.

[0149] SSG&B circuit 527 may also include a NAND gate 901. NAND gate 901 can receive TRIG 526 from input node 906 and DL3 923 from the third inverter 913 of delay circuit 910 as inputs. NAND gate 901 can also output a sense pull-up (SPU) 925 according to a conventional NAND gate truth table. That is, SPU 925 will be at logic "1" unless both TRIG 526 and DL3 923 are at logic "1", causing SPU 925 to switch to logic "0".

[0150] SSG&B circuit 527 may also include PFET 902 and NFET 904, which are connected in series between a positive voltage supply rail 540 and another voltage rail 545 (e.g., a ground rail or a negative voltage supply rail). NAND gate 901 applies SPU 925 to the gate of PFET 902 to control the on and off states of PFET 902. First inverter 911 applies DL1 921 from the first inverter 911 of delay circuit 910 to the gate of NFET 904 to control the on and off states of NFET 904. As shown, output node 905 of SSG&B circuit 527 may be located at the junction between PFET 902 and NFET 904, and may output SEN 523 to the gate of common tail device 580 to control the on and off states of common tail device 580.

[0151] As described above, in some embodiments, within the sensing circuit 520.2 (see above) Figure 5B The pull-up node 786 of the sensing amplifier 521A-N can be electrically connected to the common voltage pull-up line 541, and the common voltage pull-up line 541 can be electrically connected to the common header device 570 within the sensing circuit control block 529.2. The common header device 570 can be, for example, a single PFET device 571, such as... Figure 10A As shown. Alternatively, the common header device 570 may include multiple stacked PFETs (e.g., 571a-571b) with a shared gate, as shown. Figure 8BAs shown. In any case, the common header device 570 may include: a second source region connected to the positive voltage supply rail 540 (e.g., at VDD); a second drain region connected to each sense amplifier, such that the sense amplifiers are connected in parallel between the common tail device 580 and the common header device 570; and a second gate. The on and off states of the common header device 570 may be controlled by a sleep mode control signal (LSB) 573 from the controller 595 or the sense circuit control block 529.

[0152] The low-leakage sensing circuits 520.1 and 520.2 can operate in either precharge operation mode or read operation mode. Figure 11 The diagram shows the state of various signals over time within the sensing circuits 520.1, 520.2, particularly within the sensing circuit control blocks 529.1, 529.2, and within each sensing amplifier 521A-N (e.g., during the precharge operation mode and subsequently during the readout operation mode).

[0153] Specifically, during the pre-charge operation mode at time T0 or T10, PRECHB 525 may be at a first or low voltage level (e.g., at GND), such that within each sense amplifier 521A-N (e.g., as... Figure 7 As shown), the three precharge transistors 741-743 in the precharge electronic circuit 740 are turned on, thereby precharging the first output node 751 and the second output node 752. Additionally, the PASSB 524 can be at a second voltage level higher than the first voltage level (e.g., at VDD), such that within each sense amplifier 521A-N (e.g., as shown)... Figure 7 As shown), the first and second access transistors 731-732 of each sense amplifier 521A-N are turned off. Furthermore, within the SSG&B circuit 527 (e.g., as shown...), Figure 9 As shown), TRIG 526 will be at the first voltage level, causing DL1 921 to be at the second voltage level, thereby turning on NFET 904 and pulling down the voltage level on output node 905. Since the voltage level on output node 905 of SSG&B circuit 527 controls common tail device 580 (as shown), Figure 8A The NFET 581 shown or as Figure 8BWith the set of stacked NFETs 581a-581b shown in their on and off states, the common tail device 580 will be turned off. Therefore, the voltage level on the common voltage pull-down line 585 connected to each sense amplifier 521A-N, and thus the voltage level on the pull-down node 785 (NPULL) within each sense amplifier 521A-N, will not be pulled down, but will stabilize at approximately halfway between the first voltage level (e.g., GND) and the second voltage level (e.g., VDD). Since the only leakage current path is through the common tail device 580 and not through any built-in tail devices within the sense amplifiers 521A-N, this configuration achieves a nearly 40-fold reduction in sensing circuit leakage.

[0154] The readout operation occurs between time T1 and time T9. Specifically, at time T1, PRECHB 525 switches to the second voltage level (e.g., VDD), and PASSB switches back to the first voltage level (e.g., GND). As a result, within each sense amplifier 521A-N (e.g., as...), Figure 7 As shown, precharge transistors 741-743 are turned off and access transistors 731-732 are turned on, so that for each sense amplifier 521A-N, the voltage signal on BLT 531 and BLC 532 can be received as input.

[0155] At time T2, TRIG 526 switches from a first voltage level (e.g., GND, logic "0") to a second voltage level (e.g., VDD, logic "1").

[0156] Refer to SSG&B circuit 527 (e.g., as...) Figure 9 (As shown) combined Figure 11 During the first clock cycle after TRIG 526 switches to the second voltage level (e.g., VDD, logic "1"), the first inverter 911 receiving TRIG 526 switches DL1 from the second voltage level back to the first voltage level (i.e., to ground, logic "0"). Additionally, during the first clock cycle after TRIG 526 switches to the second voltage level (e.g., VDD, logic "1"), the SPU 925 output of NAND gate 901 switches to the first voltage level (e.g., to VDD, logic "1") because at this time, both inputs to NAND gate 901 (TRIG 526 and DL3 923) are at the second voltage level (e.g., VDD, logic "1").

[0157] In the second clock cycle after TRIG 526 switches to the second voltage level (e.g., VDD, logic "1"), SPU 925 will be at the first voltage level (e.g., GND, logic "0"), thus turning on PFET 902, causing the voltage level at output node 905 and consequently the voltage level of SEN 523 to be pulled up to the second voltage level (e.g., to VDD, logic "1") (see time T3). Additionally, the second inverter 912 in delay circuit 910 receives the switched DL1 921 and outputs the switched DL2 921 (i.e., DL2 921 switches to VDD, logic "1").

[0158] In the third clock cycle after TRIG 526 switches to the second voltage level (e.g., VDD, logic "1"), the third inverter 913 receives the switched DL2 922 (which is at the second voltage level) and outputs the switched DL3 923 (i.e., DL3 switches to GND, logic "0").

[0159] In the fourth clock cycle after TRIG 526 switches to the second voltage level (e.g., VDD, logic "1"), NAND gate 901 switches SPU 925 back to the second voltage level because TRIG 526 is now at logic "1" and DL3 923 is now at logic "0". Additionally, fourth inverter 914 receives the switch DL3 (as described above, it is now at logic "0") and outputs the switch DL4 (i.e., DL4 switches to VDD). That is, at time T5, DL4 is at the second voltage level (e.g., at VDD) and thus charges coupling capacitor 903, which in turn raises the voltage level of SEN 523 from the second voltage level (e.g., VDD) to the third voltage level (e.g., VDD+), which is higher than the second voltage level (e.g., 100mV or higher, e.g., approximately 125mV) (see time T4). For example, in some embodiments, the second voltage level (e.g., VDD) may be about 0.45V, and the third voltage level (e.g., VDD+) may be about 0.55V or higher (e.g., about 0.6V).

[0160] Combination Figure 11 Referring again to the sensing amplifier 521 (e.g., as...) Figure 7As shown), during the read operation mode at time T3, when the common tail device 580 is turned on but the voltage level on the gate of the common tail device 580 (i.e., the voltage level of SEN 523) is only at the second voltage level (e.g., at VDD), the common tail device 580 does not have sufficient drive current to pull down the voltage level on one of the output nodes 751 or 752 within each sense amplifier through the pull-down node 785, the common voltage pull-down line 585 (NPULL), and the common tail device 580, so that it can be detected by the voltage differential signal on the complementary bit line pair. Only after the voltage level of SEN 523 is raised to the third voltage level (e.g., to VDD+) does the pull-down node 785, the common voltage pull-down line 585, and the common tail device 580 have sufficient pull-down strength (see times T4 to T7).

[0161] Specifically, during the read operation mode at time T4, due to the previous pre-charge operation, both the first and second output nodes 751 and 752 will be at or near the second voltage level (e.g., VDD). As described above, regarding Figure 6 In the exemplary 6T-SRAM cell 501, during read operation mode, when the data value "1" is stored on the first data node 605, the BLT 531 will remain charged at its pre-charge voltage level, and the voltage level on the BLC 532 will be pulled down through the second pass-gate transistor 614 and the second pull-down transistor 613, and vice versa. A sense amplifier 521 is used to detect and amplify the differential signal (which may be relatively weak). Once the differential signal is detected and amplified, it can be captured by the latch 522.

[0162] For example, considering the case where the data value "1" is stored on the first data node, BLT 531 will have a higher voltage level than BLC 532. When sense amplifier 521 is connected to complementary bit line pairs (e.g., such as...), Figure 7When (as shown), the first pull-down transistor 711 will be turned on, and the first pull-up transistor 712 will be turned off. Therefore, the first pull-down transistor 711 will (e.g., through pull-down node 785, common voltage pull-down line 585, and common tail device 580) pull down the voltage levels on the first cross-coupled node 713 and the second output node 752. The low voltage level on the first cross-coupled node 713 will sequentially ensure that the second pull-down transistor 721 remains off and the second pull-up transistor 722 is turned on. The boost to SEN 523 ensures sufficient drive strength to maintain the low voltage level on the first cross-coupled node 713. Therefore, the second pull-up transistor 722 will pull up the voltage levels on the second cross-coupled node 723 and the first output node 751 (e.g., through pull-up node 786). That is, the voltage level on the first output node 751 will remain at a second voltage level (e.g., VDD) indicating the stored data value "1", and the voltage level on the second output node 752 will be pulled down to a first voltage level (e.g., GND) (see time T7).

[0163] A latch 522 having first and second input nodes connected to first and second output nodes 751-752 of a sensing amplifier 521 can capture a voltage difference and output an output signal (Q) indicating the stored data value read from a memory cell. Various configurations for such a latch are well known in the art, and therefore, their details are omitted from this specification to allow the reader to focus on the significant aspects of the disclosed embodiments.

[0164] Note that during times T5-T6, TRIG 526 can switch back to the second voltage level (e.g., to GND). In the following four clock cycles, delay circuit 910 can sequentially switch the delay signals (DL1, DL2, DL3, and DL4) to reset SEN523 back to the first voltage level and turn off common tail device 580 (see times T7-T8).

[0165] Then, during time T9-T10, PRECHB 525 can switch back to the first voltage level (e.g., to GND) and can repeat the precharge operation mode to precharge the voltage levels on the first output node 751 and the second output node 752 to the second voltage level (e.g., to VDD). As shown, the voltage level on the pull-down node 785 is also pulled up to approximately half between the first voltage level (e.g., GND) and the second voltage level (e.g., VDD).

[0166] As described above and in Figure 5A As shown, in sensing circuit 520.1, the pull-up node 786 of each sensing amplifier 521A-N can be directly connected to the positive voltage supply rail 540. Alternatively, as described above... Figure 5BAs shown, in sensing circuit 520.2, the pull-up node 786 of each sensing amplifier 521A-N can be connected to a common voltage pull-up line 541. In this case, sensing circuit control block 529.2 may also include a common header device 570. That is, each sensing amplifier 721A-N can be connected to the positive voltage supply rail 540 via the common header device 570 in sensing circuit control block 529.2, instead of being directly connected to the positive voltage supply rail 540. Such a common header device 570 can be controlled by a sleep mode control signal (LSB) 573 from controller 595. When memory circuit 500.2 is in idle mode for a long time and enters light sleep mode, LSB can switch to logic "1", thereby turning off the common header device 570 and simultaneously blocking any leakage current path through the sensing amplifier.

[0167] In the above embodiments, by combining the common tail device 580 with the SSG&B circuit 527 (instead of the leakage-integrated tail device within the sense amplifier), leakage from the sense circuits 520.1, 520.2 is significantly reduced during the precharge operation mode without sacrificing performance during the read operation mode. Optionally, by using the common header device 570, the positive voltage supplied to the sense amplifiers 521A-N can be selectively turned off (e.g., in response to a sleep mode control signal during sleep mode) to further reduce leakage from the sense circuit 520.2. Therefore, the low-leakage sense circuits 520.1, 520.2 disclosed in this invention reduce the contribution of sense circuit leakage to the total memory circuit leakage of the memory circuits 500.1, 500.2, which include the low-leakage sense circuits.

[0168] refer to Figure 12 The flowchart is provided, and embodiments of methods for manipulating the structure are also disclosed herein.

[0169] The method may include providing a low-leakage sensing circuit (e.g., the one described in detail above). Figure 5A The low-leakage sensing circuit 520.1 or Figure 5B 520.2 in the above) and memory circuits (e.g., those described in detail above). Figure 5A The memory circuit 500.1 or Figure 5B The memory circuit 500.2 includes low-leakage sensing circuits 520.1 and 520.2 (see processing step 1202).

[0170] The method may further include generating a sensing mode control signal (SEN) 523 (see processing step 1204) through the sensing signal generation and boost (SSG&B) circuit 527 in the sensing circuit control blocks 529.1 and 529.2 of the sensing circuits 520.1 and 520.2. SEN 523 may be generated based on the sensing mode trigger signal (TRIG) 526.

[0171] The method may further include applying SEN 523 to the gate of a common tailing device 580 via SSG&B circuit 527. The common tailing device 580 is located within sensing circuit control blocks 529.1 and 529.2 and is connected to a pull-down node in each sensing amplifier 521A-N by a common voltage pull-down line 585 (see processing step 1206). Applying SEN 523 to the gate of the common tailing device 580 can be used to control the on and off states of the common tailing device 580.

[0172] When SEN 523 is at a first voltage level (e.g., GND), the common tail device 580 can be turned off (e.g., during pre-charge operation mode in the sense amplifier). Since there is only one common tail device 580, leakage from the sense circuitry is significantly reduced during pre-charge operation mode.

[0173] When SEN 523 is switched to a second voltage level (e.g., VDD), the common tail device 580 can be turned on (e.g., during readout operation mode in the sense amplifier). That is, the method may also include switching SEN 523 from a first voltage level (e.g., GND) to a second voltage level (e.g., VDD) via SSG&B circuit 527 during readout operation mode based on the voltage level of TRIG 526, in order to turn on the common tail device 580 (see processing step 1208). However, as stated above regarding... Figure 7 and Figure 11 During the readout operation mode discussed, when the common tail device 580 is turned on but the voltage level on the gate of the common tail device 580 (i.e., the voltage level of SEN 523) is only at the second voltage level (e.g., at VDD), the common tail device 580 may not have sufficient drive current to ensure that the voltage on one of the first and second output nodes 751 or 752 in each sense amplifier 521A-N is sufficiently pulled down through the pull-down node 785, the common voltage pull-down line 585 (NPULL), and the common tail device 580 to enable the detection of the voltage differential signal on the complementary bit line pair.

[0174] Therefore, the method may further include boosting SEN 523 from a second voltage level (e.g., VDD) to a third voltage level (e.g., VDD+) via SSG&B circuit 527, which is greater than the second voltage level, when the common tail device 580 is turned on during read operation mode to increase the drive current of the common tail device 580 (see processing step 1210). Boosting SEN 523 to increase the drive current of the common tail device 580 is performed in processing step 1210 such that during read operation mode in each of the sense amplifiers 521A-N, the voltage level on one of the first and second output nodes 751 and 752 is sufficiently pulled down by pull-down node 785, common voltage pull-down line 585, and common tail device 580 to enable detection of voltage differences in complementary bit line pairs, thereby preventing read failures.

[0175] Optionally, the low-leakage sensing circuit 520.2 provided in processing step 1202 (see...) Figure 5B In this circuit, the pull-up node 786 of the sense amplifiers 521A-N can be electrically connected to the common voltage pull-up line 541, and the common voltage pull-up line 541 can be electrically connected to the common header device 570 within the sense circuit control block 529.2. In this case, the method may further include applying a sleep mode control signal (LSB) 573 (e.g., from the controller 595) to the gate of the common header device 570 to control the on and off states of the header device (see processing step 1212). When the memory circuit 500.2 is in idle mode for an extended period and enters a light sleep mode, the LSB can be switched to logic "1", thereby turning off the common header device 570 and simultaneously blocking any leakage current path through the sense amplifiers.

[0176] It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not restrictive. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprising,” “including,” “comprising by,” and / or “containing” specify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Additionally, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “above,” “parallel,” and “upright” are used to describe relative positions, as shown in the accompanying drawings (unless otherwise stated), and terms such as “contact,” “direct contact,” “adjacent,” “directly adjacent,” and “closely adjacent” are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term “lateral” is used herein to describe the relative position of elements, more specifically, indicating that an element is positioned above or below another element to the side of that element, as these elements are oriented and shown in the accompanying drawings. For example, an element laterally adjacent to another element will be located next to that element; an element laterally adjacent to another element will be located directly next to that element; and an element laterally surrounding another element will be adjacent to and bound to the outer wall of that element. The corresponding structures, materials, actions, and equivalents of all means or steps plus functional elements in the appended claims are intended to include any structures, materials, or actions used to perform functions in combination with elements of the other claims specifically claimed.

[0177] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application or improvement relative to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A circuit structure comprising: Multiple sensing amplifiers, each including a pull-down node; A common tail device for the plurality of sense amplifiers, wherein the common tail device includes: a source region connected to the ground rail, a drain region connected to each of the pull-down nodes, and a gate; and The sensing signal generation and boost circuit has an output node connected to the gate of the common tail device. The sensing signal generation and boost circuit generates a sensing mode control signal at the output node to control the on and off states of the common tail device, and further boosts the sensing mode control signal when the common tail device is in the on state to increase the drive current of the common tail device.

2. The structure according to claim 1, wherein, The sensing signal generation and boost circuit includes: Input node, receives sensing mode trigger signal; A delay circuit comprising four inverter delay elements connected in series, including: a first inverter that receives the sensing mode trigger signal and outputs a first delay signal; a second inverter that receives the first delay signal and outputs a second delay signal; a third inverter that receives the second delay signal and outputs a third delay signal; and a fourth inverter that receives the third delay signal and outputs a fourth delay signal. A capacitor, wherein the delay circuit and the capacitor are connected in series between the input node and the output node; A NAND gate receives the sensing mode trigger signal and the third delay signal, and outputs a sensing pull-up signal; and A p-type transistor and an n-type transistor are connected in series between a positive voltage supply rail and a ground rail. The sense pull-up signal is applied to the gate of the p-type transistor. The first delay signal is applied to the gate of the n-type transistor by the first inverter. The output node is located at the connection point between the p-type transistor and the n-type transistor and outputs the sense mode control signal to the gate of the common tail device.

3. The structure according to claim 2, wherein, When the sensing mode trigger signal is at a first voltage level and the first delay signal is at a second voltage level greater than the first voltage level, the n-type transistor is turned on, causing the sensing mode control signal on the output node to be pulled down to the first voltage level and the common tail device to be turned off.

4. The structure according to claim 3, wherein, When the sensing mode trigger signal switches from the first voltage level to the second voltage level, the first delay signal switches from the second voltage level to the first voltage level and turns off the n-type transistor.

5. The structure according to claim 4, wherein, When the sensing mode trigger signal switches from the first voltage level to the second voltage level, the switching of the third delay signal from the second voltage level to the first voltage level is delayed for a period of time, so that both inputs of the NAND gate are at the second voltage level, causing the sensing pull-up signal to switch to the first voltage level, turning on the p-type transistor, and the sensing mode control signal on the output node is pulled up to the second voltage level.

6. The structure according to claim 5, in, When the third delayed signal switches from the second voltage level to the first voltage level, the sensing pull-up signal switches back to the second voltage level, and the fourth delayed signal switches from the first voltage level to the second voltage level. Specifically, when the fourth delay signal switches to the second voltage level, the capacitor is charged and the sensing mode control signal is boosted to a third voltage level that is greater than the second voltage level.

7. The structure according to claim 1, further comprising: A memory array, comprising memory cells arranged in columns and rows; Bit line pairs for the column, wherein all memory cells in a column of memory cells are connected to the bit lines of the bit line pairs for the column, and wherein the bit lines of the bit line pairs for the column are connected to the sense amplifier for the column; and The latches are connected to the plurality of sensing amplifiers respectively.

8. A circuit structure comprising: Multiple sensing amplifiers, each including a pull-up node, wherein the multiple sensing amplifiers also each include a pull-down node; A common tail device for the plurality of sense amplifiers, wherein the common tail device includes: a first source region connected to a ground rail; a first drain region connected to each of the pull-down nodes; and a first gate; A header device for the plurality of sense amplifiers, wherein the header device includes: a second source region connected to a positive voltage supply rail; a second drain region connected to each of the pull-up nodes, such that the plurality of sense amplifiers are connected in parallel between the common tail device and the header device; and a second gate; and The sensing signal generation and boost circuit has an output node connected to the first gate of the common tail device. Specifically, the sensing signal generation and boost circuit generates a sensing mode control signal at the output node to control the on and off states of the common tail device, and further boosts the sensing mode control signal when the common tail device is in the on state to increase the drive current of the common tail device. The sleep mode control signal is applied to the second gate to control the on and off states of the header device.

9. The structure according to claim 8, wherein, The sensing signal generation and boost circuit includes: Input node, receives sensing mode trigger signal; A delay circuit comprising four inverter delay elements connected in series, including: a first inverter that receives the sensing mode trigger signal and outputs a first delay signal; a second inverter that receives the first delay signal and outputs a second delay signal; a third inverter that receives the second delay signal and outputs a third delay signal; and a fourth inverter that receives the third delay signal and outputs a fourth delay signal. A capacitor, wherein the delay circuit and the capacitor are connected in series between the input node and the output node; A NAND gate receives the sensing mode trigger signal and the third delay signal, and outputs a sensing pull-up signal; and A p-type transistor and an n-type transistor are connected in series between a positive voltage supply rail and a ground rail. The sense pull-up signal is applied to the gate of the p-type transistor. The first delay signal is applied to the gate of the n-type transistor by the first inverter. The output node is located at the connection point between the p-type transistor and the n-type transistor and outputs the sense mode control signal to the gate of the common tail device.

10. The structure according to claim 9, wherein, When the sensing mode trigger signal is at a first voltage level and the first delay signal is at a second voltage level greater than the first voltage level, the n-type transistor is turned on, causing the sensing mode control signal on the output node to be pulled down to the first voltage level and the common tail device to be turned off.

11. The structure according to claim 10, wherein, When the sensing mode trigger signal switches from the first voltage level to the second voltage level, the first delay signal switches from the second voltage level to the first voltage level and turns off the n-type transistor.

12. The structure according to claim 11, in, When the sensing mode trigger signal switches from the first voltage level to the second voltage level, the switching of the third delay signal from the second voltage level to the first voltage level is delayed for a period of time, so that both inputs of the NAND gate are at the second voltage level. This causes the sensing pull-up signal to switch to the first voltage level, turning on the p-type transistor, and the sensing mode control signal on the output node is pulled up to the second voltage level. Specifically, when the third delayed signal switches from the second voltage level to the first voltage level, the sensing pull-up signal switches back to the second voltage level, and the fourth delayed signal switches from the first voltage level to the second voltage level. Specifically, when the fourth delay signal switches to the second voltage level, the capacitor is charged and the sensing mode control signal is boosted to a third voltage level that is greater than the second voltage level.

13. A method for operating the structure of a circuit, comprising: Provide a sensing circuit, including: Multiple sensing amplifiers, each including a pull-down node; A common tail device for the plurality of sense amplifiers includes: a source region connected to the ground rail; a drain region connected to each of the pull-down nodes; and a gate; and The sensing signal generation and boost circuit has an output node connected to the gate of the common tail device; The sensing mode control signal is generated through the sensing signal generation and boost circuit; and The sensing mode control signal is applied to the gate of the common tail device through the sensing signal generation and boost circuit to control the on and off states of the common tail device. Specifically, when the sensing mode control signal switches to the first voltage level, the common tail device is turned off and the leakage current through the plurality of sensing amplifiers is minimized. Wherein, when the sensing mode control signal switches to a second voltage level greater than the first voltage level, the common tail device is turned on; and The sensing mode control signal is boosted to a third voltage level greater than the second voltage level when the common tail device is turned on by the sensing signal generation and boosting circuit.

14. The method according to claim 13, wherein, The boost of the sensing mode control signal increases the drive current of the common tail device, which pulls down the voltage level at the pull-down node of all the plurality of sensing amplifiers.

15. The method according to claim 13, in, The sensing circuit also includes a header device comprising: a second source region connected to a positive voltage supply rail; a second drain region connected to each of the plurality of sensing amplifiers, such that the plurality of sensing amplifiers are connected in parallel between the common tail device and the header device; and a second gate, and The method further includes applying a sleep mode control signal to the second gate to control the on and off states of the header device.

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