In-line memory system and memory testing method

Abstract

An embedded memory system includes an embedded memory circuit and a host circuit. The embedded memory circuit is used to store a lookup table. The host circuit is used to test the embedded memory circuit using a test clock signal having a plurality of phases and a plurality of instructions of a program of the embedded memory circuit, and record a correspondence between each of the instructions and the phases to generate the lookup table.

Description

TECHNICAL FIELD

[0001] The present application relates to embedded memory systems, and in particular, to embedded memory systems and memory testing methods using boot loaders for timing tests. BACKGROUND

[0002] In the prior art, specific signal patterns or additional test programs are used to test the timing of memory circuits. However, since these specific signal patterns are not data that will be actually written / read by the memory circuits later, and these test programs are not programs that will be actually executed by the memory circuits later, the timing test results generated by these signal patterns or test programs can not be suitable for setting the actual operation of the memory circuits. In other words, the timing scan range obtained by the prior art is different from the timing range actually used by the memory circuits. As a result, the memory circuits can not use appropriate timing in actual applications. SUMMARY

[0003] In some embodiments, an embedded memory system includes an embedded memory circuit and a host circuit. The embedded memory circuit is configured to store a lookup table. The host circuit is configured to test the embedded memory circuit using a test clock signal having a plurality of phases and a plurality of instructions of a program of the embedded memory circuit, and record a correspondence between each of the instructions and the phases to generate the lookup table.

[0004] In some embodiments, a memory testing method includes the following operations: testing an embedded memory circuit using a test clock signal having a plurality of phases and a plurality of instructions of a program; and recording a correspondence between each of the instructions and the phases to generate a lookup table, the embedded memory circuit being configured to select a specific phase corresponding to a first instruction of the instructions from the plurality of phases according to the lookup table to execute the first instruction.

[0005] The features, implementations, and effects of the present application will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of an embedded memory system according to some embodiments of the present application is shown;

[0007] Figure 2 A flowchart of a timing scan test method according to some embodiments of the present application is shown;

[0008] Figure 3A flowchart of a memory testing method is depicted in accordance with some embodiments of the present application; and

[0009] Figure 4 A timing diagram of a timing scan test result is depicted in accordance with some embodiments of the present application. DETAILED DESCRIPTION

[0010] All words used herein are to be interpreted according to their normal meaning. Definitions of the above words in a commonly used dictionary are included in the content of the present application, and the use of any of the words discussed herein in the present specification is merely an example, and should not limit the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in the present specification.

[0011] As used herein, "coupled" or "connected" can mean either a direct electrical or physical contact between two or more components or an indirect electrical or physical contact between two or more components through another component. As used herein, the term "circuit" can be a device that processes signals by way of at least one transistor and / or at least one passive component in a certain manner.

[0012] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. In the present specification, the use of the terms first, second, and third, etc. do not denote any order or importance, but rather are used to distinguish one element from another. Therefore, a first element discussed herein could also be termed a second element without departing from the spirit of the present application. For ease of understanding, similar components in the various drawings will be designated by identical reference numerals.

[0013] Figure 1 A schematic diagram of an embedded memory system 100 is depicted in accordance with some embodiments of the present application. The embedded memory system 100 includes an embedded memory circuit 120 and a host circuit 140. In some embodiments, the embedded memory circuit 120 can be, but is not limited to, an embedded multimedia card (eMMC) chip that includes a memory array (not shown) for storing data and a controller circuit (not shown) for controlling the memory array. In some embodiments, the aforementioned memory array can be a flash memory.

[0014] In some embodiments, the host circuit 140 can be used to perform a timing scan test on the embedded memory circuit 120 to generate a lookup table LT. In some embodiments, the host circuit 140 includes a processor circuit 142, a memory circuit 144, and a clock generator circuit 146. The processor circuit 142 can be used to perform a timing scan test on the embedded memory circuit 120 to generate a lookup table LT. In some embodiments, the processor circuit 142 can be a microprocessor, a microcontroller, a digital signal processor (DSP), a programmable logic device (PLD), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable gate array (FPGA), or any other suitable device for processing data. Figure 3Multiple operations are performed to perform timing scan tests on the embedded memory circuit 120 to generate a lookup table LT. The memory circuit 144 can be used to temporarily store multiple results of the timing scan tests and output the results as the lookup table LT upon completion of the tests. The clock generator circuit 146 is used to generate a test clock signal CLK to the embedded memory circuit 120, and the embedded memory circuit 120 can use the test clock signal CLK to execute multiple instructions in the program (e.g., ...). Figure 4 (Multiple read / write instructions, etc.) are used to perform timing scan tests.

[0015] In some embodiments, the test clock signal CLK has multiple phases (e.g., ...). Figure 4 The timing scan test is performed on the embedded memory circuit 120, which uses a lookup table LT to record the correspondence between each instruction and the phase. In some embodiments, after the timing scan test is completed, the master control circuit 140 can store the lookup table LT in the embedded memory circuit 120. Thus, the embedded memory circuit 120 can select a clock signal with a suitable phase according to the lookup table LT to execute the corresponding instruction. In some embodiments, the aforementioned program can be a boot program, which is a program executed by the kernel or operating system running through the embedded memory circuit 120 at boot time. In other words, the master control circuit 140 uses the program that the embedded memory circuit 120 will actually execute to perform a timing scan test on the embedded memory circuit 120. Compared to test results obtained using additional test programs (or additional test signals), test results obtained through the boot program are more accurate. Therefore, the embedded memory circuit 120 can use the lookup table LT to select a suitable phase to execute the corresponding instruction.

[0016] In some embodiments, the main control circuit 140 may be an application-specific integrated circuit (ASIC). In some embodiments, the processor circuit 142 may be (but is not limited to) a central processing unit (CPU), a multiprocessor, a pipelined processor, a distributed processing system, etc. In some embodiments, the memory circuit 144 may be (but is not limited to) a non-transitory computer-readable storage medium. In some embodiments, the computer-readable storage medium is an electrical, magnetic, optical, infrared, and / or semiconductor device. For example, computer-readable storage media include (but are not limited to) semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), hard disks, and / or optical disks. The types of processor circuit 142 and memory circuit 144 described above are for illustrative purposes and are not intended to limit the scope of this application.

[0017] Figure 2A flowchart of a timing scan test method 200 is provided according to some embodiments of this application. In some embodiments, the timing scan test method 200 may be (but is not limited to) [the following]. Figure 1 The embedded memory system 100 executes.

[0018] In operation S210, the embedded memory system (e.g., embedded memory system 100) is powered on. In operation S220, the embedded memory circuit is tested using a test clock signal with multiple phases and multiple instructions for starting the program. For example, the main control circuit 140 can execute the following... Figure 3 Multiple operations are performed to test the embedded memory circuit 120. During operation S230, the results of the timing scan test are recorded. For example, the processor circuit 142 can record multiple test results of the timing scan test (such as...). Figure 4 (As shown) Temporarily stored in Figure 1 The memory circuit 144 in the memory circuit. During operation S240, the result of the timing scan test is output as a lookup table. For example, after the timing scan test is completed, the processor circuit 142 can output a lookup table LT based on the multiple test results stored in the memory circuit 144, and write the lookup table LT to the embedded memory circuit 120.

[0019] Figure 3 A flowchart of a memory testing method 300 is provided according to some embodiments of this application. In some embodiments, operations S310, S320, S330, S340, and S350 in the memory testing method 300 can be considered as... Figure 2 The operation S220 in the text corresponds to several specific steps. In operation S310, timing scan testing begins, and the initial timing is set to the first phase (e.g., ). Figure 4 In operation S320, execute the startup procedure. In operation S230, record the test results of the startup procedure. In operation S330, confirm whether the current timing is the last phase (e.g., phase 0). Figure 4 Phase 31 in the sequence. If the current timing is the last phase, execute... Figure 2 Operation S240. Alternatively, if the current timing is not the last phase, operation S340 is executed. In operation S340, the previous test results are reset. In operation S350, the process switches to the next timing (e.g., to...). Figure 4 (The phase 0 in the process is switched to phase 1), and operation S320 is executed again.

[0020] Figure 4 This diagram illustrates timing scan test results according to some embodiments of the present application. In some embodiments, the startup procedure includes multiple write and / or read instructions executed at different clock frequencies. For example, as... Figure 4As shown, the start-up procedures can include, but are not limited to, a command read instruction (hereinafter referred to as "first command read instruction") executed with a clock signal having a frequency of 250 kilohertz (kHz) (denoted as 250k), a command write instruction executed with a clock signal having a frequency of 250 kHz, a read instruction executed with a clock signal having a frequency of 25 megahertz (MHz) (denoted as 25M), a write instruction executed with a clock signal having a frequency of 25 MHz, a read instruction executed with a clock signal having a frequency of 50 MHz, a command write instruction executed with a clock signal having a frequency of 50 MHz, a data write instruction executed with a clock signal having a frequency of 50 MHz, a data write instruction executed in HS200 mode, a command write instruction executed in HS200 mode, a write instruction executed in HS400 mode, and a read instruction executed in HS400 mode.

[0021] In this embodiment, Figure 4 The test clock signal CLK has 32 phases (i.e., phase 0 to phase 31). First, the host circuit 140 sets the phase of the test clock signal CLK to phase 0 and controls the embedded memory circuit 120 to sequentially execute a plurality of instructions in a start-up procedure (i.e., operation S310). The embedded memory circuit 120 sequentially executes the instructions with the test clock signal CLK having phase 0 and generates corresponding test results.

[0022] For example, the embedded memory circuit 120 executes the first command read instruction with the test clock signal CLK having phase 0 and a frequency of 250 kHz. If the first command read instruction can be correctly executed (denoted as O), the embedded memory circuit 120 can read a default data (i.e., the read data is a default value). Otherwise, if the read instruction cannot be correctly executed (denoted as X), the data read by the embedded memory circuit 120 is not the default data (i.e., the read data is not a default value). Thus, the processor circuit 142 can determine whether the embedded memory circuit 120 can correctly execute the first command read instruction with the test clock signal CLK having phase 0 according to the test result corresponding to the instruction (i.e., whether the read data is a default value). Similarly, the embedded memory circuit 120 can sequentially execute a plurality of instructions with the test clock signal CLK having phase 0 and corresponding frequencies, and the processor circuit 142 can determine whether the embedded memory circuit 120 can correctly execute the instructions with the test clock signal CLK having phase 0 according to the test results corresponding to the instructions. For example, as shown, the processor circuit 142 can know that the embedded memory circuit 120 cannot correctly execute the write instruction and the read instruction in HS400 mode with the test clock signal CLK having phase 0. Figure 4 ​

[0023] Next, after obtaining the test results of all instructions corresponding to phase 0 (i.e., operation S230), the host circuit 142 can reset the embedded memory circuit 120 (i.e., operation S340) and switch phase 0 to phase 1 (i.e., operation S350) to control the embedded memory circuit 120 to sequentially execute the plurality of instructions in the startup program again (i.e., operation S320). The embedded memory circuit 120 sequentially executes the instructions using the test clock signal CLK with phase 1 and generates corresponding test results. In this way, the processor circuit 142 can obtain the correspondence between each of the instructions and the plurality of phases 0-31 (as shown in Figure 4 In some embodiments, the plurality of test results can be temporarily stored in the memory circuit 144 as shown in Figure 4 In some embodiments, according to the plurality of test results, the host circuit 140 can confirm that the embedded memory circuit 120 can correctly execute the first command read instruction according to at least a first phase (e.g., phases 0-16) among the phases 0-31. Figure 4

[0024] After obtaining the correspondence between all instructions and the plurality of phases 0-31, the processor circuit 142 can generate a lookup table LT. In some embodiments, the lookup table LT can be represented as Table 1 below:

[0025]

[0026] In some embodiments, the default memory standard can be, but is not limited to, the JEDEC (Joint Electron Device Engineering Council, JEDEC) memory standard (e.g., JESD84-B51 or subsequent versions thereof). In some embodiments, the host circuit 140 can be used to exclude at least a second phase from the at least a first phase according to the default memory standard. In some embodiments, the host circuit 140 can select a specific phase from the at least a first phase according to the default memory standard to generate the lookup table LT.

[0027] ​For example, the host circuit 140 can exclude at least a second phase (e.g., phase 0 and phase 16) from the phases 0-16 according to the default memory standard and / or user input. The at least a second phase can be a timing that is not recommended for use in the default memory standard (or a dead zone), or can be a timing that failed a test (or actually failed in operation) in other embedded memory circuits. In this way, the host circuit 140 can know that the embedded memory circuit 120 can select a particular phase (e.g., phase 8, which is the center setting shown in the above table) from the phases 1-15 to generate the lookup table LT. In some embodiments, the particular phase can be (but is not limited to) a middle phase in the at least a first phase.

[0028] In some embodiments, the center setting described above can be adjusted according to actual application and / or other design considerations, and thus the center setting in the above table is not limited to a middle phase in the at least a first phase. In some embodiments, for a particular instruction (e.g., but not limited to, a read instruction corresponding to a frequency of 200M), the embedded memory circuit 120 can perform an auto-tune mechanism to select a suitable phase, instead of using the corresponding phase according to the center setting in the lookup table LT.

[0029] In some embodiments, the host circuit 140 is also configured to determine, according to the default memory standard, a correspondence between a setup time of a particular signal generated by the embedded memory circuit 120 in response to each of a plurality of instructions and a plurality of phases (e.g., phases 0-31) to generate the lookup table LT. Similarly, in some embodiments, the host circuit 140 is configured to determine, according to the default memory standard, a correspondence between a hold time of the particular signal generated by the embedded memory circuit 120 in response to each of the plurality of instructions and the plurality of phases 0-31 to generate the lookup table LT. In some embodiments, the setup time is a period during which the particular signal is to be maintained before a transition edge of a clock signal having the corresponding phase occurs, and the hold time is a period during which the particular signal is to be maintained after a transition edge of the clock signal having the corresponding phase occurs.

[0030] For example, the specific signal can be a data signal written by the embedded memory circuit 120 in response to a write instruction executed in the HS400 mode. Since the clock frequency in the HS400 mode is 200 MHz (the data rate can be 400 MB / s), the interval between two consecutive phases of phase 0 to phase 31 is about 0.156 nanoseconds (ns) according to the period of the clock signal (i.e., 1 / 200M). According to the requirements for setup time and hold time in the default memory standard (e.g., at least 0.4 ns), the host circuit 140 can know that the sum of the setup time and the hold time needs at least the same total time as the interval of the seven phases (i.e., the standard requirement in Table 1). Furthermore, according to the test results of the embedded memory circuit 120, the embedded memory circuit 120 can execute the write instruction using the test clock signal CLK with any one of phase 6 to phase 13. Therefore, the host circuit 140 can select the middle phase 10 between phase 6 and phase 13 (i.e., the center setting in Table 1) as the specific phase used to execute the write instruction, so that the setup time margin is as close to the hold time margin as possible. For example, the setup time margin is the total time of the intervals of phase 6 to phase 9 (i.e., 4 phases in Table 1), and the hold time margin is the total time of the intervals of phase 11 to phase 13 (i.e., 3 phases in Table 1). In this way, in subsequent applications, the embedded memory circuit 120 can execute the write instruction using the clock signal with phase 10. Figure 4

[0031] The above example is explained by the test results of a single embedded memory circuit 120. It should be understood that in some embodiments, the host circuit 140 can generate the lookup table LT according to the intersection of the test results of a plurality of embedded memory circuits 120. In this way, the timing settings recorded in the lookup table LT can be applicable to memories produced by different manufacturers.

[0032] The descriptions of the operations of the timing scan test method 200 (or the memory test method 300) can refer to the above embodiments, and thus are not repeated here. The above operations are only examples, and are not limited to the order in the examples. Without departing from the operation modes and the scope of the embodiments of the present application, various operations under the timing scan test method 200 (or the memory test method 300) can be appropriately added, replaced, omitted, or executed in different orders. Alternatively, one or more operations under the timing scan test method 200 (or the memory test method 300) can be executed simultaneously or partially simultaneously.

[0033] ​In summary, the in-system memory system and the memory testing method in some embodiments of the present application can use a program in the kernel or the operating system operating through the in-system memory circuit to perform timing scan testing on the in-system memory circuit to determine a phase suitable for actual operation of the in-system memory circuit. In this way, in subsequent applications, the in-system memory circuit can operate using the appropriate phase.

[0034] Although the embodiments of the present application are described above, the embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application. Any such changes can be within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application should be determined by the scope of protection defined by the claims and the description.

[0035] Legend of reference signs

[0036] 100: in-system memory system

[0037] 120: in-system memory circuit

[0038] 140: master circuit

[0039] 142: processor circuit

[0040] 144: memory circuit

[0041] 146: clock generator circuit

[0042] 200: timing scan testing method

[0043] 300: memory testing method

[0044] CLK: test clock signal

[0045] LT: lookup table

[0046] S210, S220, S230, S240: operations

[0047] S310, S320, S330, S340, S350: operations

Claims

1. An embedded memory system, comprising: An embedded memory circuit for storing a lookup table; as well as A master control circuit is used to test the embedded memory circuit using a test clock signal with multiple phases and multiple instructions of a program of the embedded memory circuit, and to record a correspondence between each instruction and the phase to generate the lookup table. The program is a startup program, which is a program executed by a kernel or an operating system running through the embedded memory circuit when the system is powered on.

2. The embedded memory system according to claim 1, characterized in that, The main control circuit generates the lookup table according to the JEDEC (Joint Electron Device Engineering Council) memory standard.

3. The embedded memory system according to claim 1, characterized in that, The instructions include multiple read or write instructions executed at different clock frequencies.

4. The embedded memory system according to claim 1, characterized in that, The embedded memory circuit is used to sequentially execute a first instruction among the instructions using the phase to generate a test result, and the master control circuit is used to confirm, based on the test result, that the embedded memory circuit has correctly executed the first instruction using at least one first phase among the phases.

5. The embedded memory system according to claim 4, characterized in that, The master control circuit is also used to select a specific phase from the at least one first phase according to a default memory standard to generate the lookup table.

6. The embedded memory system according to claim 5, characterized in that, The master control circuit is also used to exclude at least one second phase from the at least one first phase according to the default memory standard.

7. The embedded memory system according to claim 5, characterized in that, The master control circuit is also used to confirm, according to the default memory standard, a correspondence between the setup time of a signal generated by the embedded memory circuit in response to the first instruction and the phase, so as to generate the lookup table.

8. The embedded memory system according to claim 5, characterized in that, The master control circuit is also used to confirm, according to the default memory standard, a correspondence between a hold time and the phase of a signal generated by the embedded memory circuit in response to the first instruction, so as to generate the lookup table.

9. The embedded memory system according to claim 5, characterized in that, The specific phase is an intermediate phase among the at least one first phase.

10. A memory testing method, comprising: An embedded memory circuit is tested using a test clock signal with multiple phases and multiple instructions of a program. as well as A lookup table is generated by recording a correspondence between each instruction and the phase. The embedded memory circuit is used to select a specific phase in the phase that corresponds to a first instruction in the instructions according to the lookup table, so as to execute the first instruction. The program is a startup program, which is a program executed by a kernel or an operating system running through the embedded memory circuit when the system is powered on.

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