Semiconductor structure and method of forming the same
By setting active devices in the adapter board to realize the electrical connection between the logic chip and the memory chip, the problem of high difficulty in logic chip architecture design is solved, and simplified integration of chip stacking is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2022-04-12
- Publication Date
- 2026-06-02
AI Technical Summary
In existing three-dimensional heterogeneous integration design methods, the stacking method of logic chips and memory chips has a significant impact on the architectural design difficulty and cycle of logic chips, leading to increased design difficulty.
By setting active devices in the adapter board, the first chip and the second chip are electrically connected. The active devices in the adapter board are used to integrate the functions after the chips are connected. The length and width of the adapter board are the same as the memory chip to facilitate connection.
This reduces the design difficulty of chip stacking, allowing the first and second chips to be stacked together without significant changes in design and size, thus reducing the complexity of chip stacking integration.
Smart Images
Figure CN114743951B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] Existing design methods for 3D heterogeneous integration include die-on-wafer (DoW) and wafer-on-wafer (WoW) stacking. A representative application is the stacking of DRAM dies and logic dies. This stacking method significantly alters the architecture, design, and physical implementation of the logic dies, substantially impacting the design complexity and timeline.
[0003] Therefore, it is necessary to optimize the chips and their stacking method. Summary of the Invention
[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the chip and the chip stacking method.
[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, including: a first chip; a second chip; and a connecting board located between the first chip and the second chip, wherein the connecting board is electrically connected to the first chip and the second chip, and the connecting board has an active device, which is used to realize the function after the first chip and the second chip are connected.
[0006] Optionally, the first chip may include a memory chip.
[0007] Optionally, the second chip includes a logic chip.
[0008] Optionally, the active device includes a distributed storage controller, which is a control center for the distributed allocation of storage chip resources by the logic chip.
[0009] Optionally, the length and width of the adapter board are the same as the length and width of the first chip.
[0010] Optionally, the first chip includes: a first substrate having opposing first and second surfaces; a first device layer located on the first surface of the first substrate, having a first device structure therein; and a first metal layer located on the first device layer, the first metal layer being electrically connected to the first device structure.
[0011] Optionally, the second chip includes: a second substrate having opposing third and fourth surfaces; a second device layer located on the third surface of the second substrate, the second device layer having a second device structure therein; a second connection layer penetrating the second device layer and the second substrate, the second substrate being electrically connected to the adapter board through the second connection layer exposed on the fourth surface; and a second metal layer located on the second device layer and the second connection layer, the second metal layer being electrically connected to the second device structure.
[0012] Optionally, the adapter board includes: a third substrate having opposing fifth and sixth surfaces; a third device layer located on the fifth surface of the third substrate, the third device layer having active devices therein; a third connection layer penetrating the third device layer and the third substrate, the third substrate being electrically connected to a first metal layer of the first chip through the third connection layer exposed on the sixth surface; and a third metal layer located on the third device layer and the third connection layer, the third metal layer being electrically connected to a second connection layer of the second chip.
[0013] Optionally, it may also include a weld layer located on the surface of the second metal layer.
[0014] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a first chip; providing a second chip; providing an adapter plate having active devices therein; electrically connecting the adapter plate to the first chip and the second chip respectively, wherein the active devices are used to realize the functions of the first chip and the second chip after connection.
[0015] Optionally, the first chip may include a memory chip.
[0016] Optionally, the second chip includes a logic chip.
[0017] Optionally, the active device includes a distributed storage controller, which is a control center for the distributed allocation of storage chip resources by the logic chip.
[0018] Optionally, the length and width of the adapter board are the same as the length and width of the first chip.
[0019] Optionally, the first chip includes: a first substrate having opposing first and second surfaces; a first device layer located on the first surface of the first substrate, having a first device structure therein; and a first metal layer located on the first device layer, the first metal layer being electrically connected to the first device structure.
[0020] Optionally, the second chip includes: a second substrate having opposing third and fourth surfaces; a second device layer located on the third surface of the second substrate, the second device layer having a second device structure therein; a second connection layer penetrating the second device layer and the second substrate, the second substrate being electrically connected to the adapter board through the second connection layer exposed on the fourth surface; and a second metal layer located on the second device layer and the second connection layer, the second metal layer being electrically connected to the second device structure.
[0021] Optionally, the adapter board includes: a third substrate having opposing fifth and sixth surfaces; a third device layer located on the fifth surface of the third substrate, the third device layer having active devices therein; a third connection layer penetrating the third device layer and the third substrate, the third substrate being electrically connected to a first metal layer of the first chip through the third connection layer exposed on the sixth surface; and a third metal layer located on the third device layer and the third connection layer, the third metal layer being electrically connected to a second connection layer of the second chip.
[0022] Optionally, it may also include: forming a weld layer on the surface of the second metal layer.
[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0024] The technical solution of this invention electrically connects the first chip and the second chip via an adapter board. The adapter board contains active devices that enable the functionality of the connected first and second chips. By integrating the functionality of connecting the first and second chips into the adapter board, the design and dimensions of the first and second chips can be stacked together without significant changes, reducing the design complexity of the first and second chips and decreasing the difficulty of chip stacking and integration.
[0025] Furthermore, the first chip includes a memory chip, and the second chip includes a logic chip. The length and width of the adapter board are the same as those of the first chip. This allows the adapter board to maintain consistency with the wiring layout of the memory chip, facilitating the connection between the adapter board and the memory chip. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment;
[0027] Figure 2 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation
[0028] As described in the background section, there is a need to optimize the chips and their stacking methods. This will now be analyzed and explained in conjunction with specific embodiments.
[0029] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment.
[0030] Please refer to Figure 1 The semiconductor structure includes: a first chip, the first chip including: a first substrate 100 having opposing first and second surfaces; a first device layer 101 located on the first surface of the first substrate 100, the first device layer 101 having a first device structure therein; a first metal layer 102 located on the first device layer 101; and a second chip electrically connected to the first chip, the second chip including: a second substrate 104 having opposing third and fourth surfaces; a second device layer 105 located on the third surface of the second substrate 104, the second device layer 105 having a second device structure therein; a second connection layer 107 penetrating the second device layer 105 and the second substrate 104; a second metal layer 106 located on the second device layer 105 and the second connection layer 107, the second metal layer 106 being electrically connected to the second device structure; and a bonding layer 103 located between the first chip and the second chip, the first metal layer 102 of the first chip and the second metal layer 106 of the second chip being electrically connected to the bonding layer 103 respectively.
[0031] In the semiconductor structure, the first chip is a memory chip, and the second chip is a logic chip. When stacking the first and second chips, the architecture design of the logic chip needs to be modified to leverage the high bandwidth and high storage capacity of the memory chip after electrical connection. On one hand, the dimensions of the logic chip and the memory chip need to be consistent so that their electrical connection positions correspond, reducing the connection flexibility of the logic chip. On the other hand, to utilize the high bandwidth and high storage capacity of the memory chip, additional components need to be added within the logic chip to achieve distributed memory scheduling of the memory chip, which increases the design complexity of the logic chip.
[0032] To address the aforementioned problems, the present invention provides a semiconductor structure and its formation method. A first chip and a second chip are electrically connected via an adapter board. The adapter board contains active devices that implement the functions of the connected first and second chips. By integrating the functionality of connecting the first and second chips into the adapter board, the design and dimensions of the first and second chips can be stacked together without significant changes, reducing the design complexity of the first and second chips and simplifying chip stacking integration.
[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0034] Figure 2 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.
[0035] Please refer to Figure 2 , providing the first chip.
[0036] In this embodiment, the first chip includes a memory chip, which may include a DRAM chip, an SRAM chip, or a NAND FLASH chip, etc.
[0037] The first chip includes: a first substrate 200 having a first surface and a second surface opposite to each other; a first device layer 201 located on the first surface of the first substrate 200, having a first device structure (not shown); and a first metal layer 202 located on the first device layer 201, the first metal layer 202 being electrically connected to the first device structure.
[0038] In this embodiment, the material of the first substrate 200 is silicon.
[0039] In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0040] The material of the first metal layer 202 includes metals, including one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.
[0041] Please continue to refer to this. Figure 2 Provide a second chip.
[0042] In this embodiment, the second chip includes a logic chip.
[0043] The second chip includes: a second substrate 400 having opposing third and fourth surfaces; a second device layer 401 located on the third surface of the second substrate 400, the second device layer 401 having a second device structure (not shown); a second connection layer 403 penetrating the second device layer 401 and the second substrate 400; and a second metal layer 402 located on the second device layer 401 and the second connection layer 403, the second metal layer 402 being electrically connected to the second device structure.
[0044] In this embodiment, the material of the second substrate 400 is silicon.
[0045] In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0046] The material of the second metal layer 402 includes metals, including one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.
[0047] Please continue to refer to this. Figure 2 An adapter board is provided, which contains active devices (not shown).
[0048] The adapter board is used to electrically connect the first chip and the second chip.
[0049] In this embodiment, the first chip includes a memory chip, the second chip includes a logic chip, and the active device includes a distributed storage controller, which serves as the control center for the distributed allocation of memory chip resources by the logic chip. After the first chip and the second chip are electrically connected, the distributed storage controller is required to perform distributed control of the memory chip.
[0050] The adapter plate includes: a third substrate 300 having opposing fifth and sixth surfaces; a third device layer 301 located on the fifth surface of the third substrate 300, the third device layer 301 having an active device (not shown); a third connection layer 303 penetrating the third device layer 301 and the third substrate 300; and a third metal layer 302 located on the third device layer 301 and the third connection layer 303.
[0051] In this embodiment, the material of the third substrate 300 includes a PCB.
[0052] The material of the third metal layer 302 includes metals, including one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.
[0053] In this embodiment, the length and width of the adapter board are the same as those of the first chip. This ensures that the wiring layout of the adapter board and the memory chip are consistent, facilitating connection.
[0054] Please continue to refer to this. Figure 2 The adapter board is electrically connected to the first chip and the second chip respectively, and the active device is used to realize the function after the first chip and the second chip are connected.
[0055] In this embodiment, the second chip is electrically connected to the third metal layer 302 of the adapter plate through the second connection layer 403 exposed on the fourth side of the second substrate 400; the third substrate 300 is electrically connected to the first metal layer 202 of the first chip through the third connection layer 303 exposed on the sixth side.
[0056] The method for electrically connecting the adapter plate to the first chip and the second chip respectively includes: bonding the third connection layer 303 exposed on the sixth side of the third substrate 300 to the first metal layer 202 of the first chip; after bonding the third connection layer 303 exposed on the sixth side of the third substrate 300 to the first metal layer 202 of the first chip, bonding the second connection layer 403 exposed on the fourth side of the second substrate 400 to the third metal layer 302 of the adapter plate.
[0057] In this embodiment, after the adapter board is electrically connected to the first chip and the second chip respectively, it further includes: forming a welding layer 405 located on the surface of the second metal layer 402.
[0058] The weld layer 405 is used for subsequent electrical connection to external circuits.
[0059] Thus, the semiconductor structure formed integrates the function of connecting the first chip and the second chip into the adapter board, so that the design and size of the first chip and the second chip can be stacked together without making significant changes, thereby reducing the design difficulty of the first chip and the second chip and reducing the difficulty of chip stacking and integration.
[0060] Accordingly, the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 2 ,include:
[0061] First chip;
[0062] Second chip;
[0063] An adapter board is located between a first chip and a second chip, the adapter board is electrically connected to the first chip and the second chip, and the adapter board has active devices, the active devices are used to realize the functions after the first chip and the second chip are connected.
[0064] In this embodiment, the first chip includes a memory chip.
[0065] In this embodiment, the second chip includes a logic chip.
[0066] In this embodiment, the active device includes a distributed storage controller, which is a control center for the distributed allocation of storage chip resources by the logic chip.
[0067] In this embodiment, the length and width of the adapter board are the same as the length and width of the first chip.
[0068] In this embodiment, the first chip includes: a first substrate 200 having a first surface and a second surface opposite to each other; a first device layer 201 located on the first surface of the first substrate 200, having a first device structure (not shown) within the first device layer 201; and a first metal layer 202 located on the first device layer 201, the first metal layer 202 being electrically connected to the first device structure.
[0069] In this embodiment, a second substrate 400 has opposing third and fourth surfaces; a second device layer 401 is located on the third surface of the second substrate 400, and a second device structure (not shown) is located within the second device layer 401; a second connection layer 403 penetrates the second device layer 401 and the second substrate 400, and the second substrate 400 is electrically connected to the adapter plate through the second connection layer 403 exposed on the fourth surface; a second metal layer 402 is located on the second device layer 401 and the second connection layer 403, and the second metal layer 402 is electrically connected to the second device structure.
[0070] In this embodiment, the adapter board includes: a third substrate 300 having opposing fifth and sixth surfaces; a third device layer 301 located on the fifth surface of the third substrate 300, the third device layer 301 having an active device (not shown); a third connection layer 303 penetrating the third device layer 301 and the third substrate 300, the third substrate 300 being electrically connected to the first metal layer 202 of the first chip through the third connection layer 303 exposed on the sixth surface; and a third metal layer 302 located on the third device layer 301 and the third connection layer 303, the third metal layer 302 being electrically connected to the second connection layer 403 of the second chip.
[0071] In this embodiment, a welding layer 405 located on the surface of the second metal layer 403 is also included.
[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: A first chip, the first chip comprising: a first substrate having opposing first and second surfaces; a first metal layer located on the first surface of the first substrate, the first chip comprising a memory chip; The second chip has a length and width that are different from those of the first chip. The second chip includes: a second substrate having opposing third and fourth surfaces; a second interconnect layer penetrating the second substrate, the fourth surface exposing the second interconnect layer; and a second metal layer located on the third surface of the second substrate. The second chip includes a logic chip. A connector board is located between a first chip and a second chip, electrically connecting the first chip and the second chip. The length and width of the connector board are the same as those of the first chip. The connector board contains active devices for implementing the functions of the first chip and the second chip after connection. The active devices include a distributed storage controller, which is a control center for the distributed allocation of storage chip resources by the logic chip. The connector board includes: a third substrate having opposing fifth and sixth surfaces; a third connection layer penetrating the third substrate, the sixth surface exposing the third connection layer, the third connection layer being electrically connected to a first metal layer of the first chip; and a third metal layer located on the fifth surface of the third substrate, the third metal layer being electrically connected to a second connection layer of the second chip.
2. The semiconductor structure as described in claim 1, characterized in that, The first chip further includes: a first device layer located on a first surface of a first substrate, the first device layer having a first device structure; and a first metal layer located on the first device layer, the first metal layer being electrically connected to the first device structure.
3. The semiconductor structure as described in claim 2, characterized in that, The second chip further includes: a second device layer located on the third surface of the second substrate, the second device layer having a second device structure; a second connection layer penetrating the second device layer and the second substrate, the second substrate being electrically connected to the adapter board through the second connection layer exposed on the fourth surface; and a second metal layer located on the second device layer and the second connection layer, the second metal layer being electrically connected to the second device structure.
4. The semiconductor structure as described in claim 3, characterized in that, The adapter board further includes: a third device layer located on the fifth surface of the third substrate, wherein the third device layer has active devices; a third connection layer penetrating the third device layer and the third substrate; and a third metal layer located on the third device layer and the third connection layer.
5. The semiconductor structure as described in claim 3, characterized in that, Also includes: The weld layer located on the surface of the second metal layer.
6. A method for forming a semiconductor structure, characterized in that, include: A first chip is provided, the first chip comprising: a first substrate having opposing first and second surfaces; and a first metal layer located on the first surface of the first substrate, the first chip comprising a memory chip; A second chip is provided, the length and width of which are different from those of the first chip. The second chip includes: a second substrate having opposing third and fourth surfaces; a second interconnect layer penetrating the second substrate, the fourth surface exposing the second interconnect layer; and a second metal layer located on the third surface of the second substrate. The second chip includes a logic chip. An adapter board is provided, the length and width of which are the same as the length and width of the first chip. The adapter board contains active devices, including a distributed memory controller, which is a control center for the distributed allocation of memory chip resources by the logic chip. The adapter board includes: a third substrate having opposing fifth and sixth surfaces; a third connection layer penetrating the third substrate, the sixth surface exposing the third connection layer; and a third metal layer located on the fifth surface of the third substrate. The adapter board is electrically connected to the first chip and the second chip respectively. The third connection layer is electrically connected to the first metal layer of the first chip and to the second connection layer of the second chip. The active device is used to realize the function after the first chip and the second chip are connected.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first chip further includes: a first device layer located on a first surface of a first substrate, the first device layer having a first device structure; and a first metal layer located on the first device layer, the first metal layer being electrically connected to the first device structure.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The second chip further includes: a second device layer located on the third surface of the second substrate, the second device layer having a second device structure; a second connection layer penetrating the second device layer and the second substrate, the second substrate being electrically connected to the adapter board through the second connection layer exposed on the fourth surface; and a second metal layer located on the second device layer and the second connection layer, the second metal layer being electrically connected to the second device structure.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The adapter board further includes: a third device layer located on the fifth surface of the third substrate, wherein the third device layer has active devices; a third connection layer penetrating the third device layer and the third substrate; and a third metal layer located on the third device layer and the third connection layer.
10. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: A weld layer is formed on the surface of the second metal layer.