Semiconductor device and method for manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer to form a gate stack; removing portions of the oxide layer on first and second regions of the substrate; forming first and second select gate oxide structures on the first and second regions of the substrate, respectively, and forming tunneling oxide structures on both sides of the gate stack; forming select gates on sides of the tunneling oxide structures opposite the gate stack; etching the gate stack to form a first opening; forming a source region in a portion of the substrate below the first opening; and forming a drain region in the substrate on a side of the select gate opposite the first opening.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In electronic devices, memory is needed to read and store data. Therefore, as the demand for electronic devices continues to grow, the requirements for memory technology are also getting higher and higher.

[0003] Flash memory is a non-volatile computer storage medium that is electrically erasable and reprogrammable, retaining information even after the power is turned off. Flash memory is easy to use, offers read and write flexibility, fast access speeds, and maintains information after a power outage. Consequently, flash memory technology is developing rapidly.

[0004] Flash memory includes an array of addressable memory cells, wherein each memory cell includes a floating gate transistor for storing corresponding information.Therefore, it is desirable to improve methods of manufacturing flash memory, and particularly memory cells in flash memory. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer to form a gate stack consisting of the remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer; removing portions of the oxide layer on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack; forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, and, A first tunneling oxide structure and a second tunneling oxide structure are formed on both sides of the body, respectively; a first selection gate is formed on a side of the first tunneling oxide structure opposite to the gate stack, and a second selection gate is formed on a side of the second tunneling oxide structure opposite to the gate stack; the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remaining portion of the floating gate layer; a source region is formed in a portion of the substrate located below the first opening; and a first drain region is formed in the substrate on a side of the first selection gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second selection gate opposite to the first opening.

[0006] According to some embodiments of the present disclosure, a semiconductor device is provided. The semiconductor device is manufactured by the method described in the present disclosure.

[0007] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0010] Figures 2A-2H is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0011] Figures 3A-3O is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0012] Figures 4A-4B is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 5 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 6 is a schematic cross-sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 7 is a schematic cross-sectional structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 8 is a circuit diagram of a memory cell array according to some embodiments of the present disclosure;

[0017] Figures 9A-9B is a top plan view of a memory cell array according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed below may be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0019] Spatially relative terms such as "below," "beneath," "lower," "beneath," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "beneath" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" may encompass both orientations of "above" and "beneath." Terms such as "before" or "before" and "after" or "followed by" may similarly be used, for example, to indicate the order in which light passes through the elements. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0020] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts when used in this specification, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0021] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0022] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0024] As used herein, the term "substrate" may refer to a substrate of a sawed wafer, or may refer to a substrate of an unsawed wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict.

[0025] In the prior art, common types of flash memory cells include stacked gate memory cells and split gate memory cells. Compared with stacked gate memory cells, split gate memory cells have technical advantages such as lower power consumption and higher injection efficiency. For a flash memory with a split gate memory cell, the present disclosure provides a method for manufacturing a semiconductor device, comprising: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer to form a gate stack consisting of the remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer; removing portions of the oxide layer on the first and second regions of the substrate, wherein the first and second regions are located on both sides of the gate stack; forming a first selection gate oxide structure and a second selection gate oxide structure on the first and second regions of the substrate, respectively, and, A first tunneling oxide structure and a second tunneling oxide structure are formed on both sides of the gate stack, respectively; a first selection gate is formed on a side of the first tunneling oxide structure opposite to the gate stack, and a second selection gate is formed on a side of the second tunneling oxide structure opposite to the gate stack; the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remaining portion of the floating gate layer; a source region is formed in a portion of the substrate located below the first opening; and a first drain region is formed in the substrate on a side of the first selection gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second selection gate opposite to the first opening.

[0026] Figure 1 is a schematic flowchart of a method 100 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0027] In step S101 , an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer are sequentially formed on a substrate.

[0028] According to some embodiments, the manufacturing method 100 further includes: forming shallow trench isolation in the substrate before forming the oxide layer on the substrate. According to some embodiments, the manufacturing method 100 further includes: implanting memory cell wells in the substrate before forming the oxide layer on the substrate.

[0029] According to some embodiments, a process of forming shallow trench isolation may include but is not limited to the following steps: forming a liner oxide, depositing silicon nitride, exposing an active area, etching shallow insulating trenches, filling shallow insulating trenches, planarizing shallow insulating trenches, and removing silicon nitride.

[0030] According to some embodiments, step S101 includes: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a dielectric layer on the floating gate layer; forming a control gate layer on the dielectric layer; and forming a hard mask layer on the control gate layer.

[0031] According to some embodiments, an oxide layer is grown on the upper surface of the substrate; a floating gate polysilicon is deposited on the upper surface of the oxide layer, and the floating gate polysilicon is planarized to form a floating gate layer; a dielectric material (e.g., an ONO (oxygen-nitrogen-oxygen) material) is deposited on the upper surface of the floating gate polysilicon to form a dielectric layer; a control gate polysilicon is deposited on the upper surface of the dielectric layer to form a control gate layer; and a hard mask material (e.g., a silicon nitride material) is deposited on the control gate layer to form a hard mask layer.

[0032] Figure 2A FIG shows a cross-sectional view of an exemplary structure formed after step S101. Figure 2A As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210 , an oxide layer 220 , a floating gate layer 230 , a dielectric layer 240 , a control gate layer 250 , and a hard mask layer 260 .

[0033] At step S102 , the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer are etched to form a gate stack consisting of the remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer.

[0034] According to some embodiments, first, a photolithography process is performed on the upper surface of the hard mask layer to form a photoresist pattern; then, the hard mask layer, the control gate layer and the dielectric layer are etched using the formed photoresist pattern as a mask; then, the floating gate layer is continuously etched.

[0035] According to some embodiments, after etching the hard mask layer, the control gate layer, and the dielectric layer, control gate spacers are formed on both sides of the remaining portions of the hard mask layer, the control gate layer, and the dielectric layer, for example, a control gate oxide (e.g., silicon oxide) is deposited on both sides of the remaining portions of the hard mask layer, the control gate layer, and the dielectric layer, and the deposited control gate oxide is etched to form the control gate spacers.

[0036] Figure 2B FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S102. Figure 2B As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210, an oxide layer 220 and a gate stack 270, wherein the gate stack 270 includes, from bottom to top, a floating gate layer 230, a dielectric layer 240, a control gate layer 250 and the remaining portion of the hard mask layer 260.

[0037] In step S103 , portions of the oxide layer on the first region and the second region of the substrate are removed, wherein the first region and the second region are located on both sides of the gate stack.

[0038] According to some embodiments, portions of the oxide layer on the first and second regions of the substrate are removed through steps such as cleaning, photolithography, and etching, and a substrate oxide structure located on the gate stack is formed.

[0039] Figure 2C FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S103. Figure 2C As shown, the semiconductor structure 200 includes, from bottom to top, a substrate 210, a substrate oxide structure 221 and a gate stack 270, wherein the gate stack 270 includes, from bottom to top, a floating gate layer 230, a dielectric layer 240, a control gate layer 250 and the remaining portion of the hard mask layer 260.

[0040] In step S104 , a first selection gate oxide structure and a second selection gate oxide structure are formed on the first region and the second region of the substrate, respectively, and a first tunneling oxide structure and a second tunneling oxide structure are formed on both sides of the gate stack, respectively.

[0041] According to some embodiments, a first selection gate oxide structure and a second selection gate oxide structure are respectively formed on a first region and a second region of a substrate, and a first tunneling oxide structure and a second tunneling oxide structure are respectively formed on both sides of a gate stack, including: depositing a second gate oxide film on the first region and the second region of the substrate, and on the side and upper surface of the gate stack to form a first selection gate oxide structure and a second selection gate oxide structure; and removing portions of the first gate oxide film and the second gate oxide film on the upper surface of the gate stack to form a first tunneling oxide structure and a second tunneling oxide structure.

[0042] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes, before depositing the second gate oxide film on the first and second regions of the substrate, and on the side and upper surface of the gate stack: depositing the first gate oxide film on the first and second regions of the substrate, and on the high-voltage tube region, and on the side and upper surface of the gate stack; and removing portions of the first gate oxide film on the first and second regions of the substrate, and on the upper surface and side of the gate stack, and depositing the second gate oxide film on the first and second regions of the substrate, and on the side and upper surface of the gate stack includes: depositing the second gate oxide film on the first and second regions of the substrate, and on the side and upper surface of the gate stack. In the embodiments described in the present disclosure, by depositing the oxide film twice and removing excess oxide during the two depositions, a high-voltage tube oxide structure having a thickness different from that of the selected gate oxide structure is formed on the high-voltage tube region, so as to facilitate the subsequent formation of a corresponding high-voltage logic device (e.g., a high-voltage device powered by 11V) on the high-voltage tube region.

[0043] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes, before depositing the second gate oxide film on the first and second regions of the substrate, and on the side and upper surface of the gate stack: depositing a first gate oxide film on the first and second regions of the substrate, and on the side and upper surface of the gate stack; and removing portions of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack, and removing a portion of the first gate oxide film on the side of the gate stack. According to some embodiments, the first gate oxide film is etched (e.g., dry etching and wet etching) to retain a portion of the first gate oxide film on the sidewalls of the gate stack. According to some embodiments, after etching the first gate oxide film, a high-temperature rapid thermal process is performed to enhance the quality of the oxide on the sidewalls.

[0044] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes, before depositing the second gate oxide film on the first and second regions of the substrate and the side and upper surfaces of the gate stack: depositing a first gate oxide film on the first and second regions of the substrate and the side and upper surfaces of the gate stack; removing portions of the first gate oxide film on the first and second regions of the substrate and the upper surface and side surfaces of the gate stack; and forming a sidewall oxide structure on the side surfaces of the gate stack. According to some embodiments, the sidewall oxide structure is formed on the side surfaces of the gate stack by oxidizing polysilicon.

[0045] According to the embodiments described above, by retaining or additionally forming an oxide structure on the side of the gate stack before depositing the second gate oxide film on the first and second regions of the substrate, as well as on the side and upper surface of the gate stack, the thickness of the selection gate oxide structure and the tunneling oxide structure can be made different. For example, a thicker tunneling oxide structure is beneficial for floating gate data storage, and a thinner selection gate oxide structure is beneficial for improving the performance of the memory device (for example, providing a larger read current).

[0046] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure also includes, before removing portions of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack: performing selective gate channel ion (e.g., boron or BF2) implantation in the first and second regions of the substrate.

[0047] According to some embodiments, performing select gate channel ion implantation in the first and second regions of the substrate includes: performing select gate channel photolithography to form a photoresist pattern to protect regions where ion implantation is not required; and performing select gate channel ion implantation using the formed photoresist pattern as a mask.

[0048] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes, after depositing a second gate oxide film on the first region, the second region and the high-voltage tube region of the substrate, and on the side and upper surface of the gate stack: performing logic well implantation in the substrate; forming a logic IO gate oxide structure on the substrate; and forming a logic core gate oxide structure on the substrate.

[0049] Figure 2D FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S104. Figure 2DAs shown, in addition to the substrate 210, the substrate oxide structure 221, and the gate stack 270, the semiconductor structure 200 further includes a first select gate oxide structure 222a located on a first region on the left side of the gate stack 270, a first tunnel oxide structure 271a located on the left side of the gate stack 270, a second select gate oxide structure 222b located on a second region on the right side of the gate stack 270, and a second tunnel oxide structure 271b located on the right side of the gate stack 270. It should be understood that although the first select gate oxide structure 222a and the first tunnel oxide structure 271a are shown as two separate parts, and the second select gate oxide structure 222b and the second tunnel oxide structure 271b are shown as two separate parts, the first select gate oxide structure 222a and the first tunnel oxide structure 271a may actually be continuous oxides having different thicknesses, and the second select gate oxide structure 222b and the second tunnel oxide structure 271b may actually be continuous oxides having different thicknesses, for example, formed by the two oxide film deposition steps described above.

[0050] At step S105 , a first select gate is formed on a side of the first tunneling oxide structure opposite to the gate stack, and a second select gate is formed on a side of the second tunneling oxide structure opposite to the gate stack.

[0051] According to some embodiments, forming a first selection gate on a side of the first tunneling oxide structure opposite to the gate stack, and forming a second selection gate on a side of the second tunneling oxide structure opposite to the gate stack includes: depositing selection gate polysilicon on the first selection gate oxide structure and the second selection gate oxide structure, and on the gate stack; and removing portion of the deposited selection gate polysilicon to form the first selection gate and the second selection gate.

[0052] According to some embodiments, the deposited select gate polysilicon has the same coverage on the first select gate oxide structure, the second select gate oxide structure, and the surface of the gate stack, so that the deposited select gate polysilicon presents a "convex" shape. For example, as described below with reference to Figure 3I Described in detail.

[0053] According to some embodiments, removing portions of the deposited selection gate polysilicon to form a first selection gate and a second selection gate includes: planarizing the deposited selection gate polysilicon; etching the planarized selection gate polysilicon to form a first polysilicon structure and a second polysilicon structure located on a first region and a second region of the substrate, respectively; and etching the first polysilicon structure and the second polysilicon structure to form a first selection gate and a second selection gate, respectively.

[0054] According to some embodiments, the deposited select gate polysilicon is planarized to remove the select gate polysilicon deposited above the gate stack. According to some embodiments, during the planarization of the deposited select gate polysilicon, oxide deposited above the gate stack in a previous step may also be removed.

[0055] According to some embodiments, etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on a first region and a second region of the substrate includes etching shoulders of the "L"-shaped select gate polysilicon on both sides of the gate stack to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate in a rectangular shape, so as to facilitate subsequent etching using a photoresist or a hard mask spacer as a mask to form the first select gate and the second select gate. For example, as described below with reference to Figure 3J Described in detail.

[0056] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; etching the first polysilicon structure and the second polysilicon structure using the photoresist pattern formed by the first photolithography process as a mask to form the first select gate and the second select gate, respectively; and removing the photoresist pattern formed by the first photolithography process. For example, as described below with reference to Figures 3K-3L Described in detail.

[0057] According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes: forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure; and etching the first polysilicon structure and the second polysilicon structure using the first hard mask spacer and the second hard mask spacer as masks to form the first select gate and the second select gate, respectively. For example, as described below with reference to Figures 4A-4B Described in detail.

[0058] According to some embodiments, removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate includes self-aligned etching of the deposited select gate polysilicon to form the first select gate and the second select gate, respectively. For example, as described below with reference to Figure 5 Described in detail.

[0059] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure also includes: depositing logic gate polysilicon on the logic gate region of the substrate while depositing selection gate polysilicon on the first selection gate oxide structure and the second selection gate oxide structure and on the gate stack; and removing part of the deposited selection gate polysilicon to form the first selection gate and the second selection gate while removing part of the logic gate polysilicon to form the logic gate.

[0060] According to some other embodiments, logic gate polysilicon is deposited on the logic gate region of the substrate while select gate polysilicon is deposited on the first select gate oxide structure and the second select gate oxide structure and on the gate stack; and, in a processing step different from removing the portion of the deposited select gate polysilicon, a portion of the logic gate polysilicon is removed to form a logic gate.

[0061] Figure 2E FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S105. Figure 2E As shown, the semiconductor structure 200 includes, in addition to the substrate 210, the substrate oxide structure 221, the gate stack 270, the first selection gate oxide structure 222a, the first tunneling oxide structure 271a, the second selection gate oxide structure 222b and the second tunneling oxide structure 271b, a first selection gate 280a on the side of the first tunneling oxide structure 271a opposite to the gate stack 270, and a second selection gate 280b is formed on the side of the second tunneling oxide structure 271b opposite to the gate stack 270.

[0062] At step S106 , the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remaining portion of the floating gate layer.

[0063] According to some embodiments, etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remaining portion of the floating gate layer includes: performing source photolithography to form a photoresist pattern; and etching the gate stack using the formed photoresist pattern as a mask to form the first opening.

[0064] Figure 2F FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S106. Figure 2F As shown, Figure 2EIn contrast, the first opening 272 passes through the remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer, wherein the remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer include gate structures belonging to memory cells on both sides, namely, the gate structure located on the left side consisting of the first floating gate 230a, the first dielectric structure 240a, the first control gate 250a, and the first hard mask 260a, and the gate structure located on the right side consisting of the second floating gate 230b, the second dielectric structure 240b, the second control gate 250b, and the second hard mask 260b.

[0065] At step S107 , a source region is formed in a portion of the substrate below the first opening.

[0066] According to some embodiments, the source region is formed by source ion implantation (e.g., arsenic and phosphorus), thereby forming a graded junction in the substrate. That is, in the source region, the source ion doping concentration gradually decreases from the substrate oxide structure to the substrate, thereby improving the stress-bearing capability of the semiconductor device. In the embodiments described in the present disclosure, because the gate structures and oxide structures of the memory cells on both sides are formed first, and the source region implantation is performed later, the performance of the source region is avoided due to the thermal deposition step of forming the gate structure and oxide structure.

[0067] Figure 2G FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S107. Figure 2G As shown, Figure 2F In contrast, the semiconductor device 200 includes a source region 212 in the substrate 210 below the first opening 272 .

[0068] At step S108 , a first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

[0069] According to some embodiments, forming a first drain region in the substrate on a side of the first selection gate opposite to the first opening, and forming a second drain region in the substrate on a side of the second selection gate opposite to the first opening includes: performing lightly doped drain implantation in the substrate on a side of the first selection gate opposite to the first opening and in the substrate on a side of the second selection gate opposite to the first opening to form a first lightly doped drain region located on one side of the first selection gate and a second lightly doped drain region located on one side of the second selection gate; forming a first drain spacer on a side of the first selection gate opposite to the first opening, and forming a second drain spacer on a side of the second selection gate opposite to the first opening; forming a first source spacer on a side of the first selection gate facing the first opening, and forming a second source spacer on a side of the second selection gate facing the first opening; and performing heavily doped drain implantation in the substrate on a side of the first drain spacer opposite to the first opening and in the substrate on a side of the second drain spacer opposite to the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

[0070] Figure 2H FIG shows a cross-sectional view of an exemplary structure formed after steps S101 to S108. Figure 2H As shown, Figure 2G In contrast, the semiconductor device 200 includes a first drain region 211a formed in the substrate 210 on a side of the first selection gate 280a opposite the first opening 272 and a second drain region 211b formed in the substrate 210 on a side of the second selection gate 280b opposite the first opening 272.

[0071] According to some embodiments, the method for manufacturing a semiconductor device as described in the present disclosure further includes: forming a silicide structure on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

[0072] In existing semiconductor device manufacturing methods, an opening between two adjacent memory cells and a source region below the opening are first formed, and then a select gate is formed on one side of each memory cell. This results in excess select gate material being deposited in the opening between the two adjacent memory cells when the select gate material is deposited to form the select gate. In the semiconductor device manufacturing method disclosed herein, since select gates are first formed on both sides of the gate stack, and then an opening through the gate stack and a source region below the opening are formed, excess select gate material is not deposited in the opening as described above with reference to the existing manufacturing method. This reduces the number of steps for removing excess select gate material, lowering production costs. Furthermore, by avoiding depositing conductive polysilicon in more trench areas and removing the deposited polysilicon using methods such as dry etching, the process risks increased during etching and the probability of defects on the wafer surface after etching are reduced, thereby improving chip yield.

[0073] In addition, in existing semiconductor device manufacturing methods, since the source region located below the opening between two adjacent memory cells is first formed, and then deposition is performed to form the remaining structure of the memory cell, the deposition process performed after the source region is formed will affect the performance of the source region (for example, causing the source region to further expand), thereby placing high requirements on the process of forming the source region (that is, maintaining the desired performance after undergoing heat treatment in subsequent multiple process steps (for example, deposition). In the semiconductor device manufacturing method described in the present disclosure, since various deposition processes are performed before forming the source region, the formed source region is prevented from being affected by the subsequent deposition process, thereby reducing the process requirements for the source region.

[0074] Figures 3A-3O is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device 300 according to some embodiments of the present disclosure.

[0075] According to some embodiments, Figure 3A As shown, and reference Figure 2A Similar to the description, the semiconductor structure 300 includes, from bottom to top, a substrate 210 , an oxide layer 220 , a floating gate layer 230 , a dielectric layer 240 , a control gate layer 250 , and a hard mask layer 260 .

[0076] According to some embodiments, Figure 3B As shown, photoresist is coated on the upper surface of the hard mask layer 260 and photolithography is performed to form a photoresist pattern 290 . Then, the hard mask layer 260 , the control gate layer 250 and the dielectric layer 240 are etched using the photoresist pattern 290 as a mask.

[0077] According to some embodiments, Figure 3C As shown, remove Figure 3BThe photoresist pattern shown forms a first control gate spacer 273a and a second control gate spacer 273b on both sides of the hard mask layer 260, the control gate layer 250 and the remaining portion of the dielectric layer 240, for example, by depositing a control gate oxide and etching the deposited control gate oxide to form the control gate spacers.

[0078] According to some embodiments, Figure 3D As shown, the floating gate layer 230 is etched to form a gate stack including the floating gate layer 230 , the dielectric layer 240 , the control gate layer 250 , and the hard mask layer 260 .

[0079] According to some embodiments, Figure 3E As shown, portions of the oxide layer in the first and second regions of the substrate 210 (i.e., the regions on which the select gates are to be formed) and the high-voltage tube region are removed (e.g., by cleaning, photolithography, etching, etc.) to form a substrate oxide structure 221.

[0080] According to some embodiments, Figure 3F As shown, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210 , the high voltage tube region, and the upper surface of the hard mask layer 260 .

[0081] According to some embodiments, Figure 3G As shown, performing select gate channel ion implantation in the first and second regions of the substrate 210 includes: performing select gate channel photolithography to form a photoresist pattern to protect the region where ion implantation is not required; performing select gate channel ion implantation using the formed photoresist pattern as a mask; and then removing the portion of the first gate oxide film 291 located in the first and second regions, as well as the sidewalls and upper surface of the gate stack. It should be understood that, although not shown, the portion of the first gate oxide film 291 located in the high-voltage transistor region of the substrate 210 is retained for subsequent formation of an oxide structure corresponding to the high-voltage transistor region.

[0082] According to some embodiments, Figure 3H As shown, a second gate oxide film 292 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210, the high voltage tube region, and the upper surface of the hard mask layer 260. According to some embodiments, although Figure 3H Not shown, but a logic well implant may be performed in the substrate 210 , a logic IO gate oxide structure may be formed on the substrate 210 , and a logic core gate oxide structure may be formed on the substrate 210 .

[0083] According to some embodiments, Figure 3IAs shown, a selection gate silicide 280 is deposited on the second gate oxide film 292, wherein the selection gate silicide 280 has a substantially uniform coverage. Figure 3I Together with the select gate silicide 280 in the CMOS process, logic gate polysilicon for subsequent formation of logic gates is deposited.

[0084] According to some embodiments, Figure 3J As shown, the semiconductor structure 300 is planarized and polysilicon etched to remove a portion of the selection gate silicide 280 to form a first polysilicon structure 281a located on the first region and a second polysilicon structure 281b located on the second region, and to remove portions of the first gate oxide film 291 and the second gate oxide film 292 located on the hard mask layer 260.

[0085] According to some embodiments, Figure 3K As shown, the first polysilicon structure 281a and the second polysilicon structure 281b are subjected to a photolithography process; the photoresist pattern 293 formed by the photolithography process is used as a mask to etch the first polysilicon structure 281a and the second polysilicon structure 281b to form a first selection gate 280a and a second selection gate 280b respectively. According to some embodiments, Figure 3K The steps shown are taken together to form the logic gate.

[0086] According to some embodiments, Figure 3L As shown, the source region is photolithographically processed (eg, corresponding to Figure 3L The photoresist patterns 294a and 294b are shown and etched accordingly to form a first opening 272, and a source ion implantation is performed in a portion of the substrate 210 below the first opening 272 to form a source region 212. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, in addition to the N-type ion implantation, the source ion implantation may further include an appropriately increased P-type ion implantation to adjust the floating gate channel threshold voltage.

[0087] According to some embodiments, Figure 3M As shown, a lightly doped drain (LDD) implantation lithography is performed (eg, corresponding to Figure 3MA photoresist pattern 295 is formed in the substrate 210 on the side of the first select gate 280a opposite the first opening 272 and a lightly doped drain implant (e.g., arsenic) is performed in the substrate 210 on the side of the second select gate 280b opposite the first opening 272 to form a first lightly doped drain region 2111a on one side of the first select gate 280a and a second lightly doped drain region 2111b on one side of the second select gate 280b. According to some embodiments, after the lightly doped drain implant is performed, processes related to forming logic IO / core devices may be performed. According to some embodiments, after the lightly doped drain implant is performed, the photoresist pattern 295 may be removed.

[0088] According to some embodiments, Figure 3N As shown, first, a first drain spacer 275a is formed on a side of the first selection gate 280a opposite to the first opening 272, and a second drain spacer 275b is formed on a side of the second selection gate 280b opposite to the first opening 272, a first source spacer 274a is formed on a side of the first selection gate 280a facing the first opening 272, and a second source spacer 274b is formed on a side of the second selection gate 280b facing the first opening 272; then, a heavily doped drain implantation lithography process is performed (e.g., corresponding to the lithography process of FIG. 1 ). Figure 3N A photoresist pattern 296 is formed, and a heavily doped drain implant is performed in the substrate 210 on a side of the first drain spacer 275a opposite the first opening 272 and in the substrate 210 on a side of the second drain spacer 275b opposite the first opening 272 to form a first heavily doped drain region 2112a on one side of the first drain spacer 275a and a second heavily doped drain region 2112b on one side of the second drain spacer 275b. According to some embodiments, a baseline logic process may be performed after performing the heavily doped drain implant.

[0089] According to some embodiments, a silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region. Figure 3O As shown, silicide structures 223a-223e are formed on the first selection gate 280a, the first heavily doped drain region 2112a, the source region 212, the second selection gate 280b, and the second heavily doped drain region 2112b. Figure 3OAs shown, portions of the oxide layer 220 between the first source spacer 274a and the second source spacer 274b, and on the first lightly doped drain region 2111a, the first heavily doped drain region 2112a, the second lightly doped drain region 2111b and the second heavily doped drain region 2112b are removed, and a silicide structure 223c is formed on the substrate 210 exposed by the removal of the oxide layer 220.

[0090] According to some embodiments, Figure 3O In the semiconductor structure shown, since the gate stack is etched separately on the source side, an asymmetric control gate spacer can be formed only on one side of the control gate (i.e., there is no need to form a control gate spacer on the source side), thereby increasing the coupling capacitance ratio of the control gate to the floating gate, thereby increasing the efficiency of electron injection during write operations, or reducing the voltage value of the control gate while maintaining the same efficiency, thereby reducing the requirements for high-voltage tubes.

[0091] Figures 4A-4B is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device 400 according to some embodiments of the present disclosure.

[0092] According to some embodiments, Figure 3J After forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region, as shown in FIG. Figure 4A As shown, a first hard mask spacer 282a and a second hard mask spacer 282b are respectively formed on both sides of the semiconductor device 200, wherein the first hard mask spacer 282a is located on the first polysilicon structure 281a, and the second hard mask spacer 282b is located on the second polysilicon structure 281b, for example, by depositing a hard mask material and etching the hard mask material to form the first hard mask spacer 282a and the second hard mask spacer 282b.

[0093] According to some embodiments, Figure 4B As shown, the first and second hard mask spacers 282a and 282b are used as masks to etch the first and second polysilicon structures 281a and 281b to form the first and second select gates 280a and 280b, respectively.

[0094] According to some embodiments, in forming Figure 4B After the semiconductor structure 400 is shown, the above reference Figure 3L-3O The process steps are described to form a flash memory semiconductor device.

[0095] Figure 5 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0096] According to some embodiments, Figure 3I After forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region, as shown in FIG. Figure 5 As shown, the deposited select gate polysilicon is self-alignedly etched to form a first select gate 280a and a second select gate 280b, respectively.

[0097] According to some embodiments, in forming Figure 5 After the semiconductor structure 500 is formed, the above-mentioned steps may be performed. Figure 3L-3O The process steps are described to form a flash memory semiconductor device.

[0098] Figure 6 Schematic cross-sectional views of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0099] According to some embodiments, Figure 3F After forming the first gate oxide film 291 covering the semiconductor device 300, as shown in FIG. Figure 6 As shown, a select gate channel ion implantation is performed in the first and second regions of the substrate 210, including: performing select gate channel photolithography to form a photoresist pattern to protect the region where the ion implantation is not required; performing select gate channel ion implantation using the formed photoresist pattern as a mask; then removing the portion of the first gate oxide film 291 located in the first and second regions and on the upper surface of the gate stack, and removing a portion of the first gate oxide film 291 on the side of the gate stack to form sidewall oxide structures 291a and 291b on both sides of the gate spacer. According to some embodiments, the first gate oxide film 291 is etched (e.g., dry etching and wet etching) to retain a portion of the first gate oxide film 291 on the sidewalls of the gate stack. According to other embodiments, instead of partially removing the first gate oxide film 291 on the side of the gate stack, the first gate oxide film 291 on the side of the gate stack is first completely removed, and then a certain thickness of oxide is formed on the sidewalls of the floating gate by, for example, polysilicon oxidation.

[0100] According to some embodiments, in forming Figure 6 After the semiconductor structure 600 is shown, the above reference Figures 3H-3O The process steps are described to form a flash memory semiconductor device.

[0101] According to an embodiment of the present disclosure, a semiconductor device is further provided, which is manufactured by the method for manufacturing the semiconductor device according to the present disclosure.

[0102] Figure 7is a schematic cross-sectional structural diagram of a semiconductor device 700 according to some embodiments of the present disclosure.

[0103] According to some embodiments, the semiconductor device 700 includes a substrate 210, a substrate oxide structure 221 formed above the substrate 210, gate stacks 270a and 270b located on the substrate oxide structure 221, a first selection gate 280a, a second selection gate 280b, a first drain region 211a, a second drain region 211b and a source region 212 located in the substrate 210, wherein the first gate stack 270a includes a first floating gate 230a, a first dielectric structure 240a, a first control gate 250a and a first hard mask 260a, and the second gate stack 270b includes a second floating gate 230b, a second dielectric structure 240b, a second control gate 250b and a second hard mask 260b.

[0104] According to some embodiments, the semiconductor device 700 also includes a substrate gate oxide structure 221 located below the first gate stack 270a and the second gate stack 270b, a first tunneling oxide structure 271a located between the first selection gate 280a and the first gate stack 270a, a second tunneling oxide structure 271b located between the second selection gate 280b and the second gate stack 270b, a first selection gate oxide structure 222a located below the first selection gate 280a, and a second selection gate oxide structure 222b located below the second selection gate 280b.

[0105] According to some embodiments, semiconductor device 700 includes two memory cells sharing a source region 212. According to some embodiments, semiconductor device 700 includes a first programming channel 213a, a second programming channel 213b, and a first erasure channel 214a corresponding to the memory cell on the left, and a third programming channel 213c, a fourth programming channel 213d, and a second erasure channel 214b corresponding to the memory cell on the right. According to some embodiments, a first programming channel 213a extends from the first drain region 211a to the edge of the first floating gate 230a facing the first select gate 280a, a second programming channel 213b extends from the first drain region 211a to the source region 212, a first erase channel 214a extends from the first floating gate 230a to the first select gate 280a, a third programming channel 213c extends from the second drain region 211b to the edge of the second floating gate 230b facing the second select gate 280b, a fourth programming channel 213d extends from the second drain region 211b to the source region 212, and a second erase channel 214b extends from the second floating gate 230b to the second select gate 280b. The processes for programming, erasing, and reading the memory cells on the left and right are similar. The following uses the memory cell on the left as an example to illustrate programming, erasing, and reading operations.

[0106] According to some embodiments, when a programming operation is performed, a positive voltage higher than the threshold voltage (e.g., 1.0-1.6V) is applied to the first selection gate 280a, and a positive voltage (e.g., 4.5-7V) is applied to the source terminal (i.e., the source region 212) to provide a strong lateral electric field, and a negative current (e.g., 1 μA) is injected into the first drain region 211a. At this time, due to the electron source injection effect, a portion of hot electrons are injected into the first floating gate 230a through the first programming channel 213a, while a portion of hot electrons migrate to the source terminal through the second programming channel 213b.

[0107] According to some embodiments, when an erase operation is performed, a relatively high positive voltage (e.g., 7 to 11 V) is applied to the first selection gate 280 a and a relatively high negative voltage (e.g., −7 V to 11 V) is applied to the first control gate 250 a to form a voltage difference between the first selection gate 280 a and the first floating gate 230 a, while the first drain region 211 a and the source region 212 are both set to 0 V. At this time, due to the Fowler-Nordheim (FN) tunneling effect, electrons are pulled away from the first floating gate 230 a under the action of the voltage difference between the first selection gate 280 a and the first floating gate 230 a.

[0108] According to some embodiments, when performing a read operation, a positive voltage (e.g., 1.8V) is applied to the first selection gate 280a, a positive voltage (e.g., 1.8V) is applied to the first control gate 250a, a lower positive voltage (e.g., 0.6V) is applied to the first drain region 211a, and the source region 212 is set to 0V. At this time, the state of the memory cell is determined by the current value between the source terminal and the drain terminal.

[0109] Figure 8 is a circuit diagram of a memory cell array 800 according to some embodiments of the present disclosure. It should be understood that Figure 8 The numbers of memory cells, word lines, bit lines, source lines and erase lines are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve a larger or smaller scale memory cell array.

[0110] like Figure 8 As shown, the memory cell array 800 includes a plurality of memory cells (eg, Figure 8 Memory cell 810 shown). According to some embodiments, each memory cell includes a selection transistor and a floating transistor connected in series, e.g., Figure 8 The memory cell 810 includes a selection transistor 811 and a floating-gate transistor 812 , wherein the selection transistor 811 can select a memory cell with a fixed address for operation, and the floating-gate transistor 812 can store information.

[0111] According to some embodiments, each row of memory cells corresponds to a word line, e.g. Figure 8 In FIG, the memory cells in the upper row correspond to word line WLn-1, the memory cells in the lower row correspond to word line WLn, and each word line is connected to the gate of the selection transistor in the corresponding memory cell. According to some embodiments, each column of memory cells corresponds to a bit line, for example, Figure 8 , the memory cells in the left column correspond to the bit line BLn-1, the memory cells in the middle column correspond to the bit line BLn, and the memory cells in the right column correspond to the bit line BLn+1, and each bit line is connected to the drain of the selection transistor in the corresponding memory cell. According to some embodiments, the memory cells in two adjacent rows correspond to one source line, for example, Figure 8 In the memory cell array 800, the memory cells in the upper and lower rows correspond to source lines SL, and each source line is connected to the source of the floating gate transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector of the memory are electrically connected together. According to some embodiments, in the memory cell array 800, each row of memory cells corresponds to a control line, for example, Figure 8, the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the control gate of the floating transistor in the corresponding memory cell;

[0112] According to some embodiments, the drain of the select transistor in the memory cell corresponds to, for example Figure 7 The first drain region 211a in the semiconductor device 700 shown, the gate of the selection transistor in the memory cell corresponds to, for example, Figure 7 The first selection gate 280a in the semiconductor device 700 shown in FIG. 1 corresponds to the floating gate of the floating transistor in the memory cell. Figure 7 The first floating gate 230a in the semiconductor device 700 shown in FIG. 1 corresponds to the control gate of the floating transistor in the memory cell. Figure 7 The first control gate 250a of the semiconductor device 700 shown in FIG. 1 corresponds to the source of the floating transistor in the memory cell. Figure 7 The source region 212 in the semiconductor device 700 is shown.

[0113] Figures 9A-9B is a top plan view of a memory cell array according to some embodiments of the present disclosure. Figure 9A As shown, the memory cell array 900 includes a plurality of bit lines BLn-1, BLn, and BLn+1, a plurality of word lines WLn-1 and WLn, a plurality of floating gates FG1-FG6, and a source line SL.

[0114] According to some embodiments, each column of memory cells corresponds to the same bit line, e.g. Figure 9A As shown, the two memory cells in the left column both correspond to the bit line BLn-1. It should be understood that, although not shown, the bit line structures of the memory cells in the same column are electrically connected.

[0115] According to some embodiments, each row of memory cells corresponds to the same word line, e.g. Figure 9A As shown, the three memory cells in the upper row all correspond to word line WLn-1. Figure 9A As shown, each word line extends through multiple memory cells in the same row.

[0116] According to some embodiments, each row of memory cells corresponds to a control line, e.g. Figure 9A , the memory cells in the upper row correspond to the control line CGn-1, the memory cells in the lower row correspond to the control line CGn, and each control line is connected to the floating gate in the corresponding memory cell.

[0117] According to some embodiments, adjacent rows of memory cells correspond to the same source line, e.g. Figure 9A As shown, the six memory cells in the upper and lower rows all correspond to the source line SL. Figure 9A As shown, a source line SL extends through adjacent rows of memory cells in the substrate, wherein the source line connects source regions in a plurality of bit lines.

[0118] like Figure 9B The memory cell array 900 is shown with Figure 9A The difference of the memory cell array 900 shown is that instead of the source line SL extending through the multiple bit lines in the substrate, a corresponding tungsten plug is set on each bit line (for example, the corresponding tungsten plug Wn-1 of the bit line BLn-1), and the respective tungsten plugs are connected by metal lines to connect the source regions in the multiple bit lines.

[0119] Some exemplary aspects of the disclosure are described below.

[0120] Aspect 1. A method for manufacturing a semiconductor device, comprising:

[0121] forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer in sequence on the substrate;

[0122] etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer to form a gate stack consisting of remaining portions of the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer;

[0123] removing portions of the oxide layer on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack;

[0124] forming a first selection gate oxide structure and a second selection gate oxide structure on the first region and the second region of the substrate, respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack, respectively;

[0125] forming a first select gate on a side of the first tunneling oxide structure opposite the gate stack, and forming a second select gate on a side of the second tunneling oxide structure opposite the gate stack;

[0126] etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and a remaining portion of the floating gate layer;

[0127] forming a source region in a portion of the substrate below the first opening; and

[0128] A first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

[0129] Aspect 2. The method according to aspect 1, wherein forming a first selection gate oxide structure and a second selection gate oxide structure on the first region and the second region of the substrate, respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack, respectively, comprises:

[0130] Depositing a second gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack to form the first select gate oxide structure and the second select gate oxide structure; and

[0131] Portions of the first and second gate oxide films on the upper surface of the gate stack are removed to form the first and second tunneling oxide structures.

[0132] Aspect 3. The method according to aspect 2, further comprising, before depositing a second gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack:

[0133] Depositing a first gate oxide film on the first region and the second region of the substrate, and on the side surfaces and upper surface of the gate stack; and

[0134] Portions of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack are removed, and a portion of the first gate oxide film on the side surfaces of the gate stack is removed.

[0135] Aspect 4. The method according to aspect 2, further comprising, before depositing a second gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack:

[0136] Depositing a first gate oxide film on the first region and the second region of the substrate, and on the side surfaces and upper surface of the gate stack;

[0137] removing portions of the first gate oxide film on the first and second regions of the substrate, and on the upper surface and side surfaces of the gate stack; and

[0138] A sidewall oxide structure is formed on a side surface of the gate stack.

[0139] Aspect 5. The method according to aspect 2, further comprising, before depositing a second gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack:

[0140] Depositing a first gate oxide film on the first region, the second region, and the high-voltage tube region of the substrate, and on the side surfaces and upper surface of the gate stack; and

[0141] Removing portions of the first gate oxide film on the first region, the second region, the upper surface and the side surfaces of the gate stack of the substrate, and depositing a second gate oxide film on the first region and the second region of the substrate and the side surfaces and the upper surface of the gate stack of the substrate comprises:

[0142] A second gate oxide film is deposited on the first region, the second region, and the high-voltage tube region of the substrate, as well as on the side surfaces and the upper surface of the gate stack.

[0143] Aspect 6. The method according to aspect 5, further comprising, before removing the portion of the first gate oxide film on the first region and the second region of the substrate and on the upper surface of the gate stack:

[0144] Select gate channel ion implantation is performed in the first and second regions of the substrate.

[0145] Aspect 7. The method according to Aspect 5, further comprising, after depositing a second gate oxide film on the first region, the second region, and the high-voltage tube region of the substrate, and on the side surfaces and upper surface of the gate stack:

[0146] implanting a logic well in the substrate;

[0147] forming a logic IO gate oxide structure on the substrate; and

[0148] A logic core gate oxide structure is formed on the substrate.

[0149] Aspect 8. The method according to any one of aspects 1 to 7, wherein forming a first select gate on a side of the first tunneling oxide structure opposite to the gate stack, and forming a second select gate on a side of the second tunneling oxide structure opposite to the gate stack comprises:

[0150] depositing select gate polysilicon over the first select gate oxide structure and the second select gate oxide structure and over the gate stack; and

[0151] Portions of the deposited select gate polysilicon are removed to form the first select gate and the second select gate.

[0152] Aspect 9. The method according to aspect 8, wherein removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate comprises:

[0153] performing a planarization process on the deposited select gate polysilicon;

[0154] Etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; and

[0155] The first and second polysilicon structures are etched to form the first and second select gates, respectively.

[0156] Aspect 10. The method according to aspect 9, wherein etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises:

[0157] performing a first photolithography process on the first polysilicon structure and the second polysilicon structure;

[0158] using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively; and

[0159] The photoresist pattern formed by the first photolithography process is removed.

[0160] Aspect 11. The method according to aspect 9, wherein etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises:

[0161] forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure; and

[0162] The first and second polysilicon structures are etched using the first and second hard mask spacers as masks to form the first and second select gates, respectively.

[0163] Aspect 12. The method according to aspect 8, wherein removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate comprises:

[0164] The deposited select gate polysilicon is self-alignedly etched to form the first select gate and the second select gate, respectively.

[0165] Aspect 13. The method according to aspect 8, further comprising:

[0166] Depositing logic gate polysilicon on a logic gate region of the substrate simultaneously with depositing the select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure and on the gate stack; and

[0167] While removing the portion of the deposited select gate polysilicon to form the first select gate and the second select gate, a portion of the logic gate polysilicon is removed to form the logic gate.

[0168] Aspect 14. The method according to any one of aspects 1 to 7, wherein forming a first drain region in the substrate on a side of the first select gate opposite to the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite to the first opening comprises:

[0169] performing a lightly doped drain implantation in the substrate on a side of the first select gate opposite to the first opening and in the substrate on a side of the second select gate opposite to the first opening to form a first lightly doped drain region on one side of the first select gate and a second lightly doped drain region on one side of the second select gate;

[0170] forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening;

[0171] forming a first source spacer on a side of the first select gate facing the first opening, and forming a second source spacer on a side of the second select gate facing the first opening; and

[0172] A heavily doped drain implant is performed in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

[0173] Aspect 15. The method according to any one of aspects 1 to 7, further comprising:

[0174] A silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

[0175] Aspect 16. A semiconductor device manufactured by the method according to any one of aspects 1 to 15.

[0176] Although the present disclosure has been illustrated and described in detail in the drawings and in the foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments will be understood and effected by those skilled in the art in practicing the claimed subject matter by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer in sequence on the substrate; etching the hard mask layer, the control gate layer, and the dielectric layer to form a remaining portion including the hard mask layer, the control gate layer, and the dielectric layer; forming a first control gate spacer and a second control gate spacer on both sides of the hard mask layer, the control gate layer, and a remaining portion of the dielectric layer; etching the floating gate layer to form a gate stack comprising the floating gate layer, the dielectric layer, the control gate layer, and a remaining portion of the hard mask layer; removing portions of the oxide layer on a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack; forming a first selection gate oxide structure and a second selection gate oxide structure on the first region and the second region of the substrate, respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack, respectively; forming a first select gate on a side of the first tunneling oxide structure opposite the gate stack, and forming a second select gate on a side of the second tunneling oxide structure opposite the gate stack; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and a remaining portion of the floating gate layer, and forming a first gate structure and a second gate structure on both sides of the first opening, wherein the first gate structure includes a first floating gate, a first dielectric structure, a first control gate, and a first hard mask, and the second gate structure includes a second floating gate, a second dielectric structure, a second control gate, and a second hard mask, wherein the first control gate spacer is only on one side of the first control gate, forming an asymmetric control gate spacer, and the second control gate spacer is only on one side of the second control gate, forming an asymmetric control gate spacer; forming a source region in a portion of the substrate below the first opening; and A first drain region is formed in the substrate on a side of the first select gate opposite to the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite to the first opening.

2. The method according to claim 1, wherein The forming of a first selection gate oxide structure and a second selection gate oxide structure on the first region and the second region of the substrate, respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack, respectively, comprises: depositing a second gate oxide film on the first and second regions of the substrate and on the side surfaces and upper surface of the gate stack; and A portion of the second gate oxide film on the upper surface of the gate stack is removed to form the first select gate oxide structure, the second select gate oxide structure, the first tunneling oxide structure, and the second tunneling oxide structure.

3. The method according to claim 2 , further comprising, before depositing a second gate oxide film on the first and second regions of the substrate and on the side surfaces and upper surface of the gate stack: Depositing a first gate oxide film on the first region and the second region of the substrate, and on the side surfaces and upper surface of the gate stack; and Portions of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack are removed, and a portion of the first gate oxide film on the side surfaces of the gate stack is removed.

4. The method according to claim 3, wherein depositing a first gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack further comprises: Depositing the first gate oxide film on the high voltage tube region; as well as The step of depositing a second gate oxide film on the first region and the second region of the substrate and on the side surfaces and upper surface of the gate stack further comprises: The second gate oxide film is deposited on the high-voltage tube region.

5. The method according to claim 4, wherein A portion of the first gate oxide film on the high-voltage tube region is retained to form an oxide structure corresponding to the high-voltage tube region.

6. The method according to claim 4 , further comprising, before removing the portion of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack: Select gate channel ion implantation is performed in the first and second regions of the substrate.

7. The method according to claim 5, further comprising, after depositing the second gate oxide film: implanting a logic well in the substrate; forming a logic IO gate oxide structure on the substrate; and A logic core gate oxide structure is formed on the substrate.

8. The method according to any one of claims 1 to 7, wherein: The forming of a first select gate on a side of the first tunneling oxide structure opposite to the gate stack, and forming a second select gate on a side of the second tunneling oxide structure opposite to the gate stack comprises: depositing select gate polysilicon over the first select gate oxide structure and the second select gate oxide structure and over the gate stack; and Portions of the deposited select gate polysilicon are removed to form the first select gate and the second select gate.

9. The method according to claim 8, wherein The removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate includes: performing a planarization process on the deposited select gate polysilicon; Etching the planarized select gate polysilicon to form a first polysilicon structure and a second polysilicon structure respectively located on the first region and the second region of the substrate; and The first and second polysilicon structures are etched to form the first and second select gates, respectively.

10. The method according to claim 9, wherein: The etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises: performing a first photolithography process on the first polysilicon structure and the second polysilicon structure; using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively; and The photoresist pattern formed by the first photolithography process is removed.

11. The method according to claim 9, wherein The etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, comprises: forming a first hard mask spacer and a second hard mask spacer on both sides of the gate stack, respectively, wherein the first hard mask spacer is located on the first polysilicon structure and the second hard mask spacer is located on the second polysilicon structure; and The first and second polysilicon structures are etched using the first and second hard mask spacers as masks to form the first and second select gates, respectively.

12. The method according to claim 8, wherein The removing a portion of the deposited select gate polysilicon to form the first select gate and the second select gate includes: The deposited select gate polysilicon is self-alignedly etched to form the first select gate and the second select gate, respectively.

13. The method according to claim 8, further comprising: depositing logic gate polysilicon on a logic gate region of the substrate while depositing the select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure and on the gate stack; as well as While removing the portion of the deposited select gate polysilicon to form the first select gate and the second select gate, a portion of the logic gate polysilicon is removed to form the logic gate.

14. The method according to any one of claims 1 to 7, wherein: The forming of a first drain region in the substrate on a side of the first selection gate opposite to the first opening, and the forming of a second drain region in the substrate on a side of the second selection gate opposite to the first opening comprises: performing a lightly doped drain implantation in the substrate on a side of the first select gate opposite to the first opening and in the substrate on a side of the second select gate opposite to the first opening to form a first lightly doped drain region on one side of the first select gate and a second lightly doped drain region on one side of the second select gate; forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening; forming a first source spacer on a side of the first select gate facing the first opening, and forming a second source spacer on a side of the second select gate facing the first opening; and A heavily doped drain implant is performed in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region located on one side of the first drain spacer and a second heavily doped drain region located on one side of the second drain spacer.

15. The method according to any one of claims 1 to 7, further comprising: A silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

16. A semiconductor device comprising: a substrate, wherein a source region, a first drain region, and a second drain region are formed in the substrate; a substrate oxide structure formed on the substrate; a first gate structure comprising a first floating gate, a first dielectric structure, a first control gate, and a first hard mask, wherein the first floating gate is formed on the substrate oxide structure, the first dielectric structure is formed between the first floating gate and the first control gate, and the first hard mask is formed above the first control gate; a second gate structure comprising a second floating gate, a second dielectric structure, a second control gate, and a second hard mask, wherein the second floating gate is formed on the substrate oxide structure, the second dielectric structure is formed between the second floating gate and the second control gate, and the second hard mask is formed on the second control gate; a first opening formed between the first gate structure and the second gate structure and formed on the substrate oxide structure, wherein the source region is formed in the substrate below the first opening; a first control gate spacer formed on a side of the first dielectric structure, the first control gate, and the first hard mask opposite the first opening, wherein the first control gate spacer is only on one side of the first control gate to form an asymmetric control gate spacer; a second control gate spacer formed on a side of the second dielectric structure, the second control gate, and the second hard mask opposite the first opening, wherein the second control gate spacer is only on one side of the second control gate to form an asymmetric control gate spacer; a first tunneling oxide structure formed on one side of the first floating gate and the first control gate spacer; a second tunneling oxide structure formed on one side of the second floating gate and the second control gate spacer; A first select gate oxide structure and a second select gate oxide structure are formed in a first region and a second region of the substrate, respectively, wherein the first region and the second region are located on either side of the substrate oxide structure; A first selection gate and a second selection gate are formed on the first selection gate oxide structure and the second selection gate oxide structure, respectively, wherein the first drain region is formed in the substrate on a side of the first selection gate opposite to the first opening, and the second drain region is formed in the substrate on a side of the second selection gate opposite to the first opening.

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