A gallium oxide field effect transistor device and a method of manufacturing the same

Abstract

The application provides a gallium oxide field effect transistor device and a preparation method thereof. The device comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer. The n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a portion between the drain electrode and the source electrode. The first channel is deviated to a side of the source electrode. The fin channel is arranged between the drain electrode and the first channel. A cross section of the fin channel is in a symmetrical ladder shape pointing to the source electrode, and the number of ladders is greater than or equal to 2. A vertical projection of the gate electrode on the n-type gallium oxide channel layer covers a connecting area of the fin channel and the first channel. The application can make the gate electrode have a higher surface area and increase the threshold voltage through the fin channel structure. The size of the fin channel is reduced, the peak electric field is reduced, and the breakdown voltage of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a gallium oxide field effect transistor device and a preparation method thereof. BACKGROUND

[0002] Power electronic devices are mainly used for power conversion and circuit control of power equipment, and are the core devices for power processing. At present, the global environment and resource problems are facing severe challenges, and various countries have successively promulgated energy-saving and emission-reducing policies. As the core devices for power control and conversion of industrial facilities, household appliances and other equipment, power semiconductor industry will face new technical challenges and development opportunities.

[0003] Silicon-based semiconductor devices are the most commonly used power devices in the current power system, and their performance has been quite perfect and close to the theoretical limit determined by their material properties, making the power density growth tend to be saturated.

[0004] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional silicon-based power devices in certain specific fields.

[0005] As a new semiconductor material, super-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga figure of merit and cost. The Baliga figure of merit is usually used internationally to represent the degree to which a material is suitable for power devices. For example, the Baliga figure of merit of β-Ga2O3 material is 4 times that of gallium nitride material, 10 times that of silicon carbide material, and 3444 times that of silicon material. Under the same voltage resistance condition, the on-resistance of β-Ga2O3 power device is lower, the power consumption is smaller, and the power loss during device operation can be greatly reduced.

[0006] Since the first gallium oxide metal-oxide-semiconductor field-effect transistor (Ga2O3 MOSFET) device was developed by the National Institute of Information and Communications Technology (NICT) of Japan in 2013, researchers have continuously improved the performance of Ga2O3 MOSFET devices by improving the quality of Ga2O3 crystal materials and optimizing device manufacturing processes, including optimizing channel layer doping, ohmic contact and Schottky contact processes, and gate field plate structure and other methods. In 2016, NICT used Al2O3 as a gate dielectric and combined with a gate field plate structure to prepare a Ga2O3 MOSFET device with a breakdown voltage of 750V. In 2019, ETRI used a source field plate structure, and during the test process, the device was isolated from air breakdown by a fluorinated liquid, and the device had a breakdown voltage of 2320V. In 2020, Buffalo used SU-8 passivation, and the device had a breakdown of 8000V.

[0007] However, the breakdown voltage and on-state characteristics of the Ga2O3 field effect transistor (FET) devices reported so far are still far below the expected values of the material. SUMMARY

[0008] The embodiments of the present application provide a gallium oxide field effect transistor device and a preparation method thereof, so as to further improve the breakdown voltage of the existing gallium oxide field effect transistor.

[0009] In a first aspect, the embodiments of the present application provide a gallium oxide field effect transistor device, comprising: a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer corresponds to a part between the drain electrode and the source electrode, and includes a first channel and at least one fin channel; the first channel is deviated to the side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin channel is in a symmetrical stepped shape pointing to the source electrode, and the number of steps is greater than or equal to 2; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection area of the fin channel and the first channel.

[0010] In a possible implementation, the doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

[0011] In a possible implementation, the doping concentration of the n-type gallium oxide channel layer ranges from 1.0×10 15 cm -3 to 1.0×10 20 cm -3 .

[0012] In a possible implementation, the thickness of the n-type gallium oxide channel layer ranges from 10 nanometers to 1000 nanometers.

[0013] In a possible implementation, the length of the first step of the fin channel deviated to the side of the source electrode is greater than or equal to 200 nanometers.

[0014] In a possible implementation, the n-type gallium oxide channel layer further includes an undoped gallium oxide layer between the substrate and the n-type gallium oxide channel layer.

[0015] In a second aspect, the embodiments of the present application provide a preparation method of a gallium oxide field effect transistor device, comprising:

[0016] Growing an n-type gallium oxide channel layer on a substrate.

[0017] Preparing a drain electrode and a source electrode on the n-type gallium oxide channel layer.

[0018] A mask is fabricated on the surface of the n-type gallium oxide channel layer corresponding to the portion between the drain electrode and the source electrode; the mask includes a first channel mask and at least one fin channel mask; the first channel mask is biased towards the source electrode side; the fin channel mask is disposed between the drain electrode and the first channel mask; the cross-section of the fin channel mask is symmetrically stepped in the direction of the source electrode, and the number of steps is greater than or equal to 2.

[0019] The n-type gallium oxide channel layer is etched and the mask is removed to obtain the fin channel and the first channel.

[0020] A gate dielectric layer is prepared on the surface of the fin channel and the first channel.

[0021] A gate electrode is fabricated on the gate dielectric layer; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region between the fin channel and the first channel.

[0022] In one possible implementation, the doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

[0023] In one possible implementation, the doping concentration of the n-type gallium oxide channel layer ranges from 1.0 × 10⁻⁶. 15 cm -3 Up to 1.0×10 20 cm -3 .

[0024] In one possible implementation, the thickness of the n-type gallium oxide channel layer ranges from 10 nanometers to 1000 nanometers.

[0025] In one possible implementation, the length of the first step of the fin channel biased toward the source electrode side is greater than or equal to 200 nanometers.

[0026] In one possible implementation, prior to growing the n-type gallium oxide channel layer on the substrate, the method further includes growing an undoped gallium oxide layer on the substrate.

[0027] The embodiment of the present application provides a gallium oxide field effect transistor device and a preparation method thereof, the device comprises: a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a part between the drain electrode and the source electrode; the first channel is deviated to a side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin channel is in a symmetrical stepped shape pointing to the source electrode direction, and the number of steps is greater than or equal to 2; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers a connecting area of the fin channel and the first channel. Through the symmetrical stepped fin channel structure, the gate electrode has a higher surface area, the gate control capability is improved, the threshold voltage is increased, and the breakdown voltage is improved; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, so that the peak field strength of the device is reduced, and the breakdown voltage of the device is improved; the size of the fin channel under the endpoint of the gate electrode close to the drain electrode is reduced, the sharp peak electric field is reduced, the breakdown caused by the sharp peak electric field is avoided, and the breakdown voltage of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0029] Figure 1 It is a structure schematic diagram of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0030] Figure 2 It is a top view of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0031] Figure 3 It is a cross-sectional view of a channel layer of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0032] Figure 4 It is another cross-sectional view of a channel layer of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0033] Figure 5 It is a flow chart of a preparation method of a gallium oxide field effect transistor device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the person skilled in the art better understand the present scheme, the technical solutions in the embodiments of the present scheme will be clearly described in combination with the drawings in the embodiments of the present scheme. Obviously, the described embodiments are part of the embodiments of the present scheme, rather than all the embodiments. Based on the embodiments in the present scheme, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present scheme.

[0035] The term "comprising" and other any variations thereof in the specification and claims of the present scheme and the above-mentioned drawings means "including but not limited to", which is intended to cover non-exclusive inclusion and is not limited to the examples listed in the text. In addition, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order.

[0036] The implementation of the present application is described in detail below in combination with specific drawings:

[0037] Figure 1 A structure schematic diagram of a gallium oxide field effect transistor device provided by an embodiment of the present application, corresponding to Figure 2 B-B section; Figure 2 A top view of a gallium oxide field effect transistor device provided by an embodiment of the present application; Figure 3 A cross-sectional view of a gallium oxide field effect transistor device channel layer provided by an embodiment of the present application, corresponding to Figure 1 A-A section. Referring to Figure 1 , Figure 2 and Figure 3 , the gallium oxide field effect transistor device comprises:

[0038] a substrate 1, an n-type gallium oxide channel layer 2 provided on the substrate 1, a drain electrode 3 and a source electrode 4 provided on the n-type gallium oxide channel layer 2, a gate dielectric layer 5 provided between the drain electrode 3 and the source electrode 4, and a gate electrode 6 provided on the gate dielectric layer 5; the n-type gallium oxide channel layer 2 corresponding to the part between the drain electrode 3 and the source electrode 4 comprises a first channel 21 and at least one fin channel 22; the first channel 21 is biased to the side of the source electrode 4; the fin channel 22 is provided between the drain electrode 3 and the first channel 21; the cross section of the fin channel 22 is symmetrically stepped in the direction of the source electrode 4, and the number of steps is greater than or equal to 2; the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection area of the fin channel 22 and the first channel 21.

[0039] For example, the drain electrode 3 and the source electrode 4 are respectively provided on the upper surfaces of the two ends of the n-type gallium oxide channel layer 2.

[0040] The gate dielectric layer 5 is arranged between the n-type gallium oxide channel layer 2 and the source electrode 4 and the drain electrode 3. The coverage area of the gate dielectric layer 5 is larger than that of the gate electrode 6, so that the gate electrode 6 does not directly contact the n-type gallium oxide channel layer 2, the source electrode 4 and the drain electrode 3, thereby avoiding leakage of the device.

[0041] The first channel 21 is a portion of the n-type gallium oxide channel layer 2 located on the side of the source electrode 4. The thickness of the first channel 21 is consistent with the thickness of the n-type gallium oxide channel layer 2.

[0042] Figure 4 FIG. 2 is a cross-sectional view of another gallium oxide field effect transistor device channel layer according to an embodiment of the present application; and Figure 4 :

[0043] In an optional embodiment, the n-type gallium oxide channel layer 2 includes the first channel 21 and a plurality of fin channels 22 corresponding to the portion between the source electrode 4 and the drain electrode 3. The plurality of fin channels 22 are equidistantly distributed along a direction perpendicular to the connection line of the source electrode 4 and the drain electrode 3. For example, the number of the fin channels 22 is 3.

[0044] The symmetric ladder shape is a symmetric pagoda-shaped ladder, which can be understood as being composed of a plurality of rectangles with different lengths. Each rectangle is a layer of the ladder, and the rectangles are arranged in order from large to small in length, and the centers of the rectangles are aligned.

[0045] The symmetric ladder shape is a symmetric pagoda-shaped ladder, which can be understood as being composed of a plurality of rectangles with different lengths. Each rectangle is a layer of the ladder, and the rectangles are arranged in order from large to small in length, and the centers of the rectangles are aligned.

[0046] The number of the ladder shape is the number of layers of the ladder shape. When the number of the ladder shape is 1, the number of layers of the ladder shape is 1, and the drain electrode 3 is connected to the first channel 21 through a fin channel 22 with a rectangular cross-section. For example, the number of the ladder shape is 4.

[0047] For example, the thickness of the fin channel 22 is uniform. The fin channel 22 with uniform thickness is easier to manufacture than the fin channel 22 with non-uniform thickness. For example, the thickness of the fin channel 22 is less than or equal to the thickness of the n-type gallium oxide channel layer 2. For example, the thickness of the fin channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.

[0048] For example, the thickness of the fin channel 22 decreases from the drain electrode 3 to the source electrode 4. For example, the thickness changes in a gradient manner. For example, the thickness changes in a continuous and gradual manner. The thickness of the fin channel 22 decreases from the drain electrode 3 to the source electrode 4, the size of the fin channel under the end point of the gate electrode close to the drain electrode decreases, the sharp peak electric field is reduced, the breakdown caused by the sharp peak electric field is avoided, and the breakdown voltage of the device is improved.

[0049] The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin-shaped channel 22 and the first channel 21, that is, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 deviated to the source electrode 4 side and the part of the first channel 21 deviated to the drain electrode 3 side. Among them, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 deviated to the source electrode 4 side, and cannot cover the part of the fin-shaped channel 22 deviated to the drain electrode 3 side; if the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 deviated to the drain electrode 3 side, the peak electric field of the gate electrode 6 close to the channel on the side of the drain electrode 3 is not inhibited, and the function of reducing the peak electric field and improving the breakdown voltage cannot be realized.

[0050] For example, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers 50% of the part of the fin-shaped channel 22 deviated to the source electrode 4 side and 50% of the part of the first channel 21 deviated to the drain electrode 3 side.

[0051] Correspondingly, the gate electrode 6 covers the part of the gate dielectric layer 5 corresponding to the fin-shaped channel 22 deviated to the source electrode 4 side, and the part of the gate dielectric layer 5 corresponding to the first channel 21 deviated to the drain electrode 3 side.

[0052] Through the symmetric stepped fin-shaped channel 22 structure, the gate electrode 6 has a higher surface area, improves the gate control ability, increases the threshold voltage, and improves the breakdown voltage; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown voltage of the device; the size of the fin-shaped channel 22 under the endpoint of the gate electrode 6 close to the drain is reduced, the peak electric field is reduced, the breakdown caused by the peak electric field is avoided, and the breakdown voltage of the device is improved.

[0053] In an optional embodiment, the length of the first step of the fin-shaped channel 22 deviated to the source electrode 4 side is greater than or equal to 200 nanometers. The length of the step is the size of each layer of the step along the direction perpendicular to the drain electrode 3 and the source electrode 4.

[0054] In an optional embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.

[0055] In an optional embodiment, the thickness of the n-type gallium oxide channel layer 2 ranges from 10 nanometers to 1000 nanometers.

[0056] In an optional embodiment, the doping concentration of the n-type gallium oxide channel layer 2 ranges from 1.0×10 15 cm -3 to 1.0×10 20 cm -3The n-type gallium oxide channel layer 2 is realized by doping silicon or tin in the process of epitaxial growth of gallium oxide.

[0057] In an alternative embodiment, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases from the lower layer to the upper layer. There is a strong peak electric field at the end of the channel of the gate electrode 6 biased to the drain electrode 3, which leads to device breakdown; the peak electric field is directly related to the electron concentration of the channel, and the decrease in concentration can effectively reduce the electric field strength, but it will lead to the deterioration of the device conduction characteristics; the doping concentration gradually decreases from the lower layer to the upper layer of the channel layer, and the electron concentration gradually decreases from the lower layer to the upper layer, which can not affect the conduction characteristics of the device, but also can reduce the peak electric field and improve the breakdown voltage. Illustratively, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases in a gradient from the lower layer to the upper layer.

[0058] In an alternative embodiment, the n-type gallium oxide channel layer 2 further includes an undoped gallium oxide layer between the substrate 1 and the n-type gallium oxide channel layer 2.

[0059] In an alternative embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.

[0060] In an alternative embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.

[0061] In an alternative embodiment, the n+ contact layer is further included between the drain electrode 3, the source electrode 4 and the n-type gallium oxide channel layer 2 in the vertical projection area of the drain electrode 3, the source electrode 4 on the n-type gallium oxide channel layer 2.

[0062] In an alternative embodiment, the material of the gate dielectric layer 5 is aluminum oxide, hafnium dioxide or silicon dioxide; illustratively, the material of the gate dielectric layer 5 is a composite dielectric of aluminum oxide and hafnium dioxide.

[0063] Figure 5 A preparation method of a gallium oxide field effect transistor device is provided for the embodiment of the present application, referring to Figure 5 The preparation method comprises:

[0064] Step S1, growing an n-type gallium oxide channel layer 2 on a substrate 1;

[0065] In an alternative embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate or a sapphire substrate.

[0066] In an alternative embodiment, the thickness of the n-type gallium oxide channel layer 2 ranges from 10 nanometers to 1000 nanometers.

[0067] In an alternative embodiment, the doping concentration of the n-type gallium oxide channel layer 2 ranges from 1.0×10 15 cm -3to 1.0 x 10 20 cm -3 The n-type gallium oxide channel layer 2 is realized by doping silicon or tin in the process of epitaxial growth of gallium oxide.

[0068] In an optional embodiment, the substrate 1 and the n-type gallium oxide channel layer 2 further comprise an undoped gallium oxide layer.

[0069] Step S2, preparing the drain electrode 3 and the source electrode 4 on the n-type gallium oxide channel layer 2;

[0070] For example, the electrode metal layer is deposited by electron beam evaporation; the drain electrode 3 and the source electrode 4 are prepared by a photolithography etching process or a photolithography stripping process.

[0071] In an optional embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.

[0072] In an optional embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.

[0073] In an optional embodiment, the n+ contact layer is further included between the drain electrode 3, the source electrode 4 and the n-type gallium oxide channel layer 2 in the vertical projection area of the drain electrode 3, the source electrode 4 on the n-type gallium oxide channel layer 2; for example, the n+ contact layer is prepared by an ion implantation process.

[0074] Step S3, preparing a mask on the part of the surface of the n-type gallium oxide channel layer 2 corresponding to the drain electrode 3 and the source electrode 4; the mask comprises a first channel mask and at least one fin-shaped channel mask; the first channel mask is deviated to the side of the source electrode 4; the fin-shaped channel mask is arranged between the drain electrode 3 and the first channel mask; the cross section of the fin-shaped channel mask is in the shape of a symmetric ladder pointing to the direction of the source electrode 4, and the number of the ladder steps is greater than or equal to 2.

[0075] In an optional embodiment, the mask is prepared by a contact photolithography process or an electron beam photolithography process; for example, the material of the mask is photoresist.

[0076] In an optional embodiment, the material of the mask is metal; the preparation method of the mask comprises:

[0077] By the gluing process and the photolithography process, the photoresist pattern opposite to the patterns of the first channel 21 and the fin-shaped channel 22 is prepared on the part of the surface of the n-type gallium oxide channel layer 2 corresponding to the drain electrode 3 and the source electrode 4.

[0078] The mask metal layer is deposited.

[0079] Stripping, the metal mask consistent with the patterns of the first channel 21 and the fin-shaped channel 22 is obtained.

[0080] Step S4, etching the n-type gallium oxide channel layer 2, removing the mask, and obtaining the fin-shaped channel 22 and the first channel 21.

[0081] The area covered by the mask will not be etched; for example, the etching method is a dry etching process.

[0082] For example, the etching depth is uniform. For example, the etching depth is less than or equal to the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin-shaped channel 22 is less than or equal to the thickness of the n-type gallium oxide channel layer 2. For example, the etching depth is greater than the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin-shaped channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.

[0083] In an optional embodiment, the fin-shaped channel 22 is divided into multiple parts from the drain electrode 3 to the source electrode 4 in step S3; the corresponding mask is designed according to the multiple parts of the fin-shaped channel 22; only one part of the fin-shaped channel 22 is etched each time, and the etching depth increases from the drain electrode 3 to the source electrode 4 in turn; steps S3 and S4 are repeated to complete the etching of all parts.

[0084] Step S5, preparing a gate dielectric layer 5 on the surfaces of the fin-shaped channel 22 and the first channel 21.

[0085] In an optional embodiment, the gate dielectric layer 5 is prepared on the surfaces of the fin-shaped channel 22 and the first channel 21 by an atomic layer deposition process.

[0086] In an optional embodiment, the material of the gate dielectric layer 5 is aluminum oxide, hafnium oxide or silicon dioxide; for example, the material of the gate dielectric layer 5 is a composite medium of aluminum oxide and hafnium oxide.

[0087] Step S6, preparing a gate electrode 6 on the gate dielectric layer 5; the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection area of the fin-shaped channel 22 and the first channel 21.

[0088] The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 deviated to the source electrode 4 side and the part of the first channel 21 deviated to the drain electrode 3 side. Correspondingly, the gate electrode 6 covers the corresponding part of the gate dielectric layer 5 deviated to the source electrode 4 side and the corresponding part of the gate dielectric layer 5 deviated to the drain electrode 3 side.

[0089] The symmetrical ladder-shaped fin channel 22 structure makes the gate electrode 6 have higher surface area, improves the gate control ability, increases the threshold voltage, and improves the breakdown voltage; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown voltage of the device; the size of the fin channel 22 under the end point of the gate electrode 6 close to the drain is reduced, the peak electric field is reduced, the breakdown caused by the peak electric field is avoided, and the breakdown voltage of the device is improved.

[0090] The above examples are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A gallium oxide field effect transistor device, characterized by, The application relates to a gallium oxide transistor, which comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer. The n-type gallium oxide channel layer comprises a first channel and at least one fin-shaped channel corresponding to the part between the drain electrode and the source electrode. The first channel is deviated to the side of the source electrode. The fin-shaped channel is arranged between the drain electrode and the first channel. The cross section of the fin-shaped channel is symmetrically stepped in the direction of the source electrode, and the number of steps is greater than or equal to 2. The vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connecting area of the fin-shaped channel and the first channel; wherein the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the part of the fin-shaped channel deviated to the side of the source electrode and the part of the first channel deviated to the side of the drain electrode, and cannot cover the part of the fin-shaped channel deviated to the side of the drain electrode.

2. A gallium oxide field effect transistor device as claimed in claim 1, wherein, The doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

3. A gallium oxide field effect transistor device as claimed in claim 1, wherein, The thickness of the n-type gallium oxide channel layer ranges from 10 nm to 1000 nm.

4. A gallium oxide field effect transistor device as claimed in claim 1, wherein, The length of the first step of the fin-shaped channel deviated to the side of the source electrode is greater than or equal to 200 nm.

5. A gallium oxide field effect transistor device as claimed in claim 1, wherein, The substrate and the n-type gallium oxide channel layer further comprise an undoped gallium oxide layer.

6. A method for fabricating a gallium oxide field-effect transistor device, characterized in that, The application relates to a gallium oxide transistor, which comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer. The n-type gallium oxide channel layer comprises a first channel and at least one fin-shaped channel corresponding to the part between the drain electrode and the source electrode. The first channel is deviated to the side of the source electrode. The fin-shaped channel is arranged between the drain electrode and the first channel. The cross section of the fin-shaped channel is symmetrically stepped in the direction of the source electrode, and the number of steps is greater than or equal to 2. The vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connecting area of the fin-shaped channel and the first channel; wherein the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the part of the fin-shaped channel deviated to the side of the source electrode and the part of the first channel deviated to the side of the drain electrode, and cannot cover the part of the fin-shaped channel deviated to the side of the drain electrode. The doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

7. The method of claim 6, wherein the method further comprises the step of: The thickness of the n-type gallium oxide channel layer ranges from 10 nm to 1000 nm. ​ 8. The method of claim 6, wherein the method further comprises: depositing a gate dielectric layer on the substrate; and depositing a gate electrode on the gate dielectric layer. The length of the first step of the fin-shaped channel deviated to the side of the source electrode is greater than or equal to 200 nm.

9. The method of claim 6, wherein the method further comprises: depositing a gate oxide layer on the substrate; and depositing a gate electrode on the gate oxide layer. The application further comprises the following steps before the step of growing the n-type gallium oxide channel layer on the substrate:

10. The method of claim 6, wherein the method further comprises: depositing a gate oxide layer on the substrate; and depositing a gate electrode on the gate oxide layer. An undoped gallium oxide layer is grown on the substrate. ​

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