Shielded gate trench field effect transistor with variable doping concentration structure and method of manufacture

Abstract

The application relates to a shield gate trench field effect transistor with a variable doping concentration structure, which comprises a substrate region, a drift region, a base region, a source region, a trench region, a drain and a source. The trench region comprises a shield gate, a control gate, an insulation layer and a metal gate. The shield gate and the drift region are of a variable doping concentration structure, and the doping concentration of the drift region gradually decreases from top to bottom, and the doping concentration of the shield gate gradually decreases from top to bottom. When the transistor is forward blocked, the electric field between the third stage of the drift region and the corner of the trench region is weakened. Therefore, the shield gate trench field effect transistor with the variable doping concentration structure shown in the embodiment of the application can balance the peak electric field of the voltage resistance layer at the interface between the base region and the drift region, the electric field peak value is improved, the breakdown voltage is improved, and the specific on-resistance is reduced.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a shielded gate trench field-effect transistor with variable doping concentration structure and its fabrication method. Background Technology

[0002] Split-gate trench field-effect transistors (SGTs) have been widely used in important low-voltage applications such as power management. SGTs feature high channel density and good charge compensation. Furthermore, their shielded gate structure effectively isolates the coupling between the control gate and drain, thus significantly reducing transfer capacitance.

[0003] Therefore, SGT has lower specific on-resistance, lower conduction and switching losses, and higher operating frequency.

[0004] In SGT devices, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, when the SGT device is forward blocked, the charge flux emitted by the ionized donors in the breakdown region is concentrated at the corner of the trench shielding gate, resulting in a higher peak voltage at the corner of the trench shielding gate, and it is also easier to be broken down at this point.

[0005] Therefore, in order to improve the withstand voltage at the corner of the trench shielding gate in SGT devices, it is urgent to design a new type of shielding gate trench field-effect transistor. Summary of the Invention

[0006] To overcome the problems existing in related technologies, this application provides a shielded gate trench field-effect transistor with a variable doping concentration structure, comprising:

[0007] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0008] The drift region is connected to the substrate region, with the direction from the substrate region to the drift region defined as upward. The substrate region and the source region are sequentially disposed above the drift region. The drift region is a variable doping concentration structure with the doping concentration gradually decreasing from top to bottom. The drift region includes: a first-level drift region, a second-level drift region, and a third-level drift region. The first-level drift region has a high doping concentration, the second-level drift region has a medium doping concentration, and the third-level drift region has a low doping concentration.

[0009] The trench region is disposed on the side of the substrate region and is connected to the drift region, the substrate region and the source region respectively;

[0010] The trench region includes a shielding gate, a control gate, an insulating layer, and a metal gate; the control gate and the shielding gate are arranged sequentially from top to bottom in the trench region and separated by the insulating layer; the control gate is connected to the substrate region and the source region respectively through the insulating layer, and the shielding gate is connected to the drift region through the insulating layer;

[0011] The shielding gate is a variable doping concentration structure in which the doping concentration gradually decreases from top to bottom;

[0012] The source region is composed of an N-type source region and a P-type source region; the P-type source region, the N-type source region, and the trench region are arranged sequentially along the top surface of the substrate region, and the N-type source region is connected to the control gate through the insulating layer;

[0013] The source electrode is positioned above the source region.

[0014] In one embodiment, the shielding grid includes a first-level shielding grid, a second-level shielding grid, and a third-level shielding grid;

[0015] The first-stage shielding gate has a high doping concentration; the second-stage shielding gate has a medium doping concentration; and the third-stage shielding gate has a low doping concentration.

[0016] In one embodiment, the trench region further includes a Schottky metal layer; the Schottky metal layer is disposed below the shielding grid.

[0017] In one embodiment, the direction from the substrate region to the drift region is taken as the height direction; the top and bottom surfaces of the first-stage drift region are respectively located on the same height plane as the top and bottom surfaces of the first-stage shielding gate;

[0018] The top and bottom surfaces of the second-stage drift region are located on the same height plane as the top and bottom surfaces of the second-stage shielding grid, respectively; the top and bottom surfaces of the third-stage drift region are located on the same height plane as the top and bottom surfaces of the third-stage shielding grid, respectively.

[0019] In one embodiment, the doping concentrations of both the P-type source region and the N-type source region are heavily doped.

[0020] In one embodiment, the substrate region is N-type doped and the doping concentration of the substrate region is heavily doped; the drift region is N-type doped; the matrix region is P-type doped and the doping concentration of the matrix region is medium doped; the source region is heavily doped; and the control gate is heavily doped.

[0021] The second aspect of this application provides a method for fabricating a shielded gate trench field-effect transistor with a variable doping concentration structure, used to fabricate a shielded gate trench field-effect transistor with a variable doping concentration structure as described in the first aspect of this application, comprising:

[0022] The substrate region is prepared using semiconductor materials;

[0023] A third-level drift region, a second-level drift region, and a first-level drift region are epitaxially formed sequentially on the substrate region; the doping concentration of the third-level drift region is low, the doping concentration of the second-level drift region is medium, and the doping concentration of the first-level drift region is high.

[0024] A matrix region is formed on the drift region by ion implantation or diffusion.

[0025] Grooves are etched on the side of the drift region;

[0026] Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate; wherein the shielding gate is a variable doping concentration structure; the doping concentration of the shielding gate decreases step by step from top to bottom;

[0027] A source region is formed on the matrix region;

[0028] Metal is deposited on the source region to form a source electrode;

[0029] The drain is fabricated below the substrate region.

[0030] In one embodiment, the step of sequentially depositing oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate includes:

[0031] Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form an insulating layer, a third-level shielding gate, a second-level shielding gate, a first-level shielding gate, and a control gate, respectively; the first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

[0032] In one embodiment, prior to the sequential deposition of oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate, the process includes:

[0033] Metal is deposited within the trench, forming a Schottky metal layer.

[0034] The technical solution provided in this application may include the following beneficial effects:

[0035] In this embodiment, both the shielding gate and the drift region are variable doping concentration structures. The doping concentration of the drift region gradually decreases from top to bottom, and the doping concentration of the shielding gate also gradually decreases from top to bottom. The drift region consists of a first-level drift region, a second-level drift region, and a third-level drift region, all with gradually decreasing doping concentrations from top to bottom. Therefore, the low-doped third-level drift region corresponds to the shielding gate at the same height. When the transistor is forward-biased, the electric field between the third-level drift region and the corner of the trench region is weakened. Therefore, the variable doping concentration shielding gate trench field-effect transistor shown in this embodiment can balance the peak electric field at the interface between the substrate region and the drift region, resulting in improved peak electric field and thus increased breakdown voltage and reduced specific on-resistance.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0037] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0038] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with variable doping concentration, as shown in the embodiments of this application;

[0039] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with a variable doping concentration structure as shown in the embodiments of this application;

[0040] Figure 3 This is another schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with a variable doping concentration structure as shown in the embodiments of this application. Detailed Implementation

[0041] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0042] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0044] Example 1

[0045] In SGT devices, due to the high doping concentration in the gate drift region, a depletion region forms between the drift region and the substrate region when the SGT device is forward blocked. This depletion region contains a spike electric field. This spike electric field, due to the electric field concentration effect, can cause breakdown at the corner between the trench region and the drift region.

[0046] Therefore, in order to balance the peak electric field in the depletion region, improve the peak electric field, increase the breakdown voltage, and reduce the specific on-resistance, embodiments of this application provide a shielded gate trench field-effect transistor with a variable doping concentration structure.

[0047] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with a variable doping concentration structure shown in the embodiments of this application.

[0048] See Figure 1 The shielded gate trench field-effect transistor with variable doping concentration structure shown in the embodiments of this application includes:

[0049] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0050] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top. The substrate region 3 and the source region 4 are sequentially disposed above the drift region 2. The drift region 2 is a variable doping concentration structure with the doping concentration gradually decreasing from top to bottom. The drift region 2 includes: a first-level drift region 21, a second-level drift region 22, and a third-level drift region 23. The first-level drift region 21 has a high doping concentration, the second-level drift region 22 has a medium doping concentration, and the third-level drift region 23 has a low doping concentration.

[0051] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0052] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0053] The shielding gate 51 is a variable doping concentration structure in which the doping concentration gradually decreases from top to bottom;

[0054] The source region 4 is composed of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53.

[0055] The source electrode 7 is disposed above the source region 4.

[0056] In this embodiment, the substrate region 1 is doped with N-type doping and has a heavy doping concentration; the drift region 2 is doped with N-type doping and has a light doping concentration; the substrate region 3 is doped with P-type doping and has a medium doping concentration; the source region 4 has a heavy doping concentration; and the control gate 52 has a heavy doping concentration, and the control gate 52 is doped with either P-type or N-type doping.

[0057] In this embodiment, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×1018 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0058] In the embodiments of this application, the doping type of the shielding gate is P-type doping or N-type doping.

[0059] Furthermore, the doping concentration of the shielding gate can be either heavily doped or moderately doped.

[0060] To reduce the peak electric field at the corner between the trench region and the drift region.

[0061] In this embodiment, both the shielding gate and the drift region are variable doping concentration structures. The doping concentration of the drift region gradually decreases from top to bottom, and the doping concentration of the shielding gate also gradually decreases from top to bottom. The drift region consists of a first-level drift region, a second-level drift region, and a third-level drift region, all with gradually decreasing doping concentrations from top to bottom. Therefore, the low-doped third-level drift region corresponds to the shielding gate at the same height. When the transistor is forward-biased, the electric field between the third-level drift region and the corner of the trench region is weakened.

[0062] Therefore, the shielded gate trench field-effect transistor with variable doping concentration structure shown in the embodiments of this application can balance the peak electric field at the interface between the substrate region and the drift region of the breakdown layer, thereby improving the peak electric field and increasing the breakdown voltage and reducing the specific on-resistance.

[0063] Example 2

[0064] In SGT devices, due to the electric field concentration effect and the high polysilicon doping concentration of the shielding gate, the parasitic capacitance formed between the shielding gate and the substrate region is large when the SGT device is forward blocked, which reduces the switching speed of the transistor.

[0065] Therefore, to improve the breakdown voltage of SGT devices, it is necessary to reduce the electric field strength at the corners of the trench shielding gate. This application provides a shielding gate trench field-effect transistor with a variable doping concentration structure.

[0066] Figure 1 This is a schematic diagram of the structure of a shielded gate trench field-effect transistor with a variable doping concentration structure shown in the embodiments of this application.

[0067] See Figure 1 The shielded gate trench field-effect transistor with variable doping concentration structure shown in the embodiments of this application includes:

[0068] Substrate region 1, drift region 2, substrate region 3, source region 4, trench region 5, drain 6, and source 7;

[0069] The drift region 2 is connected to the substrate region 1, with the direction from the substrate region 1 to the drift region 2 as the top. The substrate region 3 and the source region 4 are sequentially disposed above the drift region 2. The drift region 2 is a variable doping concentration structure with the doping concentration gradually decreasing from top to bottom. The drift region 2 includes: a first-level drift region 21, a second-level drift region 22, and a third-level drift region 23. The first-level drift region 21 has a high doping concentration, the second-level drift region 22 has a medium doping concentration, and the third-level drift region 23 has a low doping concentration.

[0070] The trench region 5 is disposed on the side of the substrate region 3 and is connected to the drift region 2, the substrate region 3 and the source region 4 respectively;

[0071] The trench region 5 includes a shielding gate 51, a control gate 52, an insulating layer 53, and a metal gate; the control gate 52 and the shielding gate 51 are arranged sequentially from top to bottom in the trench region 5 and are separated by the insulating layer 53; the control gate 52 is connected to the substrate region 3 and the source region 4 respectively through the insulating layer 53, and the shielding gate 51 is connected to the drift region 2 through the insulating layer 53;

[0072] The shielding gate 51 is a variable doping concentration structure in which the doping concentration gradually decreases from top to bottom;

[0073] The source region 4 is composed of an N-type source region 41 and a P-type source region 42; the P-type source region 42, the N-type source region 41 and the trench region 5 are arranged sequentially along the top surface of the substrate region 3, and the N-type source region 41 is connected to the control gate through the insulating layer 53.

[0074] The source electrode 7 is disposed above the source region 4.

[0075] In this embodiment of the application, the shielding grid 51 includes: a first-level shielding grid 510, a second-level shielding grid 511, and a third-level shielding grid 512;

[0076] The first-stage shielding gate 510 has a high doping concentration; the second-stage shielding gate 511 has a medium doping concentration; and the third-stage shielding gate 512 has a low doping concentration.

[0077] In this embodiment, the third-level shielding gate is disposed at the bottom of the shielding gate, close to the substrate region, and the doping concentration of the third-level shielding gate is low.

[0078] Furthermore, the trench region 5 also includes a Schottky metal layer 54; the Schottky metal layer 54 is disposed below the shielding grid.

[0079] In this embodiment of the application, the top and bottom surfaces of the first-stage drift region 21 are located on the same height plane as the top and bottom surfaces of the first-stage shielding grid 510.

[0080] The top and bottom surfaces of the second-stage drift region 22 are located on the same height plane as the top and bottom surfaces of the second-stage shielding grid 511, respectively; the top and bottom surfaces of the third-stage drift region 23 are located on the same height plane as the top and bottom surfaces of the third-stage shielding grid 512, respectively.

[0081] Therefore, when the transistor is forward-blocked, the third-stage shielding gate is more easily depleted under the same applied voltage, resulting in a thicker depletion layer width. Consequently, the parasitic capacitance formed between the third-stage shielding gate and the substrate region is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0082] Example 3

[0083] Corresponding to the shielded gate trench field-effect transistor with variable doping concentration structure shown in Example 1, this application also provides a method for fabricating a shielded gate trench field-effect transistor with variable doping concentration structure and corresponding embodiments.

[0084] Figure 2 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with a variable doping concentration structure as shown in the embodiments of this application.

[0085] like Figure 2 As shown in the embodiments of this application, the fabrication method of the shielded gate trench field-effect transistor includes the following steps:

[0086] 201. Fabrication of substrate regions using semiconductor materials;

[0087] In the embodiments of this application, the substrate region is prepared using N-type heavily doped semiconductor material, that is, the doping type of the substrate region is N-type doping, and the doping concentration of the substrate region is the heavy doping concentration.

[0088] 202. A third-level drift region, a second-level drift region, and a first-level drift region are epitaxially formed sequentially on the substrate region;

[0089] In this embodiment, the doping concentration of the third-level drift region is low, the doping concentration of the second-level drift region is medium, and the doping concentration of the first-level drift region is high.

[0090] In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0091] 203. A matrix region is formed on the drift region by ion implantation or diffusion;

[0092] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0093] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0094] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0095] 204. Etch grooves on the side of the drift zone;

[0096] In this embodiment, a trench is etched on one side of the drift region using photolithography, and the residual photoresist is removed by wet etching or dry etching.

[0097] 205. Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate;

[0098] Preferably, in this embodiment of the application, oxide, heavily doped polysilicon, oxide and heavily doped polysilicon are sequentially deposited in the trench to form the shielding gate, insulating layer and control gate.

[0099] In this embodiment, the doping concentration of the shielding gate decreases gradually from top to bottom, that is, the doping concentration of the portion of the shielding gate near the control gate is the highest, while the doping concentration of the portion of the shielding gate near the substrate region is the lowest.

[0100] 206. A source region is formed on the matrix region;

[0101] 207. Deposit metal on the source region to form a source electrode;

[0102] 208. Fabricate the drain below the substrate region.

[0103] To reduce the peak electric field at the corner between the trench region and the drift region.

[0104] In this embodiment, both the shielding gate and the drift region are variable doping concentration structures. The doping concentration of the drift region gradually decreases from top to bottom, and the doping concentration of the shielding gate also gradually decreases from top to bottom. The drift region consists of a first-level drift region, a second-level drift region, and a third-level drift region, all with gradually decreasing doping concentrations from top to bottom. Therefore, the low-doped third-level drift region corresponds to the shielding gate at the same height. When the transistor is forward-biased, the electric field between the third-level drift region and the corner of the trench region is weakened.

[0105] Therefore, the shielded gate trench field-effect transistor with variable doping concentration structure shown in the embodiments of this application can balance the peak electric field at the interface between the substrate region and the drift region of the breakdown layer, thereby improving the peak electric field and increasing the breakdown voltage and reducing the specific on-resistance.

[0106] Example 4

[0107] Corresponding to the shielded gate trench field-effect transistor with variable doping concentration structure shown in Example 2, this application also provides a method for fabricating a shielded gate trench field-effect transistor with variable doping concentration structure and corresponding embodiments.

[0108] Figure 3 This is a schematic flowchart illustrating the fabrication method of a shielded gate trench field-effect transistor with a variable doping concentration structure as shown in the embodiments of this application.

[0109] like Figure 3 As shown, it includes the following steps:

[0110] 301. Fabrication of a substrate region using semiconductor materials;

[0111] 302. A third-level drift region, a second-level drift region, and a first-level drift region are epitaxially formed sequentially on the substrate region;

[0112] 303. A matrix region is formed on the drift region by ion implantation or diffusion;

[0113] 304. Etch grooves on the side of the drift zone;

[0114] 305. Deposit metal within the trench to form a Schottky metal layer;

[0115] 306. Oxide, polysilicon, oxide and polysilicon are deposited sequentially in the trench to form an insulating layer, a third-level shielding gate, a second-level shielding gate and a first-level shielding gate and a control gate, respectively.

[0116] In this embodiment, the first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

[0117] 307. A source region is formed on the matrix region;

[0118] 308. Deposit metal on the source region to form a source electrode;

[0119] 309. Fabricate the drain below the substrate region.

[0120] In this embodiment of the application, the top and bottom surfaces of the first-stage drift region are located on the same height plane as the top and bottom surfaces of the first-stage shielding grid;

[0121] The top and bottom surfaces of the second-stage drift region are located on the same height plane as the top and bottom surfaces of the second-stage shielding grid, respectively; the top and bottom surfaces of the third-stage drift region are located on the same height plane as the top and bottom surfaces of the third-stage shielding grid, respectively.

[0122] Therefore, when the transistor is forward-blocked, the third-stage shielding gate is more easily depleted under the same applied voltage, resulting in a thicker depletion layer width. Consequently, the parasitic capacitance formed between the third-stage shielding gate and the substrate region is smaller, weakening the parasitic capacitance between the shielding gate and the substrate region, thereby improving the switching speed of the device.

[0123] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field-effect transistor with a variable doping concentration structure, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), trench region (5), drain (6), and source (7); The drift region (2) is connected to the substrate region (1), with the direction from the substrate region (1) to the drift region (2) as the top. The substrate region (3) and the source region (4) are sequentially disposed above the drift region (2). The drift region (2) is a variable doping concentration structure with the doping concentration gradually decreasing from top to bottom. The drift region (2) includes: a first-level drift region (21), a second-level drift region (22), and a third-level drift region (23). The doping concentration of the first-level drift region (21) is high doping concentration, the doping concentration of the second-level drift region (22) is medium doping concentration, and the doping concentration of the third-level drift region (23) is low doping concentration. The trench area (5) is located on the side of the substrate area (3) and is connected to the drift area (2), the substrate area (3) and the source area (4) respectively; The trench region (5) includes a shielding gate (51), a control gate (52), an insulating layer (53), and a metal gate; the control gate (52) and the shielding gate (51) are arranged sequentially from top to bottom in the trench region (5) and separated by the insulating layer (53); the control gate (52) is connected to the substrate region (3) and the source region (4) respectively through the insulating layer (53), and the shielding gate (51) is connected to the drift region (2) through the insulating layer (53); The shielding gate (51) is a variable doping concentration structure in which the doping concentration gradually decreases from top to bottom; The source region (4) is composed of an N-type source region (41) and a P-type source region (42); the P-type source region (42), the N-type source region (41) and the trench region (5) are arranged sequentially along the top surface of the substrate region (3), and the N-type source region (41) is connected to the control gate through the insulating layer (53); The source electrode (7) is disposed above the source region (4).

2. The shielded gate trench field-effect transistor with variable doping concentration structure according to claim 1, characterized in that, The shielding grid (51) includes a first-level shielding grid (510), a second-level shielding grid (511), and a third-level shielding grid (512). The first-level shielding gate (510) has a high doping concentration; the second-level shielding gate (511) has a medium doping concentration; and the third-level shielding gate (512) has a low doping concentration.

3. The shielded gate trench field-effect transistor with variable doping concentration structure according to claim 1, characterized in that, The trench region (5) further includes: a Schottky metal layer (54); The Schottky metal layer (54) is disposed below the shielding grid.

4. The shielded gate trench field-effect transistor with variable doping concentration structure according to claim 2, characterized in that, The direction from the substrate region (1) to the drift region (2) is taken as the height direction; The top and bottom surfaces of the first-stage drift region (21) are located on the same height plane as the top and bottom surfaces of the first-stage shielding grid (510); The top and bottom surfaces of the second-level drift region (22) are located on the same height plane as the top and bottom surfaces of the second-level shielding grid (511); the top and bottom surfaces of the third-level drift region (23) are located on the same height plane as the top and bottom surfaces of the third-level shielding grid (512).

5. The shielded gate trench field-effect transistor with variable doping concentration structure according to claim 1, characterized in that, The doping concentrations of the P-type source region (42) and the N-type source region (41) are both heavily doped.

6. The shielded gate trench field-effect transistor with variable doping concentration structure according to claim 1, characterized in that, The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavy doping concentration. The drift region (2) is doped with N-type doping; The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping concentration of the source region (4) is a heavily doped concentration; the doping concentration of the control gate (52) is a heavily doped concentration.

7. A method for fabricating a shielded gate trench field-effect transistor with a variable doping concentration structure, characterized in that, A method for fabricating a shielded gate trench field-effect transistor with a variable doping concentration structure as described in any one of claims 1 to 6, comprising: The substrate region is prepared using semiconductor materials; A first-level drift region, a second-level drift region, and a third-level drift region are epitaxially formed on the substrate region in sequence; the first-level drift region has a low doping concentration, the second-level drift region has a medium doping concentration, and the third-level drift region has a high doping concentration. A matrix region is formed on the drift region by ion implantation or diffusion. Grooves are etched on the side of the drift region; Oxide, polysilicon, oxide, polysilicon and oxide are deposited sequentially in the trench to form an insulating layer, a shielding gate and a control gate; wherein the shielding gate is a variable doping concentration structure; the doping concentration of the shielding gate decreases step by step from top to bottom; A source region is formed on the matrix region; Metal is deposited on the source region to form a source electrode; The drain is fabricated below the substrate region.

8. The method for fabricating a shielded gate trench field-effect transistor with a variable doping concentration structure according to claim 7, characterized in that, The process of sequentially depositing oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate includes: Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the trench to form an insulating layer, a first-level shielding gate, a second-level shielding gate and a third-level shielding gate, and a control gate, respectively; the first-level shielding gate has a high doping concentration, the second-level shielding gate has a medium doping concentration, and the third-level shielding gate has a low doping concentration.

9. The method for fabricating a shielded gate trench field-effect transistor with a variable doping concentration structure according to claim 8, characterized in that, Before the sequential deposition of oxide, polysilicon, oxide, polysilicon, and oxide within the trench to form an insulating layer, a shielding gate, and a control gate, the process includes: Metal is deposited within the trench, forming a Schottky metal layer.

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