SiC trench mos device structure with built-in heterojunction diode

Abstract

A SiC trench MOS device structure with built-in polysilicon heterojunction diode relates to the field of power semiconductor, comprising source metal, drain metal, substrate, N-drift region, P-shielding region, isolation oxide layer, gate oxide layer, polysilicon source, polysilicon gate, current spreading layer, P-base region, N-source region, P-plus region. One end of the substrate is in contact with the drain metal, and the other end is in contact with the drift layer; the current spreading layer is arranged on the N-drift region; the P-base region is arranged on the current spreading layer; the N-source region and the P-plus region are arranged side by side on the P-base region; a plurality of trenches are formed in the base region and extend vertically into the drift layer; the left side of the trench is filled with polysilicon gate, and the right side is filled with polysilicon source; the left side, the right side and the bottom of the polysilicon gate are in contact with the gate oxide layer; the left side of the polysilicon source is in contact with the gate oxide layer; the polysilicon source is in contact with the N-drift region to form a heterojunction. The isolation oxide layer is in contact with the source metal, the trench and the N-source region; the trench is in contact with the N-source region. The application improves the switching speed and improves the reverse recovery charge.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a SiC trench MOS device structure with an integrated heterojunction diode. Background Technology

[0002] SiC possesses excellent physical properties such as a wide bandgap, high breakdown voltage, high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity, making it a promising candidate for high-power, high-temperature, and high-frequency power electronics applications. Particularly in the development and application of SiC MOSFETs, compared to Si MOSFETs of the same power rating, SiC MOSFETs exhibit significantly lower on-resistance and switching losses, making them suitable for higher operating frequencies. Furthermore, their high-temperature operating characteristics greatly enhance their high-temperature stability.

[0003] Compared to planar SiC MOSFETs, trench SiC MOSFETs offer improved channel mobility and correspondingly lower on-resistance. However, SiC trench MOSFETs suffer from gate oxide breakdown.

[0004] Like Si MOSFETs, SiC MOSFETs also possess a body diode (parasitic diode) formed by the PN junction. However, because the bandgap of SiC is three times that of Si, the turn-on voltage of the PN diode in SiC MOSFETs is very high (2.5–3V at room temperature), far exceeding that of the body diode in silicon-based power devices (0.7–0.8V at room temperature), and the forward voltage drop (V... F The losses are also relatively high. This results in higher losses when the body diode of the silicon carbide MOSFET is used as a freewheeling diode.

[0005] Therefore, existing technologies have shortcomings and need to be improved. Summary of the Invention

[0006] To overcome the above-mentioned technical problems, the present invention provides a SiC trench MOS device structure with built-in heterojunction diode.

[0007] The present invention provides a SiC trench MOS device structure with an integrated heterojunction diode, comprising a source metal, a drain metal, a substrate, an N-drift region, a P-shielding region, an isolation oxide layer, a gate oxide layer, a polysilicon source, a polysilicon gate, a current spreading layer, a P-base region, an N-source region, and a P-plus region. One end of the substrate is in contact with the drain metal, and the other end is in contact with the N-drift region. The current spreading layer is disposed on the N-drift region, the P-base region is disposed on the current spreading layer, and the N-source region and P-plus region are arranged side-by-side on the P-base region. Multiple trenches are formed in the base region and extend vertically into the drift layer. The isolation oxide layer contacts the source metal, the trenches, and the N-source region, respectively, and the trenches are in contact with the N-source region.

[0008] Preferably, the left side of the trench is filled with a polysilicon gate, and the right side is filled with a polysilicon source. The left, right, and bottom sides of the polysilicon gate 6 are in contact with the gate oxide layer, and the left side of the polysilicon source is in contact with the gate oxide layer. The polysilicon source contacts the N-drift region to form a heterojunction. The trench-type insulating gate structure formed by the gate insulating layer and the trench has a depth ranging from 5 to 10 μm.

[0009] Preferably, the SiC trench MOS device structure with built-in heterojunction diode is characterized in that: the source metal and drain metal are both made of aluminum.

[0010] Preferably, the gate oxide layer is made of silicon dioxide and has a thickness of 40 nm to 150 nm.

[0011] Preferably, the material of the isolation oxide layer is silicon dioxide, and the thickness is 50nm to 5000nm.

[0012] Preferably, both the substrate and the N-drift region material are N-type silicon carbide, wherein the N-type doping concentration of the substrate is greater than the N-type doping concentration of the N-drift region.

[0013] Preferably, the P-shielding region material is SiC with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 / cm -3 The thickness is 1–5 μm.

[0014] Preferably, the current spreading layer material is SiC, the doping type is N-type epitaxial doping, the doping element is nitrogen or phosphorus, and the doping concentration is 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 1–5 μm.

[0015] Preferably, the polysilicon gate is made of polysilicon, which is N-type doped with phosphorus (P) as the doping element, and the doping concentration is 1 × 10⁻⁶. 19 ~1×10 20 cm -3 .

[0016] Preferably, the polycrystalline silicon source is made of polycrystalline silicon, which is N-type doped with phosphorus (P) as the doping element, and the doping concentration is 1 × 10⁻⁶. 19 ~1×10 20 cm -3 It forms a heterojunction by contacting the N-drift region.

[0017] Compared with the prior art, the SiC trench MOS device structure with built-in heterojunction diode of the present invention has the following advantages:

[0018] When the device operates in the first quadrant, the addition of a P-shielding region protects the gate oxide layer and the polysilicon source, ensuring that the breakdown capability does not decrease during breakdown. The addition of a current spreading layer prevents degradation of the conduction characteristics and avoids excessively high on-resistance. Compared with the conventional SiC trench MOS structure, the structure of this invention reduces the coupling area from the gate to the drain, resulting in a significant reduction in Miller capacitance Cgd and gate charge Qg, effectively reducing the switching time and improving the switching speed of the device.

[0019] When the device operates in the third quadrant, compared to the conventional body diode turn-on voltage of 2.7V, this invention features an N-type Poly / N-type SiC heterojunction diode formed by a polysilicon source and an N-drift region. This heterojunction diode has an extremely low barrier, causing the turn-on voltage to drop from 2.7V to 0.5V, which greatly reduces the on-resistance in the third quadrant. Since the heterojunction diode in this invention is a unipolar device while the conventional body diode is a bipolar device, the reverse recovery charge is greatly improved. Attached Figure Description

[0020] Figure 1 This is a simplified diagram of a traditional SiC trench MOS structure.

[0021] Figure 2 This is a simplified structural diagram of the SiC trench MOS device structure with built-in heterojunction diode of the present invention.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1. Source metal; 2. P-plus region; 3. N-source region; 4. Isolation oxide layer; 5. Gate oxide layer; 6. P-polysilicon gate; 7. Polysilicon source; 8. P-base region; 9. Current spreading layer; 10. P-shielding region; 11. N-drift region; 12. Substrate; 13. Drain metal Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0025] Please see Figure 2 This invention provides a SiC trench MOS device structure with an integrated heterojunction diode, including a source metal 1, a drain metal 13, a substrate 12, an N-drift region 11, a P-shielding region 10, an isolation oxide layer 4, a gate oxide layer 5, a polysilicon source 7, a polysilicon gate 6, a current spreading layer 9, a P-base region 8, an N-source region 3, and a P-plus region 2. One end of the substrate 12 is in contact with the drain metal 13, and the other end is in contact with the N-drift region 11. The current spreading layer 9 is disposed on the N-drift region 11, the P-base region 8 is disposed on the current spreading layer 9, and the N-source region 3 and the P-plus region 2 are arranged side-by-side on the P-base region 8. Multiple trenches are formed in the base region and extend vertically into the drift layer. The isolation oxide layer 4 is in contact with the source metal 1, the trenches, and the N-source region 3, respectively. The trenches are in contact with the N-source region 3.

[0026] Furthermore, the left side of the trench is filled with a polysilicon gate 6, and the right side is filled with a polysilicon source 7. The left, right, and bottom sides of the polysilicon gate 6 are in contact with the gate oxide layer 5, and the left side of the polysilicon source 7 is in contact with the gate oxide layer 5. The polysilicon source is in contact with the N-drift region 11 to form a heterojunction. The trench-type insulating gate structure formed by the gate insulating layer and the trench has a depth ranging from 5 to 10 μm.

[0027] Preferably, the SiC trench MOS device structure with built-in heterojunction diode is characterized in that: the source metal 1 and the drain metal 13 are both made of aluminum.

[0028] Preferably, the gate oxide layer 5 is made of silicon dioxide and has a thickness of 40nm to 150nm.

[0029] Preferably, the material of the isolation oxide layer 4 is silicon dioxide, and the thickness is 50nm to 5000nm.

[0030] Preferably, the substrate 12 is N-type doped, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 .

[0031] Preferably, the N-drift region 11 is made of SiC, with N-type epitaxial doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 13 ~1×10 16 cm -3 The thickness is 5–30 μm.

[0032] Preferably, the P-shielding region 10 is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 1–5 μm.

[0033] Preferably, the current spreading layer 9 is N-type doped, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 1–5 μm.

[0034] Preferably, the polysilicon gate 6 is made of polysilicon, which is N-type doped with phosphorus (P) as the doping element, and the doping concentration is 1 × 10⁻⁶. 19 ~~1×10 20 cm -3 .

[0035] Preferably, the polycrystalline silicon source 7 is made of polycrystalline silicon, which is N-type doped with phosphorus (P) as the doping element, and the doping concentration is 1 × 10⁻⁶. 19 ~1×10 20 cm -3 It forms a heterojunction by contacting the N-drift region.

[0036] Preferably, the P-base region 8 is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁸. 17 ~8×10 17 cm -3 The thickness is 0.5 to 1.5 μm.

[0037] Preferably, the N-source region 3 is N-type doped, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0 to 0.5 μm.

[0038] Preferably, the P-plus region 2 is P-type doped, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0 to 0.5 μm.

[0039] Compared with the prior art, the SiC trench MOS device structure with built-in heterojunction diode of the present invention has the following advantages:

[0040] When the device operates in the first quadrant, the addition of the P-shielding region 10 can protect the gate oxide layer 5 and the polysilicon source 7, ensuring that the breakdown capability does not decrease during breakdown. The addition of the current spreading layer ensures that the conduction characteristics do not degrade and the on-resistance is not too high. Compared with the ordinary SiC trench MOS structure, the coupling area from the gate to the drain is reduced, which significantly reduces the Miller capacitance Cgd and the gate charge Qg, effectively reducing the switching time of the device and improving the switching speed of the device.

[0041] When the device operates in the third quadrant, compared to the conventional body diode turn-on voltage of 2.7V, this invention features an N-type Poly / N-type SiC heterojunction diode formed by a polysilicon source 7 and an N-drift region 10. This heterojunction diode has an extremely low barrier, causing the turn-on voltage to drop from 2.7V to 0.5V, which greatly reduces the on-resistance in the third quadrant. Since the heterojunction diode in this invention is a unipolar device while the conventional body diode is a bipolar device, the reverse recovery charge is greatly improved.

[0042] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any modifications, equivalent substitutions and improvements made within the concept of the present invention should be included within the patent protection scope of the present invention.

Claims

1. A SiC trench MOSFET structure with an integrated heterojunction diode, the SiC trench MOSFET structure with an integrated heterojunction diode includes a source metal, a drain metal, a substrate, an N-drift region, a P-shielding region, an isolation oxide layer, a gate oxide layer, a polysilicon source, a polysilicon gate, a current spreading layer, a P-base region, an N-source region, and a P-plus region; one end of the substrate is in contact with the drain metal, and the other end is in contact with the N-drift region; the current spreading layer is disposed on the N-drift region, the P-base region is disposed on the current spreading layer, the N-source region and the P-plus region are arranged side by side on the P-base region, and multiple trenches are formed in the base region and extend vertically into the drift layer; the isolation oxide layer is in contact with the source metal, the trenches and the N-source region respectively, and the trenches are in contact with the N-source region; The trench is filled with a polysilicon gate on the left and a polysilicon source on the right. The left, right, and bottom sides of the polysilicon gate are in contact with the gate oxide layer, the left side of the polysilicon source is in contact with the gate oxide layer, and the polysilicon source is in contact with the N-drift region to form a heterojunction.

2. The SiC trench MOS device structure with built-in heterojunction diode as described in claim 1, characterized in that: Both the source metal and the drain metal are made of aluminum.

3. The SiC trench MOS device structure with built-in heterojunction diode as described in claim 1, characterized in that: The gate oxide layer is made of silicon dioxide and has a thickness of 40nm to 150nm.

4. The SiC trench MOS device structure with built-in heterojunction diode as described in claim 1, characterized in that: Both the substrate and the N-drift region are made of N-type silicon carbide, wherein the N-type doping concentration of the substrate is greater than that of the drift layer.

5. The SiC trench MOS device structure with built-in heterojunction diode as described in claim 1, characterized in that: The P-shielding region is SiC with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 / cm -3 The thickness is 1–5 μm.

6. The SiC trench MOS device structure with built-in heterojunction diode as described in claim 1, characterized in that: The current spreading layer is SiC, doped using N-type epitaxial doping, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 1–5 μm.

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