A gallium oxide field effect transistor device and a method of manufacturing the same

Abstract

The application provides a gallium oxide field effect transistor device and a preparation method thereof. The device comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer. The n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a portion between the drain electrode and the source electrode. The fin channel is arranged between the drain electrode and the first channel. The cross section of the fin channel is a trapezoid pointing to the source electrode. The vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connecting area of the fin channel and the first channel. P-type oxide dielectric layers are filled on both sides of the fin channel between the n-type gallium oxide channel layer and the gate dielectric layer. The application can reduce the size of the fin channel, deplete the carriers of the P-type dielectric channel, reduce the peak electric field, and improve the breakdown voltage of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a gallium oxide field effect transistor device and a preparation method thereof. BACKGROUND

[0002] Power electronic devices are mainly used for power conversion and circuit control of power equipment, and are the core devices for power processing. At present, the global environment and resource problems are facing severe challenges, and various countries have successively promulgated energy-saving and emission-reducing policies. As the core devices for power control and conversion of industrial facilities, household appliances and other equipment, power semiconductor industry will face new technical challenges and development opportunities.

[0003] Silicon-based semiconductor devices are the most commonly used power devices in the current power system, and their performance has been quite perfect and close to the theoretical limit determined by their material properties, making the power density growth tend to be saturated.

[0004] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional silicon-based power devices in certain specific fields.

[0005] As a new semiconductor material, super-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga figure of merit and cost. The Baliga figure of merit is usually used internationally to represent the degree to which a material is suitable for power devices. For example, the Baliga figure of merit of β-Ga2O3 material is 4 times that of gallium nitride material, 10 times that of silicon carbide material, and 3444 times that of silicon material. Under the same voltage resistance condition, the on-resistance of β-Ga2O3 power device is lower, the power consumption is smaller, and the power loss during device operation can be greatly reduced.

[0006] Since the first gallium oxide metal-oxide-semiconductor field-effect transistor (Ga2O3 MOSFET) device was developed by the National Institute of Information and Communications Technology (NICT) of Japan in 2013, researchers have continuously improved the performance of Ga2O3 MOSFET devices by improving the quality of Ga2O3 crystal materials and optimizing device manufacturing processes, including optimizing channel layer doping, ohmic contact and Schottky contact processes, and gate field plate structure and other methods. In 2016, NICT used Al2O3 as a gate dielectric and combined with a gate field plate structure to prepare a Ga2O3 MOSFET device with a breakdown voltage of 750V. In 2019, ETRI used a source field plate structure, and during the test process, the device was isolated from air breakdown by a fluorinated liquid, and the device had a breakdown voltage of 2320V. In 2020, Buffalo used SU-8 passivation, and the device had a breakdown of 8000V.

[0007] However, the breakdown voltage and on-state characteristics of the Ga2O3 field effect transistor (FET) devices reported so far are still far below the expected values of the material. SUMMARY

[0008] The embodiments of the present application provide a gallium oxide field effect transistor device and a preparation method thereof, so as to further improve the breakdown voltage of the existing gallium oxide field effect transistor.

[0009] In a first aspect, the embodiments of the present application provide a gallium oxide field effect transistor device, comprising:

[0010] a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer corresponds to a part between the drain electrode and the source electrode, and includes a first channel and at least one fin channel; the first channel is deviated to the side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin channel is a trapezoid pointing to the source electrode; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection area of the fin channel and the first channel; and a P-type oxide dielectric layer is filled between the n-type gallium oxide channel layer and the gate dielectric layer and on both sides of the fin channel.

[0011] In a possible implementation, the material of the P-type oxide dielectric layer includes NiO x , SnO2, CuO x , MnO x , FeO x , CuMO2 or ZnM2O4.

[0012] In a possible implementation, the thickness of the P-type oxide dielectric layer ranges from 10 nanometers to 1000 nanometers.

[0013] In a possible implementation, the thickness of the P-type oxide dielectric layer is determined by the flat plane formed by filling the fin channel on both sides.

[0014] In a possible implementation, the doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

[0015] In a second aspect, the embodiments of the present application provide a preparation method of a gallium oxide field effect transistor device, comprising:

[0016] growing an n-type gallium oxide channel layer on a substrate.

[0017] preparing a drain electrode and a source electrode on the n-type gallium oxide channel layer.

[0018] A mask is prepared on a portion of the surface of the n-type gallium oxide channel layer between the drain electrode and the source electrode; the mask comprises a first channel mask and at least one fin channel mask; the first channel mask is biased toward the source electrode side; the fin channel mask is arranged between the drain electrode and the first channel mask; the cross section of the fin channel mask is trapezoidal, pointing toward the source electrode.

[0019] The n-type gallium oxide channel layer is etched to obtain a fin channel and a first channel.

[0020] A P-type oxide dielectric layer is prepared to fill both sides of the fin channel.

[0021] A gate dielectric layer is prepared on the surface of the fin channel and the first channel.

[0022] A gate electrode is prepared on the gate dielectric layer; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel.

[0023] In a possible implementation, the mask is photoresist; after the n-type gallium oxide channel layer is etched to obtain a fin channel and a first channel, the mask is retained.

[0024] Correspondingly, the preparation of the P-type oxide dielectric layer to fill both sides of the fin channel comprises:

[0025] A P-type oxide dielectric layer is grown on the surface of the device.

[0026] The P-type oxide dielectric layer on the surface of the mask is removed by a stripping process to obtain a P-type oxide dielectric layer filling both sides of the fin channel.

[0027] In a possible implementation, the material of the P-type oxide dielectric layer comprises NiO x , SnO2, CuO x , MnO x , FeO x , CuMO2 or ZnM2O4.

[0028] In a possible implementation, the thickness of the P-type oxide dielectric layer ranges from 10 nanometers to 1000 nanometers.

[0029] In a possible implementation, the thickness of the P-type oxide dielectric layer is determined by flattening the fin channel on both sides to form a plane.

[0030] In a possible implementation, the doping concentration of the n-type gallium oxide channel layer gradually decreases from the lower layer to the upper layer.

[0031] The embodiment of the present application provides a gallium oxide field effect transistor device, which comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer corresponds to a part between the drain electrode and the source electrode, and comprises a first channel and at least one fin channel; the first channel is deviated to one side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin channel is a trapezoid pointing to the source electrode; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connecting area of the fin channel and the first channel; and a P-type oxide dielectric layer is filled between the n-type gallium oxide channel layer and the gate dielectric layer and on both sides of the fin channel. Through the trapezoidal fin channel structure, the gate electrode has a higher surface area, the gate control capability is improved, the threshold voltage is increased, and the breakdown voltage is improved; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, so that the peak field strength of the device is reduced, and the breakdown voltage of the device is improved; the size of the fin channel below the endpoint of the gate electrode close to the drain electrode is reduced, the peak electric field is reduced, the breakdown caused by the peak electric field is avoided, and the breakdown voltage of the device is improved; the P-type oxide dielectric can deplete the carriers of the channel, so that the peak field strength of the device is reduced, the threshold voltage is increased, and the breakdown voltage is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a structure schematic diagram of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0034] Figure 2 It is a top view of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0035] Figure 3 It is a cross-sectional view of a channel layer of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0036] Figure 4 It is a cross-sectional view of another channel layer of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0037] Figure 5 It is a cross-sectional view of a third channel layer of a gallium oxide field effect transistor device provided by the embodiment of the present application;

[0038] Figure 6 is a flow chart of a preparation method of a gallium oxide field effect transistor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative work should fall within the scope of protection of the present application.

[0040] The terms "include", "comprise" and other any variants thereof in the specification and claims of the present application and the above-mentioned accompanying drawings refer to "including but not limited to", and are intended to cover non-exclusive inclusion, and are not limited to the examples listed in the text. In addition, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order.

[0041] The implementation of the present application will be described in detail below with reference to the specific accompanying drawings:

[0042] Figure 1 is a structure schematic diagram of a gallium oxide field effect transistor device provided by an embodiment of the present application, corresponding to Figure 2 B-B cross section; Figure 2 is a top view of a gallium oxide field effect transistor device provided by an embodiment of the present application; Figure 3 is a cross-sectional view of a gallium oxide field effect transistor device channel layer provided by an embodiment of the present application, corresponding to Figure 1 A-A cross section. Referring to Figure 1 , Figure 2 and Figure 3 , the gallium oxide field effect transistor device comprises: a substrate 1, an n-type gallium oxide channel layer 2 provided on the substrate 1, a drain electrode 3 and a source electrode 4 provided on the n-type gallium oxide channel layer 2, a gate dielectric layer 5 provided between the drain electrode 3 and the source electrode 4, and a gate electrode 6 provided on the gate dielectric layer 5; the n-type gallium oxide channel layer 2 corresponding to the portion between the drain electrode 3 and the source electrode 4 comprises a first channel 21 and at least one fin channel 22; the first channel 21 is biased to the side of the source electrode 4; the fin channel 22 is provided between the drain electrode 3 and the first channel 21; the cross section of the fin channel 22 is a trapezoid pointing to the source electrode 4; the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin channel 22 and the first channel 21; a P-type oxide dielectric layer 7 is filled between the n-type gallium oxide channel layer 2 and the gate dielectric layer 5 on both sides of the fin channel 22.

[0043] A trapezoid is a quadrilateral with only one pair of parallel sides; the two parallel sides are the bases of the trapezoid; the longer base is the lower base of the trapezoid, and the shorter base is the upper base of the trapezoid; the other two sides are the legs of the trapezoid; the vertical segment between the two bases is the height of the trapezoid. The trapezoid pointing towards the source electrode 4, i.e., the direction from the lower base to the upper base of the trapezoid points towards the source electrode 4.

[0044] The breakdown voltage is a key parameter of power electronic devices, and the breakdown of gallium oxide field effect transistors usually occurs below the gate electrode 6, because the traditional rectangular gate electrode 6 has a sharp peak electric field below the side close to the drain, and the breakdown of the device also often occurs in the area of the gate electrode 6 close to the drain. The P-type oxide dielectric layer 7 is filled on both sides of the fin-shaped channel 22 between the n-type gallium oxide channel layer 2 and the gate dielectric layer 5, forming a P-type heterostructure, which can deplete the carriers in the channel, thereby reducing the peak field strength of the device, increasing the threshold voltage, and improving the breakdown voltage. For example, when the number of fin-shaped channels 22 is 1, the P-type oxide dielectric layer 7 is filled on both sides of the fin-shaped channel 22 to the edge of the device; for example, when the number of fin-shaped channels 22 is greater than or equal to 2, the P-type oxide dielectric layer 7 is filled between the fin-shaped channels 22 and on both sides of the fin-shaped channels 22 to the edge of the device.

[0045] In an optional embodiment, the material of the P-type oxide dielectric layer 7 includes NiO x , SnO2, CuO x , MnO x , FeO x , CuMO2, or ZnM2O4.

[0046] In an optional embodiment, the thickness of the P-type oxide dielectric layer 7 ranges from 10 nanometers to 1000 nanometers.

[0047] In an optional embodiment, the thickness of the P-type oxide dielectric layer 7 is determined by the flat surface formed by filling the P-type oxide dielectric layer 7 on both sides of the fin-shaped channel 22.

[0048] The first channel 21 is the portion of the n-type gallium oxide channel layer 2 on the side close to the source electrode 4. For example, the thickness of the first channel 21 is consistent with the thickness of the n-type gallium oxide channel layer 2.

[0049] Figure 4 is another cross-sectional view of the gallium oxide field effect transistor device channel layer provided by the embodiments of the present application; refer to Figure 4 :

[0050] In an optional embodiment, the portion of the n-type gallium oxide channel layer 2 between the drain electrode 3 and the source electrode 4 includes the first channel 21 and a plurality of fin-shaped channels 22; the plurality of fin-shaped channels 22 are distributed equidistantly along the direction perpendicular to the line connecting the drain electrode 3 and the source electrode 4. For example, the number of fin-shaped channels 22 is 3.

[0051] In an optional embodiment, the length of the lower base of the cross-section trapezoid of the fin-shaped channel 22 towards the drain electrode 3 ranges from 300 nm to 4000 nm; the length of the upper base of the cross-section trapezoid of the fin-shaped channel 22 towards the source electrode 4 ranges from 200 nm to 2000 nm; the angle between the lower base and the waist of the cross-section trapezoid of the fin-shaped channel 22 ranges from 5° to 85°.

[0052] Exemplarily, the thickness of the fin-shaped channel 22 is uniform. The fin-shaped channel 22 with uniform thickness is easier to be implemented in the manufacturing process than the fin-shaped channel 22 with non-uniform thickness. Exemplarily, the thickness of the fin-shaped channel 22 is less than or equal to the thickness of the n-type gallium oxide channel layer 2; exemplarily, the thickness of the fin-shaped channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.

[0053] Exemplarily, the thickness of the fin-shaped channel 22 decreases from the drain electrode 3 to the source electrode 4; exemplarily, the thickness changes in a gradient manner; exemplarily, the thickness changes in a continuous gradient manner. The thickness of the fin-shaped channel 22 decreases from the drain electrode 3 to the source electrode 4, the size of the fin-shaped channel 22 under the end point of the gate electrode 6 close to the drain electrode decreases, the sharp peak electric field is reduced, the breakdown caused by the sharp peak electric field is avoided, and the breakdown voltage of the device is improved.

[0054] The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin-shaped channel 22 and the first channel 21, that is, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 towards the source electrode 4 and the part of the first channel 21 towards the drain electrode 3. Among them, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 towards the source electrode 4, and cannot cover the part of the fin-shaped channel 22 towards the drain electrode 3; if the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin-shaped channel 22 towards the drain electrode 3, the sharp peak electric field of the channel close to the drain electrode 3 side of the gate electrode 6 cannot be inhibited, and the function of reducing the sharp peak electric field and improving the breakdown voltage cannot be achieved.

[0055] Exemplarily, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers 50% of the part of the fin-shaped channel 22 towards the source electrode 4 and 50% of the part of the first channel 21 towards the drain electrode 3.

[0056] Correspondingly, the gate electrode 6 covers the part of the gate dielectric layer 5 corresponding to the part of the fin-shaped channel 22 towards the source electrode 4, and the part of the gate dielectric layer 5 corresponding to the part of the first channel 21 towards the drain electrode 3.

[0057] The embodiment provided by the application makes the gate electrode 6 have higher surface area by the three-dimensional ladder-shaped fin channel 22 structure, improves the gate control ability, increases the threshold voltage, and improves the breakdown voltage; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown voltage of the device; the size of the fin channel 22 under the end point of the gate electrode 6 close to the drain electrode is reduced, the peak electric field is reduced, the breakdown caused by the peak electric field is avoided, and the breakdown voltage of the device is improved; the P-type oxide medium can deplete the carriers of the channel, thereby reducing the peak field strength of the device, increasing the threshold voltage, and improving the breakdown voltage.

[0058] Figure 5 is a third cross-sectional view of a gallium oxide field effect transistor device channel layer provided by the embodiment of the application; refer to Figure 5 :

[0059] In an optional embodiment, the n-type gallium oxide channel layer 2 includes the first channel 21 and at least one fin channel 22 corresponding to the portion between the drain electrode 3 and the source electrode 4; the n-type gallium oxide channel layer 2 further includes the second channel 23 corresponding to the portion between the drain electrode 3 and the fin channel 22.

[0060] In an optional embodiment, the n-type gallium oxide channel layer 2 includes the first channel 21 and a plurality of fin channels 22 corresponding to the portion between the drain electrode 3 and the source electrode 4; the plurality of fin channels 22 are equidistantly distributed along the direction perpendicular to the connection direction of the drain electrode 3 and the source electrode 4; the n-type gallium oxide channel layer 2 further includes the second channel 23 corresponding to the portion between the drain electrode 3 and the fin channel 22.

[0061] For example, the size of the second channel 23 along the direction perpendicular to the connection direction of the drain electrode 3 and the source electrode 4 is greater than the sum of the sizes of the first channel 21 and the fin channel 22. For example, the size of the second channel 23 along the direction perpendicular to the connection direction of the drain electrode 3 and the source electrode 4 is greater than twice the sum of the sizes of the first channel 21 and the fin channel 22.

[0062] The embodiment provided by the application improves the high-voltage resistance of the channel layer by increasing the second channel 23, so that the device can withstand higher voltage.

[0063] In an optional embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.

[0064] In an optional embodiment, the thickness of the n-type gallium oxide channel layer 2 ranges from 10 nanometers to 1000 nanometers.

[0065] In an optional embodiment, the doping concentration of the n-type gallium oxide channel layer 2 ranges from 1.0×10 15 cm -3 to 1.0×1020 cm -3 The n-type gallium oxide channel layer 2 is realized by doping silicon or tin in the process of epitaxial growth of gallium oxide.

[0066] In an optional embodiment, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases from the lower layer to the upper layer. There is a strong peak electric field at the end of the channel of the gate electrode 6 biased to the drain electrode 3, which leads to device breakdown; the peak electric field is directly related to the electron concentration of the channel, and the decrease of the concentration can effectively reduce the electric field strength, but it will lead to the deterioration of the device conduction characteristics; the doping concentration gradually decreases from the lower layer to the upper layer of the channel layer, and the electron concentration gradually decreases from the lower layer to the upper layer, which can not affect the conduction characteristics of the device, and can also reduce the peak electric field and improve the breakdown voltage. Illustratively, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases in a gradient from the lower layer to the upper layer.

[0067] In an optional embodiment, the n-type gallium oxide channel layer 2 further includes an undoped gallium oxide layer between the substrate 1 and the n-type gallium oxide channel layer 2.

[0068] In an optional embodiment, the n+ contact layer is further included between the drain electrode 3 and the n-type gallium oxide channel layer 2 and between the source electrode 4 and the n-type gallium oxide channel layer 2 in the vertical projection area of the drain electrode 3 and the source electrode 4 on the n-type gallium oxide channel layer 2. Illustratively, the drain electrode 3 and the source electrode 4 are respectively arranged on the upper surfaces of the two ends of the n-type gallium oxide channel layer 2.

[0069] In an optional embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.

[0070] The gate dielectric layer 5 is arranged between the drain electrode 3 and the source electrode 4 above the n-type gallium oxide channel layer 2; the coverage area of the gate dielectric layer 5 is greater than that of the gate electrode 6, so as to ensure that the gate electrode 6 does not directly contact the n-type gallium oxide channel layer 2, the drain electrode 3 and the source electrode 4, thereby avoiding the leakage of the device.

[0071] In an optional embodiment, the material of the gate dielectric layer 5 is aluminum oxide, hafnium dioxide or silicon dioxide; illustratively, the material of the gate dielectric layer 5 is a composite medium of aluminum oxide and hafnium dioxide.

[0072] In an optional embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.

[0073] In an optional embodiment, the length of the gate electrode 6 along the direction from the drain electrode 3 to the source electrode 4 ranges from 50 nanometers to 10 microns.

[0074] Figure 6 A preparation method of a gallium oxide field effect transistor device is provided for the embodiment of the present application, which is described with reference to Figure 6 The preparation method includes:

[0075] Step S1, growing an n-type gallium oxide channel layer 2 on the substrate 1.

[0076] In an optional embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.

[0077] In an optional embodiment, the thickness of the n-type gallium oxide channel layer 2 ranges from 10 nanometers to 1000 nanometers.

[0078] In an optional embodiment, the doping concentration of the n-type gallium oxide channel layer 2 ranges from 1.0×10 15 cm -3 to 1.0×10 20 cm -3 The n-type gallium oxide channel layer 2 is realized by doping silicon or tin during epitaxial growth of gallium oxide.

[0079] In an optional embodiment, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases from the lower layer to the upper layer. A strong peak electric field exists at the end of the channel where the gate electrode 6 is biased towards the drain electrode 3, leading to device breakdown. The peak electric field is directly related to the electron concentration of the channel, and reducing the concentration can effectively reduce the electric field strength, but it will lead to poor device conduction characteristics. Gradually reducing the doping concentration from the lower layer to the upper layer of the channel layer can gradually reduce the electron concentration from the lower layer to the upper layer, which can not affect the conduction characteristics of the device, but also can reduce the peak electric field and improve the breakdown voltage. Illustratively, the doping concentration of the n-type gallium oxide channel layer 2 gradually decreases in a gradient from the lower layer to the upper layer.

[0080] In an optional embodiment, the substrate 1 and the n-type gallium oxide channel layer 2 further include an undoped gallium oxide layer.

[0081] Step S2, preparing a drain electrode 3 and a source electrode 4 on the n-type gallium oxide channel layer 2.

[0082] Illustratively, the drain electrode 3 and the source electrode 4 are respectively arranged on the upper surfaces of the two ends of the n-type gallium oxide channel layer 2. Illustratively, the electrode metal layer is deposited by electron beam evaporation; the drain electrode 3 and the source electrode 4 are prepared by a photolithography etching process or a photolithography stripping process.

[0083] In an optional embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.

[0084] In an optional embodiment, in the vertical projection area of the drain electrode 3 and the source electrode 4 on the n-type gallium oxide channel layer 2, the drain electrode 3 and the source electrode 4 and the n-type gallium oxide channel layer 2 further include an n+ contact layer; illustratively, the n+ contact layer is prepared by an ion implantation process.

[0085] Step S3, making a mask on the part of the surface of the n-type gallium oxide channel layer 2 corresponding to the part between the drain electrode 3 and the source electrode 4; the mask includes a first channel mask and at least one fin channel mask; the first channel mask is biased to the side of the source electrode 4; the fin channel mask is arranged between the drain electrode 3 and the first channel mask; the cross section of the fin channel mask is a trapezoid pointing to the source electrode 4.

[0086] The trapezoid is a quadrilateral with only one pair of parallel sides; the two parallel sides are the bases of the trapezoid; the longer base is the lower base of the trapezoid, and the shorter base is the upper base of the trapezoid; the other two sides are the legs of the trapezoid; the vertical segment between the two bases is the height of the trapezoid. The trapezoid pointing to the source electrode 4 is that the direction from the lower base to the upper base of the trapezoid points to the source electrode 4.

[0087] In an optional embodiment, the mask is made by a contact photolithography process or an electron beam lithography process. For example, the material of the mask is photoresist.

[0088] In an optional embodiment, the material of the mask is metal. The method for making the metal mask includes:

[0089] By the coating process and the photolithography process, a photoresist pattern opposite to the pattern of the first channel 21 and the fin channel 22 is made on the part of the surface of the n-type gallium oxide channel layer 2 corresponding to the part between the drain electrode 3 and the source electrode 4.

[0090] A metal mask layer is deposited.

[0091] The photoresist is stripped, and a metal mask consistent with the pattern of the first channel 21 and the fin channel 22 is obtained.

[0092] Step S4, etching the n-type gallium oxide channel layer 2 to obtain the fin channel 22 and the first channel 21.

[0093] The area covered by the mask will not be etched; for example, the etching method is a dry etching process.

[0094] For example, the etching depth is consistent. For example, the etching depth is less than or equal to the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin channel 22 is less than or equal to the thickness of the n-type gallium oxide channel layer 2. For example, the etching depth is greater than the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.

[0095] The first channel 21 is the part of the n-type gallium oxide channel layer 2 biased to the side of the source electrode 4. For example, the thickness of the first channel 21 is consistent with the thickness of the n-type gallium oxide channel layer 2.

[0096] Figure 4 is another cross-sectional view of the gallium oxide field effect transistor device channel layer provided by the embodiment of the present application; refer toFigure 4 :

[0097] In an optional embodiment, the n-type gallium oxide channel layer 2 corresponding to the portion between the drain electrode 3 and the source electrode 4 includes a first channel 21 and a plurality of fin channels 22; the plurality of fin channels 22 are equidistantly distributed along a direction perpendicular to the connection direction of the drain electrode 3 and the source electrode 4. For example, the number of fin channels 22 is 3.

[0098] In an optional embodiment, the length of the lower base of the cross-sectional trapezoid of the fin channel 22 on the side of the drain electrode 3 ranges from 300 nm to 4000 nm; the length of the upper base of the cross-sectional trapezoid of the fin channel 22 on the side of the source electrode 4 ranges from 200 nm to 2000 nm; and the included angle between the lower base and the waist of the cross-sectional trapezoid of the fin channel 22 ranges from 5 degrees to 85 degrees.

[0099] For example, the thickness of the fin channel 22 is uniform. The fin channel 22 with uniform thickness is easier to achieve in the manufacturing process than the fin channel 22 with non-uniform thickness. For example, the thickness of the fin channel 22 is less than or equal to the thickness of the n-type gallium oxide channel layer 2; for example, the thickness of the fin channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.

[0100] In an optional embodiment, the fin channel 22 is divided into a plurality of portions in step S3 from the drain electrode 3 to the source electrode 4; a mask corresponding to the plurality of portions into which the fin channel 22 is divided is designed; only one portion of the fin channel 22 is etched each time, and the etching depth increases from the drain electrode 3 to the source electrode 4 in sequence; steps S3 and S4 are repeated to complete the etching of all portions.

[0101] For example, the thickness of the fin channel 22 decreases from the drain electrode 3 to the source electrode 4 in sequence; for example, the thickness changes in a gradient manner; for example, the thickness changes continuously and gradually. The thickness of the fin channel 22 decreases from the drain electrode 3 to the source electrode 4 in sequence, the size of the fin channel 22 under the end point of the gate electrode 6 close to the drain electrode decreases, the sharp peak electric field is reduced, the breakdown caused by the sharp peak electric field is avoided, and the breakdown voltage of the device is improved.

[0102] Step S5, preparing a P-type oxide dielectric layer 7 filling both sides of the fin channel 22.

[0103] In an optional embodiment, the material of the P-type oxide dielectric layer 7 includes NiO x , SnO2, CuO x , MnO x , FeO x , CuMO2 or ZnM2O4.

[0104] In an optional embodiment, the thickness of the P-type oxide dielectric layer 7 ranges from 10 nm to 1000 nm.

[0105] In an optional embodiment, the thickness of the P-type oxide dielectric layer 7 is determined by the planarization of the sides of the fin-shaped channel 22.

[0106] In an optional embodiment, the P-type oxide dielectric layer 7 is grown by sputtering, pulsed laser deposition or atomic layer deposition.

[0107] In an optional embodiment, the mask is photoresist; after etching the n-type gallium oxide channel layer 2 to obtain the fin-shaped channel 22 and the first channel 21, the mask is retained.

[0108] Correspondingly, the preparation of the P-type oxide dielectric layer 7 filling the sides of the fin-shaped channel 22 comprises:

[0109] The P-type oxide dielectric layer 7 is grown on the surface of the device.

[0110] The P-type oxide dielectric layer 7 on the surface of the mask is removed by a lift-off process to obtain the P-type oxide dielectric layer 7 filling the sides of the fin-shaped channel 22.

[0111] The breakdown voltage is a key parameter of power electronic devices. The breakdown of gallium oxide field effect transistors usually occurs below the gate electrode 6, because the traditional rectangular gate electrode 6 has a sharp peak electric field below the side close to the drain, and the breakdown of the device also usually occurs in the area close to the drain of the gate electrode 6. The P-type oxide dielectric layer 7 is filled on both sides of the fin-shaped channel 22 between the n-type gallium oxide channel layer 2 and the gate dielectric layer 5, forming a P-type heterostructure, which can deplete the carriers in the channel, thereby reducing the peak field strength of the device, increasing the threshold voltage, and improving the breakdown voltage. For example, when the number of fin-shaped channels 22 is 1, the P-type oxide dielectric layer 7 is filled on both sides of the fin-shaped channel 22 to the edge of the device; for example, when the number of fin-shaped channels 22 is greater than or equal to 2, the P-type oxide dielectric layer 7 is filled between the fin-shaped channels 22 and on both sides of the fin-shaped channels 22 to the edge of the device.

[0112] Step S6, preparing a gate dielectric layer 5 on the surface of the fin-shaped channel 22 and the first channel 21.

[0113] In an optional embodiment, the gate dielectric layer 5 is prepared on the surface of the fin-shaped channel 22 and the first channel 21 by atomic layer deposition. The gate dielectric layer 5 covers the surface of the first channel 21, the fin-shaped channel 22 and the P-type oxide dielectric layer 7.

[0114] The gate dielectric layer 5 is arranged between the n-type gallium oxide channel layer 2, the drain electrode 3 and the source electrode 4; the coverage area of the gate dielectric layer 5 is larger than that of the gate electrode 6, so as to ensure that the gate electrode 6 does not directly contact the n-type gallium oxide channel layer 2, the drain electrode 3 and the source electrode 4, thereby avoiding the leakage of the device.

[0115] In an alternative embodiment, the material of the gate dielectric layer 5 is aluminum oxide, hafnium dioxide or silicon dioxide; for example, the material of the gate dielectric layer 5 is a composite dielectric of aluminum oxide and hafnium dioxide.

[0116] In step S7, a gate electrode 6 is prepared on the gate dielectric layer 5; the vertical projection of the gate electrode on the n-type gallium oxide channel layer 2 covers the connecting region of the fin-shaped channel 22 and the first channel 21.

[0117] In an alternative embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.

[0118] In an alternative embodiment, the length of the gate electrode 6 in the direction from the drain electrode 3 to the source electrode 4 ranges from 50 nanometers to 10 micrometers.

[0119] The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connecting region of the fin-shaped channel 22 and the first channel 21, i.e., the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the portion of the fin-shaped channel 22 deviated to the source electrode 4 side and the portion of the first channel 21 deviated to the drain electrode 3 side. The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the portion of the fin-shaped channel 22 deviated to the source electrode 4 side, while it cannot cover the portion of the fin-shaped channel 22 deviated to the drain electrode 3 side; if the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the portion of the fin-shaped channel 22 deviated to the drain electrode 3 side, the sharp peak electric field of the channel near the drain electrode 3 side of the gate electrode 6 cannot be inhibited, which cannot achieve the effect of reducing the sharp peak electric field and improving the breakdown voltage.

[0120] For example, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers 50% of the portion of the fin-shaped channel 22 deviated to the source electrode 4 side and 50% of the portion of the first channel 21 deviated to the drain electrode 3 side.

[0121] Correspondingly, the gate electrode 6 covers the portion of the gate dielectric layer 5 corresponding to the fin-shaped channel 22 deviated to the source electrode 4 side and the portion of the gate dielectric layer 5 corresponding to the first channel 21 deviated to the drain electrode 3 side.

[0122] The embodiments provided by the present application make the gate electrode 6 have a higher surface area through the three-dimensional trapezoidal fin-shaped channel 22 structure, improve the gate control capability, increase the threshold voltage and improve the breakdown voltage; the field plate effect of the three-dimensional gate structure makes the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown voltage of the device; the size of the fin-shaped channel 22 under the end point of the gate electrode 6 near the drain electrode is reduced, the sharp peak electric field is reduced, the breakdown caused by the sharp peak electric field is avoided, and the breakdown voltage of the device is improved; the P-type oxide dielectric can deplete the carriers of the channel, thereby reducing the peak field strength of the device, increasing the threshold voltage and improving the breakdown voltage.

[0123] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A gallium oxide field-effect transistor device, characterized in that, The device includes a substrate, an n-type gallium oxide channel layer disposed on the substrate, a drain electrode and a source electrode disposed on the n-type gallium oxide channel layer, a gate dielectric layer disposed between the drain electrode and the source electrode, and a gate electrode disposed on the gate dielectric layer. The n-type gallium oxide channel layer, corresponding to the portion between the drain electrode and the source electrode, includes a first channel and at least one fin channel. The first channel is biased towards the source electrode side; The fin-type channel is disposed between the drain electrode and the first channel; The cross-section of the finned channel is trapezoidal, pointing towards the source electrode. The vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection area between the fin channel and the first channel; wherein, the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the portion of the fin channel biased towards the source electrode and the portion of the first channel biased towards the drain electrode, while not covering the portion of the fin channel biased towards the drain electrode. A P-type oxide dielectric layer is filled between the n-type gallium oxide channel layer and the gate dielectric layer, and on both sides of the fin channel.

2. The gallium oxide field-effect transistor device as described in claim 1, characterized in that, The material of the P-type oxide dielectric layer includes NiO. x SnO2, CuO x MnO x FeO x CuMO2 or ZnM2O4.

3. A gallium oxide field-effect transistor device as described in claim 2, characterized in that, The thickness of the P-type oxide dielectric layer ranges from 10 nanometers to 1000 nanometers.

4. A gallium oxide field-effect transistor device as described in claim 3, characterized in that, The thickness of the P-type oxide dielectric layer is determined by filling the plane formed on both sides of the fin channel.

5. A gallium oxide field-effect transistor device as described in claim 4, characterized in that, The doping concentration of the n-type gallium oxide channel layer gradually decreases from the bottom layer to the top layer.

6. A method for fabricating a gallium oxide field-effect transistor device, characterized in that, include: An n-type gallium oxide channel layer is grown on the substrate; Drain and source electrodes are fabricated on an n-type gallium oxide channel layer; A mask is fabricated on the surface of the n-type gallium oxide channel layer corresponding to the portion between the drain electrode and the source electrode; the mask includes a first channel mask and at least one fin channel mask; the first channel mask is biased towards the source electrode side; the fin channel mask is disposed between the drain electrode and the first channel mask; the cross-section of the fin channel mask is trapezoidal pointing towards the source electrode. The n-type gallium oxide channel layer is etched to obtain a fin channel and a first channel; Prepare a P-type oxide dielectric layer that fills both sides of the fin channel; A gate dielectric layer is prepared on the surfaces of the fin channel and the first channel; A gate electrode is fabricated on the gate dielectric layer; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region between the fin channel and the first channel; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the portion of the fin channel biased towards the source electrode and the portion of the first channel biased towards the drain electrode, while not covering the portion of the fin channel biased towards the drain electrode.

7. The method for fabricating a gallium oxide field-effect transistor device as described in claim 6, characterized in that, The mask is a photoresist; after etching the n-type gallium oxide channel layer to obtain the fin channel and the first channel, the mask is retained; Accordingly, the preparation of the P-type oxide dielectric layer filling both sides of the fin channel includes: A P-type oxide dielectric layer is grown on the device surface; The P-type oxide dielectric layer on the mask surface is removed by a stripping process to obtain a P-type oxide dielectric layer that fills both sides of the fin channel.

8. The method for fabricating a gallium oxide field-effect transistor device as described in claim 7, characterized in that, The material of the P-type oxide dielectric layer includes NiO. x SnO2, CuO x MnO x FeO x CuMO2 or ZnM2O4.

9. The method for fabricating a gallium oxide field-effect transistor device as described in claim 8, characterized in that, The thickness of the P-type oxide dielectric layer ranges from 10 nanometers to 1000 nanometers.

10. The method for fabricating a gallium oxide field-effect transistor device as described in claim 9, characterized in that, The thickness of the P-type oxide dielectric layer is determined by filling the plane formed on both sides of the fin channel.

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