A low-power humidity sensor interface circuit

Abstract

A low-power humidity sensor interface circuit includes: a low-power amplifier, a humidity-sensitive element interface unit coupled to the amplifier, a data conversion logic unit, and a clock control unit; the input end of the interface unit is coupled to the output end and the positive input end of the amplifier to clamp and output a stable data processing voltage, and the output end of the interface unit is coupled to an off-chip humidity-sensitive element, which is used to convert the humidity change value of the off-chip humidity-sensitive element of the circuit to obtain a voltage feedback signal that can be processed by the backend circuit; the clock control unit provides clock signals for the interface unit and the data conversion logic unit to control the working and sleep modes of the sensor interface chip, improve the working efficiency of the interface circuit and reduce the operating power consumption, and overall ensure the stability of the interface circuit connecting sensitive components. The good feasibility improves the stability of the interface circuit and realizes the performance indexes of a small static current and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to a low-power humidity sensor interface circuit. Background Art

[0002] With the continuous development of the field of electronic information technology, the applications of portable electronic products such as wireless communication and signal detection technology are becoming more and more common, and various electronic products have become indispensable in our lives. A sensor is a device that converts continuous analog quantities in nature such as various physical quantities and biological quantities in life into data quantities that are convenient for transmission and processing according to specific rules. A sensor is divided into two parts: an environment-sensitive element and a signal conversion element. Among them, the environment-sensitive conversion element refers to a unit device that can respond to the physical quantity monitored in the environment, and the signal conversion element refers to the unit in the sensor that can convert the physical output of the environment-sensitive element into an electrical signal. The functions of a sensor include information collection, information exchange, and information control. Among many sensor circuits, humidity measurement has important research significance and application value.

[0003] People cannot do without measuring the humidity value in production and life. Humidity sensing technology is the technical foundation of many high-tech fields and has become a high-tech with rapid development and wide application scope in recent years. Humidity sensors are widely used in home electronic products, medical treatment, household appliances, military industry, automotive electronics, automatic control and other fields. Since the measured humidity value is greatly affected by the ambient temperature and the humidity sensor is also easily affected by environmental pollutants when exposed to the external environment, the accuracy and reliability of the measured humidity value are reduced. A so-called low-power humidity sensor interface circuit is a transitional circuit connecting the sensor and the pre-computation circuit. In order to obtain and convert the measured humidity value into an electrical signal that can be effectively recognized by the backend data processing circuit, it is necessary to conduct in-depth research on the sensor interface circuit. Currently, commonly used interface circuits often have problems such as large power consumption and unstable conversion of sensitive elements. In order to overcome these problems of the interface circuit, an interface circuit with high reliability, small static current, low power consumption, and high integration degree to save layout area is the key research target of this application, so that it can be better widely used in various semiconductor products, which is the technical problem to be solved currently. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a highly reliable interface circuit solution to achieve the performance index of small static current and low power consumption, so that it can be widely used in systems such as industry, agriculture, and medical treatment, such as the humidity monitoring of agricultural greenhouse greenhouses, the detection system of the logistics transportation and storage environment and other new-generation monitoring system fields.

[0005] To achieve the above and other related objectives, the low-power humidity sensor interface circuit provided by the present invention includes: a low-power amplifier, a humidity-sensitive element interface unit coupled to the amplifier, a data conversion logic unit, and a clock control unit; the input end of the interface unit is coupled to the output end and the positive input end of the amplifier to clamp and output a stable data processing voltage, and the output end of the interface unit is coupled to an off-chip humidity-sensitive element for converting the humidity change value of the off-chip humidity-sensitive element of the circuit to obtain a voltage feedback signal that can be processed by the subsequent circuit; the clock control unit provides clock signals for the interface unit and the data conversion logic unit to control the working and sleep modes of the sensor interface chip, improve the working efficiency of the interface circuit, and reduce the operating power consumption, thereby ensuring the stable output of the interface circuit connected to the sensitive components as a whole.

[0006] A low-power humidity sensor interface circuit, characterized by comprising: an amplifier for amplifying an input reference signal, with its output end connected to the positive input end to form a feedback structure for clamping the reference voltage signal; and a humidity-sensitive element interface unit, the input end of the humidity-sensitive element interface unit is coupled to the output end of the amplifier, and the output end of the humidity-sensitive element interface unit is coupled to an off-chip humidity-sensitive element for detecting the change in the value of the off-chip humidity-sensitive element and performing a clamping process based on the reference voltage signal to obtain a corresponding feedback signal, and outputting the feedback signal to the amplifier, so that the amplifier adjusts the output signal according to the feedback signal, converting the change in the resistance value of the sensitive device into a voltage signal that meets the processable range of the subsequent circuit and stably outputting it; and a data conversion logic unit, the input end of the data conversion logic unit is coupled to the output end of the humidity-sensitive element interface unit, and the output end directly outputs the converted digital signal, and its internal structure adopts the circuit topology unit of a successive approximation analog-to-digital converter; and a clock control unit, the input end of the clock control unit is connected to an off-chip input clock signal, and the output end is connected to the humidity-sensitive element interface unit and the data conversion logic unit to provide the timing logic for controlling the opening and closing of the internal circuit of the chip system.

[0007] In an embodiment of the present invention, the amplifier circuit is characterized in that the amplifier includes an amplifier with a folded cascode structure having differential input and single-ended output and a bias circuit having dual working modes of on and sleep.

[0008] In an embodiment of the present invention, the humidity-sensitive element interface unit circuit is characterized in that the humidity-sensitive element interface unit clamps the reference voltage at the inverting input end of the amplifier at the output end, converts the resistance values of the humidity-sensitive resistor and the sampling resistor coupled to the output end of the humidity-sensitive element interface unit, and obtains a voltage-sensitive signal related to the humidity value result;

[0009] In an embodiment of the present invention, the data conversion logic unit circuit is characterized in that the data conversion logic unit circuit adopts a classic successive approximation analog-to-digital converter structure to convert the analog signal related to the humidity value transmitted by the humidity interface unit into a digital code for output;

[0010] In an embodiment of the present invention, the clock control unit is characterized in that the clock control unit includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal and a fifth clock signal, wherein the clock frequencies of the second clock signal, the third clock signal, the fourth clock signal and the fifth clock signal are the same; wherein, the frequency of the first clock signal is 2KHz and is provided externally by the chip, the second clock signal is obtained from the first clock signal through a frequency division network, the third clock signal is obtained from the second clock signal through a delay network, the phase of the fourth clock signal is opposite to that of the third clock signal, the fifth clock signal is obtained from the fourth clock signal through a delay network, and the phase of the sixth clock signal is opposite to that of the fifth clock signal.

[0011] In an embodiment of the present invention, the amplifier circuit is characterized in that the amplifier circuit structure is a folded cascode structure with an N-type MOS transistor differential pair input and a single-ended output. The amplifier circuit includes a first resistor, a second resistor, a first transmission gate switch, a second transmission gate switch, a P-type MOS transistor conduction switch, an N-type MOS transistor conduction switch, a first and a second N-type MOS amplification transistors, a first to a ninth N-type MOS mirror transistors and a first to a sixth P-type MOS mirror transistors; the first end of the first transmission gate switch is connected to the end of the first resistor, the second end of the first transmission gate switch is connected to the drain of the N-type MOS transistor conduction switch, and the source of the N-type MOS transistor conduction switch is connected to VSS; the first end of the second transmission gate switch is connected to the upper end of the second resistor, and the second end of the second transmission gate switch is connected to the drain of the P-type MOS transistor conduction switch; the source of the P-type MOS transistor conduction switch is connected to VDD. The gate of the P-type MOS transistor of the first transmission gate is connected to the fifth clock signal, and the gate of the N-type MOS transistor of the first transmission gate is connected to the sixth clock signal; the gate of the P-type MOS transistor of the second transmission gate is connected to the fifth clock signal, and the gate of the N-type MOS transistor of the second transmission gate is connected to the sixth clock signal; the gate of the N-type MOS transistor conduction switch is connected to the fifth clock signal, and the gate of the P-type MOS transistor conduction switch is connected to the sixth clock signal;

[0012] In an embodiment of the present invention, the humidity-sensitive element interface unit is characterized in that the optimal value of the sampling resistor of the humidity-sensitive element is selected as 32 kΩ. The humidity-sensitive element interface unit includes a pull-up conducting P-type MOS transistor, a Miller compensation capacitor, a load capacitor, a load resistor, a sampling resistor, an inverter, a first P-type MOS transistor, and a second P-type MOS transistor; the gate of the P-type MOS transistor is connected to the drain of the pull-up conducting P-type MOS transistor, and the source of the pull-up conducting P-type MOS transistor is connected to the source of the P-type MOS transistor and commonly connected to VDD; the Miller compensation capacitor is connected between the gate and the drain of the P-type MOS; both ends of the load resistor are connected between the drain of the P-type MOS and VSS; the input end of the inverter is connected to the non-inverting input end of the amplifier, and the output end of the inverter is connected to an off-chip PAD point and a load capacitor; the gate of the pull-up conducting P-type MOS transistor is connected to the second clock signal, and the inverter is connected to the third clock signal; the output end of the sensitive element interface unit is connected between the PAD point and the sampling resistor.

[0013] As described above, the low-power humidity sensor interface circuit provided by the present invention sets a transmission gate and a MOS switch in the bias circuit of the folded cascode amplifier, and responds to different gating clock signals transmitted by the clock generation circuit to perform two working modes of startup and sleep, reducing the power consumption of the operational amplifier that accounts for the largest proportion in the interface circuit. In the interface circuit unit, the power consumption is minimized by timing control of the pull-up conducting switch in the interface circuit. Through the feedback structure connected between the output end and the non-inverting input end of the operational amplifier, a corresponding feedback signal is obtained, thereby clamping the reference voltage at a fixed potential and improving the stability of the sensitive signal output by the interface circuit. Brief Description of the Drawings

[0014] Figure 1 It shows a schematic diagram of the chip system structure design of the low-power humidity sensor interface circuit according to the present invention in an embodiment;

[0015] Figure 2 It shows a schematic diagram of the chip PADRING design of the low-power humidity sensor interface circuit according to the present invention in an embodiment;

[0016] Figure 3 It shows a schematic diagram of the structure of the amplifier according to the present invention in an embodiment;

[0017] Figure 4 It shows a schematic diagram of the structure of the humidity-sensitive element interface unit and the analog-to-digital converter unit according to the present invention in an embodiment;

[0018] Figure 5 It shows the change curve of the value of the voltage Vx at the first output end of the humidity-sensitive element interface unit according to the present invention with respect to humidity

[0019] Figure 6 Shows the schematic diagram of the clock control module described in the present invention in an embodiment;

[0020] Figure 7 Shows the schematic diagram of the frequency division by two circuit in the clock control module described in the present invention in an embodiment;

[0021] Figure 8 Shows the schematic diagram of the delay module in the clock control module described in the present invention in an embodiment

[0022] Figure 9 Shows the trigger timing diagram of the clock control module described in the present invention in an embodiment;

[0023] Figure 10 Shows the delay waveform diagram of the delay module described in the present invention in an embodiment;

[0024] Figure 11 Shows the clock and current consumption simulation result diagram of the humidity sensor interface circuit described in the present invention in an embodiment;

[0025] Description of component labels

[0026] 1 Amplifier

[0027] 2 Humidity sensing element interface unit

[0028] 3 Data conversion logic unit

[0029] 4 Clock control unit

[0030] 31 Frequency division by two circuit

[0031] 32 Delay module

[0032] Mp1 to Mp13 First PMOS transistor to Thirteenth PMOS transistor

[0033] Mn1 to Mn20 First NMOS transistor to Twentieth NMOS transistor

[0034] Φ1 to Φ6 First clock signal to Sixth clock signal

[0035] Vref Reference voltage

[0036] Vcmfb Feedback voltage

[0037] Cc Miller compensation capacitor

[0038] C L Load capacitance

[0039] CS Sampling capacitor

[0040] RL Load resistance

[0041] R0 Sampling resistance

[0042] SAR A / D Successive approximation analog-to-digital converter

[0043] I_bias Bias current

[0044] CHR03 Off-chip humidity sensor

[0045] AVDD, AVSS Analog power supply, analog ground

[0046] DVDD, DVSS Digital power supply, digital ground

[0047] D0 - D16 Digital code output bit 0 to bit 16

[0048] COM_FLG Digital code flag bit Detailed implementation manners

[0049] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0050] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0051] The present invention provides a low-power humidity sensor interface circuit solution, which achieves the performance indicators of low static current and low power consumption. It is used to monitor the change of the sensitive value of an off-chip humidity-sensitive element, and performs clamping processing based on a reference voltage signal to obtain a corresponding feedback signal, and outputs the feedback signal to the amplifier, so that the amplifier adjusts the output signal according to the feedback signal, and stably outputs the humidity-sensitive value as a voltage feedback signal that can be processed by the backend circuit; the clock start signal controls two working modes of the sensor interface chip, namely the humidity monitoring mode and the static sleep mode, which improves the working efficiency of the interface circuit and reduces the operating power consumption, enabling it to be widely used in systems such as industry, agriculture, and medical care, such as the humidity monitoring of agricultural greenhouses, the detection system of the logistics transportation and storage environment, and other new-generation monitoring system fields. The following will introduce in detail with specific embodiments.

[0052] Please refer to Figure 1 , which shows a schematic diagram of the chip system structure design of the low-power humidity sensor interface circuit solution provided by the present invention in an embodiment. As Figure 1 shown, the low-power humidity sensor interface circuit includes: an amplifier 1, a humidity-sensitive element interface unit 2 coupled to the amplifier 1, a clock control unit 3, and a data conversion logic unit 4.

[0053] Among them, the amplifier 1 includes a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal. The first input terminal of the amplifier 1 is connected to a first voltage signal. The second input terminal of the amplifier 1 is connected to the second input terminal of the humidity-sensitive element interface unit 2, which is used to clamp the first voltage signal at a fixed potential in the travel feedback loop. The third input terminal of the amplifier 1 is connected to a bias current to provide a bias voltage that enables the amplifier's bias circuit to operate normally. The first input terminal and the second input terminal of the humidity-sensitive element interface unit 2 are respectively coupled to the first output terminal and the second input terminal of the amplifier 1, which is used to detect the corresponding feedback signal of the amplifier 1 and output the feedback signal to the amplifier, so that the amplifier adjusts the output signal according to the feedback signal, and stably outputs the humidity-sensitive value as a voltage feedback signal that can be processed by the subsequent circuit. The first output terminal of the humidity-sensitive element interface unit 2 is connected to the off-chip humidity-sensitive element and the first input terminal of the data conversion logic unit 4, which is used to obtain the change of the humidity-sensitive value and input it to the data conversion logic unit 4, and convert the analog voltage signal into a digital code for output. The clock control unit 3 includes a first input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The first input terminal of the clock control unit 3 is connected to a first clock signal. The first output terminal of the clock control unit 3 is connected to the fourth input terminal of the amplifier 1 to provide a gating signal to control the specific working mode of the amplifier 1. The second output terminal and the third output terminal of the clock control unit 3 are connected to the third and fourth input terminals of the humidity-sensitive element interface unit 2 to control the on and off of the humidity-sensitive element interface unit 2 circuit. The data conversion logic unit 4 includes a first input terminal, a second input terminal, and first to eighteenth output terminals. The first input terminal of the data conversion logic unit 4 is connected to the first output terminal of the humidity-sensitive element interface unit 2 to obtain the processed analog voltage signal. The second input terminal of the data conversion logic unit 4 is connected to the fourth output terminal of the clock control unit 3 to obtain the working clock signal. The first to eighteenth output terminals of the data conversion logic unit 4 are the digital codes output after converting the analog signal.

[0054] Please refer to Figure 2 , which shows the chip PAD RING design layout schematic diagram of the low-power humidity sensor interface circuit described in the present invention in an embodiment. The chip PAD RING design layout of the low-power humidity sensor interface circuit in an embodiment includes a source terminal, an input terminal, and an output terminal. As Figure 2As described above, the analog source is placed at the upper left position of the loop and includes AVDD, AVSS, AVDDP, and AVSSP, where AVSSP and AVDDP are ports for powering the PAD points; the digital source is at the upper left position of the loop and includes DVDD, DVSS, DVDDP, and DVSSP, where DVSSP and DVDDP are ports for powering the PAD points. During the design process, it is placed at the lower end of the loop away from the analog source to avoid excessive noise interference and affect the numerical accuracy of the output; the input terminal is placed on the left side of the loop and includes a reference voltage (Vref), a bias current (Ibias), an off-chip humidity-sensitive component (here, a specific example, the CHR03 humidity-sensitive resistor is cited), and a first clock signal (CLK); the output terminal is placed on the right side and includes COM_FLG, D0 to D16, where COM_FLG is a strobe signal for controlling the output of D0 to D16; 0 and 1 placed at the upper end of the loop are idle bits.

[0055] Please refer to Figure 3 , showing the structural schematic diagram of the amplifier 1 described in the present invention in an embodiment as Figure 3As described above, the amplifier 1 has an amplifier with a folded cascode structure of differential input and single-ended output and a bias circuit with two operating modes of on and sleep. It includes: a first resistor R1, a second resistor R2, a first PMOS transistor Mp1 to a ninth PMOS transistor Mp9, and a first NMOS transistor Mn1 to a fourteenth NMOS transistor Mn14. Among them, the sources of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are connected, and are connected to the ground via the drain of the ninth NMOS transistor Mn9; the gate of the first NMOS transistor Mn1 is connected to the first input terminal of the amplifier 1; the gate of the second NMOS transistor Mn2 is connected to the second input terminal of the amplifier 1; the first input terminal and the second input terminal of the amplifier 1 are used to respectively access the input reference voltage signal Vref and the feedback signal of the first output terminal of the amplifier 1; the gates of the third NMOS transistor Mn3, the fourth NMOS transistor Mn4, the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6 are connected, wherein the drain of the third NMOS transistor Mn3 is connected to the lower end of the first resistor R1, the upper end of the first resistor is connected to the third input terminal of the amplifier for receiving the bias current signal Ibias, and the upper end of the first resistor is connected to the gate of the third NMOS transistor Mn3; the gates of the seventh NMOS transistor Mn7, the eighth NMOS transistor Mn8, the ninth NMOS transistor Mn9, the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11 are connected, and the sources of the seventh NMOS transistor Mn7, the eighth NMOS transistor Mn8, the ninth NMOS transistor Mn9, the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11 are connected to the ground; the sources of the third NMOS transistor Mn3, the fourth NMOS transistor Mn4, the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6 are connected to the drains of the seventh NMOS transistor Mn7, the eighth NMOS transistor Mn8, the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11; the gates of the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11 are connected to the drain of the fifth NMOS transistor Mn5; the drain of the fourth NMOS transistor Mn4 is connected to the lower end of the second resistor, and the upper end of the second resistor is connected to the drain of the first PMOS transistor Mp1; the gates of the first PMOS transistor Mp1, the second PMOS transistor Mp2 and the third PMOS transistor Mp3 are connected; the gates of the fourth PMOS transistor Mp4, the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are connected; among them, the sources of the first PMOS transistor Mp1, the second PMOS transistor Mp2 and the third PMOS transistor Mp3 are connected to the drains of the fourth PMOS transistor Mp4, the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6; the sources of the fourth PMOS transistor Mp4, the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 are connected to VDD.The gate of the twelfth NMOS transistor Mn12 is connected to the fifth clock signal, the source of the twelfth NMOS transistor Mn12 is connected to the ground, and the drain of the twelfth NMOS transistor Mn12 is connected to the gate of the seventh NMOS transistor Mn7; the gate of the ninth PMOS transistor Mp9 is connected to the sixth clock signal, the source of the ninth PMOS transistor Mp9 is connected to VDD, and the drain of the ninth PMOS transistor Mp9 is connected to the gate of the fourth PMOS transistor Mp4; the drain and source of the seventh PMOS transistor Mp7 are respectively connected to the source and drain of the thirteenth NMOS transistor Mn13 to form a first transmission gate switch structure. The left end of the first transmission gate switch structure is connected to the lower end of the first resistor, and the right end of the first transmission gate switch structure is connected to the gate of the seventh NMOS transistor Mn7. The gate of the seventh PMOS transistor Mp7 is connected to the fifth clock signal, and the gate of the thirteenth NMOS transistor Mn13 is connected to the sixth clock signal; the drain and source of the eighth PMOS transistor Mp8 are respectively connected to the source and drain of the fourteenth NMOS transistor Mn14 to form a second transmission gate switch structure. The left end of the second transmission gate switch structure is connected to the upper end of the second resistor, and the right end of the second transmission gate switch structure is connected to the gate of the fourth PMOS transistor Mp7. The gate of the eighth PMOS transistor Mp8 is connected to the fifth clock signal, and the gate of the fourteenth NMOS transistor Mn14 is connected to the sixth clock signal;

[0056] In this embodiment, the fourth NMOS transistor Mn4 mirrors the current of the third NMOS transistor Mn3 at a ratio of 1:1, and the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6 mirror the current of the fourth NMOS transistor Mn4 at a ratio of 1:5; the eighth NMOS transistor Mn8 mirrors the current of the seventh NMOS transistor Mn7 at a ratio of 1:1, the ninth NMOS transistor Mn9 mirrors the current of the eighth NMOS transistor Mn8 at a ratio of 1:10, and the tenth NMOS transistor Mn10 and the eleventh NMOS transistor Mn11 mirror the current of the eighth NMOS transistor Mn8 at a ratio of 1:10; the second PMOS transistor Mp2 and the third PMOS transistor Mp3 mirror the current of the first PMOS transistor Mp1 at a ratio of 1:5; the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp6 mirror the current of the fourth PMOS transistor Mp4 at a ratio of 1:5; the ninth PMOS transistor Mn9 and the twelfth NMOS transistor Mn12 are respectively used as the pull-up switch and the pull-down switch; the clock control unit 3 is a falling-edge trigger circuit. When the second clock signal is at a low level, the eleventh PMOS transistor Mp11 in the humidity-sensitive interface unit 2 is turned on, pulling the gate potential of the tenth PMOS transistor Mp10 to a high level. At this time, the tenth PMOS transistor Mp10 is in a cut-off state. In order to reduce the power consumption of the humidity detection circuit to the maximum, the synchronous amplifier 1 disconnects from the working state and enters the sleep state. Therefore, the fifth clock signal and the sixth clock signal are introduced and connected to the first transmission gate switch and the second transmission gate switch; when the first clock signal is at a high level, the fourth clock signal is at a low level, the fifth clock signal is at a high level, and the twelfth NMOS transistor Mn12 is turned on. At this time, the gate potentials of the seventh NMOS transistor Mn7 and the eighth NMOS transistor Mn8 in the amplifier 1 are pulled to a low level. At this time, the seventh NMOS transistor Mn7 and the eighth NMOS transistor Mn8 are disconnected. At this time, the gate of the seventh PMOS transistor Mp7 in the first transmission gate circuit is at a high potential, and the seventh PMOS transistor Mp7 enters the cut-off state. And at this time, the gate of the thirteenth NMOS transistor Mn13 in the first transmission gate circuit is at a low potential, and the thirteenth NMOS transistor Mn13 enters the cut-off state. At this time, the first transmission gate circuit can cut off the bias current and avoid the leakage current of the twelfth NMOS transistor Mn12 that is turned on when the operational amplifier is not working.Similarly, when the fourth clock signal is at a low level, the sixth clock signal is at a low level, and the ninth PMOS transistor Mp9 is turned on. At this time, the gate potentials of the fourth PMOS transistor Mp4 and the fifth PMOS transistor Mp5 in the amplifier 1 are pulled to a high level. At this time, the fourth PMOS transistor Mp4, the fifth PMOS transistor Mp5, and the sixth PMOS transistor Mp6 are turned off. At this time, the gate of the eighth PMOS transistor Mp8 in the second transmission gate circuit is at a high potential, and the eighth PMOS transistor Mp8 enters the cut-off state. Also, at this time, the gate of the fourteenth NMOS transistor Mn14 in the second transmission gate circuit is at a low potential, and the fourteenth NMOS transistor Mn14 enters the cut-off state. At this time, the second transmission gate circuit can cut off the bias current and avoid leakage current when the operational amplifier is not working.

[0057] Please refer to Figure 4 , showing the structural schematic diagram of the humidity sensing element interface unit 2 and the analog-to-digital converter unit 3 in an embodiment. As Figure 3 described, the humidity sensing element interface unit 2 and the analog-to-digital converter unit 3 include: a first input terminal, a second input terminal, a tenth PMOS transistor Mp10, an eleventh PMOS transistor Mp11, a Miller compensation capacitor Cc, a sampling capacitor Cs, a load capacitor CL, a load resistor RL, a sampling resistor R0, a third clock signal, a fourth clock signal, an inverter, and a successive approximation analog-to-digital converter (SAR A / D). Among them, the gate of the tenth PMOS transistor Mnp10 is connected to the drain of the eleventh PMOS transistor Mnp11 and is connected to the first input terminal, externally connecting to the first output terminal of the amplifier 1; the source of the tenth PMOS transistor Mnp10 is connected to the source of the eleventh PMOS transistor Mnp11 and is connected to a high potential; the gate of the eleventh PMOS transistor Mnp11 is connected to the fourth clock signal, and the eleventh PMOS transistor Mnp11 is used as a pull-up switch; the left end of the Miller compensation capacitor Cc is connected to the gate of the tenth PMOS transistor Mnp10, and the right end of the Miller compensation capacitor Cc is connected to the drain of the tenth PMOS transistor Mnp10; the upper end of the load resistor is connected to the drain of the tenth PMOS transistor Mnp10, and the lower end of the load resistor is connected to the ground. The upper end of the inverter is connected to the second input terminal of the humidity sensing element interface unit 2, the lower end of the inverter is connected to the ground, the left end of the inverter is connected to the third clock signal, and the right end of the inverter is connected to the PAD point of the off-chip humidity sensing element; the upper end of the load capacitor is connected to the output terminal of the inverter, and the lower end of the load capacitor is connected to the ground; the upper end of the sampling resistor is connected to the first output terminal of the humidity sensing element interface unit 2, and the lower end of the sampling resistor is connected to the ground; the left end of the sampling capacitor is connected to the first switch, and the right end of the sampling capacitor is coupled to the successive approximation analog-to-digital converter.

[0058] Among them, the successive approximation analog-to-digital converter adopts an existing classic circuit structure, which will not be elaborated here.

[0059] In this embodiment, when the off-chip humidity-sensitive element selects the humidity-sensitive resistor CHR03, the resistance value of the sampling resistor can be adjusted to match the ambient humidity general value. When the resistance value of the sampling resistor is relatively large, it focuses on measuring high-humidity environments. When the resistance value of the sampling resistor is relatively low, it can improve the monitoring of low-humidity resistance values. In this example, the optimal value of the resistance value of the sampling resistor is 32K ohms. For the variation curve of the voltage Vx value at the first output end of the humidity-sensitive element interface unit 2 measured with respect to humidity, please refer to Figure 5 . When selecting the number of bits of the successive approximation analog-to-digital converter, first find the voltage value that changes on the fixed humidity curve when the humidity changes by 1% in the chart, and observe the recognition range where the voltage change value is greater than 1 LSB. In this example, the number of bits of the analog-to-digital converter is selected as 12 bits.

[0060] Please refer to Figure 6 , which shows the structural schematic diagram of the clock control module 3 in an embodiment. As Figure 6 shown, the clock control module 3 includes a frequency division by two circuit, a delay module, a first inverter, a second inverter, a third inverter, and the first to sixth clock signals; the frequency division by two circuit 31, the delay module 32, the first inverter, the second inverter, and the third inverter connected in sequence; among them, the input end of the frequency division by two circuit 31 is connected to the first clock signal Φ1, and the output end of the frequency division by two circuit 31 is connected to the second clock signal Φ2; the input end of the delay module 32 is connected to the second clock signal Φ2, and the output end of the delay module 32 is connected to the third clock signal Φ3; the input end of the first inverter is connected to the third clock signal Φ3, and the output end of the first inverter is connected to the fourth clock signal Φ4; the input end of the second inverter is connected to the fourth clock signal Φ4, and the output end of the second inverter is connected to the fifth clock signal Φ5; the input end of the third inverter is connected to the fifth clock signal Φ5, and the output end of the third inverter is connected to the sixth clock signal Φ6;

[0061] In this embodiment, for the structural schematic diagrams of the frequency division by two circuit 31 and the delay module 32 in this embodiment, please refer to Figure 7 and Figure 8 , Figure 9 which shows the timing logic diagram of the clock control module of the present invention.

[0062] Please refer to Figure 7 , which shows the structural schematic diagram of the frequency division by two circuit 31 in the clock control module of the present invention in an embodiment. As Figure 7As shown, the frequency division by two circuit 31 in the clock control module includes: a D flip-flop, an inverter, a first clock signal, and a second clock signal; the first input terminal of the flip-flop is connected to the output terminal of the inverter, the second input terminal of the flip-flop is linked to the first clock signal, the first output terminal of the flip-flop outputs the second clock signal and is linked to the input terminal of the inverter; the upper and lower ends of the flip-flop and the inverter are respectively connected to a high potential and a low potential. Among them, the flip-flop adopts an existing falling-edge D flip-flop structure, which will not be elaborated here.

[0063] In this embodiment, the first clock signal input to the flip-flop is selected as 2Khz, and the second clock signal output via this frequency division by two network is 1KHz.

[0064] Please refer to Figure 8 , which shows the schematic structural diagram of the time delay module 32 in the clock control module of the present invention in an embodiment; as Figure 8 shown, the time delay module 32 adopts a hysteresis structure and includes a thirteenth PMOS transistor Mp13, a fourteenth PMOS transistor Mp14, a fifteenth NMOS transistor Mn15 to a twentieth NMOS transistor Mn20, and a first to a third inverter; among them, the source of the thirteenth PMOS transistor Mp13 is connected to a high potential, the gate of the thirteenth PMOS transistor Mp13 is connected to a bias voltage VB1, and the drain of the thirteenth PMOS transistor Mp13 is connected to the source of the twelfth PMOS transistor Mp12; the gates of the twelfth PMOS transistor Mp12 and the fifteenth NMOS transistor Mn15 are connected and are connected to the input terminal of the time delay module; the drain of the twelfth PMOS transistor Mp12 is connected to the drain of the fifteenth NMOS transistor Mn15; the gates of the sixteenth NMOS transistor Mn16, the seventeenth NMOS transistor Mn17, and the eighteenth NMOS transistor Mn18 are connected and are connected to a bias voltage VB2; the sources of the sixteenth NMOS transistor Mn16 and the eighteenth NMOS transistor Mn18 are grounded; the source of the seventeenth NMOS transistor Mn17 is connected to the drain of the eighteenth NMOS transistor Mn18; the source of the nineteenth NMOS transistor Mn19 is connected to the drain of the eighteenth NMOS transistor Mn18, the drain of the nineteenth NMOS transistor Mn19 is connected to the drain of the twelfth PMOS transistor Mp12, and the gate of the nineteenth NMOS transistor Mn19 is connected to the output terminal of the first inverter; the input terminal of the first inverter is connected to the drain of the twelfth PMOS transistor Mp12, the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter is the output of the time delay module in the clock control module; the gate of the twentieth NMOS transistor Mn20 is connected to the drain of the twelfth PMOS transistor Mp12, and the drain and source of the twentieth NMOS transistor Mn20 are connected to the substrate to form a MOS capacitor structure.

[0065] In this embodiment, the delay module 32 in the clock control module forms a hysteresis structure, avoiding the disadvantages of large power consumption and large layout area of traditional large-sized sensors, achieving an efficient time delay effect. For the time delay simulation schematic diagram of the delay module 32 in this embodiment, please refer to Figure 10 .

[0066] To further prove the effectiveness of the low-power humidity sensor interface circuit of the present invention, the following simulation experiments are carried out. The simulation experiments adopt dynamic circuit simulation technology. In the Cadence simulation software, the SMIC 0.18um CMOS process is used, the power supply voltage value is 3.3V, the reference voltage value is 1.0V, the first clock signal is 2KHz, and the off-chip humidity sensitive element selects the CHR03 humidity-sensitive resistor. The results of the simulation experiments are as Figure 11 . Among them, Figure 11 shows the results of the first to third clock signals and the current consumption of the circuit. The actual simulation delay time of the delay module is 43.2895nS. It can be seen that the current consumption during operation is 37.956uA, and the current consumption during static sleep is 16.089pA.

[0067] In summary, for the low-power humidity sensor interface circuit provided by the present invention, the feedback structure formed by coupling the low-power amplifier and the interface unit clamps and outputs a stable data processing voltage, which is used to convert the humidity change value of the off-chip humidity sensitive element of the circuit to obtain a voltage feedback signal that can be processed by the backend circuit; the clock control unit provides clock signals for the interface unit and the data conversion logic unit to control the working and sleep modes of the sensor interface chip, improving the working efficiency of the interface circuit and reducing the operating power consumption, and overall ensuring the stable output of the interface circuit connecting the sensitive components. Moreover, in the present invention, a time delay module implementation method different from the traditional inverter is provided for the humidity sensor field. It not only has good feasibility but also excellent performance, improving the stability of the interface circuit, achieving the performance indicators of small static current and low power consumption, and enabling it to be widely used in the fields of new-generation monitoring systems such as industry, agriculture, and medical care.

[0068] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A low-power humidity sensor interface circuit, characterized in that, Including: An amplifier for amplifying an input reference signal, with its output terminal connected to the positive input terminal to form a feedback structure for clamping the reference voltage signal; And A humidity sensor interface unit, the input terminal of which is coupled to the output terminal of the amplifier, and the output terminal of which is coupled to an off-chip humidity sensor element, for detecting changes in the value of the off-chip humidity sensor element and performing a clamping process based on the reference voltage signal to obtain a corresponding feedback signal, and outputting the feedback signal to the amplifier, so that the amplifier adjusts the output signal according to the feedback signal, and converts the change in the resistance value of the off-chip humidity sensor element into a stable voltage signal that meets the processable range of the backend circuit for output; And A data conversion logic unit, the input terminal of which is coupled to the output terminal of the humidity sensor interface unit, and the output terminal directly outputs the converted digital signal, and its internal structure adopts the circuit topology unit of a successive approximation analog-to-digital converter; And A clock control unit, the input terminal of which is connected to an externally input clock signal, and the output terminal is connected to the humidity sensor interface unit and the data conversion logic unit, providing the timing logic for controlling the startup and shutdown of the internal circuit of the chip system.

2. The low-power humidity sensor interface circuit according to claim 1, wherein The amplifier circuit includes an amplifier with a folded cascode structure having differential input and single-ended output and a bias circuit with dual operating modes.

3. The low-power humidity sensor interface circuit according to claim 1, characterized in that The humidity sensor interface unit clamps the reference voltage at the inverting input terminal of the amplifier to the output terminal, and converts the resistance values of the humidity-sensitive resistor and the sampling resistor coupled to the output terminal of the humidity sensor interface unit to obtain a voltage-sensitive signal related to the humidity value result.

4. The low-power humidity sensor interface circuit according to claim 1, characterized in that The data conversion logic unit circuit adopts a classic successive approximation analog-to-digital converter structure to convert the analog signal related to the humidity value transmitted by the humidity sensor interface unit into a digital code for output.

5. The low-power humidity sensor interface circuit according to claim 1, characterized in that, The clock control unit includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, and a sixth clock signal, wherein the clock frequencies of the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, and the sixth clock signal are all the same; among them, the frequency of the first clock signal is 2KHz and is provided externally, the second clock signal is obtained from the first clock signal through a frequency division network, the third clock signal is obtained from the second clock signal through a delay network, the fourth clock signal and the third clock signal have opposite phases, the fifth clock signal is obtained from the fourth clock signal through a delay network, and the sixth clock signal and the fifth clock signal have opposite phases.

6. The low-power humidity sensor interface circuit according to claim 2, wherein The amplifier circuit structure is a folded cascode structure with differential input of N-type MOS transistor pairs and single-ended output. The amplifier circuit includes a first resistor, a second resistor, a first transmission gate switch, a second transmission gate switch, a P-type MOS transistor conduction switch, an N-type MOS transistor conduction switch, a first and a second N-type MOS amplifying transistors, a first to a ninth N-type MOS mirror transistors, and a first to a sixth P-type MOS mirror transistors; The first end of the first transmission gate switch is connected to the end of the first resistor. The second end of the first transmission gate switch is connected to the drain of the N-type MOS transistor conduction switch. The source of the N-type MOS transistor conduction switch is connected to VSS. The first end of the second transmission gate switch is connected to the upper end of the second resistor. The second end of the second transmission gate switch is connected to the drain of the P-type MOS transistor conduction switch. The source of the P-type MOS transistor conduction switch is connected to VDD. The gate of the P-type MOS transistor of the first transmission gate is connected to receive the fifth clock signal. The gate of the N-type MOS transistor of the first transmission gate is connected to receive the sixth clock signal. The gate of the P-type MOS transistor of the second transmission gate is connected to receive the fifth clock signal. The gate of the N-type MOS transistor of the second transmission gate is connected to the sixth clock signal. The gate of the N-type MOS transistor conduction switch is connected to the fifth clock signal. The gate of the P-type MOS transistor conduction switch is connected to the sixth clock signal.

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