Method for producing a composite structure comprising a thin layer of single-crystal SiC on a carrier substrate of polycrystal SiC

Abstract

The invention relates to a method for producing a composite structure (1) comprising a thin layer (10) of single-crystal silicon carbide located on a carrier substrate (20) of silicon carbide. The method comprises: a) a step of providing an initial substrate (11) of single-crystal silicon carbide, b) a step of epitaxial growth of a donor layer (110) of single-crystal silicon carbide on the initial substrate (11) to form a donor substrate (111), c) a step of implanting light species ions into the donor layer (110) to form a buried fragility plane (12) delimiting the thin layer (10), d) a step of forming a support substrate (20) of silicon carbide on the free surface of the donor layer (110), comprising a deposition at a temperature of between 400°C and 1100°C, e) a step of separation along the buried fragility plane (12) to form the composite structure (1) and a remaining portion (111') of the donor substrate, f) a step of chemical-mechanical treatment of the composite structure (1).

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials for microelectronic devices. More specifically, this invention relates to a method for producing a composite structure comprising a thin layer of single-crystal silicon carbide on a carrier substrate of crystalline silicon carbide (particularly polycrystalline silicon carbide). Background Technology

[0002] In recent years, interest in silicon carbide (SiC) has been increasing due to the semiconductor material's ability to improve energy handling capabilities. SiC is being used more and more extensively in the production of new power devices to meet the growing demands of the electronics sector, particularly in electric vehicles.

[0003] Compared to traditional silicon power devices and integrated power systems, single-crystal silicon carbide (SiC)-based power devices and integrated power systems can manage higher power densities with smaller active area sizes. To further limit the size of SiC power devices, it is advantageous to produce vertical elements rather than lateral elements. For this purpose, the SiC structure must be able to conduct vertically between the electrodes disposed on the front side and the electrodes disposed on the back side of the structure.

[0004] However, single-crystal SiC substrates intended for use in the microelectronics industry remain expensive and difficult to supply in large sizes. Therefore, it is advantageous to use thin-layer transfer solutions to produce composite structures that typically contain thin layers of single-crystal SiC on less expensive carrier substrates. A well-known thin-layer transfer solution is Smart Cut. TM The process is based on the implantation of light ions and direct bonding assembly. For example, this process can produce composite structures comprising a thin layer of single-crystal SiC (c-SiC) (derived from a c-SiC donor substrate) in direct contact with a polycrystalline SiC (p-SiC) carrier substrate, which are capable of vertical conductivity. However, achieving high-quality direct bonding through molecular adhesion between the two c-SiC and p-SiC substrates remains challenging because managing the roughness and surface conditions of the substrates is complex.

[0005] Various methods derived from this process are also known in the prior art. For example, F. Mu et al. (ECS Transactions, 86(5)3-21, 2018) performed direct bonding (SAB stands for "Surface Activated Bonding") after activating the surfaces to be bonded by argon bombardment: this pre-bonding treatment produces a very high density of dangling bonds (which promotes the formation of covalent bonds at the assembly interface) and thus produces a high bonding energy. However, a drawback of this method is that it produces an amorphous layer on the surface of the single-crystal SiC donor substrate, which negatively affects the vertical conductivity between the c-SiC thin layer and the p-SiC carrier substrate.

[0006] Solutions have been proposed to solve this problem, more particularly in document EP3168862, which injects a dopant species into the amorphous layer to restore its electrical properties. The main drawback of this method is its complexity and its cost.

[0007] It is also known from document US8436363, which describes a method for producing a composite structure comprising a thin layer of c-SiC arranged on a metal carrier substrate, the coefficient of thermal expansion of which matches that of the thin layer. This production method comprises the following steps:

[0008] - forming a buried brittle plane in a c-SiC donor substrate and delimiting a thin layer between the above-mentioned buried brittle plane and the front surface of the donor substrate;

[0009] - depositing a layer of metal (for example tungsten or molybdenum) on the front surface of the donor substrate to form a carrier substrate with a sufficient thickness to achieve the role of reinforcement;

[0010] - separating along the buried brittle plane, thus forming on the one hand a composite structure comprising a metal carrier substrate and a thin layer of c-SiC, and on the other hand the remaining part of the c-SiC donor substrate.

[0011] However, this production method is incompatible when the material forming the carrier substrate is p-SiC, which requires a deposition at a temperature higher than 1200°C (usual temperature for the production of p-SiC). In particular, at these high temperatures, the growth kinetics of the cavities present in the buried brittle plane is faster than that of the p-SiC layer, and the thickness required for the reinforcement effect is not reached before the onset of blistering, which is associated with the deformation of the layer aligned perpendicularly to the cavities.

[0012] Whatever the layer transfer technique used, another problem arises in providing a composite structure comprising a thin c-SiC layer with extremely high quality, more particularly free of extended defects (or with an extremely low density of such defects), which can have a detrimental effect on the performance and reliability of the power devices to be produced on the thin layer. SUMMARY

[0013] OBJECT OF THE INVENTION

[0014] The present invention relates to an alternative solution to the prior art and aims to overcome the above-mentioned drawbacks, wholly or partly. The present invention more particularly relates to a method for producing a composite structure comprising a thin layer of high-quality c-SiC arranged on a crystalline SiC carrier substrate.

[0015] BRIEF DESCRIPTION OF THE INVENTION

[0016] The invention relates to a method for producing a composite structure comprising a thin layer of single-crystal silicon carbide arranged on a carrier substrate of silicon carbide. The method comprises:

[0017] a) a step of providing an initial substrate of single-crystal silicon carbide,

[0018] b) a step of epitaxially growing a donor layer of single-crystal silicon carbide on the initial substrate to form a donor substrate, the donor layer having a lower crystal defect density than the initial substrate,

[0019] c) a step of implanting light species ions into the donor layer to form a buried brittleness plane delimiting a thin layer between the buried brittleness plane and a free surface of the donor layer,

[0020] d) a step of forming a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature between 400°C and 1100°C, and defining a non-insulating interface between the donor layer and the carrier substrate,

[0021] e) a step of separation along the buried brittleness plane to form on the one hand the composite structure and on the other hand a remaining portion of the donor substrate,

[0022] f) a step of mechanical and / or chemical treatment of the composite structure to smooth the free surface of the thin layer and to correct the thickness uniformity of the composite structure.

[0023] Other advantageous and non-limiting features (alone or according to any technically feasible combination) according to the invention:

[0024] • the deposition of step d) is carried out at a temperature between 600°C and 900°C, even preferably between 700°C and 800°C, and is based on a chemical vapor deposition technique or a sintering technique or a liquid deposition technique using a solution of ceramic powder;

[0025] • the deposition of step d) is a chemical vapor deposition assisted by direct liquid injection;

[0026] • the deposition of step d) is a plasma-enhanced chemical vapor deposition or a low-pressure chemical vapor deposition;

[0027] • the deposition of step d) is carried out at a rate greater than 10 microns / hour, even preferably greater than 50 microns / hour;

[0028] • at the end of the deposition of step d), the carrier substrate has a thickness greater than or equal to 50 microns, even preferably greater than or equal to 100 microns;

[0029] • step a) comprises forming a single-crystal conversion layer on the initial substrate for converting basal plane dislocation defects of the initial substrate into screw edge dislocation defects;

[0030] • the epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably between 1500°C and 1650°C;

[0031] • the light species injected during step c) are chosen from hydrogen and / or helium;

[0032] • the separation step e) is operated at a temperature higher than or equal to the temperature of the deposition of step d);

[0033] • the separation step e) is operated by applying a mechanical stress to the stack comprising the carrier substrate bonded to the donor substrate;

[0034] • step f) comprises simultaneously chemically-mechanically polishing the front and back faces of the composite structure;

[0035] • the method comprises a step of heat treatment at a temperature between 1000°C and 1800°C, before or after step f);

[0036] • the method comprises a second step g) of epitaxial growth of an additional layer of monocrystalline silicon carbide on the thin layer of the composite structure;

[0037] • the method comprises a step of repairing the remaining part of the donor substrate to reuse it as an initial substrate or donor substrate;

[0038] • the remaining part of the donor substrate is reused as a brand new donor substrate at least twice. BRIEF DESCRIPTION OF DRAWINGS

[0039] Other characteristics and advantages of the application will become apparent from the following detailed description of the application, made with reference to the attached drawings, in which:

[0040] [ Figure 1 ] Figure 1 a composite structure produced by the production method according to the application is shown;

[0041] [ Figure 2a ]

[0042] [ Figure 2b ]

[0043] [ Figure 2c ]

[0044] [ Figure 2d ]

[0045] [ Figure 2e ]

[0046] [ Figure 2f ]

[0047] [ Figure 2g ] Figures 2a to 2gThe steps of the production method according to the application are shown.

[0048] [ Figure 3a ]

[0049] [ Figure 3b ] Figure 3a and Figure 3b The steps of the production method according to the application are shown. DETAILED DESCRIPTION

[0050] In the description, identical references in the figures can be used for identical types of elements. The figures are schematic and not drawn to scale for the sake of clarity; in particular, the thickness of the layers along the z-axis is not to scale relative to the lateral dimensions along the x-axis and y-axis; and the relative thicknesses of these layers relative to one another are not to be considered in the figures.

[0051] The application relates to a method for producing a composite structure 1 comprising a thin layer 10 of single-crystal silicon carbide arranged on a carrier substrate 20 of silicon carbide. Figure 1 ) The carrier substrate 20 is crystalline and advantageously polycrystalline (“p-SiC” will be used hereinafter to denote polycrystalline SiC).

[0052] The method first comprises a step a) Figure 2a ) of providing an initial substrate 11 of single-crystal silicon carbide. In the remainder of the present description, “c-SiC” will be used to denote single-crystal silicon carbide.

[0053] The initial substrate 11 preferably presents the form of a wafer having a diameter of 100 mm or 150 mm or even 200 mm and a thickness generally comprised between 300 microns and 800 microns. It has a front face 11a and a back face 11b. The surface roughness of the front face 11a is advantageously less than 1 nm Ra (average roughness), as measured by atomic force microscopy (AFM) on a scan area of 20 microns x 20 microns.

[0054] The method subsequently comprises a step b) Figure 2b ) of epitaxially growing a single-crystal silicon carbide donor layer 110 on the initial substrate 11 to form a donor substrate 111. The epitaxial growth step is performed so that the donor layer 110 has a lower crystalline defect density than the initial substrate 11.

[0055] The initial substrate 11 of c-SiC is generally 4H or 6H polytype and exhibits an orientation deviation (“off-cut”) of less than 4.0° ± 0.5° relative to the <11-20> crystallographic axis and a dislocation density of less than or equal to 5 / cm 2 , or even less than 1 / cm 2of screw dislocations ("micropipes"). N (nitrogen) -doping, with resistivity preferably comprised between 0.015 ohm.cm and 0.030 ohm.cm. The selected initial substrate 11 can have a lower basal plane dislocation (BPD) defect density, typically less than or equal to 3000 / cm 2 . The BPD density is about 1500 / cm 2 . Substrates of c-SiC are more readily available, thus easier to supply.

[0056] It is desirable that the donor layer 110 of the thin c-SiC layer 10 forming the composite structure 1 at the end of the method of the present application has a higher crystal quality than the initial substrate 11, so as to comply with the required specifications of the vertical elements to be produced on said thin layer 10. The reason is that in layers or substrates of c-SiC there are various types of extended defects. These extended defects can have a detrimental effect on the performance and reliability of the elements. In particular, BPD defects are fatal for bipolar elements: the reason is that Shockley stacking faults (SSF) extend from dislocations when the recombination energy of electron-hole pairs is available. The extension of SSF stacking faults within the active region of the element causes an increase in the resistance of the element in the on-state.

[0057] Therefore, the c-SiC donor layer 110 is produced so that its BPD defect density is less than or equal to 1 / cm 2 .

[0058] For this purpose, the epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably comprised between 1500°C and 1650°C. The precursors used are silane (SiH4), propane (C3H8) or ethylene (C2H4); the carrier gas can be argon-containing or argon-free hydrogen.

[0059] The low BPD defect rate in the donor layer 110 is obtained by promoting the conversion of the BPD defects present in the initial substrate 11 into screw edge dislocations or TEDs.

[0060] According to a particular embodiment, step a) comprises forming a monocrystalline conversion layer 13, preferably of c-SiC, for maximising the conversion of the BPD defects in the initial substrate 11 into TED defects Figure 3a . For this purpose, it is advantageous to select for the initial substrate 11 of c-SiC a low off-cut angle close to 4°, to enhance the in situ etching achieved before epitaxial growth, to target a high growth rate (typically greater than 5 μm / h) and, finally, to select growth conditions of the monocrystalline conversion layer 13 with a C / Si ratio close to 1 in the precursor flow.

[0061] Step b) then requires the epitaxial growth of the donor layer 110 on said conversion layer 13 Figure 3b). According to this particular embodiment, it is also possible to obtain a donor layer 110 of c-SiC with a BPD defect density less than or equal to 1 / cm2 2 , or even less than 0.1 / cm2 2 . Moreover, since the monocrystalline conversion layer 13 is not intended to be transferred into the composite structure 1, the probability of bipolar degradation (the probability of holes reaching below the BPD / TED conversion point) at the end of the method according to the application is negligible (< 0.1%). The prior art aiming at reducing the bipolar degradation involves integrating a composite layer (doped with more than 1 E 8 at / cm2 3 of nitrogen) between the conversion layer and the active layer. At the cost of a thickness of 10 pm and a concentration greater than 5 E 8 / cm2 3 , this composite layer is able to reduce the probability of the presence of holes to 0.1% relative to a base structure that does not contain this composite layer. In the present application, since the monocrystalline conversion layer 13 is not transferred, the probability of holes reaching the nucleation point of bipolar degradation (BPD-TED conversion point or any BPD point) is at least less than 0.1%, or even close to 0%.

[0062] A conventional cleaning or etching procedure of the initial substrate 11 aiming at eliminating some or all of the particulate matter, metals or organic contaminants or natural oxide layer that can be present on the front face 11a can be implemented before the epitaxial growth step b).

[0063] The production method according to the application also comprises a step c) of implanting light species ions into the donor layer 110 up to a predetermined depth representative of the desired thickness of the thin layer 10 and in any case not reaching the initial substrate 11 (and / or the conversion layer 13, when it is present). This implantation creates a buried fragility plane 12 in the donor layer 110, which delimits the thin layer 10 Figure 2c ) between said buried fragility plane 12 and the free surface 11a of said donor layer 110.

[0064] The implanted light species are preferably hydrogen, helium or a co-implantation of these two species. With reference to the Smart Cut TM process, these light species will form microcavities around a given depth, said microcavities being distributed in the thin layer and parallel to the free surface 11a of the donor layer 110 (i.e. parallel to the plane (x, y) in the figures). For the sake of brevity, this thin layer will be called buried fragility plane 12.

[0065] The implantation energy of the light species is chosen so as to reach a determined depth in the donor layer 110.

[0066] Generally, the energy is between 10 keV and 250 keV and the dose is between 5 E 16 / cm2and 1 E17 / cm2, thereby defining a thin layer 10 having a thickness of about 100 nm to 1500 nm.

[0067] Before the ion implantation step, a protective layer can be deposited on the free face of the donor layer 110. This protective layer can be composed of a material such as silicon oxide or silicon nitride.

[0068] The method according to the application subsequently comprises a step d) of forming a support substrate 20 of crystalline silicon carbide on the free surface of the donor layer 110. Figure 2d ) This step d) comprises a deposition at a temperature between 400°C and 1100°C. The deposition of step d) is advantageously performed at a temperature between 600°C and 900°C, even more preferably between 700°C and 800°C.

[0069] Furthermore, step d) defines a non-insulating interface between the donor layer 110 and the support substrate 20. In other words, performing step d) makes the interface between the donor layer 110 and the support substrate 20 conductive: the specific resistance of said interface is generally less than 1 mohm.cm 2 , or even less than 0.1 mohm.cm 2 . Advantageously, in order to ensure the conductivity of the interface, the native oxide present on the free face of the donor layer 110 is removed by HF (hydrofluoric acid) deoxidation, wet or dry. Alternatively, the first nanometres of the deposition on the support substrate 20 can be overdoped, which promotes the conductivity of the interface between the donor layer 110 and the support substrate 20.

[0070] Likewise advantageously, before deoxidation and / or formation of the support substrate 20, a cleaning procedure is applied to the donor substrate 111, thereby removing some or all of the particulate matter, metal contaminants or organic contaminants that can be present on the free face of said substrate.

[0071] The deposition of step d) can be performed by various techniques.

[0072] According to a first option, the support substrate 20 can be shaped by sintering techniques. According to this technique, SiC powder is compacted at high temperature and high pressure. A solid ceramic layer can be obtained in this way. In the context of the application, sintering is performed directly on the implanted donor substrate 111, thereby obtaining a support substrate 20 that is thick and adheres to the donor layer 110 immediately after sintering. The sintered material (support substrate 20) needs to obtain sufficient cohesion to be able to perform the subsequent separation step e) described below. Therefore, the sintering temperature of the SiC powder needs to be lowered below this separation temperature. To this end, conventional additives are used (such as boron, carbon or AIN), or SiC nanopowder is used.

[0073] According to a second option, the carrier substrate 20 can be shaped by using a liquid deposition technique of a solution of ceramic powder. In this case, a ceramic precursor polymer material (PDC stands for "Polymer Derived Ceramics") is mixed with a ceramic powder (for example SiC). A viscous solution is obtained, which can be deposited in the form of a layer by spreading, spin-coating or molding. A low temperature (about 200°C) baking leads to the polymerization and cross-linking of the material and to the solidification of the deposited layer. The shaping of the carrier substrate 20 is thus carried out at low temperature. Subsequently, a baking operation at high temperature (> 600°C) enables the pyrolysis of the polymer. The material obtained is then pure ceramic. In the context of the application, the objective will be to obtain a SiC material or a SiCN material. The ceramic raw material is SiC in powder form and the PDC is a molecule from the family of polycarbosilanes or polyorganosilicones (for obtaining SiC) and polyorganosilazanes (for obtaining SiCN).

[0074] According to a third option, the deposition of step d) can be carried out by a chemical vapor deposition technique (CVD).

[0075] For example, the deposition can be carried out by a thermal CVD technique (for example atmospheric pressure deposition (APCVD) or low pressure deposition (LPCVD)). The precursors can be chosen from methylsilane, dimethyldichlorosilane or dichlorosilane + isobutane.

[0076] The deposition can be a plasma enhanced CVD technique (PECVD), for example with silicon tetrachloride and methane as precursors. The frequency of the source used to create the plasma discharge is preferably about 3.3 MHz, more generally between 10 kHz and 100 GHz.

[0077] The deposition of step d) can also be based on a direct liquid injection assisted chemical vapor deposition technique (DLI-CVD). This technique offers a high yield between the substance provided (precursor) and the thickness of the deposit obtained, without the need to use chlorine-containing precursors, thus limiting the cost and environmental constraints. The DLI-CVD deposition uses disilane butane precursors or polymethylsilyl ethylene precursors, which are pure or diluted. This technique is described in the thesis of Guilhaume Boisselier (2013, "Chemical vapour deposition of chromium, silicon and hafnium carbides, assisted by pulsed liquid injection") for the application of depositing a ceramic coating on a part (for example a metal part made of steel or an alloy) to protect it during processes that handle extremely high temperatures.

[0078] The Applicant has developed a deposition step d) based on DLI-CVD technology for a completely different application, i.e. the formation of a carrier substrate 20 of SiC on a donor layer 110 of c-SiC, for the production of composite substrates intended for use in the microelectronics field. The parameters of the deposition are determined (for example, a pressure of 6.7 kPa, a temperature of between 700°C and 850°C) so that the carrier substrate 20 has good electrical conductivity (between 0.015 ohm.cm and 0.03 ohm.cm), high thermal conductivity (greater than or equal to 200 W.m -1 .K -1 ) and a thermal expansion coefficient similar to that of the thin layer 10 (typically between 3.8 E -6 / K and 4.2 E -6 / K at ambient temperature).

[0079] To obtain these properties, the carrier substrate 20 can for example have the following structural characteristics: polycrystalline structure, 3C SiC crystalline grains, 111 orientation, average size of 1-10 μιη, N-type doping with final resistivity less than or equal to 0.03 ohm.cm.

[0080] Regardless of the technology adopted, the CVD deposition advantageously takes place at a rate greater than 10 microns / hour, even greater than 50 microns / hour, and still even greater than 100 microns / hour. In addition to the obvious economic interest, it is important to reach significant thicknesses of the carrier substrate 20 quickly, to ensure the effect of reinforcement with respect to the buried brittle plane 12 in which the cavities follow a thermal activation growth.

[0081] At the end of step d), the carrier layer 20 has a thickness greater than or equal to 50 microns, or even greater than or equal to 100 microns. The stack 211 resulting from step d) comprises the carrier substrate 20 arranged on the donor layer 110, which in turn is arranged on the initial substrate 11.

[0082] The method according to the application subsequently comprises a step e) Figure 2e ) of separation along the buried brittle plane 12, to form on the one hand the composite structure 1 and on the other hand the remaining portion 111' of the donor substrate.

[0083] According to an advantageous embodiment, the separation step e) is operated by applying a thermal treatment to the stack 211 at a separation temperature greater than or equal to the temperature of the deposition of step d). In particular, the microcavities present in the buried brittle plane 12 follow a growth kinetics until the appearance of a fracture wave that will propagate throughout the range of the buried brittle plane 12 and cause the separation between the composite structure 1 and the remaining portion 111' of the initial substrate. In practice, the temperature can be between 950°C and 1200°C, depending on the implantation conditions of step c).

[0084] According to an alternative embodiment, the separation step e) is operated by applying a mechanical stress to the stack 211. For example, the stress can be applied by inserting a tool, such as a razor blade, close to the buried brittle plane 12. As an example, the separation stress can be about a few GPa, preferably greater than 2 GPa.

[0085] According to another embodiment, the separation step e) along the buried brittle plane 12 is directly performed during the process of forming the carrier substrate 20 in step d) or at the end of the formation of the carrier substrate 20 in step d), more particularly when the deposition temperature in this step is in the range of 800°C to 1100°C.

[0086] As known per se, at the end of the separation step e), the free face 10a of the thin layer 10 of the composite structure 1 has a surface roughness comprised between 5 nm RMS and 100 nm RMS (measured by using an Atomic Force Microscope (AFM) on a 20 microns x 20 microns scan area).

[0087] Accordingly, the method according to the application comprises a step f) of mechanical and / or chemical treatment of the composite structure 1 to smooth the free surface 10a of the thin layer 10 and to correct the thickness uniformity of the composite structure 1. Figure 2f ).

[0088] Accordingly, step f) can comprise a chemical-mechanical polishing (CMP) of the free face 10a of the thin layer 10, typically removing about 50 nm to 1000 nm of material, to obtain a final roughness of less than 0.5 nm Rms (within a 20 pm x 20 pm AFM field of view), or even less than 0.3 nm. Step f) can also comprise a chemical treatment or a plasma treatment (cleaning or etching), such as SC1 / SC2 (standard clean 1, standard clean 2) cleaning and / or HF (hydrofluoric acid) cleaning or N2, Ar, CF4 plasma, etc., to further improve the quality of the free face 10a of the thin layer 10.

[0089] Furthermore, step f) can comprise a chemical-mechanical polishing (CMP) and / or a chemical treatment (etching or cleaning) and / or a mechanical treatment (lapping) of the back face 20b of the carrier substrate 20 to improve the thickness uniformity of said carrier substrate 20 and the roughness of its back face 20b. A roughness of less than 0.5 nm RMS (measured by using an Atomic Force Microscope (AFM) on a 20 microns x 20 microns field of view) is desired, so as to produce at least one vertical element of the composite substrate 1 in which a metal electrode is present at the back face 20b.

[0090] In this step f), the edges of the composite structure 1 can also be polished or lapped so as to conform their circular profile and edge radius shape to the requirements of the microelectronic manufacturing process.

[0091] According to an advantageous implementation, the chemical-mechanical treatment step f) comprises simultaneously polishing (CMP) the front face 10a and the back face 20b of the composite structure 1 to smooth and improve the thickness uniformity of said structure 1. The polishing parameters can be different for the front and back faces and the smoothing of the c-SiC surface and p-SiC surface generally requires different consumables. When the carrier substrate 20 is made of p-SiC, the mechanical component of the polishing of the back face 20b is more particularly emphasized, thus limiting the preferential attack of the grain boundaries by the chemical component of the polishing. By way of example, the polishing parameters (such as the rotation speed (polishing head and polishing plate), the pressure, the concentration and the physical properties of the abrasive (i.e. the diameter of the diamond nanoparticles is comprised between about 10 nm and 1 pm)) can be modified to emphasize the mechanical component.

[0092] Also according to an advantageous implementation, step f) is preceded or followed by a step f’) of heat treatment at a temperature comprised between 1000°C and 1800°C for about one hour to several hours. The purpose of this step is to stabilize the composite structure 1 by forming, where appropriate, the crystalline configuration of the carrier substrate 20, so that the structure 1 is compatible with the subsequent heat treatment at high temperature, which is necessary to manufacture the element on the thin layer 10.

[0093] The method according to the application can comprise a second step g) of epitaxial growth of an additional layer 10’ of monocrystalline silicon carbide on the thin layer 10 of the composite structure 1. Figure 2g This step is applied when a relatively high useful layer thickness 100 (typically about 5 to 50 pm) is required to manufacture the element. The epitaxial conditions can be optionally chosen similar to the epitaxial conditions of step b) (preferably at low temperature), thus limiting the stresses induced in the useful layer 100 (corresponding to the assembly of the thin layer 10 and the additional layer 10’) due to the composite structure 1.

[0094] Finally, the production method can comprise a step of repairing the remaining portion 111’ of the donor substrate to reuse it as an initial substrate 1 or as a donor substrate 111. This repair step is based on one or more treatments of the face 110’a by edge or surface chemical-mechanical polishing and / or by mechanical grinding and / or by wet or dry chemical etching. Figure 2e The thickness of the donor layer 110 formed in step b) is preferably defined so that the remaining portion 111’ of the donor substrate 111 can be reused as a donor substrate 111 at least twice. Preferably, when the transformation layer 13 is present, care is taken to leave said layer intact, in other words, always leaving a portion of the donor layer 10 on the remaining portion 111’ of the donor substrate. Thus, when a portion of the donor substrate 10 is insufficient to produce the composite structure 1, only the epitaxial growth step of the donor layer 10 is required, without the previous growth step of the transformation layer 13.

[0095] Example 1:

[0096] According to one non-limiting exemplary embodiment, the initial substrate 11 provided in step a) of the production method is a wafer made of c-SiC, of 4H polytype, having an orientation of 4.0° ± 0.5° with respect to the <11-20> axis, and having a diameter of 150 mm and a thickness of 350 pm.

[0097] Prior to step b) of epitaxial growth of the c-SiC donor layer 110, a conventional RCA cleaning procedure (standard clean 1 + standard clean 2) is performed on the initial substrate 11, followed by a Caro’s acid (mixture of sulfuric acid and hydrogen peroxide), and then by HF (hydrofluoric acid).

[0098] Growth is performed in an epitaxial chamber at a temperature of 1650 °C using precursors such as silane (SiH4) and propane (C3H8) or ethylene (C2H4), so as to produce a c-SiC donor layer 110 having a thickness of 30 microns (growth rate: 10 microns / hour). The BPD defect density of the donor layer is about 1 / cm2. 2 .

[0099] Hydrogen ions are implanted through the free surface of the donor layer 110 at an energy of 150 keV and a dose of 6 E 16 H+ / cm 2 The implantation of hydrogen ions at a depth of about 800 nm in the initial substrate 11 creates a buried fragile plane 12.

[0100] A cleaning procedure of RCA + Caro’s acid is performed on the donor substrate 111 to remove possible contaminants from the free face of the donor layer 110.

[0101] DLI-CVD deposition is performed on the donor layer 110 using the precursor disilane butane (DSB) at a temperature of 850 °C under a pressure of 6.7 kPa for 7 minutes, so as to bring the carrier substrate 20 to a thickness of at least 10 microns. Under these conditions, the carrier substrate 20 is polycrystalline.

[0102] A 1000 °C bake is then applied to the stack 211 for 50 minutes, and separation occurs at the buried fragile plane 12 during said bake.

[0103] At the end of this separation step e), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the remaining portion 111’ of the donor substrate.

[0104] Double-sided polishing is performed to restore the surface roughness of the back face of the thin layer 10 and of the carrier substrate 20.

[0105] Example 2:

[0106] According to one non-limiting exemplary embodiment, the initial substrate 11 provided in step a) of the production method is a wafer made of c-SiC, which is 4H polytype, has an orientation of 4.0° ± 0.5° with respect to the <11-20> axis, and has a diameter of 150 mm and a thickness of 350 pm.

[0107] Prior to step b) of epitaxial growth of the c-SiC donor layer 110, a conventional RCA cleaning procedure (standard clean 1 + standard clean 2) is performed on the initial substrate 11, followed by Caro’s acid (a mixture of sulfuric acid and hydrogen peroxide), and then by HF (hydrofluoric acid).

[0108] The conversion layer 13 is formed in an epitaxial chamber. Prior to starting the epitaxial growth of this layer 13 on the initial substrate 11, a hydrogen bake is performed in the chamber at a temperature of 1700 °C for a time of 10 to 20 minutes. The epitaxial growth of the conversion layer 13 of c-SiC is then performed at a temperature of 1650 °C using precursors (e.g. silane (SiH4) and propane (C3H8) or ethylene (C2H4)) at a growth rate of about 6 pm / hour to obtain a thickness of 1 pm. The C / Si ratio obtained from the gaseous precursors is kept around a value close to 1, typically between 0.95 and 1.05.

[0109] In the same epitaxial chamber, the c-SiC donor layer 110 is grown at a temperature of 1650 °C using the same precursors, but the C / Si ratio is adjusted to a value of 1.2 or substantially greater. The total flow of precursors is increased - e.g. doubled - with respect to the flow used for growing the conversion layer 13. After about 180 minutes, a donor layer 10 of thickness 30 pm is obtained (growth rate: 10 pm / hour). The BPD defect density of the donor layer 10 is about 1 / cm 2 , or even less than 1 / cm 2 .

[0110] Hydrogen ions are implanted through the free surface of the donor layer 110 at an energy of 150 keV and a dose of 6 E 16 H+ / cm 2 . Thereby a buried fragile plane 12 is created in the initial substrate 11 at a depth of about 800 nm.

[0111] The donor substrate 111 is subjected to a cleaning procedure of RCA + Caro’s acid to remove possible contaminants from the free face of the donor layer 110.

[0112] PECVD deposition is performed on the donor layer 110 at a temperature of 800°C in a SiCl4 / CH4 / Ar atmosphere at a plasma generation frequency of 3.3 MHz; the pressure inside the deposition chamber is adjusted so as to obtain a deposition rate of about 300 microns / hour for the carrier substrate 20. The deposition rate must not be too high so as to limit the roughness of the free surface of the carrier substrate 20 after deposition. Under these conditions, the carrier substrate 20 is polycrystalline.

[0113] An 1100°C bake is then applied to the stack 211 for 50 minutes, and during said bake separation occurs in the buried fragile face 12.

[0114] At the end of this separation step e), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the remaining portion 111' of the donor substrate.

[0115] Double-sided polishing is performed to restore the surface roughness of the thin layer 10 and of the back face 20b of the carrier substrate 20.

[0116] The application is of course not limited to the embodiments and examples described, and variants can be introduced therein without departing from the scope of the application as defined by the claims.

Claims

1. Method for producing a composite structure (1) comprising a thin layer (10) of monocrystalline silicon carbide arranged on a carrier substrate (20) of silicon carbide, said method comprising: a) a step of providing an initial substrate (11) of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer (110) of monocrystalline silicon carbide on the initial substrate (11) at a temperature comprised between 1500°C and 1650°C to form a donor substrate (111), said donor layer (110) having a lower crystal defect density than the initial substrate (11), c) a step of implanting light species ions into the donor layer (110) to form a buried fragile face (12) delimiting a thin layer (10) between said buried fragile face (12) and a free surface of said donor layer (110), d) a step of forming a carrier substrate (20) of silicon carbide on the free surface of the donor layer (110) comprising a deposition at a temperature comprised between 400°C and 1100°C and defining a non-insulating interface between the donor layer (110) and the carrier substrate (20), e) a step of separation along the buried fragile face (12) to form on one hand the composite structure (1) and on the other hand a remaining portion (111') of the donor substrate, f) a step of mechanical and / or chemical treatment of the composite structure (1) to smooth the free surface of the thin layer (10) and to correct the thickness uniformity of the composite structure (1).

2. The method of claim 1, wherein, The deposition of step d) is carried out at a temperature comprised between 600°C and 900°C and is based on a chemical vapor deposition technique or a sintering technique or a liquid deposition technique using a solution of ceramic powder.

3. The method of claim 2, wherein, The deposition of step d) is a chemical vapor deposition assisted by direct liquid injection.

4. The method of claim 2, wherein, The deposition of step d) is a plasma-enhanced chemical vapor deposition or a low-pressure chemical vapor deposition.

5. The method of any one of claims 1-4, wherein, The deposition of step d) is carried out at a rate greater than 10 microns / hour.

6. The method of claim 1, wherein, At the end of the deposition of step d), the carrier substrate (20) has a thickness greater than or equal to 50 microns, even greater than or equal to 100 microns.

7. The method of claim 1, wherein, Step a) comprises forming a monocrystalline conversion layer (13) on the initial substrate (11) for converting basal plane dislocation defects of the initial substrate (11) into screw edge dislocation defects.

8. The method of claim 1, wherein, The temperature at which the separation step e) is operated is greater than or equal to the temperature of the deposition of step d).

9. The method of claim 1, wherein, Step f) comprises simultaneously chemically-mechanically polishing the front and back faces of the composite structure (1).

10. Method according to claim 1, comprising a step of heat treatment at a temperature comprised between 1000°C and 1800°C before or after step f).

11. Method according to claim 1, comprising a step of repairing the remaining portion (111') of the donor substrate to reuse it as an initial substrate or a donor substrate.

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