Bonding assembly having vertical power and control signal connections adjacent to a sense amplifier region and method of forming the same

Abstract

The present invention provides a bonding assembly, the bonding assembly comprising: a memory die including a memory device and a plurality of bit lines, and a logic die bonded to the memory die. The logic die includes a control circuit configured to control the operation of the memory device. The control circuit includes a peripheral circuit region, a sense amplifier region, and a power and control signal region, the power and control signal region being positioned adjacent to the sense amplifier region and including at least one power and control signal interconnect structure configured to provide power or control signals to or from the peripheral circuit region.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non - Provisional Patent Application No. 16 / 774,372, filed on January 28, 2020, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices and, more particularly, to a bonding assembly of a semiconductor die including vertical power and control signal connections adjacent to a sense amplifier region and a method of forming the same. Background Art

[0004] A bonding assembly of a memory die and a logic die can provide a high - performance three - dimensional memory device. The logic die can include control circuitry for controlling the operation of a three - dimensional memory array within the memory die. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a bonding assembly includes: a memory die including memory devices and a plurality of bit lines, and a logic die bonded to the memory die. The logic die includes control circuitry configured to control the operation of the memory devices. The control circuitry includes a peripheral circuit region, a sense amplifier region, and a power and control signal region that is positioned adjacent to the sense amplifier region and includes at least one power and control signal interconnect structure configured to provide power or control signals to or from the peripheral circuit region.

[0006] According to another aspect of the present disclosure, a method of forming a bonding assembly includes: providing a memory die including memory devices and bit lines; providing a logic die including control circuitry configured to control the operation of the memory devices, wherein the control circuitry includes a peripheral circuit region, a sense amplifier region, and a power and control signal region that is positioned adjacent to the sense amplifier region and includes at least one power and control signal interconnect structure configured to provide power or control signals to or from the peripheral circuit region; and bonding the logic die to the memory die. Brief Description of the Drawings

[0007] Figure 1A is a schematic vertical cross - sectional view of a memory die in a first configuration after forming a memory - side bonding dielectric layer and a memory - side bonding pad, according to one embodiment of the present disclosure.

[0008] Figure 1B is Figure 1A a top - down view of the memory die of

[0009] Figure 1C Is a schematic vertical cross-sectional close-up view of an area of a memory opening filling structure of a memory die including Figure 1A .

[0010] Figure 2A Is a schematic vertical cross-sectional view of a logic die in a first configuration after forming a logic-side bonding dielectric layer and a logic-side bonding pad according to an embodiment of the present disclosure.

[0011] Figure 2B Is Figure 2A A schematic horizontal cross-sectional view of an area of the logic die along plane B-B'.

[0012] Figure 2C Is Figure 2A A top-down view of the logic die.

[0013] Figure 3 Is according to an embodiment of the present disclosure Figure 1A And Figure 1B Of the memory die and Figure 2A And Figure 2B A vertical cross-sectional view of a bonding assembly of the logic die.

[0014] Figure 4A And Figure 4B Show a plan view of an alternative embodiment of a memory array area of a memory die in a bonding assembly located Figure 3 And a plan view of a power and control signal area and a sense amplifier area of the logic die.

[0015] Figure 5 Is a vertical cross-sectional view of a bonding assembly after thinning the back side of a substrate within a memory die according to an embodiment of the present disclosure.

[0016] Figure 6 Is a vertical cross-sectional view of a bonding assembly after forming a back-side insulating layer, external bonding pads, and solder material portions according to an embodiment of the present disclosure.

[0017] Figure 7A Is according to a first embodiment of the present disclosure Figure 6 A schematic horizontal cross-sectional view of a logic die within a bonding assembly.

[0018] Figure 7B Is including Figure 7A A perspective view of a portion of a logic die including area B shown.

[0019] Figure 8A Is a schematic horizontal cross-sectional view of a second configuration of a logic die according to a second embodiment of the present disclosure.

[0020] Figure 8Bis part of a logic die including Figure 8A a perspective view of the area C shown. DETAILED DESCRIPTION

[0021] The interconnection between the logic die and the memory die includes several vertical levels of metal wiring, which increases the total production cost of the bonding assembly. As described above, embodiments of the present disclosure relate to a bonding assembly of semiconductor dies including vertical power and control signal connections adjacent to a sense amplifier region and a method of forming the same, aspects of which will be described in detail below. The vertical power and control signal connections may be located between two read amplifier regions and / or adjacent to the read amplifier region below a platform (i.e., step) region in the word line switch region. These vertical connection locations may eliminate an additional vertical level of metal interconnect, which simplifies the process and reduces the production cost of the device.

[0022] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Ordinal numbers such as "first", "second", and "third" are used solely to identify similar elements and different ordinal numbers may be used throughout the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0023] Like reference numerals denote like or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or mutually, then the two elements are "separated" from each other or mutually "separated". As used herein, a first element positioned "on" a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected to" a second element if there is an electrical conduction path between the first element and the second element composed of at least one conductive material. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0024] As used herein, a "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer can be a region in a uniform or non-uniform continuous structure that has a thickness less than the thickness of the first continuous structure. For example, a layer can be positioned between the top and bottom surfaces of the first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. The layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, above it, and / or below it.

[0025] As used herein, if a second surface is above or below a first surface and if there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface, then the first surface and the second surface are "vertically coincident" with each other. A substantially vertical plane is a plane that extends linearly in a direction that is at an angle of less than 5 degrees from the vertical direction. The vertical plane or the substantially vertical plane is straight along the vertical direction or the substantially vertical direction and can include or not include curvature in a direction perpendicular to the vertical direction or the substantially vertical direction.

[0026] As used herein, a "memory level" or "memory array level" refers to a level of a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) corresponding to the topmost surface of an array of memory elements and a second horizontal plane that includes the bottommost surface of the array of memory elements. As used herein, a "through-stack" element is an element that extends vertically through the memory level.

[0027] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of electrical dopants and capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 5 S / m when appropriately doped with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulator material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5A material with a conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×10 5 S / m) when formed as a crystalline material or when converted to a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. An "intrinsic semiconductor material" refers to a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of the electrical dopant therein. As used herein, "metal material" refers to a conductive material including at least one metal element. All conductivity measurements are made under standard conditions.

[0028] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 titled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned before bonding or removed from the memory levels, but since the memory levels were initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays.

[0029] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips"), which are through-bonded, for example, by flip-chip bonding or another chip-to-chip bonding method. The package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of its planes. Each die includes one or more planes. The same concurrent operations can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0030] Reference Figure 1A and Figure 1B , a first semiconductor die 900 according to an embodiment of the present disclosure is shown. The first semiconductor die 900 includes a first substrate 908, a first semiconductor device 920 covering the first substrate 908, a first dielectric material layer (290, 960, 970) covering the first semiconductor device, and a first metal interconnect structure 980 embedded in the first dielectric material layer (290, 960, 970). In one embodiment, the first substrate 908 may be a commercially available silicon wafer with a thickness in the range of 500 micrometers to 1 mm.

[0031] By applying a photoresist layer above the upper surface of the first substrate 908, lithographically patterning the photoresist layer to form an array of discrete openings, and transferring the pattern of the array of discrete openings into the upper portion of the first substrate by performing an anisotropic etching process, discrete substrate recess cavities can be formed in the upper portion of the first substrate 908. Subsequently, the photoresist layer can be removed, for example, by ashing. The depth of each discrete substrate recess cavity can be in the range of 500 nm to 10,000 nm, but smaller and larger depths can also be used. A dielectric through-substrate liner 386 (e.g., a silicon oxide liner) and a conductive through-substrate via structure 388 (e.g., a tungsten via structure) can be formed within each discrete substrate recess cavity.

[0032] Typically, the first semiconductor device 920 may include any semiconductor device known in the art. In one embodiment, the first semiconductor die 900 includes a memory die and may include a memory device, such as a three-dimensional NAND memory device. In an illustrative example, the first semiconductor device 920 may include a vertical alternating stack of an insulating layer 32 and a conductive layer 46, and a two-dimensional array of memory openings extending vertically through the vertical alternating stack (32, 46). The conductive layer 46 may include word lines of the three-dimensional NAND memory device.

[0033] A memory opening fill structure 58 may be formed within each memory opening in the memory array region 100. As Figure 1C shown, the memory opening fill structure 58 may include a memory film 50 and a vertical semiconductor channel 60 contacting the memory film. A drain region 63 is located on the top portion of the vertical semiconductor channel 60. An optional dielectric fill region 62 may be located below the drain region 63 and surrounded by the vertical semiconductor channel 60. The memory film may include a blocking dielectric 52, a tunneling dielectric 46, and a charge storage material 54 located between the blocking dielectric and the tunneling dielectric. The charge storage material 54 may include a charge trapping layer (such as a silicon nitride layer) or a plurality of discrete charge trapping regions (such as a floating gate or discrete portions of a charge trapping layer). The portion of the charge storage material 54 adjacent to the conductive layer (i.e., word line / control gate electrode) 46 includes a memory element (e.g., a memory cell). In this case, each memory opening fill structure 58 and the adjacent portion of the conductive layer 46 constitute a vertical NAND string. Alternatively, the memory opening fill structure 58 may include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase change memory element, etc. The memory device may include an optional horizontal semiconductor channel layer 10 connected to the bottom end of each vertical semiconductor channel, and an optional dielectric isolation layer 910 providing electrical isolation between the first substrate 908 and the horizontal semiconductor channel layer 10.

[0034] The conductive layer 46 may be patterned to provide a stepped region (i.e., a platform region) 200, where each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Contact via structures (not shown) may be formed on the conductive layer 46 in the platform region to provide electrical connection to the conductive layer 46. Dielectric material portions 65 may be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46).

[0035] The through-dielectric material portion 65, optional dielectric isolation layer 910, and horizontal semiconductor channel layer 10 form a through-memory hierarchical via cavity. Optional through-memory hierarchical dielectric liners 486 and through-memory hierarchical via structures 488 may be formed within each through-memory hierarchical via cavity. Each through-memory hierarchical dielectric liner 486 includes a dielectric material such as silicon oxide. Each through-memory hierarchical via structure 488 includes any suitable conductive material (e.g., tungsten, copper, titanium nitride, etc.) that may be formed directly on a corresponding one of the through-substrate via structures within the through-substrate via structure 388.

[0036] The first dielectric material layer (290, 960, 970) may include a first contact-level dielectric layer 290 that embeds contact via structures and bit lines 982, a first interconnect-level dielectric layer 960 that is a subset above the first contact-level dielectric layer 290 and embeds the first metal interconnect structure 980, and a first bonding dielectric layer 970 that is formed above the first interconnect-level dielectric layer 960. The bit lines 982 are a subset of the first metal interconnect structure 980 and may electrically contact the drain region 63 located above the semiconductor channel 60 at the top of the memory opening fill structure 58. The contact via structures contact respective nodes of the first semiconductor device or the through-memory hierarchical via structures 488. Interconnect metal lines and interconnect metal via structures (which are a subset of the first metal interconnect structure 980) may be embedded within the first interconnect-level dielectric layer 960. Thus, the first metal interconnect structure 980 may be located within the first interconnect-level dielectric layer 960. In one illustrative example, the first metal interconnect structure 980 may include a first memory-side metal tier M0 and a second memory-side metal tier M1, the first memory-side metal tier including memory-side first-tier metal lines (including bit lines 982 and other first-tier metal lines), and the second memory-side metal tier including memory-side second-tier metal lines.

[0037] Each of the first contact-level dielectric layer 290 and the first interconnect-level dielectric layer 960 may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, silicon nitride, dielectric metal oxide, or a combination thereof. The first bonding dielectric layer 970 may include a silicon oxide material (e.g., undoped silicate glass (e.g., silicon oxide) or doped silicate glass) and / or consist essentially of a silicon oxide material. The thickness of the first bonding dielectric layer 970 may be in the range of 100 nm to 3,000 nm, although smaller and larger thicknesses may also be employed. The first bonding dielectric layer 970 may have a flat top surface that may be provided, for example, by a planarization process such as a chemical mechanical polishing (CMP) process. The topmost layer within the first interconnect-level dielectric layer 960 may be a dielectric diffusion barrier layer (not explicitly shown), which may be a silicon nitride layer having a thickness in the range of 10 nm to 300 nm.

[0038] For example, a first bonding pad 988 is formed in the first bonding dielectric layer 970 by forming a bonding pad cavity in the first bonding dielectric layer 970 and filling the bonding pad cavity with at least one conductive material. Alternatively, the first bonding pad 988 is first formed on the first metal interconnect structure 980, then the first bonding dielectric layer 970 is formed above and around the first bonding pad 988, and then the first bonding dielectric layer 970 is planarized to expose the top surface of the first bonding pad 988. The at least one conductive material may be a metal (i.e., a metal or metal alloy) material that can be bonded to the same metal material or another metal material by metal-to-metal or hybrid bonding. For example, each first bonding pad in the first bonding pad 988 may include an optional metal liner and a metal fill material portion, the metal liner including TiN, TaN, and / or WN, and the metal fill material portion including a metal material that can be bonded to the same metal material or another metal material by metal-to-metal bonding. For example, the metal fill material portion may include any material selected from and / or consist essentially of: copper; a copper alloy containing a copper atom concentration greater than 70% (which may be greater than 90% and / or 95%); or a cobalt or nickel alloy, such as CoW, CoWP, CoMoP, NiW, and / or NiWP.

[0039] Each first bonding pad in the first bonding pad 988 is surrounded by the first bonding dielectric layer 970 and contacts a corresponding one of the first metal interconnect structures 980 below the first metal interconnect structure. Each first bonding pad in the first bonding pad 988 is electrically connected to a corresponding node of the first semiconductor device 920. In the case where the first semiconductor die 900 includes a memory die, the first bonding pad 988 is also referred to as a memory-side bonding pad.

[0040] Generally speaking, the first semiconductor die 900 may include a memory die. The memory die may include a three-dimensional memory element array located within a memory array region, the memory array region having an array region length l along a first horizontal direction hd1 (e.g., the bit line direction) and having an array region width w along a second horizontal direction hd2 (e.g., the word line direction) perpendicular to the first horizontal direction dh1. Memory elements (e.g., charge storage regions 54 in the memory film 50) may be arranged around a two-dimensional array of vertical semiconductor channels, and the bit lines 982 may be connected to the drain regions 63 at the top portions of corresponding subsets of the vertical semiconductor channels 60. The first semiconductor die 900 may include a through-substrate via structure 388 that is electrically connected to a subset of the first bonding pads 988 (i.e., memory-side bonding pads) located along the front-side edge of the first semiconductor die 900.

[0041] In Figure 1BIn one embodiment shown, the first bonding pad 988 may include a first input / output bonding pad 988A located within a pair of memory-side input / output regions MIO. The first input / output bonding pad 988A is connected to an input / output node of a corresponding one of the memory elements in the three-dimensional array of memory elements. In one embodiment, the memory-side input / output regions MIO may be positioned along a pair of front-side edges of the first semiconductor die 900. In one embodiment, a subset of the through-substrate via structures 388 and the through-memory-level via structures 488 may be located within the memory-side input / output regions MIO.

[0042] In one embodiment, the first bonding pad 988 may include a first word-line hook-up bonding pad 988B located above a stepped surface of a corresponding alternating stack of the insulating layer 32 and the conductive layer 46 in the stepped region 200. The first word-line hook-up bonding pad 988B is connected to a corresponding one of the conductive lines 46 that serve as word lines of the three-dimensional array of memory elements. Each cluster of the first word-line hook-up bonding pads 988B may be located within a corresponding memory-side word-line hook-up region MWLHU. Each memory-side word-line hook-up region MWLHU may be positioned adjacent to a corresponding memory-side input / output region MIO.

[0043] In one embodiment, the first bonding pad 988 may include a first bit-line hook-up bonding pad 988C positioned adjacent to a corresponding memory array region of a corresponding three-dimensional array including memory elements. The first bit-line hook-up bonding pad 988C is connected to a corresponding one of the bit lines 982. Each cluster of the first bit-line hook-up bonding pads 988C may be located within a corresponding memory-side bit-line hook-up region MBLHU. Each memory-side bit-line hook-up region MBLHU may be positioned adjacent to a corresponding memory-side input / output region MIO and a corresponding memory-side word-line hook-up region MWLHU.

[0044] In one embodiment, the first bonding pad 988 may include a first peripheral bonding pad 988D located within the area of a corresponding memory array region. The first peripheral bonding pad 988D is connected to various peripheral circuit elements located in the first semiconductor die 900. The various peripheral circuit elements may include, for example, a source-side select electrode and a drain-side select electrode. In one embodiment, the source-side select electrode may include a set of at least one bottommost conductive layer within each alternating stack of the insulating layer 32 and the conductive layer 46, and the drain-side select electrode may include a set of at least one topmost conductive layer within each alternating stack of the insulating layer 32 and the conductive layer 46. Each cluster of the first peripheral bonding pads 988D may be located within a corresponding memory-side peripheral connection region MPERI. Each memory-side peripheral connection region MPERI may be positioned adjacent to a corresponding memory-side bit line hook-up region MBLHU and a corresponding memory-side word line hook-up region MWLHU. In an illustrative example, each memory-side word line hook-up region MWLHU may be positioned adjacent to the memory-side peripheral connection region MPERI and may be laterally offset therefrom along a second horizontal direction (e.g., the word line direction) hd2. Additionally, each memory-side bit line hook-up region MBLHU may be positioned adjacent to the memory-side peripheral connection region MPERI and may be laterally offset therefrom along a first horizontal direction hd1 (e.g., the bit line direction).

[0045] Each memory-side power and control signal region MPCS may not include the first bonding pad 988, or if the device requires additional bonding pads, it may include various first bonding pads 988E. Each memory-side power and control signal region MPCS may be positioned adjacent to a corresponding memory-side peripheral connection region MPERI, a corresponding memory-side bit line hook-up region MBLHU, and a corresponding memory-side input / output region MIO. In an illustrative example, each memory-side power and control signal region MPCS may be laterally offset from the corresponding memory-side peripheral connection region MPERI and from the corresponding memory-side input / output region MIO along the first horizontal direction hd1, and may be laterally offset from the corresponding memory-side bit line hook-up region MBLHU along the second horizontal direction hd2. In other words, each memory-side power and control signal region MPCS may be located between the corresponding memory-side peripheral connection region MPERI and the corresponding memory-side input / output region MIO along the first horizontal direction hd1. Additionally, each memory-side power and control signal region MPCS may be located between two corresponding memory-side bit line hook-up regions MBLHU along the second horizontal direction hd2.

[0046] Reference Figures 2A to 2C, showing the second semiconductor die 700. The second semiconductor die 700 includes a second substrate 708, a second semiconductor device 720 covering the second substrate 708, second dielectric material layers (760, 770) covering the second semiconductor device 720, and a second metal interconnect structure 780 embedded in the second dielectric material layers (760, 770). At least one of the second metal interconnect structures in the second metal interconnect structure 780 may include a power and control signal interconnect structure 780P located in the power and control signal region PCS.

[0047] In one embodiment, the second semiconductor device 720 may include field effect transistors in a complementary metal oxide semiconductor (CMOS) configuration. In one embodiment, the second substrate 708 may be a commercially available silicon substrate with a thickness in the range of 500 microns to 1 mm.

[0048] Generally speaking, the second semiconductor device may include any semiconductor device that can operate in combination with the first semiconductor device in the first semiconductor die 900 to provide enhanced functionality. In one embodiment, the first semiconductor die 900 includes a memory die and the second semiconductor die 700 includes a logic die, and the logic die includes support circuits (i.e., control circuits, such as peripheral circuits) for the operation of memory devices (such as a three-dimensional array of memory elements) within the memory die. In one embodiment, the first semiconductor die 900 may include a three-dimensional memory device (which includes a three-dimensional array of memory elements), word lines (which may include a subset of the conductive lines 46), and bit lines 982, and the second semiconductor device 720 of the second semiconductor die 700 may include peripheral circuits for the operation of the three-dimensional array of memory elements. The peripheral circuits may include: one or more word line driver circuits for driving the word lines of the three-dimensional array of memory elements of the first semiconductor die 900; one or more bit line driver circuits for driving the bit lines 982 of the first semiconductor die 900; one or more word line decoder circuits for address decoding of the word lines; one or more bit line decoder circuits for address decoding of the bit lines 982; one or more sense amplifier circuits for sensing the state of the memory elements within the memory opening filling structure 58 of the first semiconductor die 900; a source power supply circuit for supplying power to the horizontal semiconductor channel layer 10 in the first semiconductor die 900; data buffers and / or latches, and / or any other semiconductor circuits that can be used to operate the three-dimensional memory device of the first semiconductor die 900.

[0049] The second dielectric material layer (760, 770) may include a second interconnect level dielectric layer 760 embedding the second metal interconnect structure 780, and a second bonding dielectric layer 770 formed above the second interconnect level dielectric layer 760. The second interconnect level dielectric layer 760 may include a dielectric material such as undoped silicate glass (e.g., silicon oxide), doped silicate glass, organosilicate glass, silicon nitride, dielectric metal oxide, or a combination thereof. In one illustrative example, the second metal interconnect structure 780 may include a first logic side metal level D0, a second logic side metal level D1, and a third logic side metal level D2. The first logic side metal level includes logic side first level metal lines, the second logic side metal level includes logic side second level metal lines, and the third logic side metal level includes logic side third level metal lines. Level D0 may be used for local routing / interconnect, level D1 may be used for bus routing / interconnect, and level D2 may be used for global routing / interconnect. As described below, the fourth logic side metal level may be omitted, and global delivery may be provided by vertical interconnects located in the power and control signal region PCS adjacent to the sense amplifier region.

[0050] The second bonding dielectric layer 770 may include undoped silicate glass or doped silicate glass (e.g., doped or undoped silicon oxide material). The thickness of the second bonding dielectric layer 770 may be in the range of 100 nm to 3,000 nm, but smaller and larger thicknesses may also be employed. The second bonding dielectric layer 770 may have a flat top surface that may be provided, for example, by a planarization process such as a chemical mechanical polishing (CMP) process.

[0051] For example, a second bonding pad 788 is formed in the second bonding dielectric layer 770 by forming a bonding pad cavity in the second bonding dielectric layer 770 and filling the bonding pad cavity with at least one conductive material. Alternatively, the second bonding pad 788 is first formed on the second metal interconnect structure 780, then the second bonding dielectric layer 770 is formed above and around the second bonding pad 788, and then the second bonding dielectric layer 770 is planarized to expose the top surface of the second bonding pad 788. The at least one conductive material may be a metal (i.e., a metal or metal alloy) material that can be bonded to the same metal material or another metal material by metal-to-metal or hybrid bonding. For example, each first bonding pad in the first bonding pad 988 may include an optional metal liner and a metal fill material portion, the metal liner including TiN, TaN, and / or WN, and the metal fill material portion including a metal material that can be bonded to the same metal material or another metal material by metal-to-metal bonding. For example, the metal fill material portion may include any material selected from and / or consist essentially of: copper; a copper alloy containing a copper atom concentration greater than 70% (which may be greater than 90% and / or 95%); or a cobalt or nickel alloy such as CoW, CoWP, CoMoP, NiW, and / or NiWP. The material of the second bonding pad 788 may be the same as or different from the material of the first bonding pad 988.

[0052] Each second bonding pad in the second bonding pad 788 is embedded in the second bonding dielectric layer 770 and contacts a corresponding one of the second metal interconnect structures 780 below the second metal interconnect structure. Each second bonding pad in the second bonding pad 788 is electrically connected to a corresponding node of the second semiconductor device 720. When the second semiconductor die 700 includes a logic die, the second bonding pad 788 is also referred to as a logic-side bonding pad.

[0053] The device types of the first semiconductor die 900 and the second semiconductor die 700 can be selected in any manner such that the devices 920 of the first semiconductor die 900 and the second semiconductor devices 720 of the second semiconductor die 700 can communicate with each other, control devices in the other semiconductor die, or be controlled by devices in the other semiconductor die. In one embodiment, one of the first semiconductor die 900 and the second semiconductor die 700 includes a memory die including memory elements (such as a three-dimensional array of memory elements), and the other of the first semiconductor die 900 and the second semiconductor die 700 includes a logic die including peripheral circuits configured to operate the memory elements (such as a three-dimensional array of memory elements).

[0054] Generally speaking, the second semiconductor die 700 may include a logic die. The logic die may include a control circuit 702 configured to control the operation of a three-dimensional array of memory elements of the second semiconductor die 900. Figure 2BAn example of a logic die 700 configured to control a memory die 900 including four memory planes is shown. However, the logic die 700 may be configured to control a memory die 900 including fewer than four (e.g., one or more) or more than four (e.g., six to eight) memory planes. As Figure 2B shown, the control circuit 702 includes: a peripheral circuit region (PERI) located within an area that overlaps in a planar view with the area of the memory array region 100 of the first semiconductor die 900 after the first semiconductor die 900 is bonded to the second semiconductor die 700; a sense amplifier region (S / A) laterally offset from the peripheral circuit region PERI along a first horizontal direction (e.g., bit line direction) hd1; a word line switch region (WLSW) located between respective peripheral regions PERI and between respective sense amplifier regions S / A along a second horizontal direction (e.g., word line direction) hd2; an input / output circuit region (I / O) positioned along at least one edge of the logic die; and a power and control signal region (PCS) having a boundary that abuts the peripheral circuit region PERI, the sense amplifier region S / A, and the input / output circuit region I / O. The peripheral circuit region PERI may include one or more of a bit line drive circuit ( Figure 7B and Figure 8B BLDRV as shown in

[0055] ), a bit line decoder / column direction logic control circuit, a latch circuit serving as a cache memory for the NAND memory device 920, a word line drive circuit, a memory well bias circuit, a shunt circuit, and various other circuits. The word line switch WLSW region may include word line control transistors, a word line decoder, and optionally a word line drive circuit.

[0056] In one embodiment, the control circuit 702 may include an input / output circuit region I / O positioned along the edge of the logic die, and the power and control signal region PCS may have a boundary that abuts the peripheral circuit region PERI, the sense amplifier region S / A, and the input / output circuit region I / O. In one embodiment, the logic die includes a metal interconnect structure, i.e., a second metal interconnect structure 780, that electrically connects nodes of the input / output circuit region (e.g., nodes of the power and control signal vias) to a subset 788A of second bond pads 788 positioned along the front-side edge of the logic die.

[0057] As Figure 2C shown, the second bond pads 788 may be arranged in a mirror image pattern of the first bond pads 988. For example, if the first bond pads 988 are arranged as a first I×J rectangular periodic array, the second bond pads 788 may be arranged as a second I×J rectangular periodic array having the same period as the first I×J rectangular periodic array. I and J may be independent integers greater than 8. For example, I of the second bond pads 788 may be located within each column of the second bond pads 788 extending along a first horizontal direction hd1, and J of the second bond pads 788 may be located within each row of the second bond pads 788 extending along a second horizontal direction hd2. In one embodiment, the second bond pads 788 may have the same size as the first bond pads 988. In another embodiment, the size of the second bond pads 788 may be modified relative to the size of the first bond pads 988. In this case, the second bond pads 788 may be larger or smaller than the first bond pads 988.

[0058] In one embodiment, the second bond pads 788 may include second input / output bond pads 788A located within a pair of logic-side input / output regions LIO. The second input / output bond pads 788A are connected to nodes of the input / output circuit region I / O positioned along at least one edge of the second semiconductor die 700. In one embodiment, the logic-side input / output regions LIO may be positioned along one or a pair of front-side edges of the second semiconductor die 700. The area of the logic-side input / output regions LIO of the second semiconductor die 700 may be a mirror image of the area of the memory-side input / output regions MIO of the first semiconductor die 900. The input / output circuit region I / O is located below the region LIO.

[0059] In one embodiment, after bonding the memory die 900 to the logic die 700, the second bonding pad 788 may include a second word line routing bonding pad 788B above the stepped surface of the respective alternating stacks of the insulating layer 32 and the conductive layer 46 in the stepped (i.e., platform) region 200 of the memory die 900. The second word line hook-up bonding pad 788B is connected to the respective nodes of the word line decoder in the word line switch region WLSW. Each cluster of the second word line hook-up bonding pads 788B may be located within the respective logic side word line hook-up region LWLHU. The word line decoder provides control signals through each logic side word line hook-up region LWLHU to activate a selected subset of the word lines 46 in the respective three-dimensional memory devices 920 in the first semiconductor die 900. The word line decoder in the word line switch region WLSW is located below the region LWLHU. Each logic side word line hook-up region LWLHU may be positioned adjacent to the respective logic side input / output region LIO along a first horizontal direction (e.g., the bit line direction) hd1. The area of the logic side word line hook-up region LWLHU of the second semiconductor die 700 may be a mirror image of the area of the memory side word line hook-up region MWLHU of the first semiconductor die 900.

[0060] In one embodiment, the second bonding pad 788 may include a second bit line hook-up bonding pad 788C connected to a sense amplifier within the second semiconductor die 700. The area of the second bit line hook-up bonding pad 788C is referred to herein as the logic side bit line hook-up region LBLHU. The area of the sense amplifier is referred to herein as the sense amplifier region S / A. In one embodiment, the sense amplifier region S / A may be located below the logic side bit line hook-up region LBLHU. In another embodiment, the sense amplifier region may have an area that overlaps with at least 50% and / or at least 80% and / or at least 90% of the area of the logic side bit line hook-up region LBLHU. Each cluster of the second bit line hook-up bonding pads 788C may be located within the respective logic side bit line hook-up region LBLHU. Each logic side bit line hook-up region LBLHU may be positioned adjacent to the respective logic side input / output region LIO along the first horizontal direction hd1 and adjacent to the respective logic side word line hook-up region LWLHU along a second horizontal direction. Thus, each region LWLHU located above the word line switch region WLSW may be positioned between two regions LBLHU (which are located above the respective sense amplifier regions S / A) along the second horizontal direction hd2. The area of the logic side bit line hook-up region LBLHU of the second semiconductor die 700 may be a mirror image of the area of the memory side bit line hook-up region MBLHU of the first semiconductor die 900.

[0061] In one embodiment, the second bonding pad 788 may include a second peripheral bonding pad 788D located within the area of the corresponding logic-side peripheral connection region LPERI, which area is located above the peripheral circuit region PERI. The second peripheral bonding pad 788D is connected to various peripheral circuit elements in the corresponding peripheral circuit region in the second semiconductor die 700. Each peripheral circuit region may be located within an area that is a mirror overlap of the area of the corresponding memory array region in the first semiconductor die 900. In one embodiment, each sense amplifier region located below the region LBLHU may be laterally offset from the corresponding peripheral circuit region located below the region LPERI along the first horizontal direction hd1.

[0062] The various peripheral circuit elements in the region PERI may include, for example, control transistors configured in CMOS to generate control signals for bit lines and / or word lines in the three-dimensional memory array in the first semiconductor die 900. Each cluster of the second peripheral bonding pads 788D may be located within the corresponding logic-side peripheral connection region LPERI. Each logic-side peripheral connection region LBLHU may be positioned adjacent to the corresponding logic-side input / output region LIO along the first horizontal direction and adjacent to the corresponding logic-side word line hook-up region LWLHU along the second horizontal direction. In an illustrative example, each logic-side word line hook-up region LWLHU may be positioned adjacent to the logic-side peripheral connection region LPERI and may be laterally offset from it along the second horizontal direction hd2. Further, each logic-side bit line hook-up region LBLHU may be positioned adjacent to the logic-side peripheral connection region LPERI and may be laterally offset from it along the first horizontal direction hd1. The area of the logic-side peripheral connection region LBLHU of the second semiconductor die 700 may be a mirror of the area of the memory-side peripheral connection region MBLHU of the first semiconductor die 900.

[0063] According to one aspect of the present disclosure, the region LPCS may not have any second bonding pads 788. Alternatively, if additional bonding pads are desired, the second bonding pads 788 may include second various bonding pads 788E in the region LPCS. The power supply and control interconnect structure 780P is a subset of the second metal interconnect structure 780 configured to transmit a power supply voltage and control signals. The area of the group of power supply and control interconnect structures is referred to herein as the power supply and control signal region PCS. If present, the second various bonding pads 788E may be located within the corresponding logic side power and control signal region LPCS that covers the power supply and control signal region PCS. Each logic side power and control signal region LPCS may be positioned adjacent to the corresponding logic side peripheral connection region LPERI along a first horizontal direction hd1, adjacent to the corresponding logic side bit line hook-up region LBLHU along a second horizontal direction hd2, and adjacent to the corresponding logic side input / output region LIO along the first horizontal direction hd1. In one illustrative example, each logic side power and control signal region LPCS may be located between the corresponding logic side peripheral connection region LPERI and the corresponding logic side input / output region LIO and be laterally offset from both along the first horizontal direction hd1, and may be located between two corresponding logic side bit line hook-up regions LBLHU and be laterally offset from both along the second horizontal direction hd2.

[0064] The area of the logic side power and control signal region LPCS of the second semiconductor die 700 may be a mirror image of the area of the memory side power and control signal region LPCS of the first semiconductor die 900. In one embodiment, each power and control signal region PCS may have a boundary that interfaces with the corresponding peripheral circuit region PERI, the corresponding sense amplifier region S / A, and the input / output circuit region I / O, as Figure 2B shown.

[0065] Reference Figure 3, the first semiconductor die 900 and the second semiconductor die 700 are oriented such that the first bonding dielectric layer 970 faces the second bonding dielectric layer 770. The second semiconductor die 700 and the first semiconductor die 900 are brought into contact such that the surface of the second bonding dielectric layer 770 contacts the surface of the first bonding dielectric layer 970, and each surface of the second bonding pads 788 contacts the surface of a corresponding one of the first bonding pads 988 in the first bonding pads. In one embodiment, the pattern of the second bonding pads 788 may be a mirror image of the pattern of the first bonding pads 988, where there may be an optional difference in the size of the bonding pads between the first semiconductor die 900 and the second semiconductor die 700. In one embodiment, the first bonding pads 988 and the corresponding second bonding pads 788 may have the same size (i.e., lateral width). In another embodiment, the first bonding pads 988 and the corresponding second bonding pads 788 may have different sizes. In one embodiment, the area overlap between each facing pair of the first bonding pads 988 and the second bonding pads 788 may be at least 80% and / or at least 90%, such as 90% to 100%, of the area of the smaller of the first bonding pads 988 and the second bonding pads 788.

[0066] The second bonding pads 788 may be bonded to the first bonding pads 988 by performing an annealing process that causes a metal-to-metal bond between the second bonding pads 788 and the first bonding pads 988 and optionally causes a dielectric bond between the first bonding dielectric layer 970 and the second bonding dielectric layer 770. The annealing temperature may be selected based on the composition of the second bonding pads 788 and the first bonding pads 988. For example, if the second bonding pads 788 and the first bonding pads 988 include a metal-filled portion consisting primarily of copper, the annealing temperature may be in the range of 250 degrees Celsius to 400 degrees Celsius.

[0067] Each second input / output bonding pad in the second input / output bonding pads 788A located within a pair of logic-side input / output regions LIO can be bonded to a corresponding one of the first input / output bonding pads 988A located within the pair of memory-side input / output regions MIO. Accordingly, the input / output nodes in the first semiconductor die 900 are electrically connected to the nodes of the input / output circuit control circuit 702 in the second semiconductor die 700 through the bonding pairs of the second input / output bonding pads 788A and the first input / output bonding pads 988A. This subset of bonding pads (788A, 988B) is configured to transmit power and / or control signals through the power and control signal interconnect structure 780P located in the power and control signal region PCS of the second semiconductor die 700. The power or control signal is transmitted between the first semiconductor die 900 (which may be a memory die) and the peripheral circuit region PERI of the second semiconductor die 700 and / or between the peripheral circuit region PERI of the second semiconductor die 700 and the sense amplifier region S / A.

[0068] In a plan view that is a view along a direction perpendicular to the bonding interface 800 between the first semiconductor die 900 and the second semiconductor die 700, the area of the logic-side input / output region LIO can be the same as the area of the memory-side input / output region MIO.

[0069] The through-substrate via structure 388 in the first semiconductor die 900 can be electrically connected to a subset (e.g., the memory-side input / output bonding pads 988A) located along the front-side edge of the first semiconductor die 900 of the first bonding pads 988. The second semiconductor die 700 (which may be a logic die) can include a second metal interconnect structure 788 that electrically connects the nodes of the input / output circuit region I / O to the second input / output bonding pads 788A (which may be a subset of the logic-side bonding pads located along the front-side edge of the second semiconductor die 700).

[0070] Each second word-line hook-up bonding pad in the second word-line hook-up bonding pads 788B located within the corresponding logic-side word-line hook-up region LWLHU can be bonded to a corresponding one of the first word-line hook-up bonding pads 988B located within the corresponding memory-side word-line hook-up region MWLHU. Accordingly, the conductive lines 46 serving as word-lines of the three-dimensional array of memory elements are connected to the corresponding nodes of the word-line decoder located in the word-line switch region WLSW through the corresponding bonding pairs of the second word-line hook-up bonding pads 788B and the first word-line hook-up bonding pads 988B. In a plan view, the area of the logic-side word-line hook-up region LWLHU of the second semiconductor die 700 can be the same as the area of the memory-side word-line hook-up region MWLHU of the first semiconductor die 900.

[0071] Each second bit line hook connection pad 788C within the logical side bit line hook-up region LBLHU can be joined to a corresponding one of the first bit line hook connection pads 988C within the corresponding memory side bit line hook-up region within the memory side bit line hook-up region MBLHU. Accordingly, each bit line 982 in the first semiconductor die 900 can be electrically connected to a corresponding sense amplifier in one of the sense amplifier regions in the sense amplifier region S / A in the second semiconductor die 700 via the joining pair of the second bit line hook connection pad 788C and the first bit line hook connection pad 988C. In a plan view, the area of the logical side bit line hook-up region LBLHU of the second semiconductor die 700 can be the same as the area of the memory side bit line hook-up region MBLHU of the first semiconductor die 900.

[0072] Each second peripheral pad 788D within the logical side peripheral connection region LPERI can be joined to a corresponding one of the first peripheral pads 988D within the corresponding memory side peripheral connection region within the memory side peripheral connection region MPERI. Accordingly, peripheral circuit elements (such as source side select electrodes and drain side select electrodes) in the first semiconductor die 900 are electrically connected to peripheral circuit elements (such as select electrode drivers) in the second semiconductor die 700 via the pair of the second peripheral pad 788D and the first peripheral pad 988D. In a plan view, the area of the logical side peripheral connection region LPERI of the second semiconductor die 700 can be the same as the area of the memory side peripheral connection region MPERI of the first semiconductor die 900.

[0073] As will be referred to below Figure 7B and Figure 8B As described, the vertical and lateral interconnections between the corresponding read amplifier drive circuit (SADRV) elements in the peripheral circuit region PERI and the corresponding read amplifier circuit elements in the read amplifier region S / A, and between the peripheral circuit region PERI and the corresponding elements in the input / output circuit region I / O, extend through the power and control signal region PCS located below the logical side power and control signal region LPCS. In a plan view, the area of the logical side power and control signal region LPCS of the second semiconductor die 700 can be the same as the area of the memory side power and control signal region MPCS of the first semiconductor die 900.

[0074] Figure 4A shown Figure 3A plan view of a memory array region 100 of a memory die 900 and a plan view of a sense amplifier region S / A and a power and control signal region PCS of a logic die 700 within a bonding assembly. The memory array region 100 of the first semiconductor die 900 may include a three-dimensional array of memory elements 920 and overlying bit lines 982. The area of the memory array region 100 may be the same as or may substantially overlap with the area of the memory side peripheral region MPERI. For example, at least 50% (such as at least 80%) of the entire area of the memory side peripheral region MPERI may overlap with the area of the memory array region. In one embodiment, the area of the memory array region 100 may be the same as the area of the memory side peripheral region MPERI. The memory array region 100 may overlie L bit lines. The bit lines 982 in the first semiconductor die 900 may extend laterally in a first horizontal direction (e.g., the bit line direction) hd1 and may be separated from each other in a second horizontal direction (e.g., the word line direction) hd2 within the bonding assembly of the first semiconductor die 900 and the second semiconductor die 700.

[0075] The area of the sense amplifier region S / A may be the same as or may substantially overlap with the area of the logic side bit line hook-up region LBLHU. For example, at least 50% (such as at least 90%) of the entire area of the logic side bit line hook-up region LBLHU may overlap with the area of the sense amplifier region. In one embodiment, the area of the sense amplifier region S / A may be the same as the area of the logic side bit line hook-up region LBLHU. In one embodiment, the sense amplifier region S / A includes N sense amplifier assemblies SAA arranged in the second horizontal direction hd2. Each sense amplifier assembly in the sense amplifier assemblies SAA may include M sense amplifier units SAU arranged in the first horizontal direction hd1. The total number of sense amplifier units may be M×N, which is the same as the total number of bit lines L. Each sense amplifier unit SAU may include at least one field effect transistor and may be used to activate a corresponding one of the bit lines 982.

[0076] Figure 4B shown Figure 3 A plan view of a memory array region 100 of a memory die 900 and an alternative embodiment of a sense amplifier region S / A and a power and control signal region PCS of a logic die 700 within a bonding assembly. In this alternative embodiment, a plurality of sense amplifier regions S / A and power and control signal regions PCS alternate in the second horizontal direction. Thus, the power and control signal region PCS may be located between two sense amplifier regions S / A, and the sense amplifier regions S / A may be located between two power and control signal regions PCS.

[0077] According to one aspect of the present disclosure, a total of L bit lines 982 may extend horizontally along a first horizontal direction hd1 and may have a bit line pitch P along a second horizontal direction hd2. In this case, the width WB of the area occupied by the bit lines 982 may be at least L×P (e.g., WB = L×P) along the second horizontal direction hd2. If there is an intermediate structure between the L bit lines 982, the width WB of the area occupied by the bit lines 982 along the second horizontal direction hd2 may be greater.

[0078] The sense amplifier assemblies SAA may be arranged in a one-dimensional array along the second horizontal direction hd2, and the pitch of the sense amplifier assemblies SAA along the second horizontal direction hd2 may be less than M times the pitch P of the bit lines 982 along the second horizontal direction hd2. For example, the pitch P of the sense amplifier assemblies SAA along the second horizontal direction hd2 may be in the range of 40% to 90%, such as 60% to 80%, of the product of the number M and the pitch of the bit lines 982 along the second horizontal direction hd2. Accordingly, the width of the sense amplifier region along the second horizontal direction hd2 may be in the range of 40% to 90%, such as 60% to 80%, of the product of the number M and the pitch P of the bit lines 982 along the second horizontal direction hd2. The width WB of the memory array region 100 in the first semiconductor die 900 along the second horizontal direction hd2 may be the same as the product of the number L and the pitch P of the bit lines 982 along the second horizontal direction hd2. The sum of the widths of the power and control signal region PCS and the sense amplifier region S / A along the second horizontal direction hd2 may be the same as the width WB of the memory array region 100 along the second horizontal direction hd2. The width of the sense amplifier region S / A along the second horizontal direction hd2 may be less than the width WB.

[0079] In one embodiment, each sense amplifier assembly SAA may include 16 sense amplifier units SAU (i.e., M = 16). Each of the corresponding 16 sense amplifier units SAU in the SAA may be electrically connected to 16 corresponding bit lines 982, such that each sense amplifier unit SAU is electrically connected to and controls a corresponding one of the bit lines 982. However, the width (WS) of each sense amplifier assembly SAA along the second horizontal direction hd2 may be shorter than (i.e., less than) the width of the pitch of the 16 corresponding bit lines 982 along the second horizontal direction hd2 (i.e., WS < 16×P, or more generally WS < M×P). This results in an effective sense amplifier unit SAU pitch that is less than the bit line pitch P. For example, if the width (WS) of each sense amplifier assembly SAA along the second horizontal direction is equal to the width of the pitch of 12 corresponding bit lines 982 (i.e., M - X bit lines, where X is a positive integer), the pitch ratio of the effective sense amplifier unit SAU pitch to the bit line pitch P is equal to 0.75. This leaves additional space for the power and signal connection area PCS in the second horizontal direction. It should be noted that each SAA may include more or less than 16 SAUs, and the width WS may be greater or less than the width of 12 bit lines. Thus, each SAA includes M SAUs that are electrically connected to M corresponding bit lines 982. The width WS of each SAA in the second horizontal direction hd2 is less than M×P, where P is the bit line pitch in the second horizontal direction (i.e., the word line direction) hd2.

[0080] Accordingly, the width of the logical side bit line hook-up region LBLHU along the second horizontal direction hd2 may be less than the width of the logical side peripheral region LPERI along the second horizontal direction hd2, which may be the same as the width of the memory side peripheral region MPERI along the second horizontal direction hd2. Each of the sense amplifier units SAU in the sense amplifier unit may be electrically connected to a corresponding one of the bit lines 982 in the memory die (i.e., the first semiconductor die 900) via a second bit line hook-up bonding pad 788C and a first bit line hook-up bonding pad 988C, the second bit line hook-up bonding pad and the first bit line hook-up bonding pad being subsets of the bonding pads (988, 788) that are located at the bonding interface 800 and have an area overlap with the sense amplifier region.

[0081] The logic - side power and control signal region LPCS may be positioned adjacent to the logic - side peripheral region LPERI and the logic - side bit - line hook - up region LBLHU. The logic - side power and control signal region LPCS may abut the logic - side peripheral region LPERI and may be laterally offset from the logic - side peripheral region LPERI along a first horizontal direction hd1. The logic - side power and control signal region LPCS may abut the logic - side bit - line hook - up region LBLHU and may be laterally offset from the logic - side bit - line hook - up region LBLHU along a second horizontal direction hd2. In one embodiment, the width of the logic - side power and control signal region LPCS along the second horizontal direction hd2 may be the same as the difference between the width of the logic - side peripheral region LPERI along the second horizontal direction hd2 and the width of the logic - side bit - line hook - up region LBLHU along the second horizontal direction hd2. In other words, the sum of the width of the logic - side power and control signal region LPCS along the second horizontal direction hd2 and the width of the logic - side bit - line hook - up region LBLHU along the second horizontal direction hd2 may be the same as the width of the logic - side peripheral region LPERI along the second horizontal direction hd2.

[0082] According to one aspect of the present disclosure, the combination of the logic - side bit - line hook - up region LBLHU and the logic - side power and control signal region LPCS may be accommodated within an area defined by the extension of two longitudinal edges of the logic - side peripheral region LPERI extending laterally along the first horizontal direction hd1. Additionally, the combination of the logic - side bit - line hook - up region LBLHU and the logic - side power and control signal region LPCS may abut the logic - side peripheral region LPERI on one side and the logic - side input / output region LIO on the other side. The logic - side peripheral region LPERI may be laterally offset from the combination of the logic - side bit - line hook - up region LBLHU and the logic - side power and control signal region LPCS along the first horizontal direction hd1, and the logic - side input / output region LIO may be laterally offset from the combination of the logic - side bit - line hook - up region LBLHU and the logic - side power and control signal region LPCS along the first horizontal direction hd1.

[0083] Reference Figure 5 Referring to

[0084] Reference Figure 6, a backside insulating layer 610 can be formed on the backside of the first substrate 908. The backside insulating layer 610 includes an insulating material such as silicon oxide. The thickness of the backside insulating layer 610 can be in the range of 50 nm to 500 nm, but smaller and larger thicknesses can also be employed. A photoresist layer (not shown) can be applied over the backside insulating layer 610 and can be lithographically patterned to form an opening over the area of the through-substrate via structure 388. An etching process can be performed to form a via cavity through the backside insulating layer 610 under each opening in the photoresist layer. The top surface of the through-substrate via structure 388 can be physically exposed at the bottom of each via cavity through the backside insulating layer 610.

[0085] At least one metal material can be deposited through the backside insulating layer 610 into the opening and deposited over the flat surface of the backside insulating layer 610 to form a metal material layer. The at least one metal material can include copper, aluminum, ruthenium, cobalt, molybdenum, and / or any other metal material that can be deposited by physical vapor deposition, chemical vapor deposition, electroplating, vacuum evaporation, or other deposition methods. For example, a metal nitride liner material (such as TiN, TaN, or WN) can be directly deposited on the physically exposed surface of the through-substrate via structure 388, on the sidewalls of the opening through the backside insulating layer 610, and over the physically exposed planar surface of the backside insulating layer 610. The thickness of the metal nitride liner material can be in the range of 10 nm to 100 nm, but smaller and larger thicknesses can also be employed. At least one metal fill material, such as copper or aluminum, can be deposited on the metal nitride liner material. In one embodiment, the at least one metal fill material can include a stack of a highly conductive metal layer (such as a copper layer or an aluminum layer) and an under-bump metallization (UBM) layer stack for bonding a solder ball thereon. Exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stack, Al / Ni / Cu stack, Cu / Ni / Au stack, Cu / Ni / Pd stack, Ti / Ni / Au stack, Ti / Cu / Ni / Au stack, Ti-W / Cu stack, Cr / Cu stack, and Cr / Cu / Ni stack. The thickness of the metal material layer over the flat horizontal surface of the backside insulating layer 610 can be in the range of 0.5 micrometers to 10 micrometers, such as 1 micrometer to 5 micrometers, but smaller and larger thicknesses can also be employed.

[0086] At least one metal fill material and the metal material layer may then be patterned to form discrete backside bonding pads 650 of a respective one of the through-substrate via structures in the contact through-substrate via structure 388. The backside bonding pads 650 can be used as external bonding pads that can be used to electrically connect various nodes within the first semiconductor die 900 and the second semiconductor die 700 to external nodes, such as bonding pads on a package substrate or C4 bonding pads of another semiconductor die. For example, a solder material portion 660 can be formed on the backside bonding pads 650, and a C4 bonding process or a wire bonding process can be performed to electrically connect the backside bonding pads 650 to external electrically active nodes.

[0087] Generally, the backside bonding pads 650 can be formed on a backside surface of the first semiconductor die 900 (which can be a memory die), the backside surface being on an opposite side of a bonding interface 800 between the first semiconductor die 900 and the second semiconductor die 700. The through-substrate via structure 388 can extend vertically through the first semiconductor die 900 and can provide an electrical connection between the backside bonding pads 650 and a subset of the bonding pads (988, 788), the subset can include a first input / output bonding pad 988A and a second input / output bonding pad 788A.

[0088] Reference Figure 7A and Figure 7B , shows a spatial arrangement of a set of consecutive input / output circuits I / O, a sense amplifier region S / A, a peripheral circuit region PERI including a sense amplifier driver circuit (SADRV), and a set of power supply and control interconnect structures 780P in a power and signal connection region PCS in a portion of the bonding assembly of Figure 6 . Figure 7A Same as Figure 2B except that Figure 7AShows the position of region C shown in FIG. 7C. The volume of the second semiconductor die 700 below the area of the logic-side power and control signal region LPCS includes a set of power supply and control interconnect structures located in region PCS. This set of power supply and control interconnect structures 780P may include a subset of the second metal interconnect structures 780. This set of power supply and control interconnect structures 780P can be used to route the power supply voltage and control signals between the second semiconductor die 700 and the first semiconductor die 900 through the corresponding input / output bonding pads (988A, 788A). The power and control signal region PCS, including vertical and horizontal interconnections, can be laterally bounded by the input / output circuit region I / O, by the sense amplifier region S / A located below the logic-side bit line hook-up region LBLHU, and by the peripheral circuit region PERI located below the logic-side peripheral connection region LPERI between two sense amplifier regions S / A. A part of the conduction path from the sense amplifier drive circuit SADRV to the sense amplifier region S / A is schematically shown and labeled "SADRV to S / A signal". A part of the power connection path or signal connection path from the bonding pad 650 to the peripheral circuit region PERI is schematically shown and labeled "power / control signal".

[0089] Reference Figures 8A to 8B , in a second embodiment, the power and control signal region PCS is located in the word line switch region WLSW adjacent to the sense amplifier region SA. Since the word line switch region WLSW in the logic die 700 may have a larger area than the step (i.e., platform) region 200 in the memory die 900, a part of the word line switch region WLSW may be occupied by the power and control signal region PCS. Figures 8A to 8B Shows a set of consecutive input / output circuit regions I / O, word line decoders in the word line switch region WLSW, sense amplifier regions S / A, peripheral circuit regions PERI, and an alternative spatial arrangement of a set of power supply and control interconnect structures 780P in the power and control signal region PCS in a part of the bonding assembly in Figure 6

[0090] The volume of the second semiconductor die 700 within the area of the power and control signal region PCS that is located below the logic side power and control signal region LPCS includes a set of power supply and control interconnect structures 780P. The set of power supply and control interconnect structures 780P may include a subset of the second metal interconnect structures 780. The set of power supply and control interconnect structures 780P may be used to route a power supply voltage and control signals between the second semiconductor die 700 and the first semiconductor die 900 through corresponding input / output bonding pads (988A, 788A). The power and control signal region PCS may be laterally bounded by the input / output circuit region I / O, by the sense amplifier region S / A, by the word line switch WLSW region, and by the peripheral circuit region PERI. A portion of the conductive path from the sense amplifier unit SAU to the bit line 782 is schematically shown and is labeled "S / A to BL" in Figure 8B which is marked as "S / A to BL". A portion of the power connection path or signal connection path between the first semiconductor die 900 and the second semiconductor die 700 is schematically shown and is labeled "Power / Control Signal". A portion of the power connection path or signal connection path from the region SADRV to the region S / A is labeled SADRV to S / A signal. A contact conductive layer 46 (which may be a word line) and a layer contact via structure (e.g., a word line contact via structure) 86 located in the memory die 900 are schematically shown.

[0091] Referring collectively to all of the figures and in accordance with various embodiments of the present disclosure, the bonding assembly includes a memory die (such as the first semiconductor die 900) that includes a memory device 920 and a plurality of bit lines 982, and a logic die (such as the second semiconductor die 700) that is bonded to the memory die 900. The logic die 700 includes a control circuit 702 that is configured to control the operation of the memory device 920. As Figure 7A and Figure 8A shown, the control circuit 702 includes a peripheral circuit region PERI, a sense amplifier region S / A, and a power and control signal region PCS that is positioned adjacent to the sense amplifier region S / A and includes at least one power and control signal interconnect structure 780P that is configured to supply power or control signals to or from the peripheral circuit region PERI.

[0092] In one embodiment, the memory device 920 includes a three-dimensional memory device. The three-dimensional memory device includes: a memory array region 100 including a plurality of memory elements 54 arranged in a two-dimensional array around a vertical semiconductor channel 60, a drain region 63 located at a top portion of a corresponding semiconductor channel, and a plurality of word lines 46 extending in a second horizontal direction (e.g., word line direction) hd2. Bit lines 982 extend in a first horizontal direction (e.g., bit line direction) hd1 and are electrically connected to corresponding drain regions 63.

[0093] In Figure 4A , Figure 4B , Figure 7A and Figure 7B In the first embodiment shown, in a plan view along a direction perpendicular to the bonding interface 800 between the memory die 900 and the logic die 700, the peripheral circuit region PERI is located within an area that overlaps with the area of the memory array region 100. The sense amplifier region S / A is laterally offset from the peripheral circuit region PERI along the first horizontal direction hd1 and has a sense amplifier region width that is less than the width of the memory array region 100, as Figure 4A shown. The power and control signal region PCS is laterally offset from the peripheral circuit region PERI along the first horizontal direction hd1 and is laterally offset from the sense amplifier region S / A along the second horizontal direction, as Figure 7A shown. Figure 7B A subset (988A, 788A) of the bonding pads shown in is located at the bonding interface 800 between the memory die 900 and the logic die 700 and is configured to transfer power or control signals between the memory die 900 and the peripheral circuit region PERI through the power and control signal interconnect structure 780P. In one embodiment, the power and control signal interconnect structure 780P provides vertical and horizontal electrical connections between the subset (988A, 788A) of the bonding pads and the peripheral circuit region PERI.

[0094] In one embodiment, the width of the peripheral circuit region PERI along the second horizontal direction hd2 is the same as the sum of the width of the sense amplifier region S / A along the second horizontal direction and the width of the power and control signal region PCS along the second horizontal direction, as Figure 7A shown.

[0095] In Figure 4A and Figure 4BIn one embodiment shown, the memory array region includes L bit lines having a pitch P along a second horizontal direction hd2. The sense amplifier region S / A includes N sense amplifier assemblies SAA arranged along the second horizontal direction hd2. Each sense amplifier assembly in the sense amplifier assemblies SAA includes M sense amplifier units SAU arranged along a first horizontal direction hd1. Each sense amplifier unit in the sense amplifier units SAU is electrically connected to a corresponding one of the L bit lines 982. The width of each sense amplifier assembly SAA in the second horizontal direction hd2 is less than the product of M and P, where L, M, and N are positive integers and L = M×N. In one embodiment, the width of each sense amplifier assembly SAA in the second horizontal direction hd2 is 40% to 90% of the product of M and P.

[0096] In one embodiment, each sense amplifier unit in the sense amplifier units SAU is electrically connected to a corresponding one of the bit lines 982 in the memory die 900 through another subset (988C, 788C) of bonding pads located at a bonding interface 800 and having an area overlap with the sense amplifier region S / A.

[0097] In one embodiment, the control circuit 702 further includes an input / output circuit region I / O located along an edge of the logic die 700. A subset (988A, 788A) of bonding pads is located above the input / output circuit region I / O. The power and control signal region PCS is located between the two sense amplifier regions S / A and has a boundary that interfaces with the peripheral circuit region PERI, the two sense amplifier regions S / A, and the input / output circuit region I / O, as Figure 7A shown. In one embodiment, the power and control signal interconnect structure 780P is electrically connected to the subset (988A, 788A) of bonding pads through metal vias 780V in the input / output circuit region I / O, as Figure 7B shown.

[0098] In Figure 6 and Figure 7B In one embodiment shown, the memory die 900 further includes a backside bonding pad 650 located on a backside surface of the memory die 900 (i.e., on the backside of the substrate 908 of the memory die), the backside surface being on an opposite side of the bonding interface 800, and a through-substrate via structure 388 vertically extends through the memory die 900 and provides an electrical connection between the backside bonding pad 650 and the subset (988A, 788A) of bonding pads through a via structure 488. In Figure 7A 、 Figure 7B 、 Figure 8A and Figure 8BIn some embodiments shown, the power and control signal interconnect structure 780P further electrically connects the peripheral circuit region PERI and the sense amplifier region S / A.

[0099] In Figure 8A and Figure 8B In the second embodiment shown, the control circuit 702 further includes a word line switch region WLSW, and the power and control signal region PCS is located in the word line switch region WLSW adjacent to the sense amplifier region S / A. In Figure 8B In one embodiment shown, in a plan view along a direction perpendicular to the bonding interface 800 between the memory die and the logic die, the peripheral circuit region PERI is located within an area that overlaps the area of the memory array region 100. As Figure 8A shown, the sense amplifier region S / A is laterally offset from the peripheral circuit region PERI along a first horizontal direction hd1 and has a sense amplifier region width that is the same as the width of the memory array region 100. The power and control signal region PCS is laterally offset from the peripheral circuit region PERI and the sense amplifier region S / A along a second horizontal direction hd2 and has a length along the first horizontal direction hd1 that is the same as the sum of the lengths of the peripheral circuit region PERI and the sense amplifier region S / A along the first horizontal direction.

[0100] In Figure 8B In one embodiment shown, the memory die 900 includes an alternating stack of an insulating layer 32 and word lines 46. All the layers of the alternating stack are present within the memory array region 100. The word lines 46 have different lateral extents along the second horizontal direction hd2, and the lateral extent increases with the vertical distance from the bonding interface 800 in a stepped region 200 that is laterally offset from the memory array region 100 along the second horizontal direction hd2. At least a portion of the power and control signal region PCS has an area overlap with the stepped region 200.

[0101] In Figure 8B In one embodiment shown, the memory die 900 includes word line contact via structures 86 that include a respective one of the word lines 46 in the stepped region 200 and extend toward the bonding interface 800. The control circuit 702 further includes an input / output circuit region I / O located along the edge of the logic die 700. The power and control signal region PCS has a boundary that interfaces with the peripheral circuit region PERI, the sense amplifier region S / A, and the input / output circuit region I / O.

[0102] In Figure 6 、 Figure 7B and Figure 8BIn some embodiments shown, the memory die 900 further includes a backside bonding pad 650 on a backside surface of the memory die 900, the backside surface being on an opposite side of the bonding interface 800, and the through-substrate via structure 388 vertically extends through the memory die and provides an electrical connection between the backside bonding pad 650 and a subset of the bonding pads (988A, 788A).

[0103] In some embodiments, a method of operating a bonding assembly includes transmitting a power or control signal from the backside bonding pad 650 to the peripheral circuit region PERI through the through-substrate via structure 388 (and through the via structure 488), through the bonding pads 988A (and the bonding pad 788A), and through the power and control signal interconnect structure 780P. The method further includes transmitting a power or control signal from the peripheral circuit region PERI to the sense amplifier region S / A through the power and control signal interconnect structure 780P.

[0104] Various embodiments of the present disclosure provide conductive paths between the power supply and control signal interconnect structures in the logic die and the memory die in a manner that simultaneously minimizes the total number of metal wire levels in the bonding assemblies of the logic die and the memory die. Specifically, the power supply and control interconnect structures are positioned adjacent to the sense amplifier region S / A, and the horizontal portions of the electrical wiring for the power supply voltage and control signals can be formed on the same level as the electrical wiring for providing signals to the bit lines and word lines, without requiring a separate fourth-level metallization in the logic die for providing such signals. The power supply and control interconnect structures can be evenly distributed on the logic die, thereby avoiding a centralized power bus or control signal bus that extends across the entire logic die or memory die. In one embodiment, a total of five metal levels including a first memory-side metal level M0, a second memory-side metal level M1, a first logic-side metal level D0, a second logic-side metal level D1, and a third logic-side metal level D2 can be employed to distribute the power supply voltage and control signals on the bonding assemblies of the logic die and the memory die. Thus, various embodiments of the present disclosure can be used to provide an effective electrical wiring with a smaller number of metal levels for the bonding assemblies of the logic die and the memory die.

[0105] Although specific embodiments have been mentioned previously, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or "consisting of..." replace the words "comprising" or "including". In embodiments shown using a specific structure and / or configuration in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are hereby incorporated by reference in their entirety.

Claims

1. A bonding assembly, the bonding assembly comprising: A memory die, the memory die including a memory device and a plurality of bit lines; And A logic die, the logic die bonded to the memory die; Wherein: The logic die includes control circuitry configured to control the operation of the memory device; The control circuitry includes a peripheral circuit region, a sense amplifier region, and a power and control signal region, the power and control signal region being positioned adjacent to the sense amplifier region and including at least one power and control signal interconnect structure configured to provide power or control signals to or from the peripheral circuit region; The memory device includes a three-dimensional memory device; The three-dimensional memory device includes: a memory array region including a plurality of memory elements arranged in a two-dimensional array around a vertical semiconductor channel, a drain region located at a top portion of a corresponding semiconductor channel, and a plurality of word lines extending in a second horizontal direction; The bit lines extend in a first horizontal direction and are electrically connected to corresponding drain regions; In a plan view along a direction perpendicular to a bonding interface between the memory die and the logic die, the peripheral circuit region is located within an area that overlaps an area of the memory array region; The sense amplifier region is laterally offset from the peripheral circuit region along the first horizontal direction and has a sense amplifier region width smaller than a width of the memory array region; The power and control signal region is laterally offset from the peripheral circuit region along the first horizontal direction and is laterally offset from the sense amplifier region along the second horizontal direction; A subset of bonding pads is located at the bonding interface between the memory die and the logic die and is configured to transfer the power or control signals between the memory die and the peripheral circuit region through the power and control signal interconnect structure; and A width of the peripheral circuit region along the second horizontal direction is the same as a sum of a width of the sense amplifier region along the second horizontal direction and a width of the power and control signal region along the second horizontal direction.

2. A bonding assembly, the bonding assembly comprising: A memory die, the memory die including a memory device and a plurality of bit lines; And A logic die, the logic die bonded to the memory die; Wherein: The logic die includes control circuitry configured to control the operation of the memory device; The control circuitry includes a peripheral circuit region, a sense amplifier region, and a power and control signal region, the power and control signal region being positioned adjacent to the sense amplifier region and including at least one power and control signal interconnect structure configured to provide power or control signals to or from the peripheral circuit region; The memory device includes a three-dimensional memory device; The three-dimensional memory device includes: a memory array region including a plurality of memory elements arranged in a two-dimensional array around a vertical semiconductor channel, a drain region located at a top portion of a corresponding semiconductor channel, and a plurality of word lines extending in a second horizontal direction; The bit lines extend in a first horizontal direction and are electrically connected to corresponding drain regions; In a plan view along a direction perpendicular to a bonding interface between the memory die and the logic die, the peripheral circuit region is located within an area overlapping an area of the memory array region; The sense amplifier region is laterally offset from the peripheral circuit region in the first horizontal direction and has a sense amplifier region width smaller than a width of the memory array region; The power and control signal region is laterally offset from the peripheral circuit region in the first horizontal direction and is laterally offset from the sense amplifier region in the second horizontal direction; A subset of bonding pads is located at the bonding interface between the memory die and the logic die and is configured to transfer the power or control signal between the memory die and the peripheral circuit region through the power and control signal interconnect structure; The memory array region includes L bit lines having a pitch P in the second horizontal direction; The sense amplifier region includes N sense amplifier components arranged in the second horizontal direction; Each sense amplifier component in the sense amplifier components includes M sense amplifier units arranged in the first horizontal direction; Each sense amplifier unit in the sense amplifier units is electrically connected to a corresponding one of the L bit lines; Each sense amplifier component has a width in the second horizontal direction smaller than a product of M and P; and L, M, and N are positive integers, where L = M×N.

3. The bonding component according to claim 2, wherein the width of each sense amplifier component in the second horizontal direction is 40% to 90% of the product of M and P.

4. A bonding component, the bonding component including: A memory die, the memory die including a memory device and a plurality of bit lines; And A logic die, the logic die being bonded to the memory die; Wherein: The logic die includes a control circuit configured to control operations of the memory device; The control circuit includes a peripheral circuit region, a sense amplifier region, and a power and control signal region, the power and control signal region being positioned adjacent to the sense amplifier region and including at least one power and control signal interconnect structure configured to supply power or control signals to or from the peripheral circuit region; The memory device includes a three-dimensional memory device; The three-dimensional memory device includes: a memory array region including a plurality of memory elements arranged in a two-dimensional array around a vertical semiconductor channel, a drain region located at a top portion of a corresponding semiconductor channel, and a plurality of word lines extending in a second horizontal direction; The bit lines extend in a first horizontal direction and are electrically connected to corresponding drain regions; In a plan view along a direction perpendicular to the bonding interface between the memory die and the logic die, the peripheral circuit region is located within an area that overlaps with the area of the memory array region; The sense amplifier region is laterally offset from the peripheral circuit region along the first horizontal direction and has a sense amplifier region width that is less than the width of the memory array region; The power and control signal region is laterally offset from the peripheral circuit region along the first horizontal direction and is laterally offset from the sense amplifier region along the second horizontal direction; A subset of the bonding pads is located at the bonding interface between the memory die and the logic die and is configured to transmit the power or control signal between the memory die and the peripheral circuit region through the power and control signal interconnection structure; The control circuit further includes an input / output circuit region located along the edge of the logic die; The subset of the bonding pads is located above the input / output circuit region; and The power and control signal region is located between two sense amplifier regions and has a boundary that abuts the peripheral circuit region, the two sense amplifier regions, and the input / output circuit region.

5. The bonding assembly according to claim 4, wherein the power and control signal interconnection structure is electrically connected to the subset of the bonding pads through metal vias in the input / output circuit region.

6. The bonding assembly according to claim 5, wherein the memory die further includes: A backside bonding pad located on the backside surface of the memory die, the backside surface being on the opposite side of the bonding interface; and A through-substrate via structure that vertically extends through the memory die and provides an electrical connection between the backside bonding pad and the subset of the bonding pads.

7. A bonding assembly, the bonding assembly comprising: A memory die including memory devices and a plurality of bit lines; and A logic die bonded to the memory die; Wherein: The logic die includes a control circuit configured to control the operation of the memory devices; The control circuit includes a peripheral circuit region, a sense amplifier region, and a power and control signal region, the power and control signal region being positioned adjacent to the sense amplifier region and including at least one power and control signal interconnection structure configured to supply or receive power or control signals to or from the peripheral circuit region; The memory devices include three-dimensional memory devices; The three-dimensional memory devices include: a memory array region including a two-dimensional array arrangement of a plurality of memory elements surrounding a vertical semiconductor channel, a drain region located at the top portion of the corresponding semiconductor channel, and a plurality of word lines extending in a second horizontal direction; The bit lines extend in a first horizontal direction and are electrically connected to the corresponding drain regions; The control circuit further includes a word line switch region; The power and control signal region is located in the word line switch region adjacent to the sense amplifier region; In a plan view in a direction perpendicular to the bonding interface between the memory die and the logic die, the peripheral circuit region is located within an area that overlaps the area of the memory array region; The sense amplifier region is laterally offset from the peripheral circuit region in the first horizontal direction and has a sense amplifier region width that is the same as the width of the memory array region; and The power and control signal region is laterally offset from the peripheral circuit region and the sense amplifier region in the second horizontal direction and has a length in the first horizontal direction that is the same as the sum of the lengths of the peripheral circuit region and the sense amplifier region in the first horizontal direction.

8. The bonding assembly according to claim 7, wherein: The memory die includes an alternating stack of insulating layers and word lines; All layers of the alternating stack are present within the memory array region; The word lines have different lateral extents in the second horizontal direction, the lateral extent increasing with the vertical distance from the bonding interface in a stepped region that is laterally offset from the memory array region in the second horizontal direction; and At least a portion of the power and control signal region has an area overlap with the stepped region.

9. The bonding assembly according to claim 8, wherein: The memory die includes a word line contact via structure that contacts a respective one of the word lines in the stepped region and extends towards the bonding interface; The control circuit includes an input / output circuit region located along the edge of the logic die; And The power and control signal region has a boundary that abuts the peripheral circuit region, the sense amplifier region, and the input / output circuit region.

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