Resistive random access memory integrated with vertical transport field effect transistors

Abstract

A semiconductor structure (100) can include two vertical transport field effect transistors including a top source drain (124), a bottom source drain (106), and an epitaxial channel (120), and a resistive random access memory between the two vertical transport field effect transistors, which can include an oxide layer (144), a top electrode (146), and a bottom electrode, wherein the oxide layer (144) can contact the top source drain of the two vertical field effect transistors. The top source drain (124) can be used as the bottom electrode of the resistive random access memory. The semiconductor structure (100) can include a shallow trench isolation (136) between the two vertical transport field effect transistors, which can be embedded in a first spacer (108), a doped source (106), and a portion of a substrate (102).

Description

Technical Field

[0001] The present invention generally relates to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a semiconductor structure including a resistive random access memory (ReRAM) integrated with a vertical transfer field effect transistor (VTFET). Background Art

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be either volatile or nonvolatile. Nonvolatile memory retains its stored data in the absence of power, while volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is a promising candidate for the next generation of nonvolatile memory due to its simple structure and compatibility with complementary metal oxide semiconductor (CMOS) logic manufacturing processes. Some applications of ReRAM can include high-speed searches in computer networks, such as for routing MAC addresses.

[0003] Resistive random access memory (RRAM) works by changing the resistance of a dielectric solid-state material. A typical ReRAM consists of a bottom electrode, a top electrode, and an oxide layer between the two electrodes. However, there are problems in providing suitable ReRAM. ReRAM is a promising technology for high-speed content-addressable memory. For example, oxide ReRAM requires electroforming of conductive filaments. This process relies on randomness, so the position of the filaments in existing oxide ReRAM cannot be well controlled. This leads to high forming voltages and increased device variability as the ReRAM cell is scaled down.

[0004] Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0005] From a first aspect, the present invention provides a semiconductor structure comprising: two vertical transfer field effect transistors, each of which includes a top source and drain, a bottom source and drain, and an epitaxial channel; and a resistive random access memory between the two vertical transfer field effect transistors, each of which includes an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two vertical field effect transistors.

[0006] From another aspect, the present invention provides a semiconductor structure comprising: two or more vertical transfer field effect transistors, each vertical transfer field effect transistor including a top source and drain, a bottom source and drain, and an epitaxial channel; and a resistive random access memory between the two or more vertical transfer field effect transistors, the resistive random access memory including an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two or more vertical field effect transistors.

[0007] From another perspective, the present invention provides a method for forming a semiconductor structure, the method comprising: forming two vertical transfer field effect transistors, the vertical transfer field effect transistors comprising a top source and drain, a bottom source and drain, and an epitaxial channel; and forming a resistive random access memory between the two vertical transfer field effect transistors, the resistive random access memory comprising an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two vertical field effect transistors.

[0008] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include: two vertical transfer field-effect transistors, each including a top source and drain, a bottom source and drain, and an epitaxial channel; and a resistance random access memory (RRAM) between the two vertical transfer field-effect transistors. The RRAM may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source and drain of the two vertical field-effect transistors. The top source and drain may serve as the bottom electrode of the RRAM. The semiconductor structure may include shallow trench isolation (STI) between the two vertical transfer field-effect transistors. The STI may be embedded in a first spacer, a doped source, and a portion of a substrate. The two vertical transfer field-effect transistors may include a metal gate material surrounding the epitaxial channel and STI between the two vertical transfer field-effect transistors. The STI may be embedded in a first spacer, a doped source, and a portion of the substrate, wherein the doped source may be disposed on the substrate. The doped source may include a doped region on a substrate, the doped region including a first dopant, and an anti-doped layer including a second dopant different from the first dopant may be disposed between the doped region and the substrate. The semiconductor structure may include a metal fill between the two vertical transfer field-effect transistors, the metal fill may be disposed on the top electrode. The semiconductor structure may also include a source contact in contact with the doped source, a gate contact in contact with the metal gate material, and an oxide resistive random access memory contact structure in contact with a top portion of the metal fill.

[0009] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include: two or more vertical transfer field-effect transistors, each comprising a top source and drain, a bottom source and drain, and an epitaxial channel; and a resistance random access memory (RRAM) between the two or more vertical transfer field-effect transistors, the RRAM comprising an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two vertical field-effect transistors. The top source and drain may serve as the bottom electrode of the oxide RRAM. The structure may include two or more shallow trench isolations (STIs) between the two or more vertical transfer field-effect transistors, the two or more STIs may be embedded in a first spacer, a doped source, and a portion of a substrate. The two or more vertical transfer field-effect transistors may include a metal gate material surrounding the epitaxial channel and two or more STIs between the two vertical transfer field-effect transistors. The two or more STIs may be embedded in a first spacer, a doped source, and a portion of the substrate, wherein the doped source may be disposed on the substrate. The doped source may include a doped region on a substrate, the doped region including a first dopant, and an anti-doped layer including a second dopant different from the first dopant may be disposed between the doped region and the substrate. The semiconductor structure may include a metal filler between two or more vertical transfer field effect transistors. The metal filler may be disposed on a top electrode. The semiconductor structure may include two or more source contact structures in contact with the doped source, two or more gate contact structures in contact with a metal gate material, and two or more oxide resistive random access memory contact structures in contact with a top portion of the metal filler.

[0010] According to another embodiment of the present invention, a method is provided. The method may include forming two vertical transfer field-effect transistors, the vertical transfer field-effect transistors including a top source and drain, a bottom source and drain, and an epitaxial channel; and forming a resistive random access memory (RRAM) between the two vertical transfer field-effect transistors. The RRAM may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source and drain of the two vertical field-effect transistors. The top source and drain may serve as the bottom electrode of the oxide RRAM. The method may include forming a shallow trench isolation (STI) between the two vertical transfer field-effect transistors. The STI may extend from a top surface of a first spacer through a doped source and a portion of a substrate. The method may include forming a metal gate material surrounding the epitaxial channel, and forming a STI between the two vertical transfer field-effect transistors. The STI may be embedded in the first spacer, the doped source, and a portion of the substrate, wherein the doped source may be disposed on the substrate. The doped source may include a doped region on a substrate, the doped region including a first dopant, and an anti-doped layer including a second dopant different from the first dopant disposed between the doped region and the substrate. The method may include depositing a metal filler between the two vertical transfer field-effect transistors, the metal filler being disposed on the top electrode. The method may also include forming two source contact structures in contact with the doped source, forming two gate contact structures in contact with the metal gate material, and forming an oxide resistive random access memory contact structure in contact with a top portion of the metal filler. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following detailed description, which is given by way of example and is not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a dummy gate and a dielectric capping layer disposed on a substrate according to an exemplary embodiment;

[0013] Figure 2 is a cross-sectional view illustrating a trench formed to expose a doped source according to an exemplary embodiment;

[0014] Figure 3 is a cross-sectional view illustrating an epitaxial layer and a dielectric material according to an exemplary embodiment;

[0015] Figure 4 is a cross-sectional view illustrating forming a top source and drain on an epitaxial channel according to an exemplary embodiment;

[0016] Figure 5is a cross-sectional view illustrating deposition of spacers on top source and drain electrodes according to an exemplary embodiment;

[0017] Figure 6 is a cross-sectional view illustrating removal of a dummy gate according to an exemplary embodiment;

[0018] Figure 7 is a cross-sectional view illustrating deposition of gate dielectric material and work function metal according to an exemplary embodiment;

[0019] Figure 8 is a cross-sectional view illustrating depositing an interlayer dielectric according to an exemplary embodiment;

[0020] Figure 9 is a cross-sectional view illustrating a deposition mask to cover a portion of a third spacer according to an exemplary embodiment;

[0021] Figure 10 is a cross-sectional view illustrating recessing a portion of an interlayer dielectric according to an exemplary embodiment;

[0022] Figure 11 is a cross-sectional view showing a portion where a third spacer is removed according to an exemplary embodiment;

[0023] Figure 12 is a cross-sectional view illustrating a deposition switching layer according to an exemplary embodiment;

[0024] Figure 13 is a cross-sectional view illustrating a deposited electrode layer according to an exemplary embodiment;

[0025] Figure 14 is a cross-sectional view illustrating a deposited metal filler according to an exemplary embodiment; and

[0026] Figure 15 is a cross-sectional view illustrating forming a contact according to an exemplary embodiment.

[0027] The accompanying drawings are not necessarily to scale. The accompanying drawings are merely schematic representations and are not intended to depict specific parameters of the invention. The accompanying drawings are intended to depict only typical embodiments of the invention. In the accompanying drawings, the same reference numerals represent the same elements. DETAILED DESCRIPTION

[0028] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it will be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0029] For purposes of the description below, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. The terms "overlying," "on top of," "on top of," "located on," or "located on top of" indicate that a first element, e.g., a first structure, is present on a second element, e.g., a second structure, wherein an intermediate element, e.g., an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element (e.g., a first structure) and a second element (e.g., a second structure) are connected without any intervening conductive, insulating, or semiconducting layer at the interface of the two elements.

[0030] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and for illustrative purposes, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0031] Embodiments of the present invention generally relate to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a semiconductor structure including a resistive random access memory (ReRAM) integrated with a vertical transfer field effect transistor (VTFET).

[0032] ReRAM is a type of random-access computer memory that works by changing the resistance of a dielectric solid-state material. ReRAM is a promising technology for high-speed content-addressable memory.

[0033] Typically, ReRAM can include a bottom electrode, a top electrode, and an oxide layer between the two electrodes. In oxide ReRAM, the conductive filaments need to be electroformed. This process relies on randomness, so the position of the filaments in existing oxide ReRAM cannot be well controlled. This leads to high formation voltages and increased device variability as the ReRAM cell is scaled down. Therefore, there is a need to form a ReRAM cell that can be scaled.

[0034] Embodiments of the present invention propose a two-transistor, two-resistor (2T2R) ReRAM structure. More specifically, embodiments of the present invention propose an oxide ReRAM co-integrated with two vertical transistors, using portions of the top source / drain regions of the two vertical transistors as the bottom electrode of the ReRAM structure. Embodiments of the present invention propose forming the oxide ReRAM in the faceted epitaxial drain regions of the vertical transistors. The faceted epitaxial drain regions are redefined as pointed cones, thereby enhancing the electric field at the tips of the cones.

[0035] Figure 1-15 An exemplary structure of a 2T2R ReRAM structure and a method of manufacturing the 2T2R ReRAM structure according to one embodiment are shown.

[0036] Now refer to Figure 1 , shows a structure 100 according to an embodiment. The structure 100 may include a substrate 102, an anti-doped layer 104, a doped source 106, a first spacer 108, a dummy gate 110, a second spacer 112, and a dielectric capping layer 114. The substrate 102 may include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials may include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon germanium carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. In one embodiment, the substrate 102 may include germanium.

[0037] An anti-doped layer 104 is deposited on the top surface of the substrate 102. A doped source 106 is then disposed on the substrate 102 above the anti-doped layer 104. The doped source 106 and the anti-doped layer 104 may be formed on the substrate 102 by incorporating dopants into the substrate 102 or forming an epitaxial growth on the substrate 102. The doped source 106 is heavily doped with a dopant, which may be a p-type dopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0038] The anti-doped layer 104 includes a dopant that is different from / opposite to the dopant in the doped source 106. For example, when the doped source 106 includes a p-type dopant, the anti-doped layer 104 includes an n-type dopant, and when the doped source 106 includes an n-type dopant, the anti-doped layer 104 includes a p-type dopant. The doped source 106 is heavily doped, including from about 1019 to about 1022 atoms / cm 3 The dopant concentration in the range of 100 nm to 200 nm can be selected from the group consisting of: 100 nm to 200 nm. The thickness of the anti-doping layer 104 can be in the range of about 5 to about 50 nm, or about 10 to about 20 nm. The thickness of the doped source 106 can be in the range of about 50 to about 250 nm, or about 100 to about 200 nm. The anti-doping layer 104 acts as an insulator, insulating the doped source 106 from the substrate 102 so that current is not dissipated into the substrate 102.

[0039] The dummy gate 110 is disposed between the first spacer 108 and the second spacer 112 on the doped source 106. The first spacer 108 is deposited on the doped source 106, the dummy gate 110 is deposited on the first spacer 108, and the second spacer 112 is deposited on the dummy gate 110.

[0040] The first spacer 108 and the second spacer 112 may include an insulating material, such as silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the first spacer 108 and the second spacer 112 may include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The first spacer 108 and the second spacer 112 materials are deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 108 and the second spacer 112 may each have a thickness of about 3 to about 15 nm or about 5 to about 10 nm.

[0041] The dummy gate 110 may include a sacrificial gate material, such as amorphous silicon (aSi) or polysilicon. The sacrificial material may be deposited by a deposition process, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material forming the dummy gate 110 may have a thickness of about 8 nm to about 100 nm, or about 10 nm to about 30 nm.

[0042] A dielectric capping layer 114 is deposited on the second spacer 112 above the dummy gate 110. The dielectric capping layer 114 may also be referred to as an oxide layer. Non-limiting examples of materials for the dielectric capping layer 114 may include silicon dioxide, tetraethyl orthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, an oxide formed by an atomic layer deposition (ALD) process (e.g., silicon oxide), or any combination thereof. The dielectric capping layer 114 may have a thickness ranging from about 30 nm to about 200 nm, or from about 50 nm to about 100 nm.

[0043] Now refer to Figure 2 , shows a structure 100 having two trenches 116 according to an embodiment. Each trench 116 undergoes a fabrication process as described below to form a vertical transistor. The trenches 116 extend from the top surface of the dielectric cap layer 114 to the doped source 106, thereby exposing the top surface of the doped source 106. The trenches 116 are formed by performing an etching process that is selective to (does not substantially remove) the doped source 106 material. The etching process can be, for example, reactive ion etching.

[0044] Multiple etching processes may be performed to form trenches 116 within structure 100. For example, a first etching process may be performed to selectively remove a portion of dielectric capping layer 114 relative to the material of second spacers 112. A second etching process may then be performed to selectively remove a portion of second spacers 112 relative to the material of dummy gate 110, underlying the portion of trench 116 formed by the first etching process. A third etching process may then be performed to selectively remove a portion of dummy gate 110 relative to the material of first spacers 108, underlying the portion of trench 116 formed by the second etching process. A fourth etching process may then be performed to remove a portion of first spacers 108, thereby exposing the top surface of doped source 106. The resulting trenches 116 may extend through the top surface of dielectric capping layer 114 and down to the top surface of the exposed portion of doped source 106. The width of trenches 116 may be approximately 3 nm to approximately 20 nm, or approximately 5 nm to approximately 10 nm. The depth of the trench 116 may be from about 50 nm to about 300 nm, or from about 100 nm to about 200 nm.

[0045] Once the trench 116 is formed, portions of the sidewalls of the dummy gate 110 are oxidized. This oxidation allows a thin oxide layer 118 to form along the sidewalls of the trench 116. The oxidation can be performed by a plasma oxidation process or other oxidation process that forms the thin oxide layer 118. Portions of the first spacer 108 or the doped source 106 may also be oxidized. However, in performing the oxidation process described herein, reference is made to Figure 3-15 Any oxide formed in these areas may be removed prior to the additional steps described.

[0046] Now refer to Figure 3 , shows a structure 100 having an epitaxial channel 120 and a dielectric material 122 according to an embodiment. Once portions of the dummy gate 110 sidewalls are oxidized, an epitaxial layer is grown on the top surface of the doped source 106 to form the epitaxial channel 120. The epitaxial growth may include epitaxial semiconductor material, and the epitaxial growth and / or deposition process may be selective for formation on the semiconductor surface and not deposit material, such as oxide 118, first spacer 108, or second spacer 112, on other surfaces.

[0047] The epitaxial channel 120 can be grown using a suitable growth process, such as chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD), or other suitable processes.

[0048] The source of the epitaxial channel material can be, for example, silicon, germanium, or a combination thereof. The gas source used to deposit the epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germanium, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources can be used to form an epitaxial silicon-germanium alloy layer. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0049] During the growth process, the epitaxial growth in the epitaxial channel 120 may extend above the dielectric cap layer 114 (not shown). A planarization process, such as a chemical mechanical polishing (CMP) process, may be used to remove excess epitaxial growth on the dielectric cap layer 114. Additionally, the epitaxial channel 120 may be partially recessed and then backfilled with dielectric material 122. The epitaxial channel 120 may be partially recessed to a level still within the dielectric cap layer 114 but above the second spacer 112. The epitaxial channel 120 may be recessed by etching, such as by a reactive ion etching or wet etching process.

[0050] The opening formed above the recessed epitaxial channel 120 is filled with a dielectric material. Dielectric material 122 can be a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. Dielectric material 122 is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). After deposition, dielectric material 122 is planarized by, for example, CMP. Dielectric material 122 forms a dielectric cap above epitaxial channel 120.

[0051] Now refer to Figure 4, shows the structure 100 with top source and drain electrodes 124 according to an embodiment. Substantially all of the dielectric cap layer 114 is removed, exposing the top surface of the second spacer 112. The dielectric cap layer 114 can be etched using a process that is selective to (does not substantially remove) the second spacer 112. Once the dielectric cap layer 114 is removed, top source and drain electrodes 124 are epitaxially grown from the exposed sidewalls of the epitaxial channel 120. The top source and drain electrodes 124 of the source / drain are disposed between the dielectric material 122 and the epitaxial channel 120. The top source and drain electrodes 124 are also disposed between the dielectric material 122 and the dummy gate 110. Prior to forming the top source and drain electrodes 124, a portion of the epitaxial channel 120 above the second spacer 112 can be recessed along the sidewalls. The top source and drain electrodes 124 are the faceted epitaxial source and drain regions of the vertical transistor. The faceted top source and drain electrodes 124 are grown in a pointed cone shape, wherein the tip of the top source and drain electrodes 124 extends horizontally away from the epitaxial channel 120. The pointed cone shape of the top source and drain electrodes 124 enhances the electric field at the tip of the cone.

[0052] Now refer to Figure 5 , shows a structure 100 with a third spacer 126 according to an embodiment. The third spacer 126 is deposited on the top source and drain 124. The third spacer 126 protects the top source and drain 124. The third spacer 126 is also disposed on the sidewalls of the dielectric material 122. The third spacer 126 may include an insulating material, such as a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The third spacer 126 material is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The spacer material can be etched by a dry etching process, such as an RIE process, so that it covers the top source and drain 124 and is removed from the surface of the dielectric material 122 and the second spacer 112.

[0053] Once the third spacer 126 is deposited, portions of the second spacer 112 and the dummy gate 110 are removed. The second spacer 112 and the dummy gate 110 are recessed to remove portions that extend horizontally beyond the material of the third spacer 126. An etching process is performed that is selective to (substantially does not remove) the first spacer 108. The etching process can be a dry etching process, such as an RIE process.

[0054] Now refer to Figure 6 , shows structure 100 with the remaining dummy gate 110 removed according to an embodiment. Removal of the remaining dummy gate 110 below the third spacer 126 exposes oxide 118. The dummy gate 110 may be removed by a wet etching process, such as a process including hot ammonia.

[0055] Referring now to Figure 7 A structure 100 with gate dielectric material 128 and work function metal 130 is shown, in accordance with an embodiment. Prior to deposition of gate dielectric material 128, the remaining portion of oxide 118 is removed such that sidewalls of epitaxial channel 120 are exposed. Gate dielectric material 128 is then deposited conformally along the top surface of structure 100. Work function metal 130 is then deposited conformally on top portions of gate dielectric material 128. Gate dielectric material 128 and work function metal 130 form part of a gate stack that replaces dummy gate 110. Gate dielectric material 128 and work function metal 130 are disposed on first spacers 108, epitaxial channel 120, third spacers 126, and the remaining portion of second spacers 112 below top source / drain 124.

[0056] Gate dielectric material 128 can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for gate dielectric material 128 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum and aluminum.

[0057] Gate dielectric material 128 separates epitaxial channel 120 from work function metal 130, thereby reducing leakage current effects while increasing the capacitance of work function metal 130. The gate dielectric material 128 layer can be formed by a suitable deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of gate dielectric material 128 can vary depending on the deposition process and the composition and amount of high-k dielectric material used.

[0058] The work function metal 130 may be disposed above the gate dielectric material 128. The type of work function metal 130 depends on the type of transistor. Non-limiting examples of suitable work function metals 130 include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal 130 may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering.

[0059] Now refer to Figure 8 , shows a structure 100 having a metal gate material 132, shallow trench isolation (STI) 136, and an interlayer dielectric (ILD) 138 according to an embodiment. The structure 100 is first filled with the metal gate material 132 so that the top portion of the metal gate material 132 is substantially flush with the top portion of the dielectric material 122 and the third spacer 126. The metal gate material 132 is deposited over the gate dielectric material 128 and the work function metal 130. The metal gate material 132, the work function metal 130, and the gate dielectric material 128 may be collectively referred to as a gate stack. Non-limiting examples of the metal gate material 132 may include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, and sputtering.

[0060] The metal gate material 132 is then partially recessed by an etching process (e.g., a reactive ion etching process) to expose portions of the gate dielectric material 128 and the work function metal 130. Thereafter, an anisotropic etch, such as an RIE process, may be performed to recess the gate dielectric material 128 and the work function metal 130 down to the level of the metal gate material 132. In addition, a mask may be provided on the metal gate material 132 and subsequently patterned. The pattern is transferred to the metal gate material 132 to remove a portion of the metal gate material 132 and define the gate 134. In addition, the gate dielectric material 128 and the work function metal 130 are also etched during this step. A combination of RIE processes may be performed. A portion of the first spacer 108 is arranged between the gate stack of the gate 134 and the doped source 106.

[0061] Forming shallow trench isolation (STI) 136 can be accomplished in a variety of ways. In one embodiment, a single etching process or multiple etching processes can also be performed to remove the first spacer 108, the doped source 106, the anti-doped layer 104, and a portion of the substrate 102 between the two gates 134. The resulting trench (not shown) can extend from the top surface of the first spacer 108 through a portion of the substrate 102. The trench is then filled with a dielectric material that forms STI 136. STI 136 is a form of dielectric plug that separates the two transistors so that current applied to one transistor has no effect on the second transistor. Typically, STI 136 extends through a portion of the substrate 102 to a depth that allows the two transistors to be electrically separated.

[0062] In alternative embodiments, the STI 136 may be formed before the work function metal 130 and the metal gate material 132 are deposited. For example, the STI 136 may be formed before the oxide 118 is removed, as described with reference to FIG. Figure 7 In another example, the STI 136 may be formed before the remaining portion of the dummy gate 110 is removed, as described in reference to FIG. Figure 5 In both cases, a trench is etched between the two transistor structures and then filled with a dielectric material that forms the STI 136 before the work function metal 130 and metal gate material 132 are deposited.

[0063] Continue to refer Figure 8 , an interlayer dielectric (ILD) 138 may be deposited such that the top surface of the ILD 138 is substantially flush with the top surfaces of the dielectric material 122 and the third spacer 126. The ILD 138 may be formed of, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 138 is deposited by a deposition process, including but not limited to CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or the like. The resulting structure 100 includes two vertical transistors separated by the STI 136. Each vertical transistor includes a gate 134.

[0064] Now refer to Figure 9, shows structure 100 with mask 140 according to an embodiment. After depositing ILD 138, excess ILD 138 can be removed from the top surface of structure 100 using a planarization process, such as a CMP process. Mask 140 is then deposited on the top surface of structure 100, covering only a portion of third spacer 126 and a portion of dielectric material 122 of each vertical transistor. The ILD 138 between the two vertical transistors is not covered by mask 140. Instead, the ILD 138 between the two vertical transistors is exposed. Mask 140 can be made of a material that is resistant to etching processes, thereby protecting the portion of structure 100 covered by mask 140. Mask 140 is deposited to protect the covered surface when structure 100 is further processed to form a ReRAM structure.

[0065] Now refer to Figure 10 , shows a structure 100 having a recessed portion of the ILD 138 according to an embodiment. The exposed portion of the ILD 138 located between the two vertical transistors is removed by performing an etching process that is selective to (will not substantially remove) the third spacer 126 and the dielectric material 122. The etching process can be, for example, a reactive ion etch. Once the ILD 138 is recessed, an opening 142 is formed between the two transistors. The opening 142 is formed so that it can be subsequently backfilled with other materials, as described herein with reference to FIG. Figure 12-14 described.

[0066] Now refer to Figure 11 , shows structure 100 with a recessed portion of third spacer 126 in accordance with an embodiment. Once ILD 138 between the two transistors is recessed, another etching process can be used to remove portions of third spacer 126 not protected by mask 140. For example, third spacer 126 is removed without further recessing ILD 138. Removing portions of third spacer 126 exposes portions of top source / drain 124 and portions of dielectric material 122. Furthermore, the second etching process enlarges opening 142.

[0067] Now refer to Figure 12 , shows structure 100 with a second oxide layer 144 according to an embodiment. Once portions of third spacers 126 are removed, thereby exposing portions of top source and drain electrodes 124, mask 140 is removed. Furthermore, second oxide layer 144 is conformally deposited in opening 142 along the exposed sidewalls of dielectric material 122 and top source and drain electrodes 124, as well as the top surfaces of second spacers 112 and ILD 138.

[0068] The second oxide layer 144 can be conformally deposited using known deposition techniques, such as atomic layer deposition. The second oxide layer 144 can be made of a metal oxide material or a high-k material. Non-limiting examples of suitable materials for the second oxide layer 144 include titanium oxide, tantalum oxide, and hafnium oxide. The second oxide layer 144 serves as a dielectric layer in the ReRAM structure, separating the top source and drain 124 from the electrodes.

[0069] Now refer to Figure 13 , shows the structure 100 with the electrode 146 according to an embodiment. The electrode 146 may also be referred to as the top electrode in the ReRAM structure. The electrode 146 is conformally deposited on top of the second oxide layer 144. The electrode 146 may be deposited using known deposition techniques, such as atomic layer deposition. The electrode 146 may be made of materials such as titanium nitride and aluminum-doped titanium nitride. The electrode 146 serves as the top electrode in the ReRAM structure, while the top source and drain 124 has two functions. The top source and drain 124 is the top source / drain of the vertical transistor, while the doped source 106 serves as the bottom source / drain of the vertical transistor. The top source and drain 124 is also the bottom electrode in the ReRAM structure.

[0070] Now refer to Figure 14 , shows structure 100 with metal fill 148 according to an embodiment. Once electrode 146 is conformally deposited onto the sidewalls and bottom of opening 142, opening 142 is filled with metal fill 148, after which structure 100 undergoes a CMP process. Metal fill 148 can be made of a suitable low-resistivity metal, such as tungsten or copper. Metal fill 148 serves as an electrical conductor between electrode 146 and a contact formed on the top surface of metal fill 148.

[0071] Now refer to Figure 15, shows structure 100 having a source contact 150 and a gate contact 152 according to an embodiment. Source contact 150 extends through ILD 138 and first spacer 108 to reach doped source 106 and is formed within a trench. To remove ILD 138 and form the source trench, a resist, such as a photoresist, may be deposited and patterned. An etching process, such as RIE, may be performed using the patterned resist as an etch mask to remove ILD 138 and first spacer 108 until doped source 106 is exposed. The source trench is filled with a conductive material or a combination of conductive materials to form source contact 150. The conductive fill material may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of ILD 138 .

[0072] Gate contact 152 extends from the surface of ILD 138 to metal gate material 132. Gate contact 152 is formed by patterning a trench in ILD 138. To remove ILD 138 and form the gate contact trench, a resist, such as a photoresist, may be deposited and patterned. An etching process, such as RIE, may be performed using the patterned resist as an etch mask to remove ILD 138 until metal gate material 132 is exposed. The gate contact trench is filled with a conductive material or a combination of conductive materials to form gate contact 152. The conductive material may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the surface of ILD 138.

[0073] In addition to the source contact 150 and the gate contact 152, a ReRAM contact (not shown) may be subsequently formed over and in direct contact with the ReRAM metal fill 148. The ReRAM contact may be made of a conductive metal such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof.

[0074] like Figure 15As shown, the resulting structure 100 includes two vertical transfer field effect transistors (VTFETs) separated by STI 136 and a ReRAM structure located between the two VTFETs. The ReRAM structure includes a portion of the top source and drain 124 in direct contact with the second oxide layer 144, the second oxide layer 144, and an electrode 146. The ReRAM structure has a tip region defined by the pointed cone of the top source and drain 124, a second oxide layer 144 conformally deposited on the tip region of the top source and drain 124, and an electrode 146. The tip region of the ReRAM enhances the electroforming of the conductive filament of the ReRAM. Therefore, the randomness of the electroforming of the conductive filament is reduced in the ReRAM structure of the present invention. In addition, integrating the VTFET with the ReRAM structure saves space, allowing more VTFETs to be manufactured in the same occupied area.

[0075] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: two vertical transfer field effect transistors, each comprising a top source and drain, a bottom source and drain, and an epitaxial channel; as well as A resistance random access memory is physically disposed between the two vertical pass field effect transistors, the resistance random access memory comprising an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two vertical field effect transistors.

2. The semiconductor structure according to claim 1, wherein The top source and drain serve as the bottom electrode of the resistance random access memory.

3. The semiconductor structure of any preceding claim, further comprising: A shallow trench isolation is formed between the two vertical pass field effect transistors, wherein the shallow trench isolation is embedded in the first spacer, the doped source, and a portion of the substrate.

4. The semiconductor structure according to claim 1 or 2, wherein: The two vertical transfer field effect transistors further include: a metal gate material surrounding the epitaxial channel; and a shallow trench isolation between the two vertical transfer field effect transistors, the shallow trench isolation being embedded in a first spacer, a doped source, and a portion of a substrate, wherein the doped source is disposed on the substrate, the doped source includes a doped region on the substrate, the doped region includes a first dopant, and an anti-doped layer including a second dopant different from the first dopant is disposed between the doped region and the substrate.

5. The semiconductor structure according to claim 1 or 2, further comprising: A metal filling is provided between the two vertical transfer field effect transistors, the metal filling being disposed on the top electrode.

6. The semiconductor structure according to claim 1 or 2, wherein: The oxide layer separates the top electrode from the bottom electrode.

7. The semiconductor structure according to claim 4, further comprising: a source contact in contact with the doped source; a gate contact in contact with the metal gate material; as well as An oxide RRAM contact structure in contact with a top portion of the metal fill.

8. The semiconductor structure according to any one of the preceding claims 1 to 2 and 7, wherein: The two vertical transfer field effect transistors include two or more vertical transfer field effect transistors, and the vertical transfer field effect transistors include the top source and drain, the bottom source and drain, and the epitaxial channel; and The oxide layer contacts the top source and drain of two or more vertical field effect transistors.

9. The semiconductor structure according to claim 8, further comprising: Two or more shallow trench isolations are formed between the two or more vertical pass field effect transistors, the shallow trench isolations being embedded in the first spacer, the doped source, and a portion of the substrate.

10. The semiconductor structure according to claim 8, wherein The two or more vertical transfer field effect transistors further include: a metal gate material surrounding the epitaxial channel; and Two or more shallow trench isolations between the two vertical transfer field effect transistors, the two or more shallow trench isolations being embedded in a first spacer, a doped source, and a portion of a substrate, wherein the doped source is disposed on the substrate, the doped source includes a doped region on the substrate, the doped region includes a first dopant, and an anti-doped layer including a second dopant different from the first dopant is disposed between the doped region and the substrate.

11. The semiconductor structure according to claim 8, further comprising: A metal fill between the two or more vertical transfer field effect transistors is disposed on the top electrode.

12. The semiconductor structure according to claim 8, wherein The oxide layer separates the top electrode from the bottom electrode.

13. The semiconductor structure according to any one of claims 10 to 12, further comprising: two or more source contact structures contacting the doped source; two or more gate contact structures in contact with the metal gate material; as well as Two or more oxide RRAM contact structures are in contact with a top portion of the metal fill.

14. A method of forming a semiconductor structure, the method comprising: forming two vertical transfer field effect transistors, the vertical transfer field effect transistors including a top source and drain, a bottom source and drain, and an epitaxial channel; as well as A resistance random access memory is formed between the two vertical transfer field effect transistors. The resistance random access memory is physically arranged between the two vertical transfer field effect transistors. The resistance random access memory includes an oxide layer, a top electrode and a bottom electrode, wherein the oxide layer contacts the top source and drain of the two vertical field effect transistors.

15. The method for forming a semiconductor structure according to claim 14, wherein: The top source and drain serve as bottom electrodes of the resistance random access memory.

16. The method for forming a semiconductor structure according to claim 14 or 15, further comprising: A shallow trench isolation is formed between the two vertical pass field effect transistors, the shallow trench isolation extending from a top surface of the first spacer through the doped source and a portion of the substrate.

17. The method for forming a semiconductor structure according to claim 14 or 15, wherein: Forming the two vertical transfer field effect transistors further includes: forming a metal gate material surrounding the epitaxial channel; and A shallow trench isolation is formed between the two vertical transfer field effect transistors, the shallow trench isolation being embedded in a first spacer, a doped source, and a portion of a substrate, wherein the doped source is disposed on the substrate, the doped source includes a doped region on the substrate, the doped region includes a first dopant, and an anti-doped layer including a second dopant different from the first dopant is disposed between the doped region and the substrate.

18. The method for forming a semiconductor structure according to claim 14 or 15, further comprising: A metal fill is deposited between the two vertical transfer field effect transistors, the metal fill being arranged on the top electrode.

19. The method for forming a semiconductor structure according to claim 17, further comprising: forming two source contact structures in contact with the doped source; forming two gate contact structures in contact with the metal gate material; as well as An oxide RRAM contact structure is formed in contact with a top portion of the metal fill.

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